- DDR Training sequence happens very fast. The speedup in boot time is
negligible by skipping the training sequence during 2nd boot or after.
So remove the check and skip.
- This change improves the robustness of DDR training. If u-boot crashed
during DDR training, the training could be left in a limbo state, where
the BootROM has recorded that it is already in a 2nd boot. The training
must be repeated in this scenario to get out of this limbo state, but due
to the check it cannot be performed.
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Now that all differences in functionality are covered by individual
flags, remove the enumeration of SoC variants.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
While R40 puts the EMAC syscon register at a different address from
other variants, the relevant portion of the register's layout is the
same. Factor out the register offset so the same code can be shared
by all variants. This matches what the Linux driver does.
This change provides two benefits beyond the simplification:
- R40 boards now respect the RX delays from the devicetree
- This resolves a warning on architectures where readl/writel
expect the address to have a pointer type, not phys_addr_t.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Describe this feature instead of using the SoC ID.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Describe this feature instead of using the SoC ID.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Currently, EMAC variants are distinguished by their identity, but this
gets unwieldy as more overlapping variants are added. Add a structure so
we can describe the individual feature differences between the variants.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The HDMI PHY depends on the HVCC supply being enabled. So far we have
relied on it being enabled by an earlier firmware stage (SPL or TF-A).
Attempt to enable the regulator here, so we can remove that dependency.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
This abstracts away the CCU register layout, which is necessary for
supporting new SoCs like H6 with a reorganized CCU. One of the resets is
referenced from the PHY node instead of the controller node, so it will
have to wait until the PHY code is factored out to a separate driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
This driver is actually used for powerpc and m68k/ColdFire.
On ColdFire SoC's, interrupt flag get not set if IIEN flag (mbcr bit6,
interrupt enabled) is not set appropriately before each transfert.
As a result, the transfert hangs forever waiting for IIEN.
This patch set IIEN before each transfert, while considering this fix
as not harming powerpc arch.
Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
The IS_ENABLED, which does not consider SPL build, should be replaced
by CONFIG_IS_ENABLED.
For the case that we only enable DM CLK for u-boot but not in SPL, the
IS_ENABLED(CONFIG_CLK) still returns true, then cause clock failure.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Current code use dm_gpio_get_value() to get SDA and SCL value, and the
value depends on whether DTS file config the GPIO_ACTIVE_LOW. In ususal
case for i2c GPIO, DTS need to set GPIO_ACTIVE_LOW for SCL/SDA pins. So
here the logic is not correct.
And we must not use GPIOD_ACTIVE_LOW in client code include the
dm_gpio_set_dir_flags(), it is DTS's responsibility for this flag. So
remove GPIOD_ACTIVE_LOW here.
Fixes: aa54192d4a ("dm: i2c: implement gpio-based I2C deblock")
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Alexander Kochetkov <al.kochet@gmail.com <mailto:al.kochet@gmail.com>>
This code first figures out if there is an i2c,speeds property, if so
its size in u32s, and then reads the value into the local speeds[]
array. Both 'size' and 'speeds' are completely unused thereafter.
It's not at all clear what this is supposed to do. Of course, it could
be seen as a sanity check that the DT node does have an i2c,speeds
property with an appropriate number of elements, but for that one
wouldn't actually need to read it into speeds[]. Also, I can't find
anywhere else in the U-Boot code which makes use of values from that
property (this is is the only C code referencing "i2c,speeds"), so it
seems pointless to insist that it's there.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
All build targets using this driver already use DM_MMC. So let's depend
this driver on this Kconfig symbol and remove the non-DM driver part.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
CONFIG_MMC_SDHCI_IO_ACCESSORS is not supported and/or used by this
driver so let's remove these unused parts completely.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
This driver already depends on CONFIG_ARCH_MVEBU, so there is no need
to have some checks for this Kconfig symbol in the driver itself. Let's
remove these superfluous checks.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
The default erase command applies on erase group unit, and
simply round down to erase group size. When the start block
is not aligned to erase group size (e.g. erasing partition)
it causes unwanted erasing of the previous blocks, part of
the same erase group (e.g. owned by other logical partition,
or by the partition table itself).
To prevent this issue, a simple solution is to use TRIM as
argument of the Erase command, which is usually supported
with eMMC > 4.0, and allow to apply erase operation to write
blocks instead of erase group
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
When secure/insecure TRIM operations are supported.
When used as erase command argument it applies the
erase operation to write blocks instead of erase
groups.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
- improve tegra DC driver to work with panel ops and implement
native 180 degree panel rotation support
- add T30 support to tegra DC driver
- add DSI driver (based on mainline Linux one with minor
adjustments, only T30 tested)
- add get_display_timing ops to simple panel driver
- extend simple panel driver to use it for MIPI DSI panels
which do not require additional DSI commands for setup
-----BEGIN PGP SIGNATURE-----
iGwEABECACwWIQSC4hxrSoIUVfFO0kRM6ATMmsalXAUCZDBwUw4cYWd1c3RAZGVu
eC5kZQAKCRBM6ATMmsalXL3+AJ9EkQKAWXZtlYdAOVl4/nzJnuTCAQCfY58zkDsw
TnAlwmMGWFl3RF6yGXY=
=uYUp
-----END PGP SIGNATURE-----
Merge tag 'video-20230407' of https://source.denx.de/u-boot/custodians/u-boot-video
- fix building sandbox without SDL
- improve tegra DC driver to work with panel ops and implement
native 180 degree panel rotation support
- add T30 support to tegra DC driver
- add DSI driver (based on mainline Linux one with minor
adjustments, only T30 tested)
- add get_display_timing ops to simple panel driver
- extend simple panel driver to use it for MIPI DSI panels
which do not require additional DSI commands for setup
The DM_REGULATOR symbol has SPL counterpart in:
drivers/power/regulator/Kconfig:config SPL_DM_REGULATOR
Use CONFIG_IS_ENABLED() macro to match on the correct
variant depending on the build stage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The DM_REGULATOR symbol has SPL counterpart in:
drivers/power/regulator/Kconfig:config SPL_DM_REGULATOR
Use CONFIG_IS_ENABLED() macro to match on the correct
variant depending on the build stage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The DM_REGULATOR symbol has SPL counterpart in:
drivers/power/regulator/Kconfig:config SPL_DM_REGULATOR
Use CONFIG_IS_ENABLED() macro to match on the correct
variant depending on the build stage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The DM_REGULATOR symbol has SPL counterpart in:
drivers/power/regulator/Kconfig:config SPL_DM_REGULATOR
Use CONFIG_IS_ENABLED() macro to match on the correct
variant depending on the build stage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The DM_REGULATOR symbol has SPL counterpart in:
drivers/power/regulator/Kconfig:config SPL_DM_REGULATOR
Use CONFIG_IS_ENABLED() macro to match on the correct
variant depending on the build stage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The DM_REGULATOR symbol has SPL counterpart in:
drivers/power/regulator/Kconfig:config SPL_DM_REGULATOR
Use CONFIG_IS_ENABLED() macro to match on the correct
variant depending on the build stage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Re-use simple panel driver for MIPI DSI panels
which do not require additional DSI commands
for setup.
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # Paz00
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF700T T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Some cases may require passing display timings from
panel driver. To handle such cases support parsing
device tree panel node for timing subnode.
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # Paz00
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Google Nexus 7 2012
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Adds support for both DSI outputs found on Tegra. Only very
minimal functionality is implemented, so advanced features
like ganged mode won't work. Driver is heavily based on
mainline Tegra DSI and re-uses much of its features.
Only T30 is supported for now but T20 support can be added
if any supported devices will be found.
Driver is wrapped as panel driver since Tegra DC driver supports
only panel drivers calls.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Internal video devices like DSI and HDMI controllers
require sending commands into DC register field.
To make this available, lets create platform data,
which is restricted to pass DC regmap only to
pre-defined devices.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # Paz00
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Tegra DC driver does not call panel_set_backlight, which can
result in absence of backlight on device. Fix this by calling
panel_set_backlight with BACKLIGHT_DEFAULT just after
panel_enable_backlight.
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # Paz00
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Unlike 90 and 270 degree rotation, 180 degree rotation is more
common and does not require scaling. Implement it for correct
grouper support.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # Google Nexus 7 2012
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Google Nexus 7 2012
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Check if panel driver has display timings and get those.
If panel driver does not pass timing, try to find timing
under rgb node for backwards compatibility.
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # Paz00
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
DISP1 clock may use PLLP, PLLC and PLLD as parents.
Instead of hardcoding, lets pass clock and its
parent from device tree. Default parent is PLLP.
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # Paz00
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Move tegra dc driver to tegra20 directory and also mention
T30 in description of the driver's config option.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
[agust: add commit description]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
On popular request make the display driver from T20 work on T30 as
well. Turned out to be quite straight forward. However a few notes
about some things encountered during porting: Of course the T30 device
tree was completely missing host1x as well as PWM support but it turns
out this can simply be copied from T20. The only trouble compiling the
Tegra video driver for T30 had to do with some hard-coded PWM pin
muxing for T20 which is quite ugly anyway. On T30 this gets handled by
a board specific complete pin muxing table. The older Chromium U-Boot
2011.06 which to my knowledge was the only prior attempt at enabling a
display driver for T30 for whatever reason got some clocking stuff
mixed up. Turns out at least for a single display controller T20 and
T30 can be clocked quite similar. Enjoy.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Add pinctrl tables for R8A779G0 V4H SoC.
Based on Linux next 20230228 PFC tables tables up to
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync with Linux next 20230228, sort sh_pfc_pinconf_set voltage args]
Add clock tables for R8A779G0 V4H SoC from Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")
There is an adjustment to the clock tables to make them easier suitable
for U-Boot, PLL2 is not treated as GEN4 PLL type PLL2_VAR, but rather a
plain PLL2. This should be sufficient until PLL2_VAR is implemented in
the clock core.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync with Linux next 20230228 . Update from CLK to CPG core driver
Treat PLL2 as non-PLL2_VAR for now]
Add pinctrl tables for R8A779F0 S4 SoC.
Based on Linux next 20230228 PFC tables tables up to
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Use RCAR_64 Kconfig, sync with Linux next 20230228]
Add clock tables for R8A779F0 S4 SoC
Based on Linux commit 24aaff6a6ce4 ("clk: renesas: cpg-mssr: Add support
for R-Car S4-8") by Yoshihiro Shimoda and sync the tables up to Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync with Linux next 20230228 . Update from CLK to CPG core driver]
Update R-Car Gen4 support in Gen3 clock driver. This patch renames the
V3U clock parts to Gen4 and extends them by new PLL2, PLL3, PLL4, PLL6
as well as SDSRC clock which use undocumented bits so far, and RPCSRC
clock which uses its own more capable divider table. The Gen4 module
standby and reset tables are also updated.
This patch makes use of union to alias Gen3 and more extensive Gen4
PLL tables, as the driver cannot ever be instantiated on hardware
that would identify itself as both Gen3 and Gen4.
The V3U clock driver is updated to match Gen4 clock driver behavior,
it is augmented with a more extensive PLL table and a valid MODEMR
register offset.
This supersedes "clk: renesas: Introduce R-Car Gen4 CPG driver"
from Hai Pham as the R-Car Gen3 and Gen4 clock core drivers are
extremely similar. That implementation was in turn based on Linux
commit 470e3f0d0b15 ("clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver")
by Yoshihiro Shimoda .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Use CONFIG_RCAR_64 to make the driver available on both
R-Car Gen3 and R-Car Gen4.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Provide the basic HSCIF support for R-Car SoC.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Fill in HSSRR offset for Gen2 and SCBRR calculation for Gen2 and Gen3]
Reviewed-by: Simon Glass <sjg@chromium.org>
Add R-Car Gen4 family support. The basic function is as same as previous
R-Car Generation.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Swap RZ/A1 and Gen4 to keep the GenN sequence, use RCAR_64]
Add support for R-Car Gen4 SoCs and a matching DT compatible.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Drop SoC specific compatible, use RCAR_64 Kconfig symbol, update commit message]
Support R-Car Gen4 family. The default quirk is similar to previous
generation.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Use RCAR_64 Kconfig
Instead of #if and #ifdef, use IS_ENABLED and CONFIG_IS_ENABLED macros.
This improves build test coverage. The CONFIG_SPL_BUILD must remain an
ifdef, as CONFIG_SPL_STACK may not always be defined, e.g. in U-Boot
proper build. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
The 64bit limitation check is compiled and optimized out on 32bit
platforms, but generates a type width warning:
drivers/mmc/tmio-common.c: In function ‘tmio_sd_addr_is_dmaable’:
drivers/mmc/tmio-common.c:376:26: warning: right shift count >= width of type [-Wshift-count-overflow]
376 | if (addr >> 32)
| ^~
Fix the warning by checking the addr type width to see whether the
shift even makes sense in the first place. The width check is also
optimized out at compile time.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Add support for R-Car Gen4 SoCs into the driver.
While I2C on R-Car Gen4 does support some extra features (Slave Clock
Stretch Select), for now it is treated the same as I2C on R-Car Gen3,
which let us share the same driver.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Use RCAR_64 Kconfig
Reviewed-by: Heiko Schocher <hs@denx.de>
Add support for the GPIO controller block in the R-Car Gen4 family.
It has a General Input Enable Register (INEN), whose reset state is to
have all inputs disabled.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add two new callbacks matching the Linux ones. The .set_mode is used to set
PHY mode and submode, where mode is either USB, Ethernet, and so on, while
submode is e.g. for Ethernet case RGMII, RMII, and so on. The .set_speed is
used to configure link speed into the PHY. Unlike the existing configure
callback, which is used to pass arbitrary custom information to the PHY,
these two callbacks are used to pass standardized set of information to
the PHY.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Pull Marvell 10G PHY driver from Linux 6.1.y as of commit
d6d29292640d3 ("net: phy: marvell10g: select host interface configuration")
and heavily adapt to match U-Boot PHY framework. Support for
hwmon is removed as is much other functionality which could
not be tested, this results in much simpler driver which can
only bring the PHY up and set MAC type.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Add phy_modify_mmd()/phy_modify_mmd_changed() from Linux 5.1.y as of commit
b8554d4f7288f ("net: phy: add register modifying helpers returning 1 on change")
This is used by the upcoming Marvell 10G PHY driver.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Import marvell_phy.h from Linux 5.14.y as of commit
a5de4be0aaaa6 ("net: phy: marvell10g: fix differentiation of 88X3310 from 88X3340")
and use it in marvell PHY driver instead of current ad-hoc macros.
Two of the PHY IDs are unknown to Linux, 88E1149S and 88E1680, for
those two, only sync the length of the hexadecimal number to 8 digits.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Synchronize PHY interface modes with Linux next 6.2.y commit:
0194b64578e90 ("net: phy: improve phy_read_poll_timeout")
Retain LX2160A/LX2162A PHY modes as those are not yet supported
by the Linux kernel, but isolate those with ifdeffery.
Isolate NCSI which are also not supported by Linux kernel. Note
that the ifdeffery cannot be avoided with IS_ENABLED() here due
to compilation of the entire conditional, which would fail in
case NCSI symbols are not available.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Replace PHY_INTERFACE_MODE_SFI with PHY_INTERFACE_MODE_5GBASER,
PHY_INTERFACE_MODE_10GBASER and PHY_INTERFACE_MODE_XAUI to match
Linux PHY interface modes.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
This mode does not seem to be well defined and used anywhere, remove support for it.
Based on discussion:
- 1000baseX does c37 AN of duplex+pause
- SGMII does AN of duplex+pause+speed, at lower speed bytes are repeated 10x/100x
- 2500baseX does not do AN, or does very different c73 AN
- SGMII 2500 behavior is unclear
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
The phy_init() is now used only to perform manual relocation of PHY
driver callbacks. Wrap it in ifdeffery and only call it on systems
which still require manual relocation, i.e. m68k .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Wrap phy_drv_reloc() back into phy_init() to reduce ifdeffery,
since phy_drv_reloc() is now called only from one call site.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
This function is no longer used, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
The static phy_drivers list is superseded by linker list of struct phy_drivers
now that all drivers have been converted to the later. Drop the phy_drivers
list as well as list_head from struct phy_driver.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
This particular PHY driver is slightly more spread out across additional
source files. Since the phy_register() calls are no longer necessary, all
the registration calls across those source files is dropped. Furthermore,
the Makefile can now be updated to only compile generic TI PHY support if
matching Kconfig symbol is enabled and the ifdeffery in the generic TI PHY
driver can be dropped.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Introduce U_BOOT_PHY_DRIVER() macro which is used to add struct phy_driver
into a new linker list section containing all compiled in struct phy_driver
drivers. This is so far empty until PHY drivers are converted over to this
macro.
Iterate over both drivers registered using soon to be legacy phy_register()
as well as drivers in the new linker list when looking up a suitable PHY
driver. This way, PHY drivers can be converted over to the new macro one
driver at a time.
The relocation of callbacks for linker list based drivers now happens in
phy_init() call as the drivers are available at that point in time, and
phy_register() is not called for those drivers.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Create separate function to implement manual relocation of PHY driver
functions and make use of that function. This is a preparatory patch
for introduction of PHY driver definition using linker lists.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
These struct phy_driver ... instances are local to this source code
file, staticize them. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
These struct phy_driver ... instances are local to this source code
file, staticize them. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
These struct phy_driver ... instances are local to this source code
file, staticize them. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
These struct phy_driver ... instances are local to this source code
file, staticize them. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
CONFIG_SYS_SCSI_MAX_SCSI_ID is not defined if CONFIG_SCSI=n.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Building with CONFIG_AHCI_PCI=y and CONFIG_SCSI_AHCI=n leads to
drivers/ata/ahci-pci.o: in function `ahci_pci_probe':
drivers/ata/ahci-pci.c:21: undefined reference to `ahci_probe_scsi_pci'
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The Freescale ESPI driver (CONFIG_FSL_ESPI) relies to the MPC85xx platform
(PowerPC) through arch/powerpc/include/asm/immap_85xx.h. The driver can't
compile on another architecture/platform.
Signed-off-by: Corentin Guillevic <corentin.guillevic@smile.fr>
On mpc832x, SPI can be either handled by CPU or QE.
In order to work in CPU mode, bit 17 of SPMODE has to
be set to 1, that bit is called OP.
Also, data is located at a different place than the one expected
by the driver today. In 8 bits mode with REV set, data to be
transmitted is located in the most significant byte while
received data is located in second byte. So perform the
necessary shifts.
In order to differentiate with other CPUs, a new compatible is
added for mpc832x: fsl,mpc832x-spi
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Cc: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
The mpc832x has GPIOs handled by the QUICC Engine.
The registers are different from the one for the
non QE mpc83xx GPIOs.
Implement a GPIO driver for those.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
gd->arch.sdhc_clk only exists when CONFIG_FSL_ESDHC is set,
so enclose it inside ifdefs.
gd->arch.qe_clk and gd->arch.brg_clk must be populated when
CONFIG_QE is set.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Introduce a new compatible "fsl,pq2pro-wdt"
On mpc83xx, the prescaling factor is 0x10000.
Don't write the watchdog configuration register in
start.S as it can be written only once.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
mpc8xx, mpc83xx and mpc86xx have similar watchdog with almost same
memory registers.
Refactor the driver to get the register addresses from the
device tree and use the compatible to know the prescale factor.
Calculate the watchdog setup value from the provided timeout.
Don't declare it anymore as an HW_WATCHDOG, u-boot will start
servicing the watchdog early enough.
On mpc8xx the watchdog configuration register is also used for
configuring the bus monitor. So add it as an option to the watchdog
when it is mpc8xx. When watchdog is not selected, leave the
configuration of the initial SYPCR from Kconfig.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
mpc8xx, mpc83xx and mpc86xx have similar watchdog with almost same
memory registers.
Rename it mpc8xxx which is the generic name used for drivers supporting
several mpc families.
The driver will be made more generic in following patch.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Allow a slice of an existing block device to be mapped to a
blkmap. This means that filesystems that are not stored at exact
partition boundaries can be accessed by remapping a slice of the
existing device to a blkmap device.
Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Allow a slice of RAM to be mapped to a blkmap. This means that RAM can
now be accessed as if it was a block device, meaning that existing
filesystem drivers can now be used to access ramdisks.
Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
blkmaps are loosely modeled on Linux's device mapper subsystem. The
basic idea is that you can create virtual block devices whose blocks
can be backed by a plethora of sources that are user configurable.
This change just adds the basic infrastructure for creating and
removing blkmap devices. Subsequent changes will extend this to add
support for actual mappings.
Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With vendor boot image introduced in version 3 and 4 of boot
image header, boot information is located in both boot image
and vendor boot image.
Flashing zImage is not supported for version 3 and 4 since this
requires updating vendor boot image and/or generating a new image.
Print an error message when the boot image header version is
greater than 2.
Signed-off-by: Safae Ouajih <souajih@baylibre.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
With the new vendor boot image introduced in versions 3 and 4
of boot image header, the header check must be done for both boot
image and vendor boot image. Thus, replace android_image_check_header()
by is_android_boot_image_header() to only refer to boot image header check.
Signed-off-by: Safae Ouajih <souajih@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Android introduced boot header version 3 or 4.
The header structure change with version 3 and 4 to support
the new updates such as:
- Introducing Vendor boot image: with a vendor ramdisk
- Bootconfig feature (v4)
Change andr_img_hdr struct name to maintain support for version v0,
v1 and v2 while introducing version 3 and 4.
Signed-off-by: Safae Ouajih <souajih@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
The spl_board_prepare_for_boot() should be called before jump_to_image_no_args()
to perform board-specific deinitialization before jumping to the next stage.
This board-specific deinitialization can be very much anything, e.g. disable
dcache in case it was enabled, or such.
Add the missing spl_board_prepare_for_boot() call into f_sdp .
Signed-off-by: Marek Vasut <marex@denx.de>
Sometimes a multi-element array is used for "gpio-ranges" property in
dts file:
qe_pio_e: gpio-controller@1460 {
......
gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
......
};
But the function pinctrl_gpio_get_pinctrl_and_offset can't handle this
case because the "index" argument passed to dev_read_phandle_with_args
is fixed to be "0". Use a loop to traverse the array to fix it.
Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
A condition in the rk3399 RAM initialization code used the old
CONFIG_RAM_RK3399_LPDDR4 constant name. This commit changes the
condition to use the correct CONFIG_RAM_ROCKCHIP_LPDDR4 constant.
Reviewed-by: Simon Glass <sjg@chromium.org>
%s/supporedt/supported/
Fixes: edca8cf721 ("Convert CONFIG_SCSI_AHCI_PLAT et al to Kconfig")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---------------------------------
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/15819
i.MX patches queued for next:
- Conversions to DM_SERIAL
- Fixes for Toradex boards
- Gateworks Boards
- i.MX8ULP
- EQoS support / fixes, changes in boards
-----BEGIN PGP SIGNATURE-----
iG0EABECAC0WIQS2TmnA27QKhpKSZe309WXkmmjvpgUCZCaU0Q8cc2JhYmljQGRl
bnguZGUACgkQ9PVl5Jpo76YCKgCgk4OueoIggmes+Ccj8bu1BcQbrfYAoJAgMeKE
It0hrVAifD62TPb2rmHt
=hFVG
-----END PGP SIGNATURE-----
Merge tag 'u-boot-imx-next-20230331' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
u-boot-imx-next-20230331 for next
---------------------------------
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/15819
i.MX patches queued for next:
- Conversions to DM_SERIAL
- Fixes for Toradex boards
- Gateworks Boards
- i.MX8ULP
- EQoS support / fixes, changes in boards
It should return -EINPROGRESS if successful otherwise sysreset-uclass
will continue to the next sysreset device.
Signed-off-by: Jonathan Liu <net147@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Remove need of dts binding for button keyboard since it reuses
gpio-keys binding. Select gpio-keys driver if button keyboard
is selected since button keyboard can not operate on its own.
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Adding support for Analog Devices MAX313XX series RTCs.
This is ported from the Linux driver and adapted for use in u-boot.
Notable differences are
- handling of tm_year and tm_mon differ
- clock source support is omitted
- hwmon support for the MAX31328 and MAX31343 is omitted
- rtc_ops->reset is added
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The API is more convenient to use if one doesn't have to know upfront
which gpio controller has a line with the name one is searching for,
and arrange to look that device up somehow. Or implement this loop
oneself.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Glass <sjg@chromium.org>
These operations are required by dm_rtc_read and
dm_bootcount_get helpers.
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reports the sandbox swapcase PCI Express device to support a 256 byte
Maximum Payload Size for MPS tuning tests.
Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
There can certainly be a lot more elements in the "revisions" (and
"names") arrays than there are gpios used to form the trinary number
we're searching for; we simply don't know the array size up-front.
Nor do we need to, because the loop body already knows to recognize
-EOVERFLOW as "not that many elements present" (and we have a test
that specifically ensures that dev_read_u32_index() returns exactly
that). So just drop the i < priv->gpio_num condition.
While in here, fix the weird placement of the default: keyword.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
Implement common board_interface_eth_init() and call it from the FEC
driver to configure IOMUXC GPR[1] register according to the PHY mode
obtained from DT. This supports all three interface modes supported by
the i.MX8M Mini/Nano/Plus FEC and supersedes the current board-side
configuration of the same IOMUX GPR[1] duplicated in the board files.
Signed-off-by: Marek Vasut <marex@denx.de>
The FEC ref clock frequency on i.MX8M Mini/Nano/Plus was so far configured
via ad-hoc board code. Replace that with DM clock clk_set_rate() instead.
This way, the driver claims all its required clock and sets the ref clock
rate, without any need of architecture specific register fiddling.
Signed-off-by: Marek Vasut <marex@denx.de>
Implement common board_interface_eth_init() and call it from the DWMAC
driver to configure IOMUXC GPR[1] register according to the PHY mode
obtained from DT. This supports all three interface modes supported by
the i.MX8M Plus DWMAC and supersedes current board-side configuration
of the same IOMUX GPR[1] duplicated in the board files.
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
With DM clock support in place, it is easy to add RMII support into the
MAC driver. The RMII cannot operate at 1000 Mbps and at 100 and 10 Mbps
the clock frequency is 50 MHz and 5 MHz instead of 25 MHz and 2.5 MHz.
The board DT requires the following adjustments to EQoS node:
phy-mode = "rmii";
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
<&clk IMX8MP_SYS_PLL2_100M>,
<&clk IMX8MP_SYS_PLL2_50M>;
assigned-clock-rates = <0>, <100000000>, <50000000>;
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
The DWMAC clock in i.MX8M Plus were so far configured via ad-hoc
architecture code. Replace that with DM clock instead. This way,
the driver claims all its required clock, enables and disables
them, and even gets the CSR clock rate and sets the TX clock rate,
without any need of architecture specific register fiddling. Drop
the architecture specific code while at it too.
The adjustment here is modeled after STM32MP15xx clock handling
in this driver.
Signed-off-by: Marek Vasut <marex@denx.de>
The driver currently only waits for DMA_MODE SWR bit to clear itself.
This is insufficient e.g. on i.MX8M Plus, where the MAC must be reset
before IOMUX GPR[1] content is latched into the MAC and used. Without
the proper reset, the i.MX8M Plus MAC variant does not take the value
in IOMUX GPR[1] into account, which makes it impossible e.g. to switch
interface mode from RGMII to any other.
Since proper reset is desired in general to put the block into defined
state, always assert the DMA_MODE SWR bit before waiting for the bit
to clear itself.
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
This function is only used within the driver, staticize it.
Fixes: 149e80f74b ("net: dwc_eth_qos: public some functions")
Signed-off-by: Marek Vasut <marex@denx.de>
The dm_gpio_free() is never called, because for stm32, the phy_reset_gpio
pointer is never valid. This is because only tegra186 ever claims the
phy_reset_gpio, all other platforms use the PHY framework to reset the
PHY instead. Drop the dm_gpio_free() and dm_gpio_is_valid().
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
The return is never triggered due to the goto just above it.
Drop it. No functional change.
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Move the board_interface_eth_init() into common ethernet uclass code,
since this function could be shared by multiple drivers.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marek Vasut <marex@denx.de>
Add clock for the DWMAC EQoS block. This is used among other things
to configure the MII clock via DM CLK.
Acked-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
The ocotp driver is available for regular and SPL builds using the
(SPL_)MXC_OCOTP configuration. Also, the ocotp driver does not support
the driver model (DM) configuration.
But, for SPL builds, the SPL_MXC_OCOTP configuration depends on
SPL_MISC which implies on SPL_DM.
This commit replaces the dependency on SPL_MISC with SPL_DRIVERS_MISC.
So the only requirement is to have enabled miscellaneous drivers for
the SPL.
Signed-off-by: Jean-Marie Lemetayer <j.lemetayer@kerlink.fr>
PCA9451A uses similar BUCKs and LDO regulators as PCA9450B/C but
has LDO2 and LDO3 removed. So reuse pca9450 PMIC and regulator driver
and add new type for PCA9451A.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Remove legacy command definitions, change to use new ELE_xxx command
request.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Add get_events API to retrieve any singular events that has occurred
since the FW has started from sentinel
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The ECC fuse on 8ULP can't be written twice. If any user did it, the
ECC value would be wrong then cause accessing problem to the fuse.
The patch will lock the ECC fuse word to avoid this problem.
For iMX9, the OTP controller automatically prevents an ECC fuse word to
be written twice. So it does not need the setting.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Since new 8ULP A1 S400 FW (v0.0.8-e329b760) can support to read
more fuses: like PMU trim, Test flow/USB, GP1-5, GP8-10. Update
the u-boot driver for the new mapping.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Alice Guo <alice.guo@nxp.com>
To align with ARM trusted firmware's change, adjust DRAM timing
save area to new position 0x20055000. So we can release the space
since 0x2006c000 for the NOBITS region of ARM trusted firmware
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
The Linux devicetrees for Apple silicon devices are after review
feedback switching from deleting unused PCIe ports to disabling them.
Link: https://lore.kernel.org/asahi/1ea2107a-bb86-8c22-0bbc-82c453ab08ce@linaro.org/
Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
The WIZ acts as a wrapper for SerDes and has Lanes 0 and 2 reserved
for USB for type-C lane swap if Lane 1 and Lane 3 are linked to the
USB PHY that is integrated into the SerDes IP. The WIZ control register
has to be configured to support this lane swap feature.
The support for swapping lanes 2 and 3 is missing and therefore
add support to configure the control register to swap between
lanes 2 and 3 if PHY type is USB.
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
It's possible that the Type-C plug orientation on the DIR line will be
implemented through hardware design. In that situation, there won't be
an external GPIO line available, but the driver still needs to address
this since the DT won't use the typec-dir-gpios property.
Add code to handle LN10 Type-C swap if typec-dir-gpios property is not
specified in DT.
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
-----BEGIN PGP SIGNATURE-----
iQFQBAABCgA6FiEEqxhEmNJ6d7ZdeFLIHrMeAg6sL8gFAmQirs0cHGV1Z2VuLmhy
aXN0ZXZAY29sbGFib3JhLmNvbQAKCRAesx4CDqwvyIWBCACz3Bh76v3vbqhaQPBq
ZGB+jnaZQsWW9r285dCmQFA/xGLbQoMVIhzvLVmEcZdr0d9wHUEsy1IzC6tak2MJ
NkiYcNRb3lnYEDthvjGdpz6QIGZBBOj8l8ha70z4ZvzBwTfOReB04N5207n5Tzq/
hAFAWcM3VxfVXF2Xb8O/HbyEbOVXKY65xWinAIZqvGscox+vx3Vj9m1aLqcQP0Wy
bCZowynfyKWiFrHr5TYgpmL4ROsj3jbnRhC0dqyB+ewRdRAK4uVJXRj23ywwDcGH
VqlYFVFT8EY5HSzCG8VGMtGqV+H4+K4RYiTLtDwtbHWdXnUKLKORXtXi2xcHHxS1
rj5U
=kb6/
-----END PGP SIGNATURE-----
Merge tag 'u-boot-at91-2023.07-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next
First set of u-boot-at91 features for the 2023.07 cycle:
This feature set includes the clock changes required for sam9x60 SoC to
support USB host.
In order for some of the functionalities, such as the USB clocks,
to work properly we need some clocks to be properly initialised
at the very beginning of booting.
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Clock setup was intended for setting clocks at boot time on SAMA7G5,
e.g. for root clocks like PLLs, that were used to feed IPs needed alive
in u-boot (e.g. Ethernet clock feed by a PLL). Export this functionality
to all at91 clocks as it may be necessary on other SoCs.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Register into DM the clocks required to properly enable USB functionality
within the bootloader.
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Implement sam9x60 USB clock driver. This clock has
three parents: PLLA, UPLL and MAINXTAL. The driver is
aware of the three possible parents with the help of the
two mux tables provied to the driver during the registration
of the clock.
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
- Fixes for booting newer revs of the SoC in the Raspberry Pi 4
- Propagate some firmware DT properties to the loaded DT
- Update the Zero2W upstream DT name
Newer firmware can manage the SDCDIV clock divisor register, allowing
the divisor to scale with the core as necessary.
Leverage this ability if the firmware supports it.
Adapted from the following raspberrypi Linux kernel commit:
bcm2835-sdhost: Firmware manages the clock divisor
08532d242d
Signed-off-by: Vincent Fazio <vfazio@xes-inc.com>
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Setting RX flow error handling will stall the channel until descriptors
are available to move RX data. Setting this bit causes issues when
tearing down ethernet DMA channel at the end of TFTP transfer as
unrelated network packets can cause teardown to stall indefinitely waiting
for driver to queue add more desc leading to channel hang with error
logs:
udma_stop_dev2mem TIMEOUT !
udma_stop_dev2mem: peer not stopped TIMEOUT !
udma_stop_dev2mem TIMEOUT !
Fix this by clearing rx_error_handling similar to how its done for UDMA
as part of udma_alloc_rchan_sci_req()
This fixes occasional TFTP Failures seen when downloading multiple files
one after the other on AM64/AM62 SoCs.
Fixes: 9a92851c33 ("dma: ti: k3-udma: Add BCDMA and PKTDMA support")
Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The reset identifier must be processed via MOD_CLK_PACK() before it is
used to look up register and bit within reset_regs or reset_clear_regs
arrays, otherwise completely bogus register and bit is picked from the
arrays, one which may even be out of range.
Fixes: 326e05c5e2 ("clk: renesas: Add and enable CPG reset driver")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
In the binding for the Rockchip timer the compatible string
consists of a SoC orientated string and a fall back string
"rockchip,rk3288-timer", so remove all unneeded ones and
fix driver name.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
For Rockchip platform, DLL bypass bit and start bit need to be set if
DLL is not locked.
With this change applied eMMC in my NanoPi R5S can run at 52 MHz.
Based on linux commit b75a52b0dda3 ("mmc: sdhci-of-dwcmshc: Update DLL
and pre-change delay for rockchip platform")
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Device tree contains assigned-clock-rates property for these,
but default value will work just fine
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
The get_mmc_clk ops is expected to set a clock rate and return the
configured rate as an unsigned value. However, if clk_set_rate fails,
e.g. using a fixed rate clock, a negative error value is returned.
The mmc core will treat this as a valid unsigned rate and tries to
configure a divider based on this bogus clock rate.
Use 0 as the return value when setting clock rate fails, the mmc core
will configure to use bypass mode instead of using a bogus divider.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The rate and error value is not returned for aux16m clocks, fix this.
Fixes: 7a474df740 ("clk: rockchip: Add rk3588 clk support")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Make the indent of these macro elements consistent with the
rest of this table. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add support for debug output very early during boot using the DEBUG_UART
mechanism. This uses a static fixed UART port configuration selected via
Kconfig options and dedicated print functions from debug_uart.h. This is
useful e.g. when debugging problems so early during boot, that not even
the DM is initialized at that point, and thus DM_SERIAL is not available
either.
This functionality is disabled by default. To activate it, define the
following Kconfig options and select SCIF type using CFG_SCI/CFG_SCIF_A/
CFG_HSCIF/<nothing for regular SCIF>:
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_SCIF=y
CONFIG_DEBUG_UART_BASE=0xe6540000
CONFIG_DEBUG_UART_CLOCK=24000000
The later two options define the SCIF physical base address and SCIF
input clock in Hz. Optionally, to validate DEBUG_UART works, enable
the following as well to get early serial output message by default:
CONFIG_DEBUG_UART_ANNOUNCE=y
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Both CONFIG_SCI and CONFIG_SCIF_USE_EXT_CLK options do not have a
matching Kconfig entry because they are internal to the SCIF driver.
Change their prefix to CFG_, i.e. CFG_SCIF_USE_EXT_CLK and CFG_SCI,
to reflect that and avoid interferring with Kconfig symbols. Since
neither of those options are defined elsewhere, no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Switch ifdef in sh_gpio_get_value() to IS_ENABLED() macro.
The CONFIG_RCAR_GEN3 will never have SPL counterpart, so
the IS_ENABLED() macro is the right one here. No functional
change, except for improved build test coverage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Calling old U-Boot API doesn't allow to use fixed PHY.
Searching by mask is the part of new function, after
scanning FDT for a fixed PHY definition
Fixes: e821a7bdb1 ("net: ravb: Detect PHY correctly")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Mikhail Lappo <mikhail.lappo@esrlabs.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
[Hai Pham: Drop phy_connect_dev since it's called in phy_connect]
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Use mask -1 instead of 0 to reinstate the search behavior
over all PHY addresses. Add Fixes tag, sort the tag list.]
Sort the list of "depends" symbols in ascending order.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Sort the list of "depends" symbols in ascending order.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Do not cache the single CPG MODE register bit 12, instead cache the
entire register value, and only pick the matching bit from the cached
value when core clock of type MDSEL or PE are used. Both MDSEL and PE
clock type currently define .offset field as 12 on Gen3, which means
this code will use bit 12 on Gen3 again, however there are additional
clock on Gen4 which use different bits, and having this flexibility
in place now will be useful when adding Gen4.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This reverts commit 9f62a472df.
The changes here aren't quite right, and on platforms such as Raspberry
Pi where we can have both serial and video output, the change above
causes output to change. This can be seen as the hush tests we have now
fail.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
It is better to clear the console device rather than the video device,
since the console has the text display. We also need to reset the cursor
position with the console, but not with the video device.
Add a new function to handle this and update the 'cls' command to use it.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present it is not possible for the video driver to use a pre-allocated
frame buffer (such as is done with EFI) with the copy framebuffer. This
can be useful to speed up the display.
Adjust the implementation so that copy_size can be set to the required
size, with this being allocated if the normal framebuffer size is 0.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add support for this to EFI in case it becomes useful. At present it just
slows things down. You can enable CONFIG_VIDEO_COPY to turn it on.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is not yet clear how to read the timer via EFI. The current value seems
much too high on a Framework laptop I tried. Adjust it to a lower
hard-coded value for now.
Signed-off-by: Simon Glass <sjg@chromium.org>
The current vesa structure only provides a 32-bit value for the frame
buffer. Many modern machines use an address outside the range.
It is still useful to have this common struct, but add a separate
frame-buffer address as well.
Add a comment for vesa_setup_video_priv() while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Put this into a function, as we have done for the app implementation.
Comment both functions. FOr now the app still does not access it
correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add new sysinfo IDs for R-Car V3H Condor/Condor-I .
Enable support for sysinfo on R-Car V3H Condor/Condor-I. The sysinfo is
used e.g. to access and decode board-specific information and then in
turn used by board-info to print those information.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Drop compatible from I2C node, this is in r8a77980.dtsi already.
Drop status = "okay" from EEPROM node.
Add dts: tag.
Update the commit message, note the new sysinfo IDs.
Fix Kconfig EEPROM address to be 0x50 and match the DT, sync config.]
Correct the board code ID based on the hardware documentation
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Remove PFC info table entries which are never instantiated,
since there are no drivers for those. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The CLK_RCAR_GEN3 registers two subdrivers, clk_gen3 and rst_gen3.
The former depends on the clock framework, which is always enabled
in this context of clock framework driver, while the later depends
on reset framework which may not always be enabled.
Ensure the reset framework is also always enabled to prevent inobvious
early boot time bind failure of the CPG driver, which leads to system
showing no activity and is difficult to debug.
Note that one possible approach to debug this is to use CONFIG_DEBUG_UART
and add debug printascii()s into the drivers/clk/renesas/clk-rcar-gen3.c .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
In case one of the calls in probe fail, trigger a fail path and
undo all the steps done in probe until the point of failure.
The current implementation failed to stop controller clock and
free claimed clock, so fix that. Furthermore, print return code
in error prints for easier debugging.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The prior stage bootloader might have left the SDnCKCR register in completely
arbitrary state before passing control to U-Boot, which includes the register
being populated with incorrect values. Currently the SDHI driver will attempt
to use clock framework to configure SDn clock, which may fail in case SDnCKCR
contains invalid values for the SDnH clock, because the clock framework would
not be able to determine SDnH clock rate and would get -EINVAL instead, which
in turn would not allow the clock framework to determine the correct SDn clock
divider ratio.
This failure occurs specifically in case SDnCKCR reads back 0x209 .
Correct the problem by first setting default SDnH clock rate to 800 MHz, thus
assuring the SDnCKCR SDnH bits are correct, and only afterward set up the SDn
clock rate to default 200 MHz.
Note that the SDHI driver may reconfigure SDnH clock later based on IOS
settings obtained from the attached card, the 800 MHz set up here is only
the default value.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This configuration setting is only relevant if the board supports USB.
It should not be in the main menu but in the USB menu.
The setting is only relevant in USB host mode.
Fixes: 5454dea313 ("usb: hub: allow to increase HUB_DEBOUNCE_TIMEOUT")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Ofnode value is not set, so all the DT properties are not being read
and due to this default values are being used.
Find nand node and set chip->flash_node value.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230224050709.30014-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Bad block table option is hardcoded to read from flash with
NAND_BBT_USE_FLASH option. This decision should be done based on DT
property. Remove this hardcoding, to be able to use DT property.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230224050709.30014-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
It was incorrectly using an old priv->regs pointer, which was
initialized to zero. SPI resets won't happen on first call.
Signed-off-by: Jiajie Chen <c@jia.je>
Link: https://lore.kernel.org/r/20230227150938.211820-1-c@jia.je
Signed-off-by: Michal Simek <michal.simek@amd.com>
When using the fpga loads command, the driver is passing the AES encryption
key address is all cases. However, for the authenticated, but not encrypted
use case, there is no AES encryption key, and this value is 0.
When AES encryption is not used on the fpga bitstream, the pmufw assumes that
the AES key address is a bitstream size value like what is used by the
unsecure fpga load command.
To fix the problem, this patch checks to see if the AES key address is zero.
If the AES key address is zero, it means that AES is not being used on the
bitstream and the bitstream size should be passed instead. Thus, matching
the fpga load functionality.
Signed-off-by: Neal Frager <neal.frager@amd.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230214131959.40298-1-neal.frager@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
There are missing Kconfig dependencies in the code which is using
firmware interface.
The commit 71efd45a5f ("arm64: zynqmp: Change firmware dependency")
add option to also disable ZYNQMP_FIRMWARE. But not all Kconfig
dependencies were properly described and also sdhci and gem drivers
didn't protect the code properly.
So, add the missing ZYNQMP_FIRMWARE dependencies.
Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230201095553.11219-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
- support for fonts wider than 1 byte
- use named header for 8x16 font data
- support multiple fonts configuration
- move get_font_size() to truetype driver ops
- support font size configuration at runtime
- add 16x32 Terminus font from linux
- add 12x22 Sun font from linux
- add 12x22 console simple font test
-----BEGIN PGP SIGNATURE-----
iGwEABECACwWIQSC4hxrSoIUVfFO0kRM6ATMmsalXAUCZAdiLw4cYWd1c3RAZGVu
eC5kZQAKCRBM6ATMmsalXDtGAJ9ZjsnfneJpUjwYJWOw2ibnm9Dh2QCfVCAy+Bxa
YfqV8y7TbOuCQKTEY1s=
=FJhw
-----END PGP SIGNATURE-----
Merge tag 'next-20230307' of https://source.denx.de/u-boot/custodians/u-boot-video into next
- video console refactoring and optimization
- support for fonts wider than 1 byte
- use named header for 8x16 font data
- support multiple fonts configuration
- move get_font_size() to truetype driver ops
- support font size configuration at runtime
- add 16x32 Terminus font from linux
- add 12x22 Sun font from linux
- add 12x22 console simple font test
Modern mobile phones typically have high pixel density.
Bootmenu is hardly readable on those with 8x16 font.
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Modern mobile phones typically have high pixel density.
Bootmenu is hardly readable on those with 8x16 font.
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Allow font size configuration at runtime for console_simple.c
driver. This needed for unit testing different fonts.
Configuring is done by `font` command, also used for font
selection in true type console.
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Since multiple vidconsole drivers exists, vidconsole_get_font_size()
implementation cannot longer live in vidconsole_uclass.c file.
Move current vidconsole_get_font_size logic to truetype driver ops.
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This needed for unit testing different fonts.
Configured fonts are placed in an array of fonts.
First font is selected by default upon console probe.
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[agust: fixed build error when bmp logo disabled]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Devices with high ppi may benefit from wider fonts.
Current width implementation is limited by 1 byte, i.e. 8 bits.
New version iterates VIDEO_FONT_BYTE_WIDTH times, to process all
width bytes, thus allowing fonts wider than 1 byte.
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
- move common code to vidconsole_internal.h and console_core.c
- unite probe functions
- get rid of code duplications in switch across bpp values
- extract common pixel fill logic in two functions one per
horizontal and vertical filling
- rearrange statements in put_xy* methods in unified way
- replace types - uint*_t to u*
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
As the file spear_sdhci.c file is already removed, delete the associated
configuration CONFIG_MMC_SDHCI_SPEAR.
Fixes: c942fc925e ("mmc: spear: remove the entire spear_sdhci.c file")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
According to the PLL vendor, we should keep the PLL power on, so we
shouldn't toggle the power-down bit during PLL initialization.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
According to the PLL vendor, we should keep the PLL power on, so we
shouldn't toggle the power-down bit during PLL initialization.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
The fttmr010 timer driver was deleted by
commit 29fc6f2492 ("ARM: remove a320evb board support")
The original source file was: arch/arm/cpu/arm920t/a320/timer.c
Return the driver to the codebase in a DM compatible form.
A platform using fttmr010 will be submitted later.
This hardware is described in the datasheet [1], starting from page 348.
According to the datasheet, there is a Revision Register at offset 0x3C,
which is not present in 'struct fttmr010'. Add it and debug() print
revision in probe function.
[1]
https://bitbucket.org/Kasreyn/mkrom-uc7112lx/src/master/documents/FIC8120_DS_v1.2.pdf
Signed-off-by: Sergei Antonov <saproj@gmail.com>
- Partial merge of a series of mine to select some framework options
that shouldn't be prompted for (and remove some unused code related to
that), and a partial merge of a series from Simon to remove some dead
code and address various CONFIG_IS_ENABLED/IS_ENABLED issues in code.
Add a new SPL_PHY_ATHEROS to avoid a build error on am335x_evm with split
config.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
At present we enable the sandbox I2C driver for all builds. Add a separate
Kconfig option to control this, so that it can be disabled in TPL, where
it is not needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
At present we enable the sandbox RTC driver for all builds. Add a separate
Kconfig option to control this, so that it can be disabled in TPL, where
it is not needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 3 usages of this option to the non-SPL form, since there is
no SPL_PHY_FIXED defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 3 usages of this option to the non-SPL form, since there is
no SPL_MULTIPLEXER defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_DISPLAY_AER_FULL defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This is not used since time out of mind.
Drop the driver and Kconfig option.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Michael Trimarchi <michael@amarulasolutions.com>
There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
exclude IP0) have a wrong default SOF/ITP interval which is
calculated from the frame counter clock 24Mhz by default, but
in fact, the frame counter clock is 48Mhz, so we shall set the
accurate interval according to 48Mhz for those controllers.
Note:
The first controller no need set it, but if set it, shall change
tphy's pll at the same time.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Marek Vasut <marex@denx.de>
The T-PHY controller is designed to use use PLL integer mode, but
in fact use fractional mode for some ones on mt8195 by mistake,
this causes signal degradation (e.g. eye diagram test fail), fix
it by switching PLL to 26Mhz from default 48Mhz to improve signal
quality.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Prefer to make use of FIELD_PREP() macro to prepare bitfield value,
then no need local macros anymore.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Imply means you can turn off the option and expect things to work
- "it's a good idea to have X enabled" is when to use imply
- "you must have X for Y to work" is when to use select
Use "select" here.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Building sandbox_defconfig with CONFIG_SPL_TIMER=y results in an error
include/dm/platdata.h:63:33: error: static assertion failed:
"Cannot use U_BOOT_DRVINFO with of-platdata.
Please use devicetree instead"
Add a missing condition in the sandbox driver.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Currently, pinctrl drivers are getting probed during post-bind, however
that is being reverted, and on A37XX pinctrl driver is the one that
registers the GPIO driver during the probe.
So, if the pinctrl driver doesn't get probed GPIO-s won't get registered
and thus they cannot be used.
This is a problem on the Methode eDPU as it just uses SB pins as GPIO-s
and without them being registered networking won't work as it only has
one SFP slot and the TX disable GPIO is on the SB controller.
So, lets just add a flag only to A37XX driver to probe after binding
in order for the GPIO driver to always get registered.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a new Kconfig option CONFIG_MVEBU_SPL_BOOT_DEVICE_NAND which instruct
make to generate kwbimage with NAND header. This image is used for booting
from NAND flash (either SPI or parallel).
Support is very simple, SPL after finishes DDR training returns back to the
BootROM (via CONFIG_SPL_BOOTROM_SUPPORT option) and BootROM then loads and
executes U-Boot proper.
To generate correct kwbimage NAND header, it is required to set following
Kconfig options:
CONFIG_SYS_NAND_PAGE_SIZE
CONFIG_SYS_NAND_BLOCK_SIZE
CONFIG_MVEBU_SPL_NAND_BADBLK_LOCATION
They are used only by make / mkimage when generating final kwbimage.
CONFIG_MVEBU_SPL_NAND_BADBLK_LOCATION is a new mvebu specific Kconfig
option which is set into kwbimage NAND_BADBLK_LOCATION header field.
Signed-off-by: Pali Rohár <pali@kernel.org>
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEgWII69YpahbL5iK5gS8AYozs+qIFAmP9sq4ACgkQgS8AYozs
+qJ0tA//T46yeQ5H33yCxOTlNOwvtqfYWc4zQhJsTHkrXx9vdqW/Woz2GGxhADac
MVe1RyqHwWKymyNKCyi8nZIYdkpzaGutUhaCK4S8iddnL9A15oe3jxNtvrVfmvZw
jHPgJUrYdDvX0SoJy5xcRaxiO48+ja005ILw7H2zS+/vR7lQPJQJ1IuHStKCny6j
uYksHFcFK+qRscWjKGNdgcZLjQNpBIcigyGYPOxJ0swIDmZd84vSFoOG5p48QpAu
yo6VCnGgtaDKGOBPBICzyCw7J7a4zt3hM2mQ6xMI66IEBLpHwA999RSl1Gxtxhzz
3QG5Ore6E6hmkZk++jiA5VVhkX5ZpmoMDY2SiveCLyjknhKIwY5/lOmVn/kPAwHt
jAUbagf1ntrFnTum8OFtyg7skAmTckmZzaf4OuUhtrD3710dfdZ0dPuFxFDXRfTX
yLZaprwI+M8ziXbw1/Ao5iMx8ck5zGVn+mOBawYx/x/h5X76BxqqzPBExzQ+Qj6E
UgWKccPxVvbDENB2EZY05j3/JylGGU2Sxn2idu+UPXkfZRO/9CQKGiLmmhQ/aX4C
zAREx0/XSux/lkas9yXVjJXnvTCBcAbiu24MlTZDLdOQK+kGSIBY9yA+9fAxWtFG
33npVegUjMG+EPqpntVHPS/NuFOxuNu/X7kk2ievjsCPnLkVpts=
=6a0G
-----END PGP SIGNATURE-----
Merge tag 'tpm-next-28022023' of https://source.denx.de/u-boot/custodians/u-boot-tpm into next
TPM auto startup and testing:
Due to U-Boot's lazy binding we always relied on command line tools to
initialize the TPM subsystem and devices. One exception is the EFI
subsystem. When compiled with TCG2 measured boot support the TPM was
automatically initialized.
However that init was not complete. The TCG specs [0] (and specifically
§12.3 Self-test modes) describe how self-tests on the device should be
performed. This PR is adding an extra API function, that can be used to
initialize the TPM2.0 properly.
Simon added the equivalent for TPM1.2 and refactored the DM tests to
include the new funtion.
[0] https://trustedcomputinggroup.org/wp-content/uploads/TPM-Rev-2.0-Part-1-Architecture-01.07-2014-03-13.pdf
- mark reserved blocks from Ashok Reddy Soma
- backport BRCMNAND changes from Linux from Linus Walleij
- fix display of unknown raw ID from Patrice Chotard
- show reserved block in chip.erase from Michael Trimarchi
-----BEGIN PGP SIGNATURE-----
iQJYBAABCgBCFiEE6GOTDNYiFygVXvMmQBtB6IWRjvEFAmP83RIkHGRhcmlvLmJp
bmFjY2hpQGFtYXJ1bGFzb2x1dGlvbnMuY29tAAoJEEAbQeiFkY7xpp8P/1gykNwl
UvIjmhKu2pLDSJd9g75Ao4SDrkSYqVK1FT0RusxgB0YPfu1beWK9JPpfcabt+VHS
i/h4Qy40MJk3VpJ0mRH4OqPL2Ezl3RAuFp0P9mz5gVlLZGUKWRXRuNoh0ZAxrBcu
nYydUdh+p9Ov323969P2+7P8Ld/4Zb/dNsycRSsXXNI0FpyA7O5Prxrlk0aujtNa
0bONHEJ/wp68qqp4bucJjhMiLD5dZAJQxtzW/TZCYoJ+i2juWHgSZbA/4kDx9Mii
jV2pdHMkBcPBmF2HZujQxxorIxw+NXep0aydH/VxKfZxXzZU6PPO22wzKjbaZSYP
dkWL7Gik16T2RtU7QNqQq8UnAwzAIIaqFQo7UtG1vYfaPeB/TI5jNpQL3uQamMD9
4GwaU6jr6MjhIi/waoGsJLlUBBxmFlPVfSp95qY1UGUNtC9QsbvONmqvmH0dfhug
2vWYSVpXoSZG7DftxIIEg0Y2N+WZvODPyftsj3j/jp7e6ghBzvBeGtkIaKYYzSOx
dbEWsdKQOHFIhBBTan3MihVQUJFNkeWyRcO+DMGBuTZwMAifASg46mbLxBjysBXc
yccNNfDJUhHR/GGOJTZJlJ6av60OqCjPY9rGcUFfZUrT/Qmef2mQ/wylAf7ep47L
/bcvPoQv9xnowd9IztLyJJ0LFbhKONVTvDlz
=0HB0
-----END PGP SIGNATURE-----
Merge tag 'u-boot-nand-20230227' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash into next
Pull request for u-boot-nand-20230227
- mark reserved blocks from Ashok Reddy Soma
- backport BRCMNAND changes from Linux from Linus Walleij
- fix display of unknown raw ID from Patrice Chotard
- show reserved block in chip.erase from Michael Trimarchi
SDHCI driver may attempt to set 26MHz clock, but clk_rk3568
will return error in this case. Apparently, SDHCI silently ignores the
error and as a result eMMC initialization fails.
Add 25 MHz and 26 MHz clk rates for sdmmc and emmc on rk3568 to fix that.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add support for rk3066a, rk3188, rk322x and rk3288 compatible.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Refactor the driver to use driver data and ops to simplify handling
of SoCs that require a unique read op.
Move handling of the aligned bounce buffer to main read op in order to
keep the SoC unique read op simple.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add a simple debug command to dump the content of the otp.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add support for rk3588 compatible.
Adjust offset using driver data in main read op.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add support for rk3568 compatible.
Handle allocation of an aligned bounce buffer in main read op in order
to keep the SoC unique read op simple.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Refactor the driver to use driver data and ops to simplify handling
of SoCs that require a unique read op.
Use readl_poll_sleep_timeout instead of a custom poll loop, and add
validation of input parameter to main read op.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add ddr driver for rk3588 to get the ram capacity.
Co-developed-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add RK3588 pll set and get rate clock support.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add clock driver support for Rockchip RK3588 SoC.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Use the new devicetree property of gpio-ranges to determine the GPIO
bank ID. Preserve the "old" way of doing things too, so that boards
can be migrated and tested gradually (I only have a 3566 and 3326 to
test).
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
RK3568 has two USB 2.0 PHYs, and each PHY has two ports, the OTG port
of PHY0 support OTG mode with charging detection function, they are
similar to previous Rockchip SoCs.
However, there are three different designs for RK3568 USB 2.0 PHY.
1. RK3568 uses independent USB GRF module for each USB 2.0 PHY.
2. RK3568 accesses the registers of USB 2.0 PHY IP directly by APB.
3. The two ports of USB 2.0 PHY share one interrupt.
This patch only PHY1 with necessary attributes required to function
USBPHY1 on U-Boot.
Co-developed-by: Ren Jianing <jianing.ren@rock-chips.com>
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Co-developed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
New Rockchip devices have the usb phy nodes as standalone devices.
These nodes have register nodes with #address_cells = 2, but only
use 32 bit addresses.
Adjust the driver to check if the returned address is "0", and adjust
the index in that case.
Derived and adjusted the similar change from linux-next with below
commit <9c19c531dc98> ("phy: phy-rockchip-inno-usb2: support
#address_cells = 2")
Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The RK3288 TRM states that, for 8-bit DDR modes:
The CLKDIV register should always be programmed with a value
higher than zero (0); that is, a clock divider should always be
used for 8-bit DDR mode.
In Linux, the driver applies this logic for all SoCs using the driver
and does not distinguish RK3288, so presumably this requirement is the
same for all other Rockchip SoCs using this IP.
Add the necessary code to double the clock frequency when 8-bit DDR is
selected. The dw_mmc core already handles setting CLKDIV correctly
given the input clock and desired bus clock.
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
All the TPM drivers as well as out TCG TIS API for a TPM2.0 device
return -EBUSY if the device has already been opened. Adjust
the sandbox TPM do return the same error code.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
The "nand chip.erase" command always printed as bad blocks even in the
case of reserved blocks. Reserved blocks are used for storing bad block
tables. The patch displays "bbt reserved" when printing reserved blocks in
"nand chip.erase" command.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
In case ID is not found in manufacturer table, the raw ID is
printed using %*phN format which is not supported by lib/vsprintf.c.
The information displayed doesn't reflect the raw ID return by the
unknown spi-nand.
Use %02x format instead, as done in spi-nor-core.c.
For example, before this patch:
ERROR: spi-nand: spi_nand flash@0: unknown raw ID f74ec040
after
ERROR: spi-nand: spi_nand flash@0: unknown raw ID 00 c2 26 03
Fixes: 0a6d6bae03 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Acked-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Hamming ECC doesn't cover the OOB data, so reading or writing OOB shall
always be done without ECC enabled.
This is a problem when adding JFFS2 cleanmarkers to erased blocks. If JFFS2
clenmarkers are added to the OOB with ECC enabled, OOB bytes will be changed
from ff ff ff to 00 00 00, reporting incorrect ECC errors.
Fixes: 27c5b17cd1b1 ("mtd: nand: add NAND driver "library" for Broadcom STB NAND controller")
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20210224080210.23686-1-noltari@gmail.com
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Only v3.3-v5.0 have a different CS0 layout.
Controllers before v3.3 use the same layout for every CS.
Fixes: 27c5b17cd1b1 ("mtd: nand: add NAND driver "library" for Broadcom STB NAND controller")
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200522121524.4161539-3-noltari@gmail.com
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
These registers are also used on v3.3.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200522121524.4161539-2-noltari@gmail.com
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
The current code checks that the whole OOB area is erased.
This is a problem when JFFS2 cleanmarkers are added to the OOB, since it will
fail due to the usable OOB bytes not being 0xff.
Correct this by only checking that data and ECC bytes aren't 0xff.
Fixes: 02b88eea9f9c ("mtd: brcmnand: Add check for erased page bitflips")
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200512082451.771212-1-noltari@gmail.com
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
This change adds support for flash dma v0.0.
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
In brcmstb_nand_verify_erased_page(), the ECC chunk pointer calculation
while correcting erased page bitflips is wrong, fix it.
Fixes: 02b88eea9f9c ("mtd: brcmnand: Add check for erased page bitflips")
Signed-off-by: Claire Lin <claire.lin@broadcom.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
This change adds support for brcm NAND v7.3 controller. This controller
uses a newer version of flash_dma engine and change mostly implements
these differences.
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Refactored NAND ECC and CMD address configuration code to use helper
functions.
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reserved blocks are used for storing bad block tables. With "nand bad"
command, these reserved blocks are shown as bad blocks. This is leading
to confusion when compared with Linux bad blocks. Hence, display
"bbt reserved" when printing reserved blocks with "nand bad" command.
To acheive this, return 2 which represents reserved from nand_isbad_bbt()
instead of 1 in case of reserved blocks and catch it in cmd/nand.c.
"nand bad" command display's hexadecimal numbers, so add "0x" prefix.
Example log will show up as below.
ZynqMP> nand bad
Device 0 bad blocks:
0x00400000
0x16800000
0x16c00000
0x17000000
0x3d800000
0x3e400000
0xe8400000
0xff000000 (bbt reserved)
0xff400000 (bbt reserved)
0xff800000 (bbt reserved)
0xffc00000 (bbt reserved)
0x116800000
0x116c00000
0x1ff000000 (bbt reserved)
0x1ff400000 (bbt reserved)
0x1ff800000 (bbt reserved)
0x1ffc00000 (bbt reserved)
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-By: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
All Nvidia boards use the same manufacturer, vendor ID and product ID
for the gadgets. Make them the defaults to remove some boilerplate from
the defconfigs.
Inspired by commit e02687bda9 ("sunxi: provide default USB gadget
setup") which did the same for Allwinner boards.
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Original t20 slink could work with commands only
fully divisible by 8. This patch removes such
restriction, so commands of any bitlength now
can be passed and processed.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Default parent clock for the PWM on Tegra is a 32kHz clock and
is unable to support the requested PWM period.
Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by
updating the parent clock for the PWM to be the PLL_P.
This commit is equivalent to Linux kernel commit:
https://lore.kernel.org/all/20221010100046.6477-1-jonathanh@nvidia.com/
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # ASUS TF201 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Make sure the PHY subsystem is activated for the uniphier DWC3 glue
logic, as it depends on PHY implementation there.
Signed-off-by: Marek Vasut <marex@denx.de>
dwc3-uniphier depends on xhci-dwc3 framework, however, it is preferable
to use dwc3-generic.
This driver calls the exported dwc3-generic functions and redefine
the SoC-dependent operations to fit dwc3-generic.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Add USB3 PHY driver support to control clocks and resets needed to enable
PHY. The phy_ops->init() and exit() control PHY clocks and resets only,
and clocks and resets for the controller and the parent logic are enabled
in advance.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
The USB SS-PHY needs its own clock, however, some clocks don't have
clock gates. Define missing clock entries for the PHY as reference
clock.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Add reset control support in USB glue logic. This needs to control
the external clocks and resets for the logic before accessing the
glue logic.
The USB dm tree when using dwc3-generic is the following:
USB glue
+-- controller (need controller-reset)
+-- controller-reset (need syscon-reset)
+-- phy
The controller needs to deassert "controller-reset" in USB glue before
the controller registers are accessed. The glue needs to deassert
"syscon-reset" before the glue registers are accessed.
The glue itself doesn't have "syscon-reset", so the controller-reset
controls "syscon-reset" instead.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Add the size of regs property to the glue structure to correctly
specify the register region to map.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
In order to allow external SoC-dependent glue drivers to use dwc3-generic
functions, push the glue structures and export the functions to a header
file.
The exported structures and functions are:
- struct dwc3_glue_data
- struct dwc3_glue_ops
- dwc3_glue_bind()
- dwc3_glue_probe()
- dwc3_glue_remove()
The SoC-dependent glue drivers can only define their own wrapper driver
and specify these functions. The drivers can also add their own compatible
strings and configure functions.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Same as the reset cotnrol, should add a clock initialization in child DT
node, if the glue node doesn't have any clocks.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
The most of devicetree has the following USB node structure.
The controller node is placed as a child node of the glue node.
Current dwc3-generic driver works on this premise.
glue {
/* glue node */
usb {
/* controller node */
};
};
However, UniPhier original devicetree has the following USB node structure.
The controller node is separately placed from the glue node.
usb {
/* controller node */
};
glue {
/* glue node */
};
In dwc_glue_bind(), this patch provides .glue_get_ctrl_dev() callback to
get such a controller node and binds the driver related to the node.
If this callback isn't defined, dwc_glue_bind() looks for the controller
nodes from the child nodes, as before.
Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
There are currently four disparate placement possibilities of DWC3
reference clock phandle in SoC DTs:
- in top level glue node, with generic subnode without clock (ZynqMP)
- in top level generic node, with no subnode (i.MX8MQ)
- in generic subnode, with other clock in top level node (i.MX8MP)
- in both top level node and generic subnode (Rockchip)
Cover all the possibilities here by looking into both nodes, start
with the top level node as that seems to be used in majority of DTs
to reference the clock.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
As the "reset-gpios" property is optional, don't return the
error and just skip the gpio reset sequence.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
This patch fixes following warning for the riscv32 toolchain.
drivers/cache/cache-v5l2.c:122:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
122 | regs = (struct l2cache *)dev_read_addr(dev);
| ^
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Update the compatible string of L2 cache.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
The L2C configuration register has MAP field to indicate its version
is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver
compatible with both memory-mapped scheme.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
There is no need for RISCV_NDS_CACHE config to control cache switches.
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Add a CONFIG option to deal with this automatically, printing a warning
when U-Boot starts up. This can be useful if the device tree comes from
another project.
We will maintain this through the 2023.07 release, providing 6 months
for people to notice.
Signed-off-by: Simon Glass <sjg@chromium.org>
Version 4:
Acked-by: Michal Simek <michal.simek@amd.com>
Enable driver to fetch the optional parameter (fifo-depth) from device
tree. If the parameter is not found in the device tree, it will use
the default value declared in the driver.
Signed-off-by: Pei Yue Ho <peiyue.ho@starfivetech.com>
Reviewed-by: Wei Liang Lim <weiliang.lim@starfivetech.com>
Reviewed-by: Eng Lee Teh <englee.teh@starfivetech.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add i2c new register mode driver to support AST2600 i2c
new register mode. AST2600 i2c controller have legacy and
new register mode. The new register mode have global register
support 4 base clock for scl clock selection, and new clock
divider mode.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Printing the I2C controller base address in decimal notation
is not helpful.
Change it to hex notation, which is the standard format found
in the Reference Manual and devicetree.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
This contains various fixes and small features. I've included a reset patch as
well since it was in the same series as a clock patch.
-----BEGIN PGP SIGNATURE-----
iQGTBAABCgB9FiEEkGEdW86NSNID6GAoPuiP7LShEG4FAmPpRBJfFIAAAAAALgAo
aXNzdWVyLWZwckBub3RhdGlvbnMub3BlbnBncC5maWZ0aGhvcnNlbWFuLm5ldDkw
NjExRDVCQ0U4RDQ4RDIwM0U4NjAyODNFRTg4RkVDQjRBMTEwNkUACgkQPuiP7LSh
EG6fgggAo6vMZZw1RPCDiI25s2mGnnKXe1MZDruTipeVFUaBCJZDVKzF94oarKZK
BhQyzZ/0WkWH8BbEn/mOiW/M4MpZjif6cEnB/uLg8kqvIEz/NbOLLCkpAq6bccm5
0l9ycdhvXzwhLR+hsx8WlzatIE79TqR4hXc8kFfYXbJAITbWsqhh6g+0ILbYuajm
Uz1Hvjn1SGptgL7pfTb5NiiTjDrKv4Fr+F11KCqpgIwu81a8Sfv0kQ29W3qCDEj/
r3jov9PSf3g/MZmL+R0qVhcsPQeqf7/KdcDvn0Py++jqi3zfBialpFUQV3MLPqEP
82dPV5ObgjD6a5u6TPkG0roNpmpUVA==
=+n5i
-----END PGP SIGNATURE-----
Merge tag 'clk-2023.04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-clk
Clock changes for 2023.04-rc1
This contains various fixes and small features. I've included a reset patch as
well since it was in the same series as a clock patch.
- A fix for a long standing bug that has been exposed by commit
50128aeb0f ("cyclic: get rid of cyclic_init()") preventing 8xx boards
from booting since u-boot 2023.01
- A GPIO driver for powerpc 8xx chip
- Fixup for powerpc 8xx SPI driver
- A new powerpc 8xx board
- The two devices having that board.
This allows devm_reset_control_get(dev, NULL) to work and get the first
reset control, which is common in code ported from Linux.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20230122000252.53642-2-samuel@sholland.org
This allows devm_clock_get(dev, NULL) to work and get the first clock,
which is common in code ported from Linux.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20230122000252.53642-1-samuel@sholland.org
[backport from linux commit bedcf9d1dcf88ed38731f0ac9620e5a421e1e9d6]
Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the
name used in the RM is video_pll. So, let's rename "video_pll1" to
"video_pll" to be consistent with the RM and avoid misunderstandings.
No functional changes intended.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20221219113127.528282-3-dario.binacchi@amarulasolutions.com
[backport from linux commit a429c60baefd95ab43a2ce7f25d5b2d7a2e431df]
The IMX8MN platform does not have any video processing unit (VPU), and
indeed in the reference manual (document IMX8MNRM Rev 2, 07/2022) there
is no occurrence of its pll. From an analysis of the code and the RM
itself, I think vpu pll is used instead of m7 alternate pll, probably
for copy and paste of code taken from modules of similar architectures.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20221219113127.528282-2-dario.binacchi@amarulasolutions.com
Tracing is typically enabled by the time driver model starts up, so there
is no point in adding a 'notrace' to the timer-init function. However,
once the driver model timer is enabled, we do need to be able to access
the timer's private data when reading the timer, so add it to the core
function needed for that.
Update the function's documentation while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
When dropping the unused fotg210 gadget driver a leading 0 was
introduced to the next line, drop it.
Fixes: e9b4678bc7 ("usb: Drop unused fotg210 gadget")
Reported-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
This patch fixes the mpc8xx SPI driver:
- A stub callbacks for mode and speed,
- Use chip selects defined as GPIOs,
- Write proper value to disable relocation, other it fails on mpc885,
- Don't modify ports setup, ports can be different from one board to
another and are already set by board_early_init_r().
This patch was originally written by Charles Frey who's
email address is not valid anymore as he left the company.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: FRANJOU Stephane <stephane.franjou@csgroup.eu>
Ports A, C and D are 16 bits ports.
Ports B and E are 32 bits ports.
The "compatible" is used to determine each port type.
This patch was originally written by Charles Frey who's
email address is not valid anymore as he left the company.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: FRANJOU Stephane <stephane.franjou@csgroup.eu>
Register mii_bus with read and write callbacks to allow the 'mii'
command to work. Use a timeout of 10 ms to wait for the R/W
operations to complete.
Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
Replace 'phys_addr_t iobase' with 'struct ftmac100 *ftmac100' in
struct ftmac100_data. It allows to remove casting in a number of places.
Since priv->iobase is phys_addr_t, use phys_to_virt() to make
a pointer from it.
Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
So it will be named similarly to the related ftgmac100 driver.
The old name 'nds32_mac' is not referred to anywhere in U-Boot.
Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Bootmenu requires an input device with arrows and enter key.
A common smartphone luckily has power, volume up/down buttons,
which may be used for controlling bootmenu.
To use driver, add 'button-kbd' to stdin.
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Linux event code must be used in input devices, using buttons.
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
GPIO button driver requires direction functions to probe
button gpio. Those functions are blank, since pwrkey is not
really gpio, and don't support direction settings.
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Add support for Qualcomm I2C QUP driver which is inspired from
corresponding driver in Linux: drivers/i2c/busses/i2c-qup.c.
Currently this driver only support FIFO polling mode which is sufficient
to support devices like eeprom, rtc etc.
Co-developed-by: Mike Worsfold <mworsfold@impinj.com>
Signed-off-by: Mike Worsfold <mworsfold@impinj.com>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
The Qualcom ETHQOS hardware supports an RGMII macro which needs to be
configured according to following link speeds:
- SPEED_1000
- SPEED_100
- SPEED_10
So add a corresponding glue driver to configure RGMII macro.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
The GMAC controller on QCS404 SoC (support added by upcoming patch) fails
to work with maximum tx/rx_fifo_sz supported by the hardware (16K). So
allow platforms to override FIFO size using corresponding DT node
properties.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_ATMEL_PIO4 defined in Kconfig
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 3 usages of this option to the non-SPL form, since there is
no SPL_OF_BOARD defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
This converts 3 usages of this option to the non-SPL form, since there is
no SPL_FASTBOOT_FLASH_NAND defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
This converts 5 usages of this option to the non-SPL form, since there is
no SPL_FASTBOOT_FLASH_MMC defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_ARCH_VERSAL defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_DISPLAY_AER_BRIEF defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_ZYNQMP_FIRMWARE defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 4 usages of this option to the non-SPL form, since there is
no SPL_XEN_SERIAL defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_VIDEO_BPP32 defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_VIDEO_BPP16 defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_USB_MUSB_HOST defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_TPM_RNG defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_SUPPORT_EMMC_RPMB defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
This converts 12 usages of this option to the non-SPL form, since there is
no SPL_SANDBOX_CLK_CCF defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_SANDBOX defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_RENESAS_SDHI defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 6 usages of this option to the non-SPL form, since there is
no SPL_IMX_MODULE_FUSE defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_HW_WATCHDOG defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_FASTBOOT_MMC_USER_SUPPORT defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 3 usages of this option to the non-SPL form, since there is
no SPL_FASTBOOT_FLASH defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_DEBUG_UART_ZYNQ defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 7 usages of this option to the non-SPL form, since there is
no SPL_CMD_CLK defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_A003399_NOR_WORKAROUND defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_MMC_QUIRKS defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
This is not used and appears to be associated with the faraday board which
has been removed. Drop the driver and Kconfig options.
Signed-off-by: Simon Glass <sjg@chromium.org>
These are not used. Drop the drivers and Kconfig option. Also drop an
old declaration in the netdev.h header.
Signed-off-by: Simon Glass <sjg@chromium.org>
The SPL_TPL part is in the wrong place. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 71d4393f84 ("sysreset: Add Atmel/Microchip sysreset driver")
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
This is not used since this commit:
76386d6195 arm: Remove cm_t35 board
Drop the driver and Kconfig option.
Signed-off-by: Simon Glass <sjg@chromium.org>
These drivers are not used and have not been converted to driver model.
Drop them and references to the non-existent CONFIG options they use.
Signed-off-by: Simon Glass <sjg@chromium.org>
This driver is not used and has lain unconverted since:
fc47cf9d05 arm: exynos: i2c: Convert exynos boards to use DM_I2C
Drop it and the entire mfd directory, since there is nothing left.
Signed-off-by: Simon Glass <sjg@chromium.org>
This driver and bat_trats2 are not used. Drop them and the entire battery
directory, since there is nothing left.
Signed-off-by: Simon Glass <sjg@chromium.org>
This option does not exist, so the Makefile rule does nothing. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This is not used since this commit:
570c3dcfc1 arm: Remove spear600 boards and the rest of SPEAr support
Drop the driver and Kconfig option.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
This is not used since this commit:
8d1e3cb140 powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS support
Drop the driver and Kconfig option.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com>
This is not used since this commit:
7458f18e5c ppc: Remove MPC8313ERDB boards
Drop the driver and Kconfig option.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is not used since this commit:
3cf02f5ffa imx6: remove not longer supported aristainetos boards
Drop the driver and Kconfig option.
Signed-off-by: Simon Glass <sjg@chromium.org>
The KONA and KONA_GPIO options don't exist anymore, since this commit:
0f6807e77b arm: Remove bcm28155_ap board
Drop the dead code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a bootdev device for qfw so that it can be used with standard boot.
This simply checks for the correct method and then does the read. Most of
the other logic is handed in a new bootmeth driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present virtio tries to attach QEMU services to a bootdev device, which
cannot work. Add a check for this.
Also use bootdev_setup_sibling_blk() to create the bootdev device, since
it allows the correct name to be used and bootdev_get_sibling_blk() to
work as expected.
The bootdev is not created on sandbox since it does have a real virtio
device and it is not possible to read blocks.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: a60f7a3e35 ("bootstd: Add a virtio bootdev")
Reported-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Added tidss video driver support which enables display
on oldi panel using AM62x, it creates a simple pipeline
framebuffer==>vidl1==>ovr1==>vp1==>oldi_panel and
calculates clock rates for panel from panel node in
device tree.
To compile TIDSS when user sets CONFIG_VIDEO_TIDSS
add rule in Makefile. Include tidss folder location
in Kconfig.
TIDSS is ported from linux kernel version 5.10.145
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
This patch updates the necessary Kconfigs to make simple panel
driver independent of backlight driver and compiling backlight
related code in simple-panel driver conditionally to when user
has set CONFIG_BACKLIGHT.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
ofnode_decode_display_timing supports reading timing parameters from
subnode of display-timings node, for displays supporting multiple
resolution, in case if a display supports single resolution, it fails
reading directly from display-timings node, to support it
ofnode_decode_panel_timing is added.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The commit 82f7b869f5 ("video: Drop CONFIG_AM335X_LCD") removed not
only the LCD legacy implementation but also the code with driver model
support. The patch restores the code with driver model support.
Fixes: 82f7b869f5 ("video: Drop CONFIG_AM335X_LCD")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Prevent a NULL pointer dereference in the probe path by checking the
return valud of dev_read_addr_ptr() against NULL.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Remove the instances in which we have multiple blank lines.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
There were some cases in which the function parameters were not aligned
to the open paranthesis. Fix those instances.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Remove all the explicit casts from the void* returned by calloc.
With this we also improve a bit the length of those lines and there is
no need to split the assignment.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
The fsl-mc driver printed debug information which used the 0x prefix for
decimal values. This only confuses anyone looking through the log.
Because of this, just remove the prefix and use the "DPXY.<id>" notation
which is the standard one for the DPAA2 objects.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
The break statement is just after a goto statement, thus it will not get
executed. Just remove it.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
The cur_ptr variable is set to the start of the log buffer but then it's
not used. Just remove the assignment altogether.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Add a DSA driver for the MV88E6xxx compatible Ethernet switches.
Cc: Marek Behún <marek.behun@nic.cz>
Cc: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Add support for DM_MDIO by registering a UCLASS_MDIO driver and
attempting to use it. This is necessary if wanting to use a DSA
driver for example hanging off of the FEC MAC.
Care is taken to fallback to non DM_MDIO mii bus as several boards define
DM_MDIO without having the proper device-tree configuration necessary
such as an mdio subnode, a phy-mode prop, and either a valid phy-handle
prop or fixed-phy subnode which will cause dm_eth_phy_connect() to fail.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Remove the unnecessary xmit and recv functions.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Add timer support for T20/T30/T114/T124 and T210 based devices.
Driver is based on DM, has device tree support and can be
used on SPL and early boot stage.
Arm64 Tegra (apart T210) according to comment in tegra-common.h use
architected timer.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Co-developed-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
Enum clock_osc_freq was designed to use only with T20.
This patch remaps it to use additional frequencies, added in
T30+ SoC while maintaining backwards compatibility with T20.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20
Tested-by: Thierry Reding <treding@nvidia.com> # T30, T124, T210
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
The current set of U-Boot upstream R-Car Gen3 DTs all contain generic
"renesas,etheravb-rcar-gen3" compatible strings, drop the SoC specific
compatible string support from U-Boot to reduce size and duplication.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
R-Car V3U has a CPG different enough to not be a generic Gen3 CPG but
similar enough to reuse code. Introduce a new CPG library, factor out
the SD clock and RPC clock handling and hook them to the generic Gen3
CPG driver so we have an equal state.
Based on Linux commit [1] and [2] by Wolfram Sang
[1] 8bb67d87346a ("clk: renesas: rcar-gen3: Factor out CPG library")
[2] 6f21d145b90f ("clk: renesas: cpg-lib: Move RPC clock registration to
the library")
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek: - Add rcar_clk_* prefix to all functions
- Rebase on changes to
clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function
- Use u32_encode_bits/GENMASK bitfield ops
On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on
the other R-Car gen3 SoCs. Hence, new clock types are introduced
respectively.
Based on Linux commit 381081ffc294 ("clk: renesas: r8a77970: Add SD0H/SD0
clocks for SDHI") by Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek: - Fix missing ~ in GENMASK(a, b), use clrsetbits_le32 instead
- Do not modify r8a77970-cpg-mssr.c much, drop enum r8a77970_clk_types
which is now part of common clock types in rcar-gen3-cpg.h instead
The old SD handling code was huge and could not handle all the details
which showed up on R-Car Gen3 SoCs meanwhile. It is time to switch to
another design. Have SDnH a separate clock, use the existing divider
clocks and move the errata handling from the clock driver to the SDHI
driver where it belongs.
Based on Linux series by Wolfram Sang, commit bb6d3fa98a41 ("clk:
renesas: rcar-gen3: Switch to new SD clock handling") and commit
e5f7e81ee430a ("mmc: renesas_sdhi: Parse DT for SDnH")
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek: - Add rcar_clk_* prefix to all functions
- Fix missing ~ in GENMASK(a, b), use clrsetbits_le32 instead
- Use DIV_ROUND_CLOSEST, else if parent clock = 199999992 and
rate = 200000000, the divider would be 0 and table lookup
would fail.
- Turn rcar_clk_get_table_val into signed integer, so it can
return 0 as a valid value and negative values as errors.
- Make the code operate on correct clock and add comment
which explains the reasoning behind it.
- Rebase on changes to
clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function
