mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-24 21:54:01 +00:00
ARM: remove a320evb board support
This is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Po-Yu Chuang <ratbert@faraday-tech.com> Acked-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Masahiro Yamada
Tom Rini
parent
a2f39e830e
commit
29fc6f2492
14 changed files with 1 additions and 573 deletions
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@ -73,10 +73,6 @@ config TARGET_INTEGRATORCP_CM920T
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bool "Support integratorcp_cm920t"
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select CPU_ARM920T
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config TARGET_A320EVB
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bool "Support a320evb"
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select CPU_ARM920T
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config ARCH_AT91
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bool "Atmel AT91"
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@ -770,7 +766,6 @@ source "board/denx/m28evk/Kconfig"
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source "board/denx/m53evk/Kconfig"
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source "board/embest/mx6boards/Kconfig"
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source "board/esg/ima3-mx53/Kconfig"
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source "board/faraday/a320evb/Kconfig"
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source "board/freescale/ls2085a/Kconfig"
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source "board/freescale/ls1021aqds/Kconfig"
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source "board/freescale/ls1021atwr/Kconfig"
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@ -10,7 +10,6 @@ extra-y = start.o
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obj-y += cpu.o
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obj-$(CONFIG_USE_IRQ) += interrupts.o
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obj-$(if $(filter a320,$(SOC)),y) += a320/
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obj-$(CONFIG_EP93XX) += ep93xx/
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obj-$(CONFIG_IMX) += imx/
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obj-$(CONFIG_S3C24X0) += s3c24x0/
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@ -1,9 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += reset.o
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obj-y += timer.o
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@ -1,10 +0,0 @@
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/*
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* (C) Copyright 2009 Faraday Technology
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* Po-Yu Chuang <ratbert@faraday-tech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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.global reset_cpu
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reset_cpu:
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b reset_cpu
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@ -1,118 +0,0 @@
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/*
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* (C) Copyright 2009 Faraday Technology
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* Po-Yu Chuang <ratbert@faraday-tech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <div64.h>
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#include <asm/io.h>
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#include <faraday/ftpmu010.h>
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#include <faraday/fttmr010.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define TIMER_CLOCK 32768
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#define TIMER_LOAD_VAL 0xffffffff
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static inline unsigned long long tick_to_time(unsigned long long tick)
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{
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tick *= CONFIG_SYS_HZ;
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do_div(tick, gd->arch.timer_rate_hz);
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return tick;
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}
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static inline unsigned long long usec_to_tick(unsigned long long usec)
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{
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usec *= gd->arch.timer_rate_hz;
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do_div(usec, 1000000);
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return usec;
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}
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int timer_init(void)
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{
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struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
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unsigned int cr;
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debug("%s()\n", __func__);
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/* disable timers */
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writel(0, &tmr->cr);
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/* use 32768Hz oscillator for RTC, WDT, TIMER */
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ftpmu010_32768osc_enable();
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/* setup timer */
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writel(TIMER_LOAD_VAL, &tmr->timer3_load);
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writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
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writel(0, &tmr->timer3_match1);
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writel(0, &tmr->timer3_match2);
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/* we don't want timer to issue interrupts */
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writel(FTTMR010_TM3_MATCH1 |
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FTTMR010_TM3_MATCH2 |
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FTTMR010_TM3_OVERFLOW,
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&tmr->interrupt_mask);
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cr = readl(&tmr->cr);
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cr |= FTTMR010_TM3_CLOCK; /* use external clock */
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cr |= FTTMR010_TM3_ENABLE;
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writel(cr, &tmr->cr);
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gd->arch.timer_rate_hz = TIMER_CLOCK;
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gd->arch.tbu = gd->arch.tbl = 0;
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return 0;
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}
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/*
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* Get the current 64 bit timer tick count
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*/
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unsigned long long get_ticks(void)
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{
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struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
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ulong now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter);
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/* increment tbu if tbl has rolled over */
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if (now < gd->arch.tbl)
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gd->arch.tbu++;
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gd->arch.tbl = now;
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return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
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}
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void __udelay(unsigned long usec)
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{
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unsigned long long start;
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ulong tmo;
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start = get_ticks(); /* get current timestamp */
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tmo = usec_to_tick(usec); /* convert usecs to ticks */
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while ((get_ticks() - start) < tmo)
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; /* loop till time has passed */
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}
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/*
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* get_timer(base) can be used to check for timeouts or
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* to measure elasped time relative to an event:
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*
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* ulong start_time = get_timer(0) sets start_time to the current
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* time value.
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* get_timer(start_time) returns the time elapsed since then.
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*
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* The time is used in CONFIG_SYS_HZ units!
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*/
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ulong get_timer(ulong base)
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{
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return tick_to_time(get_ticks()) - base;
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}
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/*
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* Return the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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return gd->arch.timer_rate_hz;
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}
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@ -1,22 +0,0 @@
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/*
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* (C) Copyright 2009 Faraday Technology
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* Po-Yu Chuang <ratbert@faraday-tech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __A320_H
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#define __A320_H
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/*
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* Hardware register bases
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*/
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#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller */
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#define CONFIG_DEBUG_LED 0x902ffffc /* Debug LED */
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#define CONFIG_FTSDMC020_BASE 0x90300000 /* SDRAM Controller */
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#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */
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#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */
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#define CONFIG_FTTMR010_BASE 0x98400000 /* Timer */
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#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock*/
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#endif /* __A320_H */
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@ -1,15 +0,0 @@
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if TARGET_A320EVB
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config SYS_BOARD
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default "a320evb"
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config SYS_VENDOR
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default "faraday"
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config SYS_SOC
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default "a320"
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config SYS_CONFIG_NAME
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default "a320evb"
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endif
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@ -1,6 +0,0 @@
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A320EVB BOARD
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M: Po-Yu Chuang <ratbert@faraday-tech.com>
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S: Maintained
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F: board/faraday/a320evb/
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F: include/configs/a320evb.h
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F: configs/a320evb_defconfig
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@ -1,9 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := a320evb.o
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obj-y += lowlevel_init.o
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@ -1,59 +0,0 @@
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/*
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* (C) Copyright 2009 Faraday Technology
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* Po-Yu Chuang <ratbert@faraday-tech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <faraday/ftsmc020.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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ftsmc020_init(); /* initialize Flash */
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return 0;
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}
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int dram_init(void)
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{
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unsigned long sdram_base = PHYS_SDRAM_1;
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unsigned long expected_size = PHYS_SDRAM_1_SIZE;
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unsigned long actual_size;
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actual_size = get_ram_size((void *)sdram_base, expected_size);
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gd->ram_size = actual_size;
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if (expected_size != actual_size)
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printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
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actual_size >> 20, expected_size >> 20);
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return 0;
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}
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int board_eth_init(bd_t *bd)
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{
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return ftmac100_initialize(bd);
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}
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ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
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{
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if (banknum == 0) { /* non-CFI boot flash */
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info->portwidth = FLASH_CFI_8BIT;
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info->chipwidth = FLASH_CFI_BY8;
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info->interface = FLASH_CFI_X8;
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return 1;
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} else
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return 0;
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}
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@ -1,106 +0,0 @@
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/*
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* (C) Copyright 2009 Faraday Technology
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* Po-Yu Chuang <ratbert@faraday-tech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/macro.h>
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#include <faraday/ftsdmc020.h>
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/*
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* parameters for the SDRAM controller
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*/
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#define TP0_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP0)
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#define TP1_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP1)
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#define CR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_CR)
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#define B0_BSR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_BANK0_BSR)
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#define ACR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_ACR)
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#define TP0_D CONFIG_SYS_FTSDMC020_TP0
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#define TP1_D CONFIG_SYS_FTSDMC020_TP1
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#define CR_D1 FTSDMC020_CR_IPREC
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#define CR_D2 FTSDMC020_CR_ISMR
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#define CR_D3 FTSDMC020_CR_IREF
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#define B0_BSR_D (CONFIG_SYS_FTSDMC020_BANK0_BSR | \
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FTSDMC020_BANK_BASE(PHYS_SDRAM_1))
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#define ACR_D FTSDMC020_ACR_TOC(0x18)
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/*
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* numeric 7 segment display
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*/
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.macro led, num
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write32 CONFIG_DEBUG_LED, \num
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.endm
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/*
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* Waiting for SDRAM to set up
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*/
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.macro wait_sdram
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ldr r0, =CONFIG_FTSDMC020_BASE
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1:
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ldr r1, [r0, #FTSDMC020_OFFSET_CR]
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cmp r1, #0
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bne 1b
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.endm
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.globl lowlevel_init
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lowlevel_init:
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mov r11, lr
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led 0x0
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bl init_sdmc
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led 0x1
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/* everything is fine now */
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mov lr, r11
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mov pc, lr
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/*
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* memory initialization
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*/
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init_sdmc:
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led 0x10
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/* set SDRAM register */
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write32 TP0_A, TP0_D
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led 0x11
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write32 TP1_A, TP1_D
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led 0x12
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/* set to precharge */
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write32 CR_A, CR_D1
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led 0x13
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wait_sdram
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led 0x14
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/* set mode register */
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write32 CR_A, CR_D2
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led 0x15
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wait_sdram
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led 0x16
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/* set to refresh */
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write32 CR_A, CR_D3
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led 0x17
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wait_sdram
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led 0x18
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write32 B0_BSR_A, B0_BSR_D
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led 0x19
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write32 ACR_A, ACR_D
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led 0x1a
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mov pc, lr
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@ -1,2 +0,0 @@
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CONFIG_ARM=y
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CONFIG_TARGET_A320EVB=y
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@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
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Board Arch CPU Commit Removed Last known maintainer/contact
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=================================================================================================
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a320evb arm arm920t - - Po-Yu Chuang <ratbert@faraday-tech.com>
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cm4008 arm arm920t - - Greg Ungerer <greg.ungerer@opengear.com>
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cm41xx arm arm920t - -
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dkb arm arm926ejs - - Lei Wen <leiwen@marvell.com>
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@ -1,211 +0,0 @@
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/*
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* (C) Copyright 2009 Faraday Technology
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* Po-Yu Chuang <ratbert@faraday-tech.com>
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*
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* Configuation settings for the Faraday A320 board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/a320.h>
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/*
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* mach-type definition
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*/
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#define MACH_TYPE_FARADAY 758
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#define CONFIG_MACH_TYPE MACH_TYPE_FARADAY
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/*
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* Linux kernel tagged list
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*/
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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/*
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* CPU and Board Configuration Options
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*/
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#undef CONFIG_SKIP_LOWLEVEL_INIT
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/*
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* Power Management Unit
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*/
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#define CONFIG_FTPMU010_POWER
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/*
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* Timer
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*/
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/*
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* Real Time Clock
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*/
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#define CONFIG_RTC_FTRTC010
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/*
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* Serial console configuration
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*/
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/* FTUART is a high speed NS 16C550A compatible UART */
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#define CONFIG_BAUDRATE 38400
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_COM1 0x98200000
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#define CONFIG_SYS_NS16550_REG_SIZE -4
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#define CONFIG_SYS_NS16550_CLK 18432000
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/*
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* Ethernet
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*/
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#define CONFIG_FTMAC100
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#define CONFIG_BOOTDELAY 3
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_PING
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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/* max number of command args */
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#define CONFIG_SYS_MAXARGS 16
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
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/*
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* SDRAM controller configuration
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*/
|
||||
#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \
|
||||
FTSDMC020_TP0_TRP(1) | \
|
||||
FTSDMC020_TP0_TRCD(1) | \
|
||||
FTSDMC020_TP0_TRF(3) | \
|
||||
FTSDMC020_TP0_TWR(1) | \
|
||||
FTSDMC020_TP0_TCL(2))
|
||||
|
||||
#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \
|
||||
FTSDMC020_TP1_INI_REFT(8) | \
|
||||
FTSDMC020_TP1_REF_INTV(0x180))
|
||||
|
||||
#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \
|
||||
FTSDMC020_BANK_DDW_X16 | \
|
||||
FTSDMC020_BANK_DSZ_256M | \
|
||||
FTSDMC020_BANK_MBW_32 | \
|
||||
FTSDMC020_BANK_SIZE_64M)
|
||||
|
||||
/*
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
|
||||
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
/*
|
||||
* Load address and memory test area should agree with
|
||||
* board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
|
||||
*/
|
||||
#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x2000000)
|
||||
|
||||
/* memtest works on 63 MB in DRAM */
|
||||
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
|
||||
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x3F00000)
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0
|
||||
|
||||
/*
|
||||
* Static memory controller configuration
|
||||
*/
|
||||
|
||||
#define CONFIG_FTSMC020
|
||||
#include <faraday/ftsmc020.h>
|
||||
|
||||
#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
|
||||
FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
|
||||
FTSMC020_BANK_SIZE_1M | \
|
||||
FTSMC020_BANK_MBW_8)
|
||||
|
||||
#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \
|
||||
FTSMC020_TPR_AST(3) | \
|
||||
FTSMC020_TPR_CTW(3) | \
|
||||
FTSMC020_TPR_ATI(0xf) | \
|
||||
FTSMC020_TPR_AT2(3) | \
|
||||
FTSMC020_TPR_WTC(3) | \
|
||||
FTSMC020_TPR_AHT(3) | \
|
||||
FTSMC020_TPR_TRNA(0xf))
|
||||
|
||||
#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \
|
||||
FTSMC020_BANK_BASE(PHYS_FLASH_2) | \
|
||||
FTSMC020_BANK_SIZE_32M | \
|
||||
FTSMC020_BANK_MBW_32)
|
||||
|
||||
#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \
|
||||
FTSMC020_TPR_CTW(3) | \
|
||||
FTSMC020_TPR_ATI(0xf) | \
|
||||
FTSMC020_TPR_AT2(3) | \
|
||||
FTSMC020_TPR_WTC(3) | \
|
||||
FTSMC020_TPR_AHT(3) | \
|
||||
FTSMC020_TPR_TRNA(0xf))
|
||||
|
||||
#define CONFIG_SYS_FTSMC020_CONFIGS { \
|
||||
{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
|
||||
{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
|
||||
}
|
||||
|
||||
/*
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
|
||||
/* use CFI framework */
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
|
||||
/* support JEDEC */
|
||||
#define CONFIG_FLASH_CFI_LEGACY
|
||||
#define CONFIG_SYS_FLASH_LEGACY_512Kx8
|
||||
|
||||
#define PHYS_FLASH_1 0x00000000
|
||||
#define PHYS_FLASH_2 0x00400000
|
||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, }
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
|
||||
|
||||
/* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2
|
||||
|
||||
/* max number of sectors on one chip */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512
|
||||
|
||||
#undef CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
|
||||
/* environments */
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000)
|
||||
#define CONFIG_ENV_SIZE 0x20000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in a new issue