mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 23:47:24 +00:00
drivers: phy: add naneng combphy for rk3568
RK3568 has three combo phys, and PCIe/USB3/SATA/QSGMII controllers
share one pipe interface for each combo phy, here is the diagram
of the complex connection.
+----------------+
| | +------+
| USB3 OTG CTRL0 |---->| |
| | | | +------------+
+----------------+ | PIPE | | |
| MUX |---->| Combo PHY0 |
+----------------+ | | | |
| | | | +------------+
| SATA CTRL0 |---->| |
| | +------+
+----------------+
+----------------+
| | +------+
| USB3 HOST CTRL1|---->| |
| | | | +------------+
+----------------+ | PIPE | | |
| MUX |---->| Combo PHY1 |
+----------------+ | | | |
| |---->| | +------------+
| SATA CTRL1 | -->| |
| | | +------+
+----------------+ |
|
+----------------+ |
| | | +------+
| QSGMII CTRL |---->| |
| | | | +------------+
+----------------+ | PIPE | | |
| MUX |---->| Combo PHY2 |
+----------------+ | | | |
| |---->| | +------------+
| SATA CTRL2 | -->| |
| | | +------+
+----------------+ |
|
+----------------+ |
| | |
| PCIe2 1-Lane |---
| |
+----------------+
Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Co-developed-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Jagan Teki
Kever Yang
parent
3da15f0b49
commit
82220526ac
3 changed files with 449 additions and 0 deletions
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@ -11,6 +11,13 @@ config PHY_ROCKCHIP_INNO_USB2
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help
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Support for Rockchip USB2.0 PHY with Innosilicon IP block.
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config PHY_ROCKCHIP_NANENG_COMBOPHY
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bool "Support Rockchip NANENG combo PHY Driver"
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depends on ARCH_ROCKCHIP
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select PHY
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help
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Enable this to support the Rockchip NANENG combo PHY.
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config PHY_ROCKCHIP_PCIE
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bool "Rockchip PCIe PHY Driver"
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depends on ARCH_ROCKCHIP
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@ -4,6 +4,7 @@
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#
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obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
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obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY) += phy-rockchip-naneng-combphy.o
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obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
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obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o
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obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
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441
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
Normal file
441
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
Normal file
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@ -0,0 +1,441 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Rockchip USB3.0/PCIe Gen2/SATA/SGMII combphy driver
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*
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* Copyright (C) 2021 Rockchip Electronics Co., Ltd.
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/lists.h>
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#include <dt-bindings/phy/phy.h>
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#include <generic-phy.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/clock.h>
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#include <regmap.h>
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#include <reset-uclass.h>
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#include <dm/device_compat.h>
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#define BIT_WRITEABLE_SHIFT 16
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struct rockchip_combphy_priv;
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struct combphy_reg {
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u16 offset;
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u16 bitend;
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u16 bitstart;
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u16 disable;
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u16 enable;
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};
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struct rockchip_combphy_grfcfg {
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struct combphy_reg pcie_mode_set;
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struct combphy_reg usb_mode_set;
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struct combphy_reg sgmii_mode_set;
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struct combphy_reg qsgmii_mode_set;
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struct combphy_reg pipe_rxterm_set;
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struct combphy_reg pipe_txelec_set;
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struct combphy_reg pipe_txcomp_set;
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struct combphy_reg pipe_clk_25m;
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struct combphy_reg pipe_clk_100m;
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struct combphy_reg pipe_phymode_sel;
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struct combphy_reg pipe_rate_sel;
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struct combphy_reg pipe_rxterm_sel;
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struct combphy_reg pipe_txelec_sel;
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struct combphy_reg pipe_txcomp_sel;
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struct combphy_reg pipe_clk_ext;
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struct combphy_reg pipe_sel_usb;
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struct combphy_reg pipe_sel_qsgmii;
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struct combphy_reg pipe_phy_status;
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struct combphy_reg con0_for_pcie;
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struct combphy_reg con1_for_pcie;
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struct combphy_reg con2_for_pcie;
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struct combphy_reg con3_for_pcie;
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struct combphy_reg con0_for_sata;
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struct combphy_reg con1_for_sata;
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struct combphy_reg con2_for_sata;
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struct combphy_reg con3_for_sata;
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struct combphy_reg pipe_con0_for_sata;
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struct combphy_reg pipe_sgmii_mac_sel;
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struct combphy_reg pipe_xpcs_phy_ready;
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struct combphy_reg u3otg0_port_en;
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struct combphy_reg u3otg1_port_en;
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};
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struct rockchip_combphy_cfg {
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const struct rockchip_combphy_grfcfg *grfcfg;
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int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
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};
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struct rockchip_combphy_priv {
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u32 mode;
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void __iomem *mmio;
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struct udevice *dev;
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struct regmap *pipe_grf;
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struct regmap *phy_grf;
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struct phy *phy;
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struct reset_ctl phy_rst;
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struct clk ref_clk;
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const struct rockchip_combphy_cfg *cfg;
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};
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static int param_write(struct regmap *base,
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const struct combphy_reg *reg, bool en)
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{
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u32 val, mask, tmp;
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tmp = en ? reg->enable : reg->disable;
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mask = GENMASK(reg->bitend, reg->bitstart);
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val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
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return regmap_write(base, reg->offset, val);
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}
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static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv)
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{
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int ret = 0;
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if (priv->cfg->combphy_cfg) {
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ret = priv->cfg->combphy_cfg(priv);
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if (ret) {
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dev_err(priv->dev, "failed to init phy for pcie\n");
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return ret;
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}
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}
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return ret;
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}
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static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv)
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{
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int ret = 0;
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if (priv->cfg->combphy_cfg) {
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ret = priv->cfg->combphy_cfg(priv);
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if (ret) {
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dev_err(priv->dev, "failed to init phy for usb3\n");
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return ret;
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}
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}
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return ret;
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}
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static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv)
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{
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int ret = 0;
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if (priv->cfg->combphy_cfg) {
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ret = priv->cfg->combphy_cfg(priv);
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if (ret) {
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dev_err(priv->dev, "failed to init phy for sata\n");
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return ret;
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}
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}
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return ret;
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}
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static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv)
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{
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int ret = 0;
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if (priv->cfg->combphy_cfg) {
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ret = priv->cfg->combphy_cfg(priv);
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if (ret) {
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dev_err(priv->dev, "failed to init phy for sgmii\n");
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return ret;
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}
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}
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return ret;
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}
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static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv)
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{
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switch (priv->mode) {
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case PHY_TYPE_PCIE:
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rockchip_combphy_pcie_init(priv);
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break;
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case PHY_TYPE_USB3:
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rockchip_combphy_usb3_init(priv);
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break;
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case PHY_TYPE_SATA:
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rockchip_combphy_sata_init(priv);
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break;
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case PHY_TYPE_SGMII:
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case PHY_TYPE_QSGMII:
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return rockchip_combphy_sgmii_init(priv);
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default:
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dev_err(priv->dev, "incompatible PHY type\n");
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return -EINVAL;
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}
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return 0;
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}
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static int rockchip_combphy_init(struct phy *phy)
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{
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struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev);
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int ret;
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ret = clk_enable(&priv->ref_clk);
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if (ret < 0 && ret != -ENOSYS)
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return ret;
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ret = rockchip_combphy_set_mode(priv);
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if (ret)
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goto err_clk;
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reset_deassert(&priv->phy_rst);
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return 0;
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err_clk:
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clk_disable(&priv->ref_clk);
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return ret;
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}
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static int rockchip_combphy_exit(struct phy *phy)
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{
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struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev);
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clk_disable(&priv->ref_clk);
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reset_assert(&priv->phy_rst);
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return 0;
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}
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static int rockchip_combphy_xlate(struct phy *phy, struct ofnode_phandle_args *args)
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{
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struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev);
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if (args->args_count != 1) {
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pr_err("invalid number of arguments\n");
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return -EINVAL;
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}
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priv->mode = args->args[0];
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return 0;
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}
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static const struct phy_ops rochchip_combphy_ops = {
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.init = rockchip_combphy_init,
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.exit = rockchip_combphy_exit,
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.of_xlate = rockchip_combphy_xlate,
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};
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static int rockchip_combphy_parse_dt(struct udevice *dev,
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struct rockchip_combphy_priv *priv)
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{
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struct udevice *syscon;
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int ret;
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ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-grf", &syscon);
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if (ret) {
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dev_err(dev, "failed to find peri_ctrl pipe-grf regmap");
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return ret;
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}
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priv->pipe_grf = syscon_get_regmap(syscon);
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ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-phy-grf", &syscon);
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if (ret) {
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dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n");
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return ret;
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}
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priv->phy_grf = syscon_get_regmap(syscon);
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ret = clk_get_by_index(dev, 0, &priv->ref_clk);
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if (ret) {
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dev_err(dev, "failed to find ref clock\n");
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return PTR_ERR(&priv->ref_clk);
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}
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ret = reset_get_by_index(dev, 0, &priv->phy_rst);
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if (ret) {
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dev_err(dev, "no phy reset control specified\n");
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return ret;
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}
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return 0;
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}
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static int rockchip_combphy_probe(struct udevice *udev)
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{
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struct rockchip_combphy_priv *priv = dev_get_priv(udev);
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const struct rockchip_combphy_cfg *phy_cfg;
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priv->mmio = (void __iomem *)dev_read_addr(udev);
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if (IS_ERR(priv->mmio))
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return PTR_ERR(priv->mmio);
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phy_cfg = (const struct rockchip_combphy_cfg *)dev_get_driver_data(udev);
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if (!phy_cfg) {
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dev_err(udev, "No OF match data provided\n");
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return -EINVAL;
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}
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priv->dev = udev;
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priv->mode = PHY_TYPE_SATA;
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priv->cfg = phy_cfg;
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return rockchip_combphy_parse_dt(udev, priv);
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}
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static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
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{
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const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
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u32 val;
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switch (priv->mode) {
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case PHY_TYPE_PCIE:
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/* Set SSC downward spread spectrum */
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val = readl(priv->mmio + (0x1f << 2));
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val &= ~GENMASK(5, 4);
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val |= 0x01 << 4;
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writel(val, priv->mmio + 0x7c);
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param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
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param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
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param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
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param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
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break;
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case PHY_TYPE_USB3:
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/* Set SSC downward spread spectrum */
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val = readl(priv->mmio + (0x1f << 2));
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val &= ~GENMASK(5, 4);
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val |= 0x01 << 4;
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writel(val, priv->mmio + 0x7c);
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/* Enable adaptive CTLE for USB3.0 Rx */
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val = readl(priv->mmio + (0x0e << 2));
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val &= ~GENMASK(0, 0);
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val |= 0x01;
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writel(val, priv->mmio + (0x0e << 2));
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/* Set PLL KVCO fine tuning signals */
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val = readl(priv->mmio + (0x20 << 2));
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val &= ~(0x7 << 2);
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val |= 0x2 << 2;
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writel(val, priv->mmio + (0x20 << 2));
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/* Set PLL LPF R1 to su_trim[10:7]=1001 */
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writel(0x4, priv->mmio + (0xb << 2));
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/* Set PLL input clock divider 1/2 */
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val = readl(priv->mmio + (0x5 << 2));
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val &= ~(0x3 << 6);
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val |= 0x1 << 6;
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writel(val, priv->mmio + (0x5 << 2));
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/* Set PLL loop divider */
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writel(0x32, priv->mmio + (0x11 << 2));
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/* Set PLL KVCO to min and set PLL charge pump current to max */
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writel(0xf0, priv->mmio + (0xa << 2));
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param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
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param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
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param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
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param_write(priv->phy_grf, &cfg->usb_mode_set, true);
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break;
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case PHY_TYPE_SATA:
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writel(0x41, priv->mmio + 0x38);
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writel(0x8F, priv->mmio + 0x18);
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param_write(priv->phy_grf, &cfg->con0_for_sata, true);
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param_write(priv->phy_grf, &cfg->con1_for_sata, true);
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param_write(priv->phy_grf, &cfg->con2_for_sata, true);
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param_write(priv->phy_grf, &cfg->con3_for_sata, true);
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param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
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break;
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case PHY_TYPE_SGMII:
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param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
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param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
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param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
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param_write(priv->phy_grf, &cfg->sgmii_mode_set, true);
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break;
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case PHY_TYPE_QSGMII:
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param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
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param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
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param_write(priv->phy_grf, &cfg->pipe_rate_sel, true);
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param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
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param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true);
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break;
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default:
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pr_err("%s, phy-type %d\n", __func__, priv->mode);
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return -EINVAL;
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}
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/* The default ref clock is 25Mhz */
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param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
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if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) {
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val = readl(priv->mmio + (0x7 << 2));
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val |= BIT(4);
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writel(val, priv->mmio + (0x7 << 2));
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}
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return 0;
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}
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static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
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/* pipe-phy-grf */
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.pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
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.usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
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.sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 },
|
||||
.qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 },
|
||||
.pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
|
||||
.pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
|
||||
.pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
|
||||
.pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
|
||||
.pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
|
||||
.pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
|
||||
.pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
|
||||
.pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
|
||||
.pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
|
||||
.pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
|
||||
.pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
|
||||
.pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
|
||||
.pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 },
|
||||
.pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
|
||||
.con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
|
||||
.con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
|
||||
.con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
|
||||
.con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
|
||||
.con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 },
|
||||
.con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 },
|
||||
.con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 },
|
||||
.con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 },
|
||||
/* pipe-grf */
|
||||
.pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 },
|
||||
.pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 },
|
||||
.pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 },
|
||||
.u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 },
|
||||
.u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 },
|
||||
};
|
||||
|
||||
static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
|
||||
.grfcfg = &rk3568_combphy_grfcfgs,
|
||||
.combphy_cfg = rk3568_combphy_cfg,
|
||||
};
|
||||
|
||||
static const struct udevice_id rockchip_combphy_ids[] = {
|
||||
{
|
||||
.compatible = "rockchip,rk3568-naneng-combphy",
|
||||
.data = (ulong)&rk3568_combphy_cfgs
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_naneng_combphy) = {
|
||||
.name = "naneng-combphy",
|
||||
.id = UCLASS_PHY,
|
||||
.of_match = rockchip_combphy_ids,
|
||||
.ops = &rochchip_combphy_ops,
|
||||
.probe = rockchip_combphy_probe,
|
||||
.priv_auto = sizeof(struct rockchip_combphy_priv),
|
||||
};
|
||||
Loading…
Reference in a new issue