mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
Prepare v2023.04-rc3
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This commit is contained in:
commit
5b197eee33
842 changed files with 3638 additions and 2667 deletions
|
@ -1298,6 +1298,7 @@ S: Maintained
|
|||
T: git https://source.denx.de/u-boot/custodians/u-boot-riscv.git
|
||||
F: arch/riscv/
|
||||
F: cmd/riscv/
|
||||
F: doc/arch/riscv.rst
|
||||
F: doc/usage/sbi.rst
|
||||
F: drivers/sysreset/sysreset_sbi.c
|
||||
F: drivers/timer/andes_plmt_timer.c
|
||||
|
|
3
Makefile
3
Makefile
|
@ -3,7 +3,7 @@
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|||
VERSION = 2023
|
||||
PATCHLEVEL = 04
|
||||
SUBLEVEL =
|
||||
EXTRAVERSION = -rc2
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||||
EXTRAVERSION = -rc3
|
||||
NAME =
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
@ -806,6 +806,7 @@ KBUILD_CPPFLAGS += $(KCPPFLAGS)
|
|||
KBUILD_AFLAGS += $(KAFLAGS)
|
||||
KBUILD_CFLAGS += $(KCFLAGS)
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||||
|
||||
KBUILD_LDFLAGS += -z noexecstack
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||||
KBUILD_LDFLAGS += $(call ld-option,--no-warn-rwx-segments)
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||||
|
||||
KBUILD_HOSTCFLAGS += $(if $(CONFIG_TOOLS_DEBUG),-g)
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||||
|
|
|
@ -442,6 +442,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
|
|||
socfpga_agilex_socdk.dtb \
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||||
socfpga_arria5_secu1.dtb \
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||||
socfpga_arria5_socdk.dtb \
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||||
socfpga_arria10_chameleonv3_270_2.dtb \
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socfpga_arria10_chameleonv3_270_3.dtb \
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socfpga_arria10_chameleonv3_480_2.dtb \
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socfpga_arria10_socdk_sdmmc.dtb \
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||||
|
|
12
arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
Normal file
12
arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
Normal file
|
@ -0,0 +1,12 @@
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|||
// SPDX-License-Identifier: GPL-2.0
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||||
/*
|
||||
* Copyright 2022 Google LLC
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||||
*/
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#include "socfpga_arria10_chameleonv3_480_2_handoff.h"
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#include "socfpga_arria10-handoff.dtsi"
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#include "socfpga_arria10_handoff_u-boot.dtsi"
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#include "socfpga_arria10_mercury_aa1-u-boot.dtsi"
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||||
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&fpga_mgr {
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altr,bitstream = "fpga-270-2.itb";
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||||
};
|
5
arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
Normal file
5
arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
Normal file
|
@ -0,0 +1,5 @@
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|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright 2022 Google LLC
|
||||
*/
|
||||
#include "socfpga_arria10_chameleonv3.dtsi"
|
|
@ -6,3 +6,7 @@
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|||
#include "socfpga_arria10-handoff.dtsi"
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||||
#include "socfpga_arria10_handoff_u-boot.dtsi"
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||||
#include "socfpga_arria10_mercury_aa1-u-boot.dtsi"
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||||
|
||||
&fpga_mgr {
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||||
altr,bitstream = "fpga-270-3.itb";
|
||||
};
|
||||
|
|
|
@ -2,4 +2,4 @@
|
|||
/*
|
||||
* Copyright 2022 Google LLC
|
||||
*/
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||||
#include "socfpga_arria10_chameleonv3.dts"
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||||
#include "socfpga_arria10_chameleonv3.dtsi"
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||||
|
|
|
@ -6,3 +6,7 @@
|
|||
#include "socfpga_arria10-handoff.dtsi"
|
||||
#include "socfpga_arria10_handoff_u-boot.dtsi"
|
||||
#include "socfpga_arria10_mercury_aa1-u-boot.dtsi"
|
||||
|
||||
&fpga_mgr {
|
||||
altr,bitstream = "fpga-480-2.itb";
|
||||
};
|
||||
|
|
|
@ -2,4 +2,4 @@
|
|||
/*
|
||||
* Copyright 2022 Google LLC
|
||||
*/
|
||||
#include "socfpga_arria10_chameleonv3.dts"
|
||||
#include "socfpga_arria10_chameleonv3.dtsi"
|
||||
|
|
|
@ -312,7 +312,7 @@
|
|||
};
|
||||
|
||||
pwm: pwm@7000a000 {
|
||||
compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
|
||||
compatible = "nvidia,tegra114-pwm";
|
||||
reg = <0x7000a000 0x100>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&tegra_car TEGRA114_CLK_PWM>;
|
||||
|
|
|
@ -377,7 +377,7 @@
|
|||
};
|
||||
|
||||
pwm: pwm@7000a000 {
|
||||
compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
|
||||
compatible = "nvidia,tegra124-pwm", "nvidia,tegra114-pwm";
|
||||
reg = <0x7000a000 0x100>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_PWM>;
|
||||
|
|
|
@ -270,6 +270,19 @@ void clock_ll_start_uart(enum periph_id periph_id);
|
|||
*/
|
||||
int clock_decode_periph_id(struct udevice *dev);
|
||||
|
||||
/**
|
||||
* Get periph clock id and its parent from device tree.
|
||||
*
|
||||
* This works by looking up the peripheral's 'clocks' node and reading out
|
||||
* the second and fourth cells, which are the peripheral and PLL clock numbers.
|
||||
*
|
||||
* @param dev udevice associated with FDT node
|
||||
* @param clk_id pointer to int array of 2 values
|
||||
* first is periph clock, second is
|
||||
* its PLL parent according to FDT.
|
||||
*/
|
||||
int clock_decode_pair(struct udevice *dev, int *clk_id);
|
||||
|
||||
/**
|
||||
* Checks if the oscillator bypass is enabled (XOBP bit)
|
||||
*
|
||||
|
@ -354,6 +367,14 @@ int get_periph_clock_source(enum periph_id periph_id,
|
|||
*/
|
||||
enum periph_id clk_id_to_periph_id(int clk_id);
|
||||
|
||||
/*
|
||||
* Convert a device tree clock ID to our PLL ID.
|
||||
*
|
||||
* @param clk_id Clock ID according to tegra device tree binding
|
||||
* Return: clock ID, or CLOCK_ID_NONE if the clock ID is invalid
|
||||
*/
|
||||
enum clock_id clk_id_to_pll_id(int clk_id);
|
||||
|
||||
/**
|
||||
* Set the output frequency you want for each PLL clock.
|
||||
* PLL output frequencies are programmed by setting their N, M and P values.
|
||||
|
|
47
arch/arm/include/asm/arch-tegra/crypto.h
Normal file
47
arch/arm/include/asm/arch-tegra/crypto.h
Normal file
|
@ -0,0 +1,47 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2011 The Chromium OS Authors.
|
||||
* (C) Copyright 2010 - 2011 NVIDIA Corporation <www.nvidia.com>
|
||||
*/
|
||||
|
||||
#ifndef _CRYPTO_H_
|
||||
#define _CRYPTO_H_
|
||||
|
||||
/**
|
||||
* Sign a block of data
|
||||
*
|
||||
* \param source Source data
|
||||
* \param length Size of source data
|
||||
* \param signature Destination address for signature, AES_KEY_LENGTH bytes
|
||||
*/
|
||||
int sign_data_block(u8 *source, unsigned int length, u8 *signature);
|
||||
|
||||
/**
|
||||
* Sign an encrypted block of data
|
||||
*
|
||||
* \param source Source data
|
||||
* \param length Size of source data
|
||||
* \param signature Destination address for signature, AES_KEY_LENGTH bytes
|
||||
* \param key AES128 encryption key
|
||||
*/
|
||||
int sign_enc_data_block(u8 *source, unsigned int length, u8 *signature, u8 *key);
|
||||
|
||||
/**
|
||||
* Encrypt a block of data
|
||||
*
|
||||
* \param source Source data
|
||||
* \param length Size of source data
|
||||
* \param key AES128 encryption key
|
||||
*/
|
||||
int encrypt_data_block(u8 *source, unsigned int length, u8 *key);
|
||||
|
||||
/**
|
||||
* Decrypt a block of data
|
||||
*
|
||||
* \param source Source data
|
||||
* \param length Size of source data
|
||||
* \param key AES128 encryption key
|
||||
*/
|
||||
int decrypt_data_block(u8 *source, unsigned int length, u8 *key);
|
||||
|
||||
#endif /* #ifndef _CRYPTO_H_ */
|
|
@ -31,4 +31,10 @@ int tegra_lcd_pmic_init(int board_id);
|
|||
*/
|
||||
int nvidia_board_init(void);
|
||||
|
||||
/**
|
||||
* nvidia_board_late_init() - perform any board-specific
|
||||
* init on late stages
|
||||
*/
|
||||
void nvidia_board_late_init(void);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -8,6 +8,7 @@
|
|||
#ifndef _TEGRA_I2C_H_
|
||||
#define _TEGRA_I2C_H_
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/types.h>
|
||||
|
||||
struct udevice;
|
||||
|
@ -154,4 +155,20 @@ struct i2c_ctlr {
|
|||
*/
|
||||
int tegra_i2c_get_dvc_bus(struct udevice **busp);
|
||||
|
||||
/* Pre-dm section used for initial setup of PMIC */
|
||||
#define I2C_SEND_2_BYTES 0x0A02
|
||||
|
||||
static inline void tegra_i2c_ll_write(uint addr, uint data)
|
||||
{
|
||||
struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
|
||||
|
||||
writel(addr, ®->cmd_addr0);
|
||||
writel(0x2, ®->cnfg);
|
||||
|
||||
writel(data, ®->cmd_data1);
|
||||
writel(I2C_SEND_2_BYTES, ®->cnfg);
|
||||
}
|
||||
|
||||
void pmic_enable_cpu_vdd(void);
|
||||
|
||||
#endif /* _TEGRA_I2C_H_ */
|
||||
|
|
|
@ -190,9 +190,9 @@ enum periph_id {
|
|||
PERIPH_ID_ACTMON,
|
||||
|
||||
/* 24 */
|
||||
PERIPH_ID_EX_RESERVED24,
|
||||
PERIPH_ID_EX_RESERVED25,
|
||||
PERIPH_ID_EX_RESERVED26,
|
||||
PERIPH_ID_EXTPERIPH1,
|
||||
PERIPH_ID_EXTPERIPH2,
|
||||
PERIPH_ID_EXTPERIPH3,
|
||||
PERIPH_ID_EX_RESERVED27,
|
||||
PERIPH_ID_SATA,
|
||||
PERIPH_ID_HDA,
|
||||
|
|
|
@ -15,6 +15,11 @@ config SPL_SERIAL
|
|||
config TEGRA_CLKRST
|
||||
bool
|
||||
|
||||
config TEGRA_CRYPTO
|
||||
bool "Tegra AES128 crypto module"
|
||||
select AES
|
||||
default n
|
||||
|
||||
config TEGRA_GP_PADCTRL
|
||||
bool
|
||||
|
||||
|
@ -224,4 +229,13 @@ config CMD_ENTERRCM
|
|||
for mechanical button actuators, or hooking up relays/... to the
|
||||
button.
|
||||
|
||||
config CMD_EBTUPDATE
|
||||
bool "Enable 'ebtupdate' command"
|
||||
depends on TEGRA20 || TEGRA30
|
||||
select TEGRA_CRYPTO
|
||||
help
|
||||
Updating u-boot from within u-boot in rather complex or even
|
||||
impossible on production devices. To make it easier procedure of
|
||||
re-cryption was created. If your device was re-crypted choose Y.
|
||||
|
||||
endif
|
||||
|
|
|
@ -16,6 +16,7 @@ obj-$(CONFIG_TEGRA_GP_PADCTRL) += ap.o
|
|||
obj-y += board.o board2.o
|
||||
obj-y += cache.o
|
||||
obj-$(CONFIG_TEGRA_CLKRST) += clock.o
|
||||
obj-$(CONFIG_$(SPL_)TEGRA_CRYPTO) += crypto.o
|
||||
obj-$(CONFIG_TEGRA_PINCTRL) += pinmux-common.o
|
||||
obj-$(CONFIG_TEGRA_PMC) += powergate.o
|
||||
obj-y += xusb-padctl-dummy.o
|
||||
|
|
|
@ -56,6 +56,7 @@ __weak void gpio_early_init_uart(void) {}
|
|||
__weak void pin_mux_display(void) {}
|
||||
__weak void start_cpu_fan(void) {}
|
||||
__weak void cboot_late_init(void) {}
|
||||
__weak void nvidia_board_late_init(void) {}
|
||||
|
||||
#if defined(CONFIG_TEGRA_NAND)
|
||||
__weak void pin_mux_nand(void)
|
||||
|
@ -267,6 +268,7 @@ int board_late_init(void)
|
|||
#endif
|
||||
start_cpu_fan();
|
||||
cboot_late_init();
|
||||
nvidia_board_late_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -678,6 +678,29 @@ int clock_decode_periph_id(struct udevice *dev)
|
|||
assert(clock_periph_id_isvalid(id));
|
||||
return id;
|
||||
}
|
||||
|
||||
/*
|
||||
* Get periph clock id and its parent from device tree.
|
||||
*
|
||||
* @param dev udevice associated with FDT node
|
||||
* @param clk_id pointer to u32 array of 2 values
|
||||
* first is periph clock, second is
|
||||
* its PLL parent according to FDT.
|
||||
*/
|
||||
int clock_decode_pair(struct udevice *dev, int *clk_id)
|
||||
{
|
||||
u32 cell[4];
|
||||
int err;
|
||||
|
||||
err = dev_read_u32_array(dev, "clocks", cell, ARRAY_SIZE(cell));
|
||||
if (err)
|
||||
return -EINVAL;
|
||||
|
||||
clk_id[0] = clk_id_to_periph_id(cell[1]);
|
||||
clk_id[1] = clk_id_to_pll_id(cell[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
|
||||
|
||||
int clock_verify(void)
|
||||
|
|
|
@ -74,4 +74,3 @@ int tegra_get_chip(void);
|
|||
int tegra_get_sku_info(void);
|
||||
int tegra_get_chip_sku(void);
|
||||
void adjust_pllp_out_freqs(void);
|
||||
void pmic_enable_cpu_vdd(void);
|
||||
|
|
|
@ -7,7 +7,7 @@
|
|||
#include <common.h>
|
||||
#include <log.h>
|
||||
#include <linux/errno.h>
|
||||
#include "crypto.h"
|
||||
#include <asm/arch-tegra/crypto.h>
|
||||
#include "uboot_aes.h"
|
||||
|
||||
static u8 zero_key[16];
|
||||
|
@ -17,6 +17,7 @@ static u8 zero_key[16];
|
|||
enum security_op {
|
||||
SECURITY_SIGN = 1 << 0, /* Sign the data */
|
||||
SECURITY_ENCRYPT = 1 << 1, /* Encrypt the data */
|
||||
SECURITY_DECRYPT = 1 << 2, /* Dectypt the data */
|
||||
};
|
||||
|
||||
/**
|
||||
|
@ -54,7 +55,7 @@ static void sign_object(u8 *key, u8 *key_schedule, u8 *src, u8 *dst,
|
|||
u8 left[AES128_KEY_LENGTH];
|
||||
u8 k1[AES128_KEY_LENGTH];
|
||||
u8 *cbc_chain_data;
|
||||
unsigned i;
|
||||
unsigned int i;
|
||||
|
||||
cbc_chain_data = zero_key; /* Convenient array of 0's for IV */
|
||||
|
||||
|
@ -92,7 +93,7 @@ static void sign_object(u8 *key, u8 *key_schedule, u8 *src, u8 *dst,
|
|||
}
|
||||
|
||||
/**
|
||||
* Encrypt and sign a block of data (depending on security mode).
|
||||
* Decrypt, encrypt or sign a block of data (depending on security mode).
|
||||
*
|
||||
* \param key Input AES key, length AES128_KEY_LENGTH
|
||||
* \param oper Security operations mask to perform (enum security_op)
|
||||
|
@ -100,44 +101,68 @@ static void sign_object(u8 *key, u8 *key_schedule, u8 *src, u8 *dst,
|
|||
* \param length Size of source data
|
||||
* \param sig_dst Destination address for signature, AES128_KEY_LENGTH bytes
|
||||
*/
|
||||
static int encrypt_and_sign(u8 *key, enum security_op oper, u8 *src,
|
||||
u32 length, u8 *sig_dst)
|
||||
static int tegra_crypto_core(u8 *key, enum security_op oper, u8 *src,
|
||||
u32 length, u8 *sig_dst)
|
||||
{
|
||||
u32 num_aes_blocks;
|
||||
u8 key_schedule[AES128_EXPAND_KEY_LENGTH];
|
||||
u8 iv[AES128_KEY_LENGTH] = {0};
|
||||
|
||||
debug("encrypt_and_sign: length = %d\n", length);
|
||||
debug("%s: length = %d\n", __func__, length);
|
||||
|
||||
/*
|
||||
* The only need for a key is for signing/checksum purposes, so
|
||||
* if not encrypting, expand a key of 0s.
|
||||
*/
|
||||
aes_expand_key(oper & SECURITY_ENCRYPT ? key : zero_key,
|
||||
AES128_KEY_LENGTH, key_schedule);
|
||||
aes_expand_key(key, AES128_KEY_LENGTH, key_schedule);
|
||||
|
||||
num_aes_blocks = (length + AES128_KEY_LENGTH - 1) / AES128_KEY_LENGTH;
|
||||
|
||||
if (oper & SECURITY_DECRYPT) {
|
||||
/* Perform this in place, resulting in src being decrypted. */
|
||||
debug("%s: begin decryption\n", __func__);
|
||||
aes_cbc_decrypt_blocks(AES128_KEY_LENGTH, key_schedule, iv, src,
|
||||
src, num_aes_blocks);
|
||||
debug("%s: end decryption\n", __func__);
|
||||
}
|
||||
|
||||
if (oper & SECURITY_ENCRYPT) {
|
||||
/* Perform this in place, resulting in src being encrypted. */
|
||||
debug("encrypt_and_sign: begin encryption\n");
|
||||
debug("%s: begin encryption\n", __func__);
|
||||
aes_cbc_encrypt_blocks(AES128_KEY_LENGTH, key_schedule, iv, src,
|
||||
src, num_aes_blocks);
|
||||
debug("encrypt_and_sign: end encryption\n");
|
||||
debug("%s: end encryption\n", __func__);
|
||||
}
|
||||
|
||||
if (oper & SECURITY_SIGN) {
|
||||
/* encrypt the data, overwriting the result in signature. */
|
||||
debug("encrypt_and_sign: begin signing\n");
|
||||
debug("%s: begin signing\n", __func__);
|
||||
sign_object(key, key_schedule, src, sig_dst, num_aes_blocks);
|
||||
debug("encrypt_and_sign: end signing\n");
|
||||
debug("%s: end signing\n", __func__);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int sign_data_block(u8 *source, unsigned length, u8 *signature)
|
||||
/**
|
||||
* Tegra crypto group
|
||||
*/
|
||||
int sign_data_block(u8 *source, unsigned int length, u8 *signature)
|
||||
{
|
||||
return encrypt_and_sign(zero_key, SECURITY_SIGN, source,
|
||||
length, signature);
|
||||
return tegra_crypto_core(zero_key, SECURITY_SIGN, source,
|
||||
length, signature);
|
||||
}
|
||||
|
||||
int sign_enc_data_block(u8 *source, unsigned int length, u8 *signature, u8 *key)
|
||||
{
|
||||
return tegra_crypto_core(key, SECURITY_SIGN, source,
|
||||
length, signature);
|
||||
}
|
||||
|
||||
int encrypt_data_block(u8 *source, unsigned int length, u8 *key)
|
||||
{
|
||||
return tegra_crypto_core(key, SECURITY_ENCRYPT, source,
|
||||
length, NULL);
|
||||
}
|
||||
|
||||
int decrypt_data_block(u8 *source, unsigned int length, u8 *key)
|
||||
{
|
||||
return tegra_crypto_core(key, SECURITY_DECRYPT, source,
|
||||
length, NULL);
|
||||
}
|
|
@ -19,6 +19,8 @@
|
|||
#include <fdtdec.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include <dt-bindings/clock/tegra114-car.h>
|
||||
|
||||
/*
|
||||
* Clock types that we can use as a source. The Tegra114 has muxes for the
|
||||
* peripheral clocks, and in most cases there are four options for the clock
|
||||
|
@ -646,6 +648,41 @@ enum periph_id clk_id_to_periph_id(int clk_id)
|
|||
return clk_id;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Convert a device tree clock ID to our PLL ID.
|
||||
*
|
||||
* @param clk_id Clock ID according to tegra114 device tree binding
|
||||
* Return: clock ID, or CLOCK_ID_NONE if the clock ID is invalid
|
||||
*/
|
||||
enum clock_id clk_id_to_pll_id(int clk_id)
|
||||
{
|
||||
switch (clk_id) {
|
||||
case TEGRA114_CLK_PLL_C:
|
||||
return CLOCK_ID_CGENERAL;
|
||||
case TEGRA114_CLK_PLL_M:
|
||||
return CLOCK_ID_MEMORY;
|
||||
case TEGRA114_CLK_PLL_P:
|
||||
return CLOCK_ID_PERIPH;
|
||||
case TEGRA114_CLK_PLL_A:
|
||||
return CLOCK_ID_AUDIO;
|
||||
case TEGRA114_CLK_PLL_U:
|
||||
return CLOCK_ID_USB;
|
||||
case TEGRA114_CLK_PLL_D:
|
||||
case TEGRA114_CLK_PLL_D_OUT0:
|
||||
return CLOCK_ID_DISPLAY;
|
||||
case TEGRA114_CLK_PLL_X:
|
||||
return CLOCK_ID_XCPU;
|
||||
case TEGRA114_CLK_PLL_E_OUT0:
|
||||
return CLOCK_ID_EPCI;
|
||||
case TEGRA114_CLK_CLK_32K:
|
||||
return CLOCK_ID_32KHZ;
|
||||
case TEGRA114_CLK_CLK_M:
|
||||
return CLOCK_ID_CLK_M;
|
||||
default:
|
||||
return CLOCK_ID_NONE;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
|
||||
|
||||
void clock_early_init(void)
|
||||
|
@ -745,7 +782,7 @@ struct periph_clk_init periph_clk_init_table[] = {
|
|||
{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
|
||||
{ PERIPH_ID_PWM, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
|
||||
|
|
|
@ -19,6 +19,9 @@
|
|||
#include <fdtdec.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include <dt-bindings/clock/tegra124-car.h>
|
||||
#include <dt-bindings/clock/tegra124-car-common.h>
|
||||
|
||||
/*
|
||||
* Clock types that we can use as a source. The Tegra124 has muxes for the
|
||||
* peripheral clocks, and in most cases there are four options for the clock
|
||||
|
@ -826,6 +829,41 @@ enum periph_id clk_id_to_periph_id(int clk_id)
|
|||
return clk_id;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Convert a device tree clock ID to our PLL ID.
|
||||
*
|
||||
* @param clk_id Clock ID according to tegra124 device tree binding
|
||||
* Return: clock ID, or CLOCK_ID_NONE if the clock ID is invalid
|
||||
*/
|
||||
enum clock_id clk_id_to_pll_id(int clk_id)
|
||||
{
|
||||
switch (clk_id) {
|
||||
case TEGRA124_CLK_PLL_C:
|
||||
return CLOCK_ID_CGENERAL;
|
||||
case TEGRA124_CLK_PLL_M:
|
||||
return CLOCK_ID_MEMORY;
|
||||
case TEGRA124_CLK_PLL_P:
|
||||
return CLOCK_ID_PERIPH;
|
||||
case TEGRA124_CLK_PLL_A:
|
||||
return CLOCK_ID_AUDIO;
|
||||
case TEGRA124_CLK_PLL_U:
|
||||
return CLOCK_ID_USB;
|
||||
case TEGRA124_CLK_PLL_D:
|
||||
case TEGRA124_CLK_PLL_D_OUT0:
|
||||
return CLOCK_ID_DISPLAY;
|
||||
case TEGRA124_CLK_PLL_X:
|
||||
return CLOCK_ID_XCPU;
|
||||
case TEGRA124_CLK_PLL_E:
|
||||
return CLOCK_ID_EPCI;
|
||||
case TEGRA124_CLK_CLK_32K:
|
||||
return CLOCK_ID_32KHZ;
|
||||
case TEGRA124_CLK_CLK_M:
|
||||
return CLOCK_ID_CLK_M;
|
||||
default:
|
||||
return CLOCK_ID_NONE;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
|
||||
|
||||
void clock_early_init(void)
|
||||
|
@ -1170,7 +1208,7 @@ struct periph_clk_init periph_clk_init_table[] = {
|
|||
{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
|
||||
{ PERIPH_ID_PWM, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
|
||||
|
|
|
@ -14,10 +14,14 @@
|
|||
#include <asm/arch/tegra.h>
|
||||
#include <asm/arch-tegra/clk_rst.h>
|
||||
#include <asm/arch-tegra/pmc.h>
|
||||
#include <asm/arch-tegra/tegra_i2c.h>
|
||||
#include <asm/arch-tegra/ap.h>
|
||||
#include <linux/delay.h>
|
||||
#include "../cpu.h"
|
||||
|
||||
/* In case this function is not defined */
|
||||
__weak void pmic_enable_cpu_vdd(void) {}
|
||||
|
||||
/* Tegra124-specific CPU init code */
|
||||
|
||||
static void enable_cpu_power_rail(void)
|
||||
|
|
|
@ -3,6 +3,7 @@ if TEGRA20
|
|||
config TEGRA_LP0
|
||||
bool
|
||||
select TEGRA_CLOCK_SCALING
|
||||
select TEGRA_CRYPTO
|
||||
|
||||
config TEGRA_PMU
|
||||
bool
|
||||
|
|
|
@ -2,9 +2,8 @@
|
|||
#
|
||||
# (C) Copyright 2010,2011 Nvidia Corporation.
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-y += cpu.o
|
||||
endif
|
||||
obj-$(CONFIG_SPL_BUILD) += cpu.o
|
||||
obj-$(CONFIG_$(SPL_)CMD_EBTUPDATE) += bct.o
|
||||
|
||||
# The AVP is ARMv4T architecture so we must use special compiler
|
||||
# flags for any startup files it might use.
|
||||
|
@ -13,6 +12,6 @@ CFLAGS_warmboot_avp.o = -march=armv4t -U__LINUX_ARM_ARCH__ \
|
|||
CFLAGS_REMOVE_warmboot_avp.o := $(LTO_CFLAGS)
|
||||
|
||||
obj-y += clock.o funcmux.o pinmux.o
|
||||
obj-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o
|
||||
obj-$(CONFIG_TEGRA_LP0) += warmboot.o warmboot_avp.o
|
||||
obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
|
||||
obj-$(CONFIG_TEGRA_PMU) += pmu.o
|
||||
|
|
79
arch/arm/mach-tegra/tegra20/bct.c
Normal file
79
arch/arm/mach-tegra/tegra20/bct.c
Normal file
|
@ -0,0 +1,79 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (c) 2022, Ramin <raminterex@yahoo.com>
|
||||
* Copyright (c) 2022, Svyatoslav Ryhel <clamor95@gmail.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <log.h>
|
||||
#include <asm/arch-tegra/crypto.h>
|
||||
#include "bct.h"
|
||||
#include "uboot_aes.h"
|
||||
|
||||
/*
|
||||
* @param bct boot config table start in RAM
|
||||
* @param ect bootloader start in RAM
|
||||
* @param ebt_size bootloader file size in bytes
|
||||
* Return: 0, or 1 if failed
|
||||
*/
|
||||
static int bct_patch(u8 *bct, u8 *ebt, u32 ebt_size)
|
||||
{
|
||||
struct nvboot_config_table *bct_tbl = NULL;
|
||||
u8 ebt_hash[AES128_KEY_LENGTH] = { 0 };
|
||||
u8 sbk[AES128_KEY_LENGTH] = { 0 };
|
||||
u8 *bct_hash = bct;
|
||||
int ret;
|
||||
|
||||
bct += BCT_HASH;
|
||||
|
||||
memcpy(sbk, (u8 *)(bct + BCT_LENGTH),
|
||||
NVBOOT_CMAC_AES_HASH_LENGTH * 4);
|
||||
|
||||
ret = decrypt_data_block(bct, BCT_LENGTH, sbk);
|
||||
if (ret)
|
||||
return 1;
|
||||
|
||||
ebt_size = roundup(ebt_size, EBT_ALIGNMENT);
|
||||
|
||||
ret = encrypt_data_block(ebt, ebt_size, sbk);
|
||||
if (ret)
|
||||
return 1;
|
||||
|
||||
ret = sign_enc_data_block(ebt, ebt_size, ebt_hash, sbk);
|
||||
if (ret)
|
||||
return 1;
|
||||
|
||||
bct_tbl = (struct nvboot_config_table *)bct;
|
||||
|
||||
memcpy((u8 *)&bct_tbl->bootloader[0].crypto_hash,
|
||||
ebt_hash, NVBOOT_CMAC_AES_HASH_LENGTH * 4);
|
||||
bct_tbl->bootloader[0].entry_point = CONFIG_SPL_TEXT_BASE;
|
||||
bct_tbl->bootloader[0].load_addr = CONFIG_SPL_TEXT_BASE;
|
||||
bct_tbl->bootloader[0].length = ebt_size;
|
||||
|
||||
ret = encrypt_data_block(bct, BCT_LENGTH, sbk);
|
||||
if (ret)
|
||||
return 1;
|
||||
|
||||
ret = sign_enc_data_block(bct, BCT_LENGTH, bct_hash, sbk);
|
||||
if (ret)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int do_ebtupdate(struct cmd_tbl *cmdtp, int flag, int argc,
|
||||
char *const argv[])
|
||||
{
|
||||
u32 bct_addr = hextoul(argv[1], NULL);
|
||||
u32 ebt_addr = hextoul(argv[2], NULL);
|
||||
u32 ebt_size = hextoul(argv[3], NULL);
|
||||
|
||||
return bct_patch((u8 *)bct_addr, (u8 *)ebt_addr, ebt_size);
|
||||
}
|
||||
|
||||
U_BOOT_CMD(ebtupdate, 4, 0, do_ebtupdate,
|
||||
"update bootloader on re-crypted Tegra20 devices",
|
||||
""
|
||||
);
|
42
arch/arm/mach-tegra/tegra20/bct.h
Normal file
42
arch/arm/mach-tegra/tegra20/bct.h
Normal file
|
@ -0,0 +1,42 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
|
||||
#ifndef _BCT_H_
|
||||
#define _BCT_H_
|
||||
|
||||
/*
|
||||
* Defines the BCT parametres for T20
|
||||
*/
|
||||
#define BCT_LENGTH 0xFE0
|
||||
#define BCT_HASH 0x10
|
||||
#define EBT_ALIGNMENT 0x10
|
||||
|
||||
/*
|
||||
* Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words)
|
||||
*/
|
||||
#define NVBOOT_CMAC_AES_HASH_LENGTH 4
|
||||
|
||||
/*
|
||||
* Defines the maximum number of bootloader descriptions in the BCT.
|
||||
*/
|
||||
#define NVBOOT_MAX_BOOTLOADERS 4
|
||||
|
||||
struct nv_bootloader_info {
|
||||
u32 version;
|
||||
u32 start_blk;
|
||||
u32 start_page;
|
||||
u32 length;
|
||||
u32 load_addr;
|
||||
u32 entry_point;
|
||||
u32 attribute;
|
||||
u32 crypto_hash[NVBOOT_CMAC_AES_HASH_LENGTH];
|
||||
};
|
||||
|
||||
struct nvboot_config_table {
|
||||
u32 unused0[4];
|
||||
u32 boot_data_version;
|
||||
u32 unused1[668];
|
||||
struct nv_bootloader_info bootloader[NVBOOT_MAX_BOOTLOADERS];
|
||||
u32 unused2[508];
|
||||
};
|
||||
|
||||
#endif /* _BCT_H_ */
|
|
@ -20,6 +20,8 @@
|
|||
#include <fdtdec.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include <dt-bindings/clock/tegra20-car.h>
|
||||
|
||||
/*
|
||||
* Clock types that we can use as a source. The Tegra20 has muxes for the
|
||||
* peripheral clocks, and in most cases there are four options for the clock
|
||||
|
@ -578,6 +580,41 @@ enum periph_id clk_id_to_periph_id(int clk_id)
|
|||
return clk_id;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Convert a device tree clock ID to our PLL ID.
|
||||
*
|
||||
* @param clk_id Clock ID according to tegra20 device tree binding
|
||||
* Return: clock ID, or CLOCK_ID_NONE if the clock ID is invalid
|
||||
*/
|
||||
enum clock_id clk_id_to_pll_id(int clk_id)
|
||||
{
|
||||
switch (clk_id) {
|
||||
case TEGRA20_CLK_PLL_C:
|
||||
return CLOCK_ID_CGENERAL;
|
||||
case TEGRA20_CLK_PLL_M:
|
||||
return CLOCK_ID_MEMORY;
|
||||
case TEGRA20_CLK_PLL_P:
|
||||
return CLOCK_ID_PERIPH;
|
||||
case TEGRA20_CLK_PLL_A:
|
||||
return CLOCK_ID_AUDIO;
|
||||
case TEGRA20_CLK_PLL_U:
|
||||
return CLOCK_ID_USB;
|
||||
case TEGRA20_CLK_PLL_D:
|
||||
case TEGRA20_CLK_PLL_D_OUT0:
|
||||
return CLOCK_ID_DISPLAY;
|
||||
case TEGRA20_CLK_PLL_X:
|
||||
return CLOCK_ID_XCPU;
|
||||
case TEGRA20_CLK_PLL_E:
|
||||
return CLOCK_ID_EPCI;
|
||||
case TEGRA20_CLK_CLK_32K:
|
||||
return CLOCK_ID_32KHZ;
|
||||
case TEGRA20_CLK_CLK_M:
|
||||
return CLOCK_ID_CLK_M;
|
||||
default:
|
||||
return CLOCK_ID_NONE;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
|
||||
|
||||
void clock_early_init(void)
|
||||
|
@ -760,14 +797,14 @@ struct periph_clk_init periph_clk_init_table[] = {
|
|||
{ PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|
||||
{ PERIPH_ID_HOST1X, CLOCK_ID_CGENERAL },
|
||||
{ PERIPH_ID_DISP1, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
|
||||
{ PERIPH_ID_PWM, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_DVC_I2C, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
|
||||
|
|
|
@ -1,19 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2011 The Chromium OS Authors.
|
||||
* (C) Copyright 2010 - 2011 NVIDIA Corporation <www.nvidia.com>
|
||||
*/
|
||||
|
||||
#ifndef _CRYPTO_H_
|
||||
#define _CRYPTO_H_
|
||||
|
||||
/**
|
||||
* Sign a block of data
|
||||
*
|
||||
* \param source Source data
|
||||
* \param length Size of source data
|
||||
* \param signature Destination address for signature, AES_KEY_LENGTH bytes
|
||||
*/
|
||||
int sign_data_block(u8 *source, unsigned length, u8 *signature);
|
||||
|
||||
#endif /* #ifndef _CRYPTO_H_ */
|
|
@ -22,6 +22,8 @@
|
|||
#include <linux/bitops.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include <dt-bindings/clock/tegra210-car.h>
|
||||
|
||||
/*
|
||||
* Clock types that we can use as a source. The Tegra210 has muxes for the
|
||||
* peripheral clocks, and in most cases there are four options for the clock
|
||||
|
@ -914,6 +916,41 @@ enum periph_id clk_id_to_periph_id(int clk_id)
|
|||
return clk_id;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Convert a device tree clock ID to our PLL ID.
|
||||
*
|
||||
* @param clk_id Clock ID according to tegra210 device tree binding
|
||||
* Return: clock ID, or CLOCK_ID_NONE if the clock ID is invalid
|
||||
*/
|
||||
enum clock_id clk_id_to_pll_id(int clk_id)
|
||||
{
|
||||
switch (clk_id) {
|
||||
case TEGRA210_CLK_PLL_C:
|
||||
return CLOCK_ID_CGENERAL;
|
||||
case TEGRA210_CLK_PLL_M:
|
||||
return CLOCK_ID_MEMORY;
|
||||
case TEGRA210_CLK_PLL_P:
|
||||
return CLOCK_ID_PERIPH;
|
||||
case TEGRA210_CLK_PLL_A:
|
||||
return CLOCK_ID_AUDIO;
|
||||
case TEGRA210_CLK_PLL_U:
|
||||
return CLOCK_ID_USB;
|
||||
case TEGRA210_CLK_PLL_D:
|
||||
case TEGRA210_CLK_PLL_D_OUT0:
|
||||
return CLOCK_ID_DISPLAY;
|
||||
case TEGRA210_CLK_PLL_X:
|
||||
return CLOCK_ID_XCPU;
|
||||
case TEGRA210_CLK_PLL_E:
|
||||
return CLOCK_ID_EPCI;
|
||||
case TEGRA210_CLK_CLK_32K:
|
||||
return CLOCK_ID_32KHZ;
|
||||
case TEGRA210_CLK_CLK_M:
|
||||
return CLOCK_ID_CLK_M;
|
||||
default:
|
||||
return CLOCK_ID_NONE;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_OF_CONTROL */
|
||||
|
||||
/*
|
||||
|
@ -1241,7 +1278,7 @@ struct periph_clk_init periph_clk_init_table[] = {
|
|||
{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
|
||||
{ PERIPH_ID_PWM, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
|
||||
|
|
|
@ -1,11 +1,5 @@
|
|||
if TEGRA30
|
||||
|
||||
config TEGRA_VDD_CORE_TPS62361B_SET3
|
||||
bool
|
||||
|
||||
config TEGRA_VDD_CORE_TPS62366A_SET1
|
||||
bool
|
||||
|
||||
choice
|
||||
prompt "Tegra30 board select"
|
||||
optional
|
||||
|
@ -17,12 +11,10 @@ config TARGET_APALIS_T30
|
|||
config TARGET_BEAVER
|
||||
bool "NVIDIA Tegra30 Beaver evaluation board"
|
||||
select BOARD_LATE_INIT
|
||||
select TEGRA_VDD_CORE_TPS62366A_SET1
|
||||
|
||||
config TARGET_CARDHU
|
||||
bool "NVIDIA Tegra30 Cardhu evaluation board"
|
||||
select BOARD_LATE_INIT
|
||||
select TEGRA_VDD_CORE_TPS62361B_SET3
|
||||
|
||||
config TARGET_COLIBRI_T30
|
||||
bool "Toradex Colibri T30 board"
|
||||
|
|
|
@ -3,5 +3,6 @@
|
|||
# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
|
||||
obj-$(CONFIG_SPL_BUILD) += cpu.o
|
||||
obj-$(CONFIG_$(SPL_)CMD_EBTUPDATE) += bct.o
|
||||
|
||||
obj-y += clock.o funcmux.o pinmux.o
|
||||
|
|
79
arch/arm/mach-tegra/tegra30/bct.c
Normal file
79
arch/arm/mach-tegra/tegra30/bct.c
Normal file
|
@ -0,0 +1,79 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (c) 2022, Ramin <raminterex@yahoo.com>
|
||||
* Copyright (c) 2022, Svyatoslav Ryhel <clamor95@gmail.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <log.h>
|
||||
#include <asm/arch-tegra/crypto.h>
|
||||
#include "bct.h"
|
||||
#include "uboot_aes.h"
|
||||
|
||||
/*
|
||||
* @param bct boot config table start in RAM
|
||||
* @param ect bootloader start in RAM
|
||||
* @param ebt_size bootloader file size in bytes
|
||||
* Return: 0, or 1 if failed
|
||||
*/
|
||||
static int bct_patch(u8 *bct, u8 *ebt, u32 ebt_size)
|
||||
{
|
||||
struct nvboot_config_table *bct_tbl = NULL;
|
||||
u8 ebt_hash[AES128_KEY_LENGTH] = { 0 };
|
||||
u8 sbk[AES128_KEY_LENGTH] = { 0 };
|
||||
u8 *bct_hash = bct;
|
||||
int ret;
|
||||
|
||||
bct += BCT_HASH;
|
||||
|
||||
memcpy(sbk, (u8 *)(bct + BCT_LENGTH),
|
||||
NVBOOT_CMAC_AES_HASH_LENGTH * 4);
|
||||
|
||||
ret = decrypt_data_block(bct, BCT_LENGTH, sbk);
|
||||
if (ret)
|
||||
return 1;
|
||||
|
||||
ebt_size = roundup(ebt_size, EBT_ALIGNMENT);
|
||||
|
||||
ret = encrypt_data_block(ebt, ebt_size, sbk);
|
||||
if (ret)
|
||||
return 1;
|
||||
|
||||
ret = sign_enc_data_block(ebt, ebt_size, ebt_hash, sbk);
|
||||
if (ret)
|
||||
return 1;
|
||||
|
||||
bct_tbl = (struct nvboot_config_table *)bct;
|
||||
|
||||
memcpy((u8 *)&bct_tbl->bootloader[0].crypto_hash,
|
||||
ebt_hash, NVBOOT_CMAC_AES_HASH_LENGTH * 4);
|
||||
bct_tbl->bootloader[0].entry_point = CONFIG_SPL_TEXT_BASE;
|
||||
bct_tbl->bootloader[0].load_addr = CONFIG_SPL_TEXT_BASE;
|
||||
bct_tbl->bootloader[0].length = ebt_size;
|
||||
|
||||
ret = encrypt_data_block(bct, BCT_LENGTH, sbk);
|
||||
if (ret)
|
||||
return 1;
|
||||
|
||||
ret = sign_enc_data_block(bct, BCT_LENGTH, bct_hash, sbk);
|
||||
if (ret)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int do_ebtupdate(struct cmd_tbl *cmdtp, int flag, int argc,
|
||||
char *const argv[])
|
||||
{
|
||||
u32 bct_addr = hextoul(argv[1], NULL);
|
||||
u32 ebt_addr = hextoul(argv[2], NULL);
|
||||
u32 ebt_size = hextoul(argv[3], NULL);
|
||||
|
||||
return bct_patch((u8 *)bct_addr, (u8 *)ebt_addr, ebt_size);
|
||||
}
|
||||
|
||||
U_BOOT_CMD(ebtupdate, 4, 0, do_ebtupdate,
|
||||
"update bootloader on re-crypted Tegra30 devices",
|
||||
""
|
||||
);
|
42
arch/arm/mach-tegra/tegra30/bct.h
Normal file
42
arch/arm/mach-tegra/tegra30/bct.h
Normal file
|
@ -0,0 +1,42 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
|
||||
#ifndef _BCT_H_
|
||||
#define _BCT_H_
|
||||
|
||||
/*
|
||||
* Defines the BCT parametres for T30
|
||||
*/
|
||||
#define BCT_LENGTH 0x17E0
|
||||
#define BCT_HASH 0x10
|
||||
#define EBT_ALIGNMENT 0x10
|
||||
|
||||
/*
|
||||
* Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words)
|
||||
*/
|
||||
#define NVBOOT_CMAC_AES_HASH_LENGTH 4
|
||||
|
||||
/*
|
||||
* Defines the maximum number of bootloader descriptions in the BCT.
|
||||
*/
|
||||
#define NVBOOT_MAX_BOOTLOADERS 4
|
||||
|
||||
struct nv_bootloader_info {
|
||||
u32 version;
|
||||
u32 start_blk;
|
||||
u32 start_page;
|
||||
u32 length;
|
||||
u32 load_addr;
|
||||
u32 entry_point;
|
||||
u32 attribute;
|
||||
u32 crypto_hash[NVBOOT_CMAC_AES_HASH_LENGTH];
|
||||
};
|
||||
|
||||
struct nvboot_config_table {
|
||||
u32 unused0[4];
|
||||
u32 boot_data_version;
|
||||
u32 unused1[972];
|
||||
struct nv_bootloader_info bootloader[NVBOOT_MAX_BOOTLOADERS];
|
||||
u32 unused2[508];
|
||||
};
|
||||
|
||||
#endif /* _BCT_H_ */
|
|
@ -19,6 +19,8 @@
|
|||
#include <fdtdec.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include <dt-bindings/clock/tegra30-car.h>
|
||||
|
||||
/*
|
||||
* Clock types that we can use as a source. The Tegra30 has muxes for the
|
||||
* peripheral clocks, and in most cases there are four options for the clock
|
||||
|
@ -377,9 +379,9 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
|
|||
PERIPHC_ACTMON,
|
||||
|
||||
/* 24 */
|
||||
NONE(RESERVED24),
|
||||
NONE(RESERVED25),
|
||||
NONE(RESERVED26),
|
||||
PERIPHC_EXTPERIPH1,
|
||||
PERIPHC_EXTPERIPH2,
|
||||
PERIPHC_EXTPERIPH3,
|
||||
NONE(RESERVED27),
|
||||
PERIPHC_SATA,
|
||||
PERIPHC_HDA,
|
||||
|
@ -628,11 +630,87 @@ enum periph_id clk_id_to_periph_id(int clk_id)
|
|||
return clk_id;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Convert a device tree clock ID to our PLL ID.
|
||||
*
|
||||
* @param clk_id Clock ID according to tegra30 device tree binding
|
||||
* Return: clock ID, or CLOCK_ID_NONE if the clock ID is invalid
|
||||
*/
|
||||
enum clock_id clk_id_to_pll_id(int clk_id)
|
||||
{
|
||||
switch (clk_id) {
|
||||
case TEGRA30_CLK_PLL_C:
|
||||
return CLOCK_ID_CGENERAL;
|
||||
case TEGRA30_CLK_PLL_M:
|
||||
return CLOCK_ID_MEMORY;
|
||||
case TEGRA30_CLK_PLL_P:
|
||||
return CLOCK_ID_PERIPH;
|
||||
case TEGRA30_CLK_PLL_A:
|
||||
return CLOCK_ID_AUDIO;
|
||||
case TEGRA30_CLK_PLL_U:
|
||||
return CLOCK_ID_USB;
|
||||
case TEGRA30_CLK_PLL_D:
|
||||
case TEGRA30_CLK_PLL_D_OUT0:
|
||||
return CLOCK_ID_DISPLAY;
|
||||
case TEGRA30_CLK_PLL_X:
|
||||
return CLOCK_ID_XCPU;
|
||||
case TEGRA30_CLK_PLL_E:
|
||||
return CLOCK_ID_EPCI;
|
||||
case TEGRA30_CLK_CLK_32K:
|
||||
return CLOCK_ID_32KHZ;
|
||||
case TEGRA30_CLK_CLK_M:
|
||||
return CLOCK_ID_CLK_M;
|
||||
default:
|
||||
return CLOCK_ID_NONE;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
|
||||
|
||||
void clock_early_init(void)
|
||||
{
|
||||
struct clk_rst_ctlr *clkrst =
|
||||
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
|
||||
struct clk_pll_info *pllinfo;
|
||||
u32 data;
|
||||
|
||||
tegra30_set_up_pllp();
|
||||
|
||||
/*
|
||||
* PLLD output frequency set to 925Mhz
|
||||
*/
|
||||
switch (clock_get_osc_freq()) {
|
||||
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
|
||||
case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
|
||||
clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
|
||||
break;
|
||||
|
||||
case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
|
||||
clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
|
||||
break;
|
||||
|
||||
case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
|
||||
case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
|
||||
clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
|
||||
break;
|
||||
|
||||
case CLOCK_OSC_FREQ_19_2:
|
||||
case CLOCK_OSC_FREQ_38_4:
|
||||
default:
|
||||
/*
|
||||
* These are not supported. It is too early to print a
|
||||
* message and the UART likely won't work anyway due to the
|
||||
* oscillator being wrong.
|
||||
*/
|
||||
break;
|
||||
}
|
||||
|
||||
/* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1, and enable lock */
|
||||
pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY];
|
||||
data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift);
|
||||
data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena);
|
||||
writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
|
||||
udelay(2);
|
||||
}
|
||||
|
||||
void arch_timer_init(void)
|
||||
|
@ -799,14 +877,14 @@ struct periph_clk_init periph_clk_init_table[] = {
|
|||
{ PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|
||||
{ PERIPH_ID_HOST1X, CLOCK_ID_CGENERAL },
|
||||
{ PERIPH_ID_DISP1, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
|
||||
{ PERIPH_ID_PWM, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_DVC_I2C, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
|
||||
{ PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
|
||||
|
|
|
@ -15,37 +15,8 @@
|
|||
#include <linux/delay.h>
|
||||
#include "../cpu.h"
|
||||
|
||||
/* Tegra30-specific CPU init code */
|
||||
void tegra_i2c_ll_write_addr(uint addr, uint config)
|
||||
{
|
||||
struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
|
||||
|
||||
writel(addr, ®->cmd_addr0);
|
||||
writel(config, ®->cnfg);
|
||||
}
|
||||
|
||||
void tegra_i2c_ll_write_data(uint data, uint config)
|
||||
{
|
||||
struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
|
||||
|
||||
writel(data, ®->cmd_data1);
|
||||
writel(config, ®->cnfg);
|
||||
}
|
||||
|
||||
#define TPS62366A_I2C_ADDR 0xC0
|
||||
#define TPS62366A_SET1_REG 0x01
|
||||
#define TPS62366A_SET1_DATA (0x4600 | TPS62366A_SET1_REG)
|
||||
|
||||
#define TPS62361B_I2C_ADDR 0xC0
|
||||
#define TPS62361B_SET3_REG 0x03
|
||||
#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG)
|
||||
|
||||
#define TPS65911_I2C_ADDR 0x5A
|
||||
#define TPS65911_VDDCTRL_OP_REG 0x28
|
||||
#define TPS65911_VDDCTRL_SR_REG 0x27
|
||||
#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
|
||||
#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
|
||||
#define I2C_SEND_2_BYTES 0x0A02
|
||||
/* In case this function is not defined */
|
||||
__weak void pmic_enable_cpu_vdd(void) {}
|
||||
|
||||
static void enable_cpu_power_rail(void)
|
||||
{
|
||||
|
@ -56,27 +27,6 @@ static void enable_cpu_power_rail(void)
|
|||
reg = readl(&pmc->pmc_cntrl);
|
||||
reg |= CPUPWRREQ_OE;
|
||||
writel(reg, &pmc->pmc_cntrl);
|
||||
|
||||
/* Set VDD_CORE to 1.200V. */
|
||||
#ifdef CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
|
||||
tegra_i2c_ll_write_addr(TPS62366A_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(TPS62366A_SET1_DATA, I2C_SEND_2_BYTES);
|
||||
#endif
|
||||
#ifdef CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
|
||||
tegra_i2c_ll_write_addr(TPS62361B_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(TPS62361B_SET3_DATA, I2C_SEND_2_BYTES);
|
||||
#endif
|
||||
udelay(1000);
|
||||
|
||||
/*
|
||||
* Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
|
||||
* First set VDD to 1.0125V, then enable the VDD regulator.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES);
|
||||
udelay(1000);
|
||||
tegra_i2c_ll_write_data(TPS65911_VDDCTRL_SR_DATA, I2C_SEND_2_BYTES);
|
||||
udelay(10 * 1000);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -142,6 +92,7 @@ void start_cpu(u32 reset_vector)
|
|||
|
||||
/* Enable VDD_CPU */
|
||||
enable_cpu_power_rail();
|
||||
pmic_enable_cpu_vdd();
|
||||
|
||||
set_cpu_running(0);
|
||||
|
||||
|
|
|
@ -8,8 +8,8 @@ choice
|
|||
prompt "Target select"
|
||||
optional
|
||||
|
||||
config TARGET_AX25_AE350
|
||||
bool "Support ax25-ae350"
|
||||
config TARGET_AE350
|
||||
bool "Support ae350"
|
||||
|
||||
config TARGET_MICROCHIP_ICICLE
|
||||
bool "Support Microchip PolarFire-SoC Icicle Board"
|
||||
|
@ -58,7 +58,7 @@ config SPL_SYS_DCACHE_OFF
|
|||
Do not enable data cache in SPL.
|
||||
|
||||
# board-specific options below
|
||||
source "board/AndesTech/ax25-ae350/Kconfig"
|
||||
source "board/AndesTech/ae350/Kconfig"
|
||||
source "board/emulation/qemu-riscv/Kconfig"
|
||||
source "board/microchip/mpfs_icicle/Kconfig"
|
||||
source "board/sifive/unleashed/Kconfig"
|
||||
|
@ -67,7 +67,7 @@ source "board/openpiton/riscv64/Kconfig"
|
|||
source "board/sipeed/maix/Kconfig"
|
||||
|
||||
# platform-specific options below
|
||||
source "arch/riscv/cpu/ax25/Kconfig"
|
||||
source "arch/riscv/cpu/andesv5/Kconfig"
|
||||
source "arch/riscv/cpu/fu540/Kconfig"
|
||||
source "arch/riscv/cpu/fu740/Kconfig"
|
||||
source "arch/riscv/cpu/generic/Kconfig"
|
||||
|
|
|
@ -6,19 +6,10 @@ config RISCV_NDS
|
|||
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
|
||||
imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
|
||||
imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE)
|
||||
imply V5L2_CACHE
|
||||
imply SPL_CPU
|
||||
imply SPL_OPENSBI
|
||||
imply SPL_LOAD_FIT
|
||||
help
|
||||
Run U-Boot on AndeStar V5 platforms and use some specific features
|
||||
which are provided by Andes Technology AndeStar V5 families.
|
||||
|
||||
if RISCV_NDS
|
||||
|
||||
config RISCV_NDS_CACHE
|
||||
bool "AndeStar V5 families specific cache support"
|
||||
depends on RISCV_MMODE || SPL_RISCV_MMODE
|
||||
help
|
||||
Provide Andes Technology AndeStar V5 families specific cache support.
|
||||
|
||||
endif
|
130
arch/riscv/cpu/andesv5/cache.c
Normal file
130
arch/riscv/cpu/andesv5/cache.c
Normal file
|
@ -0,0 +1,130 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2023 Andes Technology Corporation
|
||||
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
|
||||
*/
|
||||
|
||||
#include <asm/csr.h>
|
||||
#include <asm/asm.h>
|
||||
#include <common.h>
|
||||
#include <cache.h>
|
||||
#include <cpu_func.h>
|
||||
#include <dm.h>
|
||||
#include <dm/uclass-internal.h>
|
||||
#include <asm/arch-andes/csr.h>
|
||||
|
||||
#ifdef CONFIG_V5L2_CACHE
|
||||
void enable_caches(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_CACHE,
|
||||
DM_DRIVER_GET(v5l2_cache),
|
||||
&dev);
|
||||
if (ret) {
|
||||
log_debug("Cannot enable v5l2 cache\n");
|
||||
} else {
|
||||
ret = cache_enable(dev);
|
||||
if (ret)
|
||||
log_debug("v5l2 cache enable failed\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void cache_ops(int (*ops)(struct udevice *dev))
|
||||
{
|
||||
struct udevice *dev = NULL;
|
||||
|
||||
uclass_find_first_device(UCLASS_CACHE, &dev);
|
||||
|
||||
if (dev)
|
||||
ops(dev);
|
||||
}
|
||||
#endif
|
||||
|
||||
void flush_dcache_all(void)
|
||||
{
|
||||
#if CONFIG_IS_ENABLED(RISCV_MMODE)
|
||||
csr_write(CSR_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL);
|
||||
#endif
|
||||
}
|
||||
|
||||
void flush_dcache_range(unsigned long start, unsigned long end)
|
||||
{
|
||||
flush_dcache_all();
|
||||
}
|
||||
|
||||
void invalidate_dcache_range(unsigned long start, unsigned long end)
|
||||
{
|
||||
flush_dcache_all();
|
||||
}
|
||||
|
||||
void icache_enable(void)
|
||||
{
|
||||
#if CONFIG_IS_ENABLED(RISCV_MMODE)
|
||||
asm volatile("csrsi %0, 0x1" :: "i"(CSR_MCACHE_CTL));
|
||||
#endif
|
||||
}
|
||||
|
||||
void icache_disable(void)
|
||||
{
|
||||
#if CONFIG_IS_ENABLED(RISCV_MMODE)
|
||||
asm volatile("csrci %0, 0x1" :: "i"(CSR_MCACHE_CTL));
|
||||
#endif
|
||||
}
|
||||
|
||||
void dcache_enable(void)
|
||||
{
|
||||
#if CONFIG_IS_ENABLED(RISCV_MMODE)
|
||||
asm volatile("csrsi %0, 0x2" :: "i"(CSR_MCACHE_CTL));
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_V5L2_CACHE
|
||||
cache_ops(cache_enable);
|
||||
#endif
|
||||
}
|
||||
|
||||
void dcache_disable(void)
|
||||
{
|
||||
#if CONFIG_IS_ENABLED(RISCV_MMODE)
|
||||
asm volatile("csrci %0, 0x2" :: "i"(CSR_MCACHE_CTL));
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_V5L2_CACHE
|
||||
cache_ops(cache_disable);
|
||||
#endif
|
||||
}
|
||||
|
||||
int icache_status(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
#if CONFIG_IS_ENABLED(RISCV_MMODE)
|
||||
asm volatile (
|
||||
"csrr t1, %1\n\t"
|
||||
"andi %0, t1, 0x01\n\t"
|
||||
: "=r" (ret)
|
||||
: "i"(CSR_MCACHE_CTL)
|
||||
: "memory"
|
||||
);
|
||||
#endif
|
||||
|
||||
return !!ret;
|
||||
}
|
||||
|
||||
int dcache_status(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
#if CONFIG_IS_ENABLED(RISCV_MMODE)
|
||||
asm volatile (
|
||||
"csrr t1, %1\n\t"
|
||||
"andi %0, t1, 0x02\n\t"
|
||||
: "=r" (ret)
|
||||
: "i" (CSR_MCACHE_CTL)
|
||||
: "memory"
|
||||
);
|
||||
#endif
|
||||
|
||||
return !!ret;
|
||||
}
|
50
arch/riscv/cpu/andesv5/cpu.c
Normal file
50
arch/riscv/cpu/andesv5/cpu.c
Normal file
|
@ -0,0 +1,50 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2023 Andes Technology Corporation
|
||||
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
|
||||
*/
|
||||
|
||||
/* CPU specific code */
|
||||
#include <common.h>
|
||||
#include <cpu_func.h>
|
||||
#include <irq_func.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/csr.h>
|
||||
#include <asm/arch-andes/csr.h>
|
||||
|
||||
/*
|
||||
* cleanup_before_linux() is called just before we call linux
|
||||
* it prepares the processor for linux
|
||||
*
|
||||
* we disable interrupt and caches.
|
||||
*/
|
||||
int cleanup_before_linux(void)
|
||||
{
|
||||
disable_interrupts();
|
||||
|
||||
cache_flush();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void harts_early_init(void)
|
||||
{
|
||||
/* Enable I/D-cache in SPL */
|
||||
if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
|
||||
unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
|
||||
|
||||
mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_IC_EN |
|
||||
MCACHE_CTL_DC_EN | MCACHE_CTL_CCTL_SUEN);
|
||||
|
||||
csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
|
||||
|
||||
/*
|
||||
* Check mcache_ctl.DC_COHEN, we assume this platform does
|
||||
* not support CM if the bit is hard-wired to 0.
|
||||
*/
|
||||
if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {
|
||||
/* Wait for DC_COHSTA bit to be set */
|
||||
while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA));
|
||||
}
|
||||
}
|
||||
}
|
|
@ -1,172 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2017 Andes Technology Corporation
|
||||
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <cpu_func.h>
|
||||
#include <dm.h>
|
||||
#include <asm/cache.h>
|
||||
#include <dm/uclass-internal.h>
|
||||
#include <cache.h>
|
||||
#include <asm/csr.h>
|
||||
|
||||
#ifdef CONFIG_RISCV_NDS_CACHE
|
||||
#if CONFIG_IS_ENABLED(RISCV_MMODE)
|
||||
/* mcctlcommand */
|
||||
#define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc
|
||||
|
||||
/* D-cache operation */
|
||||
#define CCTL_L1D_WBINVAL_ALL 6
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_V5L2_CACHE
|
||||
static void _cache_enable(void)
|
||||
{
|
||||
struct udevice *dev = NULL;
|
||||
|
||||
uclass_find_first_device(UCLASS_CACHE, &dev);
|
||||
|
||||
if (dev)
|
||||
cache_enable(dev);
|
||||
}
|
||||
|
||||
static void _cache_disable(void)
|
||||
{
|
||||
struct udevice *dev = NULL;
|
||||
|
||||
uclass_find_first_device(UCLASS_CACHE, &dev);
|
||||
|
||||
if (dev)
|
||||
cache_disable(dev);
|
||||
}
|
||||
#endif
|
||||
|
||||
void flush_dcache_all(void)
|
||||
{
|
||||
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
|
||||
#ifdef CONFIG_RISCV_NDS_CACHE
|
||||
#if CONFIG_IS_ENABLED(RISCV_MMODE)
|
||||
csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
void flush_dcache_range(unsigned long start, unsigned long end)
|
||||
{
|
||||
flush_dcache_all();
|
||||
}
|
||||
|
||||
void invalidate_dcache_range(unsigned long start, unsigned long end)
|
||||
{
|
||||
flush_dcache_all();
|
||||
}
|
||||
|
||||
void icache_enable(void)
|
||||
{
|
||||
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
|
||||
#ifdef CONFIG_RISCV_NDS_CACHE
|
||||
#if CONFIG_IS_ENABLED(RISCV_MMODE)
|
||||
asm volatile (
|
||||
"csrr t1, mcache_ctl\n\t"
|
||||
"ori t0, t1, 0x1\n\t"
|
||||
"csrw mcache_ctl, t0\n\t"
|
||||
);
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
void icache_disable(void)
|
||||
{
|
||||
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
|
||||
#ifdef CONFIG_RISCV_NDS_CACHE
|
||||
#if CONFIG_IS_ENABLED(RISCV_MMODE)
|
||||
asm volatile (
|
||||
"fence.i\n\t"
|
||||
"csrr t1, mcache_ctl\n\t"
|
||||
"andi t0, t1, ~0x1\n\t"
|
||||
"csrw mcache_ctl, t0\n\t"
|
||||
);
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
void dcache_enable(void)
|
||||
{
|
||||
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
|
||||
#ifdef CONFIG_RISCV_NDS_CACHE
|
||||
#if CONFIG_IS_ENABLED(RISCV_MMODE)
|
||||
asm volatile (
|
||||
"csrr t1, mcache_ctl\n\t"
|
||||
"ori t0, t1, 0x2\n\t"
|
||||
"csrw mcache_ctl, t0\n\t"
|
||||
);
|
||||
#endif
|
||||
#ifdef CONFIG_V5L2_CACHE
|
||||
_cache_enable();
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
void dcache_disable(void)
|
||||
{
|
||||
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
|
||||
#ifdef CONFIG_RISCV_NDS_CACHE
|
||||
#if CONFIG_IS_ENABLED(RISCV_MMODE)
|
||||
csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
|
||||
asm volatile (
|
||||
"csrr t1, mcache_ctl\n\t"
|
||||
"andi t0, t1, ~0x2\n\t"
|
||||
"csrw mcache_ctl, t0\n\t"
|
||||
);
|
||||
#endif
|
||||
#ifdef CONFIG_V5L2_CACHE
|
||||
_cache_disable();
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
int icache_status(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
#ifdef CONFIG_RISCV_NDS_CACHE
|
||||
#if CONFIG_IS_ENABLED(RISCV_MMODE)
|
||||
asm volatile (
|
||||
"csrr t1, mcache_ctl\n\t"
|
||||
"andi %0, t1, 0x01\n\t"
|
||||
: "=r" (ret)
|
||||
:
|
||||
: "memory"
|
||||
);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int dcache_status(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
#ifdef CONFIG_RISCV_NDS_CACHE
|
||||
#if CONFIG_IS_ENABLED(RISCV_MMODE)
|
||||
asm volatile (
|
||||
"csrr t1, mcache_ctl\n\t"
|
||||
"andi %0, t1, 0x02\n\t"
|
||||
: "=r" (ret)
|
||||
:
|
||||
: "memory"
|
||||
);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
|
@ -1,75 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2017 Andes Technology Corporation
|
||||
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
|
||||
*/
|
||||
|
||||
/* CPU specific code */
|
||||
#include <common.h>
|
||||
#include <cpu_func.h>
|
||||
#include <irq_func.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/csr.h>
|
||||
|
||||
#define CSR_MCACHE_CTL 0x7ca
|
||||
#define CSR_MMISC_CTL 0x7d0
|
||||
#define CSR_MARCHID 0xf12
|
||||
|
||||
#define V5_MCACHE_CTL_IC_EN_OFFSET 0
|
||||
#define V5_MCACHE_CTL_DC_EN_OFFSET 1
|
||||
#define V5_MCACHE_CTL_CCTL_SUEN_OFFSET 8
|
||||
#define V5_MCACHE_CTL_DC_COHEN_OFFSET 19
|
||||
#define V5_MCACHE_CTL_DC_COHSTA_OFFSET 20
|
||||
|
||||
#define V5_MCACHE_CTL_IC_EN BIT(V5_MCACHE_CTL_IC_EN_OFFSET)
|
||||
#define V5_MCACHE_CTL_DC_EN BIT(V5_MCACHE_CTL_DC_EN_OFFSET)
|
||||
#define V5_MCACHE_CTL_CCTL_SUEN BIT(V5_MCACHE_CTL_CCTL_SUEN_OFFSET)
|
||||
#define V5_MCACHE_CTL_DC_COHEN_EN BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET)
|
||||
#define V5_MCACHE_CTL_DC_COHSTA_EN BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET)
|
||||
|
||||
|
||||
/*
|
||||
* cleanup_before_linux() is called just before we call linux
|
||||
* it prepares the processor for linux
|
||||
*
|
||||
* we disable interrupt and caches.
|
||||
*/
|
||||
int cleanup_before_linux(void)
|
||||
{
|
||||
disable_interrupts();
|
||||
|
||||
/* turn off I/D-cache */
|
||||
cache_flush();
|
||||
icache_disable();
|
||||
dcache_disable();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void harts_early_init(void)
|
||||
{
|
||||
if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
|
||||
unsigned long long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
|
||||
|
||||
if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN))
|
||||
mcache_ctl_val |= V5_MCACHE_CTL_DC_COHEN_EN;
|
||||
if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN))
|
||||
mcache_ctl_val |= V5_MCACHE_CTL_IC_EN;
|
||||
if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN))
|
||||
mcache_ctl_val |= V5_MCACHE_CTL_DC_EN;
|
||||
if (!(mcache_ctl_val & V5_MCACHE_CTL_CCTL_SUEN))
|
||||
mcache_ctl_val |= V5_MCACHE_CTL_CCTL_SUEN;
|
||||
csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
|
||||
|
||||
/*
|
||||
* Check DC_COHEN_EN, if cannot write to mcache_ctl,
|
||||
* we assume this bitmap not support L2 CM
|
||||
*/
|
||||
mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
|
||||
if ((mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) {
|
||||
/* Wait for DC_COHSTA bit be set */
|
||||
while (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHSTA_EN))
|
||||
mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
|
||||
}
|
||||
}
|
||||
}
|
|
@ -1,6 +1,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
|
||||
dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb
|
||||
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
|
||||
dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
|
||||
dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
|
||||
|
|
|
@ -112,7 +112,7 @@
|
|||
};
|
||||
|
||||
L2: l2-cache@e0500000 {
|
||||
compatible = "v5l2cache";
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-size = <0x40000>;
|
||||
reg = <0xe0500000 0x40000>;
|
||||
|
|
|
@ -112,7 +112,7 @@
|
|||
};
|
||||
|
||||
L2: l2-cache@e0500000 {
|
||||
compatible = "v5l2cache";
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-size = <0x40000>;
|
||||
reg = <0x0 0xe0500000 0x0 0x40000>;
|
||||
|
|
|
@ -45,6 +45,7 @@
|
|||
|
||||
opensbi_blob: opensbi {
|
||||
filename = "fw_dynamic.bin";
|
||||
missing-msg = "opensbi";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
31
arch/riscv/include/asm/arch-andes/csr.h
Normal file
31
arch/riscv/include/asm/arch-andes/csr.h
Normal file
|
@ -0,0 +1,31 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2023 Andes Technology Corporation
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ANDES_CSR_H
|
||||
#define _ASM_ANDES_CSR_H
|
||||
|
||||
#include <asm/asm.h>
|
||||
#include <linux/const.h>
|
||||
|
||||
#define CSR_MCACHE_CTL 0x7ca
|
||||
#define CSR_MMISC_CTL 0x7d0
|
||||
#define CSR_MARCHID 0xf12
|
||||
#define CSR_MCCTLCOMMAND 0x7cc
|
||||
|
||||
#define MCACHE_CTL_IC_EN_OFFSET 0
|
||||
#define MCACHE_CTL_DC_EN_OFFSET 1
|
||||
#define MCACHE_CTL_CCTL_SUEN_OFFSET 8
|
||||
#define MCACHE_CTL_DC_COHEN_OFFSET 19
|
||||
#define MCACHE_CTL_DC_COHSTA_OFFSET 20
|
||||
|
||||
#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET)
|
||||
#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET)
|
||||
#define MCACHE_CTL_CCTL_SUEN BIT(MCACHE_CTL_CCTL_SUEN_OFFSET)
|
||||
#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET)
|
||||
#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET)
|
||||
|
||||
#define CCTL_L1D_WBINVAL_ALL 6
|
||||
|
||||
#endif /* _ASM_ANDES_CSR_H */
|
|
@ -22,7 +22,7 @@ struct arch_global_data {
|
|||
void __iomem *clint; /* clint base address */
|
||||
#endif
|
||||
#ifdef CONFIG_ANDES_PLICSW
|
||||
void __iomem *plicsw; /* plic base address */
|
||||
void __iomem *plicsw; /* andes plicsw base address */
|
||||
#endif
|
||||
#if CONFIG_IS_ENABLED(SMP)
|
||||
struct ipi_data ipi[CONFIG_NR_CPUS];
|
||||
|
|
|
@ -37,7 +37,8 @@ KBUILD_LDFLAGS += -m $(if $(IS_32BIT),elf_i386,elf_x86_64)
|
|||
|
||||
# This is used in the top-level Makefile which does not include
|
||||
# KBUILD_LDFLAGS
|
||||
LDFLAGS_EFI_PAYLOAD := -Bsymbolic -Bsymbolic-functions -shared --no-undefined -s
|
||||
LDFLAGS_EFI_PAYLOAD := -Bsymbolic -Bsymbolic-functions -shared --no-undefined \
|
||||
-s -zexecstack
|
||||
|
||||
OBJCOPYFLAGS_EFI := -j .text -j .sdata -j .data -j .dynamic -j .dynsym \
|
||||
-j .rel -j .rela -j .reloc --strip-all
|
||||
|
|
|
@ -1,10 +1,10 @@
|
|||
if TARGET_AX25_AE350
|
||||
if TARGET_AE350
|
||||
|
||||
config SYS_CPU
|
||||
default "ax25"
|
||||
default "andesv5"
|
||||
|
||||
config SYS_BOARD
|
||||
default "ax25-ae350"
|
||||
default "ae350"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "AndesTech"
|
||||
|
@ -13,7 +13,7 @@ config SYS_SOC
|
|||
default "ae350"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "ax25-ae350"
|
||||
default "ae350"
|
||||
|
||||
config ENV_SIZE
|
||||
default 0x2000 if ENV_IS_IN_SPI_FLASH
|
|
@ -1,8 +1,8 @@
|
|||
AX25-AE350 BOARD
|
||||
AE350 BOARD
|
||||
M: Rick Chen <rick@andestech.com>
|
||||
S: Maintained
|
||||
F: board/AndesTech/ax25-ae350/
|
||||
F: include/configs/ax25-ae350.h
|
||||
F: board/AndesTech/ae350/
|
||||
F: include/configs/ae350.h
|
||||
F: configs/ae350_rv32_defconfig
|
||||
F: configs/ae350_rv64_defconfig
|
||||
F: configs/ae350_rv32_xip_defconfig
|
|
@ -3,4 +3,4 @@
|
|||
# Copyright (C) 2017 Andes Technology Corporation.
|
||||
# Rick Chen, Andes Technology Corporation <rick@andestech.com>
|
||||
|
||||
obj-y := ax25-ae350.o
|
||||
obj-y := ae350.o
|
|
@ -5,6 +5,7 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <cpu_func.h>
|
||||
#include <flash.h>
|
||||
#include <image.h>
|
||||
#include <init.h>
|
||||
|
@ -72,6 +73,14 @@ void *board_fdt_blob_setup(int *err)
|
|||
return NULL;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_BOARD_INIT
|
||||
void spl_board_init()
|
||||
{
|
||||
/* enable v5l2 cache */
|
||||
enable_caches();
|
||||
}
|
||||
#endif
|
||||
|
||||
int smc_init(void)
|
||||
{
|
||||
int node = -1;
|
||||
|
@ -96,18 +105,10 @@ int smc_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void v5l2_init(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
|
||||
uclass_get_device(UCLASS_CACHE, 0, &dev);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_BOARD_EARLY_INIT_F
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
smc_init();
|
||||
v5l2_init();
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -3,4 +3,6 @@
|
|||
# (C) Copyright 2013
|
||||
# Avionic Design GmbH <www.avionic-design.de>
|
||||
|
||||
obj-y := ../common/tamonten-ng.o
|
||||
obj-$(CONFIG_SPL_BUILD) += tec-ng-spl.o
|
||||
|
||||
obj-y += ../common/tamonten-ng.o
|
||||
|
|
34
board/avionic-design/tec-ng/tec-ng-spl.c
Normal file
34
board/avionic-design/tec-ng/tec-ng-spl.c
Normal file
|
@ -0,0 +1,34 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* (C) Copyright 2010-2013
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*
|
||||
* (C) Copyright 2021
|
||||
* Svyatoslav Ryhel <clamor95@gmail.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch-tegra/tegra_i2c.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
/* I2C addr is in 8 bit */
|
||||
#define TPS65911_I2C_ADDR 0x5A
|
||||
#define TPS65911_VDDCTRL_OP_REG 0x28
|
||||
#define TPS65911_VDDCTRL_SR_REG 0x27
|
||||
#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
|
||||
#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
|
||||
|
||||
void pmic_enable_cpu_vdd(void)
|
||||
{
|
||||
/*
|
||||
* Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
|
||||
* First set VDD to 1.0125V, then enable the VDD regulator.
|
||||
*/
|
||||
udelay(1000);
|
||||
tegra_i2c_ll_write(TPS65911_I2C_ADDR,
|
||||
TPS65911_VDDCTRL_OP_DATA);
|
||||
udelay(1000);
|
||||
tegra_i2c_ll_write(TPS65911_I2C_ADDR,
|
||||
TPS65911_VDDCTRL_SR_DATA);
|
||||
udelay(10 * 1000);
|
||||
}
|
|
@ -3,5 +3,6 @@ M: Tim Harvey <tharvey@gateworks.com>
|
|||
S: Maintained
|
||||
F: arch/arm/dts/imx8m*-venice*
|
||||
F: board/gateworks/venice/
|
||||
F: doc/board/gateworks/*venice*
|
||||
F: include/configs/imx8m*_venice.h
|
||||
F: configs/imx8m*_venice_defconfig
|
||||
|
|
|
@ -1,35 +0,0 @@
|
|||
U-Boot for the Gateworks i.MX8M Mini Venice Development Kit boards
|
||||
|
||||
Quick Start
|
||||
===========
|
||||
- Build the ARM Trusted firmware binary
|
||||
- Get ddr firmware
|
||||
- Build U-Boot
|
||||
- Flash to eMMC
|
||||
- Boot
|
||||
|
||||
Get and Build the ARM Trusted firmware
|
||||
======================================
|
||||
$ git clone https://github.com/nxp-imx/imx-atf
|
||||
$ git checkout imx_5.4.47_2.2.0
|
||||
$ make PLAT=imx8mm CROSS_COMPILE=aarch64-linux-gnu- bl31
|
||||
$ cp build/imx8mm/release/bl31.bin .
|
||||
|
||||
Get the DDR Firmware
|
||||
====================
|
||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
|
||||
$ chmod +x firmware-imx-8.9.bin
|
||||
$ ./firmware-imx-8.9.bin
|
||||
$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin .
|
||||
|
||||
Build U-Boot
|
||||
============
|
||||
$ make imx8mm_venice_defconfig
|
||||
$ make CROSS_COMPILE=aarch64-linux-gnu-
|
||||
|
||||
Update eMMC
|
||||
===========
|
||||
=> tftpboot $loadaddr flash.bin
|
||||
=> setexpr blkcnt $filesize + 0x1ff && setexpr blkcnt $blkcnt / 0x200
|
||||
=> mmc dev 2 && mmc write $loadaddr 0x42 $blkcnt # for IMX8MM
|
||||
=> mmc dev 2 && mmc write $loadaddr 0x40 $blkcnt # for IMX8MN
|
13
board/google/chameleonv3/environment.txt
Normal file
13
board/google/chameleonv3/environment.txt
Normal file
|
@ -0,0 +1,13 @@
|
|||
# MMC boot command
|
||||
bootcmd_mmc=load mmc 0:1 ${loadaddr} kernel.itb; bootm
|
||||
|
||||
# Network boot command and vars
|
||||
bootcmd_net=dhcp; tftpboot ${loadaddr} kernel.itb; bootm
|
||||
autoload=no
|
||||
serverip=192.168.0.1
|
||||
|
||||
# U-Boot will run this after loading this file
|
||||
bootcmd_txt=run bootcmd_mmc
|
||||
|
||||
# Kernel cmdline
|
||||
bootargs=cma=256M console=ttyS1,115200 root=/dev/mmcblk0p3 rootflags=subvol=root rw rootwait
|
|
@ -2,4 +2,6 @@
|
|||
#
|
||||
# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
|
||||
obj-$(CONFIG_SPL_BUILD) += beaver-spl.o
|
||||
|
||||
obj-y = ../cardhu/cardhu.o
|
||||
|
|
43
board/nvidia/beaver/beaver-spl.c
Normal file
43
board/nvidia/beaver/beaver-spl.c
Normal file
|
@ -0,0 +1,43 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* (C) Copyright 2010-2013
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*
|
||||
* (C) Copyright 2021
|
||||
* Svyatoslav Ryhel <clamor95@gmail.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch-tegra/tegra_i2c.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
/* I2C addr is in 8 bit */
|
||||
#define TPS65911_I2C_ADDR 0x5A
|
||||
#define TPS65911_VDDCTRL_OP_REG 0x28
|
||||
#define TPS65911_VDDCTRL_SR_REG 0x27
|
||||
#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
|
||||
#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
|
||||
|
||||
#define TPS62366A_I2C_ADDR 0xC0
|
||||
#define TPS62366A_SET1_REG 0x01
|
||||
#define TPS62366A_SET1_DATA (0x4600 | TPS62366A_SET1_REG)
|
||||
|
||||
void pmic_enable_cpu_vdd(void)
|
||||
{
|
||||
/* Set VDD_CORE to 1.200V. */
|
||||
tegra_i2c_ll_write(TPS62366A_I2C_ADDR,
|
||||
TPS62366A_SET1_DATA);
|
||||
|
||||
udelay(1000);
|
||||
|
||||
/*
|
||||
* Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
|
||||
* First set VDD to 1.0125V, then enable the VDD regulator.
|
||||
*/
|
||||
tegra_i2c_ll_write(TPS65911_I2C_ADDR,
|
||||
TPS65911_VDDCTRL_OP_DATA);
|
||||
udelay(1000);
|
||||
tegra_i2c_ll_write(TPS65911_I2C_ADDR,
|
||||
TPS65911_VDDCTRL_SR_DATA);
|
||||
udelay(10 * 1000);
|
||||
}
|
|
@ -3,4 +3,6 @@
|
|||
# (C) Copyright 2010-2012
|
||||
# NVIDIA Corporation <www.nvidia.com>
|
||||
|
||||
obj-y := cardhu.o
|
||||
obj-$(CONFIG_SPL_BUILD) += cardhu-spl.o
|
||||
|
||||
obj-y += cardhu.o
|
||||
|
|
43
board/nvidia/cardhu/cardhu-spl.c
Normal file
43
board/nvidia/cardhu/cardhu-spl.c
Normal file
|
@ -0,0 +1,43 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* (C) Copyright 2010-2013
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*
|
||||
* (C) Copyright 2021
|
||||
* Svyatoslav Ryhel <clamor95@gmail.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch-tegra/tegra_i2c.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
/* I2C addr is in 8 bit */
|
||||
#define TPS65911_I2C_ADDR 0x5A
|
||||
#define TPS65911_VDDCTRL_OP_REG 0x28
|
||||
#define TPS65911_VDDCTRL_SR_REG 0x27
|
||||
#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
|
||||
#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
|
||||
|
||||
#define TPS62361B_I2C_ADDR 0xC0
|
||||
#define TPS62361B_SET3_REG 0x03
|
||||
#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG)
|
||||
|
||||
void pmic_enable_cpu_vdd(void)
|
||||
{
|
||||
/* Set VDD_CORE to 1.200V. */
|
||||
tegra_i2c_ll_write(TPS62361B_I2C_ADDR,
|
||||
TPS62361B_SET3_DATA);
|
||||
|
||||
udelay(1000);
|
||||
|
||||
/*
|
||||
* Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
|
||||
* First set VDD to 1.0125V, then enable the VDD regulator.
|
||||
*/
|
||||
tegra_i2c_ll_write(TPS65911_I2C_ADDR,
|
||||
TPS65911_VDDCTRL_OP_DATA);
|
||||
udelay(1000);
|
||||
tegra_i2c_ll_write(TPS65911_I2C_ADDR,
|
||||
TPS65911_VDDCTRL_SR_DATA);
|
||||
udelay(10 * 1000);
|
||||
}
|
|
@ -9,26 +9,43 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm/arch-tegra/tegra_i2c.h>
|
||||
#include <linux/delay.h>
|
||||
#include "as3722_init.h"
|
||||
|
||||
/* AS3722-PMIC-specific early init regs */
|
||||
|
||||
#define AS3722_I2C_ADDR 0x80
|
||||
|
||||
#define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
|
||||
#define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
|
||||
#define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
|
||||
#define AS3722_SDCONTROL_REG 0x4D
|
||||
|
||||
#define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
|
||||
#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */
|
||||
#define AS3722_LDCONTROL_REG 0x4E
|
||||
|
||||
#if defined(CONFIG_TARGET_VENICE2)
|
||||
#define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG)
|
||||
#else /* TK1 or Nyan-Big */
|
||||
#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
|
||||
#endif
|
||||
#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
|
||||
|
||||
#if defined(CONFIG_TARGET_JETSON_TK1) || defined(CONFIG_TARGET_CEI_TK1_SOM)
|
||||
#define AS3722_SD1VOLTAGE_DATA (0x2800 | AS3722_SD1VOLTAGE_REG)
|
||||
#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG)
|
||||
#endif
|
||||
|
||||
#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG)
|
||||
#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG)
|
||||
|
||||
#define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG)
|
||||
#define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG)
|
||||
|
||||
#define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG)
|
||||
#define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG)
|
||||
|
||||
/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
|
||||
|
||||
void tegra_i2c_ll_write_addr(uint addr, uint config)
|
||||
{
|
||||
struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
|
||||
|
||||
writel(addr, ®->cmd_addr0);
|
||||
writel(config, ®->cnfg);
|
||||
}
|
||||
|
||||
void tegra_i2c_ll_write_data(uint data, uint config)
|
||||
{
|
||||
struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
|
||||
|
||||
writel(data, ®->cmd_data1);
|
||||
writel(config, ®->cnfg);
|
||||
}
|
||||
|
||||
void pmic_enable_cpu_vdd(void)
|
||||
{
|
||||
debug("%s entry\n", __func__);
|
||||
|
@ -37,8 +54,8 @@ void pmic_enable_cpu_vdd(void)
|
|||
/* Set up VDD_CORE, for boards where OTP is incorrect*/
|
||||
debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
|
||||
/* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
tegra_i2c_ll_write(AS3722_I2C_ADDR,
|
||||
AS3722_SD1VOLTAGE_DATA);
|
||||
/*
|
||||
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
|
@ -51,8 +68,8 @@ void pmic_enable_cpu_vdd(void)
|
|||
* Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
|
||||
* First set VDD to 1.0V, then enable the VDD regulator.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
tegra_i2c_ll_write(AS3722_I2C_ADDR,
|
||||
AS3722_SD0VOLTAGE_DATA);
|
||||
/*
|
||||
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
|
@ -64,8 +81,8 @@ void pmic_enable_cpu_vdd(void)
|
|||
* Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
|
||||
* First set VDD to 1.0V, then enable the VDD regulator.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
tegra_i2c_ll_write(AS3722_I2C_ADDR,
|
||||
AS3722_SD6VOLTAGE_DATA);
|
||||
/*
|
||||
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
|
@ -77,8 +94,8 @@ void pmic_enable_cpu_vdd(void)
|
|||
* Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
|
||||
* First set VDD to 1.2V, then enable the VDD regulator.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
tegra_i2c_ll_write(AS3722_I2C_ADDR,
|
||||
AS3722_LDO2VOLTAGE_DATA);
|
||||
/*
|
||||
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
|
@ -93,8 +110,8 @@ void pmic_enable_cpu_vdd(void)
|
|||
* NOTE: We do this early because doing it later seems to hose the CPU
|
||||
* power rail/partition startup. Need to debug.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
tegra_i2c_ll_write(AS3722_I2C_ADDR,
|
||||
AS3722_LDO6VOLTAGE_DATA);
|
||||
/*
|
||||
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
|
|
|
@ -1,43 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2013
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*/
|
||||
|
||||
/* AS3722-PMIC-specific early init regs */
|
||||
|
||||
#define AS3722_I2C_ADDR 0x80
|
||||
|
||||
#define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
|
||||
#define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
|
||||
#define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
|
||||
#define AS3722_SDCONTROL_REG 0x4D
|
||||
|
||||
#define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
|
||||
#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */
|
||||
#define AS3722_LDCONTROL_REG 0x4E
|
||||
|
||||
#if defined(CONFIG_TARGET_VENICE2)
|
||||
#define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG)
|
||||
#else /* TK1 or Nyan-Big */
|
||||
#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
|
||||
#endif
|
||||
#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
|
||||
|
||||
#if defined(CONFIG_TARGET_JETSON_TK1) || defined(CONFIG_TARGET_CEI_TK1_SOM)
|
||||
#define AS3722_SD1VOLTAGE_DATA (0x2800 | AS3722_SD1VOLTAGE_REG)
|
||||
#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG)
|
||||
#endif
|
||||
|
||||
#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG)
|
||||
#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG)
|
||||
|
||||
#define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG)
|
||||
#define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG)
|
||||
|
||||
#define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG)
|
||||
#define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG)
|
||||
|
||||
#define I2C_SEND_2_BYTES 0x0A02
|
||||
|
||||
void pmic_enable_cpu_vdd(void);
|
|
@ -8,26 +8,41 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm/arch-tegra/tegra_i2c.h>
|
||||
#include <linux/delay.h>
|
||||
#include "as3722_init.h"
|
||||
|
||||
/* AS3722-PMIC-specific early init regs */
|
||||
|
||||
#define AS3722_I2C_ADDR 0x80
|
||||
|
||||
#define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
|
||||
#define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
|
||||
#define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
|
||||
#define AS3722_SDCONTROL_REG 0x4D
|
||||
|
||||
#define AS3722_LDO1VOLTAGE_REG 0x11 /* VDD_SDMMC1 */
|
||||
#define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
|
||||
#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC3 */
|
||||
#define AS3722_LDCONTROL_REG 0x4E
|
||||
|
||||
#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
|
||||
#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
|
||||
|
||||
#define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG)
|
||||
#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG)
|
||||
|
||||
#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG)
|
||||
#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG)
|
||||
|
||||
#define AS3722_LDO1CONTROL_DATA (0x0200 | AS3722_LDCONTROL_REG)
|
||||
#define AS3722_LDO1VOLTAGE_DATA (0x7F00 | AS3722_LDO1VOLTAGE_REG)
|
||||
|
||||
#define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG)
|
||||
#define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG)
|
||||
|
||||
#define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG)
|
||||
#define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG)
|
||||
|
||||
/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
|
||||
|
||||
void tegra_i2c_ll_write_addr(uint addr, uint config)
|
||||
{
|
||||
struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
|
||||
|
||||
writel(addr, ®->cmd_addr0);
|
||||
writel(config, ®->cnfg);
|
||||
}
|
||||
|
||||
void tegra_i2c_ll_write_data(uint data, uint config)
|
||||
{
|
||||
struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
|
||||
|
||||
writel(data, ®->cmd_data1);
|
||||
writel(config, ®->cnfg);
|
||||
}
|
||||
|
||||
void pmic_enable_cpu_vdd(void)
|
||||
{
|
||||
debug("%s entry\n", __func__);
|
||||
|
@ -36,8 +51,8 @@ void pmic_enable_cpu_vdd(void)
|
|||
/* Set up VDD_CORE, for boards where OTP is incorrect*/
|
||||
debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
|
||||
/* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
tegra_i2c_ll_write(AS3722_I2C_ADDR,
|
||||
AS3722_SD1VOLTAGE_DATA);
|
||||
/*
|
||||
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
|
@ -49,23 +64,17 @@ void pmic_enable_cpu_vdd(void)
|
|||
* Make sure all non-fused regulators are down.
|
||||
* That way we're in known state after software reboot from linux
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(0x0003, I2C_SEND_2_BYTES);
|
||||
tegra_i2c_ll_write(AS3722_I2C_ADDR, 0x0003);
|
||||
udelay(10 * 1000);
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(0x0004, I2C_SEND_2_BYTES);
|
||||
tegra_i2c_ll_write(AS3722_I2C_ADDR, 0x0004);
|
||||
udelay(10 * 1000);
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(0x001b, I2C_SEND_2_BYTES);
|
||||
tegra_i2c_ll_write(AS3722_I2C_ADDR, 0x001b);
|
||||
udelay(10 * 1000);
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(0x0014, I2C_SEND_2_BYTES);
|
||||
tegra_i2c_ll_write(AS3722_I2C_ADDR, 0x0014);
|
||||
udelay(10 * 1000);
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(0x001a, I2C_SEND_2_BYTES);
|
||||
tegra_i2c_ll_write(AS3722_I2C_ADDR, 0x001a);
|
||||
udelay(10 * 1000);
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(0x0019, I2C_SEND_2_BYTES);
|
||||
tegra_i2c_ll_write(AS3722_I2C_ADDR, 0x0019);
|
||||
udelay(10 * 1000);
|
||||
|
||||
debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
|
||||
|
@ -73,8 +82,8 @@ void pmic_enable_cpu_vdd(void)
|
|||
* Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
|
||||
* First set VDD to 1.0V, then enable the VDD regulator.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
tegra_i2c_ll_write(AS3722_I2C_ADDR,
|
||||
AS3722_SD0VOLTAGE_DATA);
|
||||
/*
|
||||
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
|
@ -86,8 +95,8 @@ void pmic_enable_cpu_vdd(void)
|
|||
* Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
|
||||
* First set VDD to 1.0V, then enable the VDD regulator.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
tegra_i2c_ll_write(AS3722_I2C_ADDR,
|
||||
AS3722_SD6VOLTAGE_DATA);
|
||||
/*
|
||||
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
|
@ -99,8 +108,8 @@ void pmic_enable_cpu_vdd(void)
|
|||
* Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
|
||||
* First set VDD to 1.2V, then enable the VDD regulator.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
tegra_i2c_ll_write(AS3722_I2C_ADDR,
|
||||
AS3722_LDO2VOLTAGE_DATA);
|
||||
/*
|
||||
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
|
@ -115,8 +124,8 @@ void pmic_enable_cpu_vdd(void)
|
|||
* NOTE: We do this early because doing it later seems to hose the CPU
|
||||
* power rail/partition startup. Need to debug.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_LDO1VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
tegra_i2c_ll_write(AS3722_I2C_ADDR,
|
||||
AS3722_LDO1VOLTAGE_DATA);
|
||||
/*
|
||||
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_LDO1CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
|
@ -131,8 +140,8 @@ void pmic_enable_cpu_vdd(void)
|
|||
* NOTE: We do this early because doing it later seems to hose the CPU
|
||||
* power rail/partition startup. Need to debug.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
tegra_i2c_ll_write(AS3722_I2C_ADDR,
|
||||
AS3722_LDO6VOLTAGE_DATA);
|
||||
/*
|
||||
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
|
|
|
@ -1,40 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2012-2016 Toradex, Inc.
|
||||
*/
|
||||
|
||||
/* AS3722-PMIC-specific early init regs */
|
||||
|
||||
#define AS3722_I2C_ADDR 0x80
|
||||
|
||||
#define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
|
||||
#define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
|
||||
#define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
|
||||
#define AS3722_SDCONTROL_REG 0x4D
|
||||
|
||||
#define AS3722_LDO1VOLTAGE_REG 0x11 /* VDD_SDMMC1 */
|
||||
#define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
|
||||
#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC3 */
|
||||
#define AS3722_LDCONTROL_REG 0x4E
|
||||
|
||||
#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
|
||||
#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
|
||||
|
||||
#define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG)
|
||||
#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG)
|
||||
|
||||
#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG)
|
||||
#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG)
|
||||
|
||||
#define AS3722_LDO1CONTROL_DATA (0x0200 | AS3722_LDCONTROL_REG)
|
||||
#define AS3722_LDO1VOLTAGE_DATA (0x7F00 | AS3722_LDO1VOLTAGE_REG)
|
||||
|
||||
#define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG)
|
||||
#define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG)
|
||||
|
||||
#define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG)
|
||||
#define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG)
|
||||
|
||||
#define I2C_SEND_2_BYTES 0x0A02
|
||||
|
||||
void pmic_enable_cpu_vdd(void);
|
|
@ -1,4 +1,6 @@
|
|||
# Copyright (c) 2014 Marcel Ziswiler
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
obj-$(CONFIG_SPL_BUILD) += apalis_t30-spl.o
|
||||
|
||||
obj-y += apalis_t30.o
|
||||
|
|
34
board/toradex/apalis_t30/apalis_t30-spl.c
Normal file
34
board/toradex/apalis_t30/apalis_t30-spl.c
Normal file
|
@ -0,0 +1,34 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* (C) Copyright 2010-2013
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*
|
||||
* (C) Copyright 2021
|
||||
* Svyatoslav Ryhel <clamor95@gmail.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch-tegra/tegra_i2c.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
/* I2C addr is in 8 bit */
|
||||
#define TPS65911_I2C_ADDR 0x5A
|
||||
#define TPS65911_VDDCTRL_OP_REG 0x28
|
||||
#define TPS65911_VDDCTRL_SR_REG 0x27
|
||||
#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
|
||||
#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
|
||||
|
||||
void pmic_enable_cpu_vdd(void)
|
||||
{
|
||||
/*
|
||||
* Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
|
||||
* First set VDD to 1.0125V, then enable the VDD regulator.
|
||||
*/
|
||||
udelay(1000);
|
||||
tegra_i2c_ll_write(TPS65911_I2C_ADDR,
|
||||
TPS65911_VDDCTRL_OP_DATA);
|
||||
udelay(1000);
|
||||
tegra_i2c_ll_write(TPS65911_I2C_ADDR,
|
||||
TPS65911_VDDCTRL_SR_DATA);
|
||||
udelay(10 * 1000);
|
||||
}
|
|
@ -1,4 +1,6 @@
|
|||
# Copyright (c) 2013-2014 Stefan Agner
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
obj-$(CONFIG_SPL_BUILD) += colibri_t30-spl.o
|
||||
|
||||
obj-y += colibri_t30.o
|
||||
|
|
34
board/toradex/colibri_t30/colibri_t30-spl.c
Normal file
34
board/toradex/colibri_t30/colibri_t30-spl.c
Normal file
|
@ -0,0 +1,34 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* (C) Copyright 2010-2013
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*
|
||||
* (C) Copyright 2021
|
||||
* Svyatoslav Ryhel <clamor95@gmail.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch-tegra/tegra_i2c.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
/* I2C addr is in 8 bit */
|
||||
#define TPS65911_I2C_ADDR 0x5A
|
||||
#define TPS65911_VDDCTRL_OP_REG 0x28
|
||||
#define TPS65911_VDDCTRL_SR_REG 0x27
|
||||
#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
|
||||
#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
|
||||
|
||||
void pmic_enable_cpu_vdd(void)
|
||||
{
|
||||
/*
|
||||
* Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
|
||||
* First set VDD to 1.0125V, then enable the VDD regulator.
|
||||
*/
|
||||
udelay(1000);
|
||||
tegra_i2c_ll_write(TPS65911_I2C_ADDR,
|
||||
TPS65911_VDDCTRL_OP_DATA);
|
||||
udelay(1000);
|
||||
tegra_i2c_ll_write(TPS65911_I2C_ADDR,
|
||||
TPS65911_VDDCTRL_SR_DATA);
|
||||
udelay(10 * 1000);
|
||||
}
|
|
@ -332,6 +332,14 @@ efi_status_t efi_install_fdt(void *fdt)
|
|||
|
||||
efi_try_purge_kaslr_seed(fdt);
|
||||
|
||||
if (CONFIG_IS_ENABLED(EFI_TCG2_PROTOCOL_MEASURE_DTB)) {
|
||||
ret = efi_tcg2_measure_dtb(fdt);
|
||||
if (ret == EFI_SECURITY_VIOLATION) {
|
||||
log_err("ERROR: failed to measure DTB\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
/* Install device tree as UEFI table */
|
||||
ret = efi_install_configuration_table(&efi_guid_fdt, fdt);
|
||||
if (ret != EFI_SUCCESS) {
|
||||
|
|
|
@ -619,10 +619,11 @@ static int get_open_session(struct AvbOpsData *ops_data)
|
|||
memset(&arg, 0, sizeof(arg));
|
||||
tee_optee_ta_uuid_to_octets(arg.uuid, &uuid);
|
||||
rc = tee_open_session(tee, &arg, 0, NULL);
|
||||
if (!rc) {
|
||||
ops_data->tee = tee;
|
||||
ops_data->session = arg.session;
|
||||
}
|
||||
if (rc || arg.ret)
|
||||
continue;
|
||||
|
||||
ops_data->tee = tee;
|
||||
ops_data->session = arg.session;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -5,5 +5,4 @@ CONFIG_SPL=y
|
|||
CONFIG_MACH_SUN8I_V3S=y
|
||||
CONFIG_DRAM_CLK=360
|
||||
# CONFIG_HAS_ARMV7_SECURE_BASE is not set
|
||||
CONFIG_SYS_MONITOR_LEN=786432
|
||||
# CONFIG_NET is not set
|
||||
|
|
|
@ -5,6 +5,7 @@ CONFIG_ARCH_CPU_INIT=y
|
|||
CONFIG_ARCH_KIRKWOOD=y
|
||||
CONFIG_SYS_KWD_CONFIG="board/alliedtelesis/SBx81LIFKW/kwbimage.cfg"
|
||||
CONFIG_TEXT_BASE=0x00600000
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000
|
||||
CONFIG_TARGET_SBx81LIFKW=y
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_OFFSET=0xC0000
|
||||
|
@ -13,8 +14,6 @@ CONFIG_DM_GPIO=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-atl-sbx81lifkw"
|
||||
CONFIG_IDENT_STRING="\nSBx81LIFKW"
|
||||
CONFIG_SYS_LOAD_ADDR=0x1000000
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_SYS_MONITOR_LEN=262144
|
||||
CONFIG_BOOTDELAY=3
|
||||
|
|
|
@ -5,6 +5,7 @@ CONFIG_ARCH_CPU_INIT=y
|
|||
CONFIG_ARCH_KIRKWOOD=y
|
||||
CONFIG_SYS_KWD_CONFIG="board/alliedtelesis/SBx81LIFXCAT/kwbimage.cfg"
|
||||
CONFIG_TEXT_BASE=0x00600000
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000
|
||||
CONFIG_TARGET_SBx81LIFXCAT=y
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_OFFSET=0xC0000
|
||||
|
@ -13,8 +14,6 @@ CONFIG_DM_GPIO=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-atl-sbx81lifxcat"
|
||||
CONFIG_IDENT_STRING="\nSBx81LIFXCAT"
|
||||
CONFIG_SYS_LOAD_ADDR=0x1000000
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_SYS_MONITOR_LEN=262144
|
||||
CONFIG_BOOTDELAY=3
|
||||
|
|
|
@ -8,10 +8,10 @@ CONFIG_SYS_MALLOC_F_LEN=0x400
|
|||
CONFIG_ARCH_EXYNOS7=y
|
||||
CONFIG_TARGET_A3Y17LTE=y
|
||||
CONFIG_NR_DRAM_BANKS=8
|
||||
CONFIG_DEFAULT_DEVICE_TREE="exynos78x0-axy17lte"
|
||||
CONFIG_SYS_LOAD_ADDR=0x40001000
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40200e50
|
||||
CONFIG_DEFAULT_DEVICE_TREE="exynos78x0-axy17lte"
|
||||
CONFIG_SYS_LOAD_ADDR=0x40001000
|
||||
CONFIG_FIT=y
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_PREBOOT="echo Read pressed buttons status;KEY_VOLUMEUP=gpa20;KEY_HOME=gpa17;KEY_VOLUMEDOWN=gpa21;KEY_POWER=gpa00;PRESSED=0;RELEASED=1;if gpio input $KEY_VOLUMEUP; then setenv VOLUME_UP $PRESSED; else setenv VOLUME_UP $RELEASED; fi;if gpio input $KEY_VOLUMEDOWN; then setenv VOLUME_DOWN $PRESSED; else setenv VOLUME_DOWN $RELEASED; fi;if gpio input $KEY_HOME; then setenv HOME $PRESSED; else setenv HOME $RELEASED; fi;if gpio input $KEY_POWER; then setenv POWER $PRESSED; else setenv POWER $RELEASED; fi;"
|
||||
|
|
|
@ -8,10 +8,10 @@ CONFIG_SYS_MALLOC_F_LEN=0x400
|
|||
CONFIG_ARCH_EXYNOS7=y
|
||||
CONFIG_TARGET_A5Y17LTE=y
|
||||
CONFIG_NR_DRAM_BANKS=12
|
||||
CONFIG_DEFAULT_DEVICE_TREE="exynos78x0-axy17lte"
|
||||
CONFIG_SYS_LOAD_ADDR=0x40001000
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40200e50
|
||||
CONFIG_DEFAULT_DEVICE_TREE="exynos78x0-axy17lte"
|
||||
CONFIG_SYS_LOAD_ADDR=0x40001000
|
||||
CONFIG_FIT=y
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_PREBOOT="echo Read pressed buttons status;KEY_VOLUMEUP=gpa20;KEY_HOME=gpa17;KEY_VOLUMEDOWN=gpa21;KEY_POWER=gpa00;PRESSED=0;RELEASED=1;if gpio input $KEY_VOLUMEUP; then setenv VOLUME_UP $PRESSED; else setenv VOLUME_UP $RELEASED; fi;if gpio input $KEY_VOLUMEDOWN; then setenv VOLUME_DOWN $PRESSED; else setenv VOLUME_DOWN $RELEASED; fi;if gpio input $KEY_HOME; then setenv HOME $PRESSED; else setenv HOME $RELEASED; fi;if gpio input $KEY_POWER; then setenv POWER $PRESSED; else setenv POWER $RELEASED; fi;"
|
||||
|
|
|
@ -8,10 +8,10 @@ CONFIG_SYS_MALLOC_F_LEN=0x400
|
|||
CONFIG_ARCH_EXYNOS7=y
|
||||
CONFIG_TARGET_A7Y17LTE=y
|
||||
CONFIG_NR_DRAM_BANKS=12
|
||||
CONFIG_DEFAULT_DEVICE_TREE="exynos78x0-axy17lte"
|
||||
CONFIG_SYS_LOAD_ADDR=0x40001000
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40200e50
|
||||
CONFIG_DEFAULT_DEVICE_TREE="exynos78x0-axy17lte"
|
||||
CONFIG_SYS_LOAD_ADDR=0x40001000
|
||||
CONFIG_FIT=y
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_PREBOOT="echo Read pressed buttons status;KEY_VOLUMEUP=gpa20;KEY_HOME=gpa17;KEY_VOLUMEDOWN=gpa21;KEY_POWER=gpa00;PRESSED=0;RELEASED=1;if gpio input $KEY_VOLUMEUP; then setenv VOLUME_UP $PRESSED; else setenv VOLUME_UP $RELEASED; fi;if gpio input $KEY_VOLUMEDOWN; then setenv VOLUME_DOWN $PRESSED; else setenv VOLUME_DOWN $RELEASED; fi;if gpio input $KEY_HOME; then setenv HOME $PRESSED; else setenv HOME $RELEASED; fi;if gpio input $KEY_POWER; then setenv POWER $PRESSED; else setenv POWER $RELEASED; fi;"
|
||||
|
|
|
@ -2,18 +2,20 @@ CONFIG_RISCV=y
|
|||
CONFIG_TEXT_BASE=0x00000000
|
||||
CONFIG_SYS_MALLOC_LEN=0x80000
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe80
|
||||
CONFIG_ENV_SECT_SIZE=0x1000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
|
||||
CONFIG_SYS_PROMPT="RISC-V # "
|
||||
CONFIG_SYS_LOAD_ADDR=0x100000
|
||||
CONFIG_TARGET_AX25_AE350=y
|
||||
CONFIG_TARGET_AE350=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe80
|
||||
CONFIG_SYS_MONITOR_LEN=786432
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SYS_MONITOR_BASE=0x88000000
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_DISPLAY_CPUINFO=y
|
||||
CONFIG_DISPLAY_BOARDINFO=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_SYS_PBSIZE=1050
|
||||
CONFIG_SYS_BOOTM_LEN=0x4000000
|
||||
|
@ -26,6 +28,7 @@ CONFIG_CMD_CACHE=y
|
|||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RETRY_COUNT=50
|
||||
CONFIG_BOOTP_SEND_HOSTNAME=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_MMC=y
|
||||
|
|
|
@ -1,27 +1,31 @@
|
|||
CONFIG_RISCV=y
|
||||
CONFIG_TEXT_BASE=0x01200000
|
||||
CONFIG_TEXT_BASE=0x01800000
|
||||
CONFIG_SYS_MALLOC_LEN=0x80000
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000
|
||||
CONFIG_ENV_SECT_SIZE=0x1000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
|
||||
CONFIG_SYS_PROMPT="RISC-V # "
|
||||
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SYS_LOAD_ADDR=0x100000
|
||||
CONFIG_TARGET_AX25_AE350=y
|
||||
CONFIG_TARGET_AE350=y
|
||||
CONFIG_RISCV_SMODE=y
|
||||
# CONFIG_AVAILABLE_HARTS is not set
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffff00
|
||||
CONFIG_SYS_MONITOR_LEN=786432
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000
|
||||
CONFIG_SYS_MONITOR_BASE=0x88000000
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_DISPLAY_CPUINFO=y
|
||||
CONFIG_DISPLAY_BOARDINFO=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_SPL_MAX_SIZE=0x100000
|
||||
CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_CACHE=y
|
||||
CONFIG_SYS_PBSIZE=1050
|
||||
CONFIG_SYS_BOOTM_LEN=0x4000000
|
||||
CONFIG_CMD_IMLS=y
|
||||
|
@ -32,6 +36,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y
|
|||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_NET_RETRY_COUNT=50
|
||||
CONFIG_BOOTP_SEND_HOSTNAME=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_MMC=y
|
||||
|
|
|
@ -1,7 +1,9 @@
|
|||
CONFIG_RISCV=y
|
||||
CONFIG_TEXT_BASE=0x01200000
|
||||
CONFIG_TEXT_BASE=0x01800000
|
||||
CONFIG_SYS_MALLOC_LEN=0x80000
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000
|
||||
CONFIG_ENV_SECT_SIZE=0x1000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
|
||||
CONFIG_SPL_TEXT_BASE=0x80000000
|
||||
|
@ -9,20 +11,22 @@ CONFIG_SYS_PROMPT="RISC-V # "
|
|||
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SYS_LOAD_ADDR=0x100000
|
||||
CONFIG_TARGET_AX25_AE350=y
|
||||
CONFIG_TARGET_AE350=y
|
||||
CONFIG_RISCV_SMODE=y
|
||||
CONFIG_SPL_XIP=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffff00
|
||||
CONFIG_SYS_MONITOR_LEN=786432
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
|
||||
CONFIG_SYS_MONITOR_BASE=0x88000000
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_DISPLAY_CPUINFO=y
|
||||
CONFIG_DISPLAY_BOARDINFO=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_SPL_MAX_SIZE=0x100000
|
||||
CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_CACHE=y
|
||||
CONFIG_SYS_PBSIZE=1050
|
||||
CONFIG_SYS_BOOTM_LEN=0x4000000
|
||||
CONFIG_CMD_IMLS=y
|
||||
|
@ -33,6 +37,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y
|
|||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_NET_RETRY_COUNT=50
|
||||
CONFIG_BOOTP_SEND_HOSTNAME=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_MMC=y
|
||||
|
|
|
@ -2,19 +2,21 @@ CONFIG_RISCV=y
|
|||
CONFIG_TEXT_BASE=0x80000000
|
||||
CONFIG_SYS_MALLOC_LEN=0x80000
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe80
|
||||
CONFIG_ENV_SECT_SIZE=0x1000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
|
||||
CONFIG_SYS_PROMPT="RISC-V # "
|
||||
CONFIG_SYS_LOAD_ADDR=0x100000
|
||||
CONFIG_TARGET_AX25_AE350=y
|
||||
CONFIG_TARGET_AE350=y
|
||||
CONFIG_XIP=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe80
|
||||
CONFIG_SYS_MONITOR_LEN=786432
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SYS_MONITOR_BASE=0x88000000
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_DISPLAY_CPUINFO=y
|
||||
CONFIG_DISPLAY_BOARDINFO=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_SYS_PBSIZE=1050
|
||||
CONFIG_SYS_BOOTM_LEN=0x4000000
|
||||
|
@ -27,6 +29,7 @@ CONFIG_CMD_CACHE=y
|
|||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RETRY_COUNT=50
|
||||
CONFIG_BOOTP_SEND_HOSTNAME=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_MMC=y
|
||||
|
|
|
@ -2,18 +2,20 @@ CONFIG_RISCV=y
|
|||
CONFIG_TEXT_BASE=0x00000000
|
||||
CONFIG_SYS_MALLOC_LEN=0x80000
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffd70
|
||||
CONFIG_ENV_SECT_SIZE=0x1000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
|
||||
CONFIG_SYS_PROMPT="RISC-V # "
|
||||
CONFIG_SYS_LOAD_ADDR=0x100000
|
||||
CONFIG_TARGET_AX25_AE350=y
|
||||
CONFIG_TARGET_AE350=y
|
||||
CONFIG_ARCH_RV64I=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffd70
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SYS_MONITOR_BASE=0x88000000
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_DISPLAY_CPUINFO=y
|
||||
CONFIG_DISPLAY_BOARDINFO=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_SYS_PBSIZE=1050
|
||||
CONFIG_SYS_BOOTM_LEN=0x4000000
|
||||
|
@ -26,6 +28,7 @@ CONFIG_CMD_CACHE=y
|
|||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RETRY_COUNT=50
|
||||
CONFIG_BOOTP_SEND_HOSTNAME=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_MMC=y
|
||||
|
|
|
@ -1,27 +1,31 @@
|
|||
CONFIG_RISCV=y
|
||||
CONFIG_TEXT_BASE=0x01200000
|
||||
CONFIG_TEXT_BASE=0x01800000
|
||||
CONFIG_SYS_MALLOC_LEN=0x80000
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000
|
||||
CONFIG_ENV_SECT_SIZE=0x1000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
|
||||
CONFIG_SYS_PROMPT="RISC-V # "
|
||||
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SYS_LOAD_ADDR=0x100000
|
||||
CONFIG_TARGET_AX25_AE350=y
|
||||
CONFIG_TARGET_AE350=y
|
||||
CONFIG_ARCH_RV64I=y
|
||||
CONFIG_RISCV_SMODE=y
|
||||
# CONFIG_AVAILABLE_HARTS is not set
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe70
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000
|
||||
CONFIG_SYS_MONITOR_BASE=0x88000000
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_DISPLAY_CPUINFO=y
|
||||
CONFIG_DISPLAY_BOARDINFO=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_SPL_MAX_SIZE=0x100000
|
||||
CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_CACHE=y
|
||||
CONFIG_SYS_PBSIZE=1050
|
||||
CONFIG_SYS_BOOTM_LEN=0x4000000
|
||||
CONFIG_CMD_IMLS=y
|
||||
|
@ -32,6 +36,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y
|
|||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_NET_RETRY_COUNT=50
|
||||
CONFIG_BOOTP_SEND_HOSTNAME=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_MMC=y
|
||||
|
|
|
@ -1,7 +1,9 @@
|
|||
CONFIG_RISCV=y
|
||||
CONFIG_TEXT_BASE=0x01200000
|
||||
CONFIG_TEXT_BASE=0x01800000
|
||||
CONFIG_SYS_MALLOC_LEN=0x80000
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000
|
||||
CONFIG_ENV_SECT_SIZE=0x1000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
|
||||
CONFIG_SPL_TEXT_BASE=0x80000000
|
||||
|
@ -9,20 +11,22 @@ CONFIG_SYS_PROMPT="RISC-V # "
|
|||
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SYS_LOAD_ADDR=0x100000
|
||||
CONFIG_TARGET_AX25_AE350=y
|
||||
CONFIG_TARGET_AE350=y
|
||||
CONFIG_ARCH_RV64I=y
|
||||
CONFIG_RISCV_SMODE=y
|
||||
CONFIG_SPL_XIP=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe70
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
|
||||
CONFIG_SYS_MONITOR_BASE=0x88000000
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_DISPLAY_CPUINFO=y
|
||||
CONFIG_DISPLAY_BOARDINFO=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_SPL_MAX_SIZE=0x100000
|
||||
CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_CACHE=y
|
||||
CONFIG_SYS_PBSIZE=1050
|
||||
CONFIG_SYS_BOOTM_LEN=0x4000000
|
||||
CONFIG_CMD_IMLS=y
|
||||
|
@ -33,6 +37,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y
|
|||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_NET_RETRY_COUNT=50
|
||||
CONFIG_BOOTP_SEND_HOSTNAME=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_MMC=y
|
||||
|
|
|
@ -2,19 +2,21 @@ CONFIG_RISCV=y
|
|||
CONFIG_TEXT_BASE=0x80000000
|
||||
CONFIG_SYS_MALLOC_LEN=0x80000
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffd70
|
||||
CONFIG_ENV_SECT_SIZE=0x1000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
|
||||
CONFIG_SYS_PROMPT="RISC-V # "
|
||||
CONFIG_SYS_LOAD_ADDR=0x100000
|
||||
CONFIG_TARGET_AX25_AE350=y
|
||||
CONFIG_TARGET_AE350=y
|
||||
CONFIG_ARCH_RV64I=y
|
||||
CONFIG_XIP=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffd70
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SYS_MONITOR_BASE=0x88000000
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_DISPLAY_CPUINFO=y
|
||||
CONFIG_DISPLAY_BOARDINFO=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_SYS_PBSIZE=1050
|
||||
CONFIG_SYS_BOOTM_LEN=0x4000000
|
||||
|
@ -27,6 +29,7 @@ CONFIG_CMD_CACHE=y
|
|||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RETRY_COUNT=50
|
||||
CONFIG_BOOTP_SEND_HOSTNAME=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_MMC=y
|
||||
|
|
|
@ -10,6 +10,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000
|
|||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000
|
||||
CONFIG_ENV_SIZE=0x40000
|
||||
CONFIG_ENV_OFFSET=0xC0000
|
||||
CONFIG_ENV_SECT_SIZE=0x40000
|
||||
|
@ -20,14 +22,13 @@ CONFIG_ARCH_RMOBILE_BOARD_STRING="Alt"
|
|||
CONFIG_R8A7794=y
|
||||
CONFIG_TARGET_ALT=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_STACK=0xe6340000
|
||||
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI=y
|
||||
CONFIG_SYS_LOAD_ADDR=0x50000000
|
||||
CONFIG_ENV_ADDR=0xC0000
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000
|
||||
CONFIG_SYS_MONITOR_LEN=262144
|
||||
CONFIG_FIT=y
|
||||
CONFIG_BOOTDELAY=3
|
||||
|
@ -36,7 +37,6 @@ CONFIG_SPL_NO_BSS_LIMIT=y
|
|||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_STACK=0xe6340000
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
|
|
|
@ -3,6 +3,8 @@ CONFIG_ARCH_CPU_INIT=y
|
|||
CONFIG_ARCH_OMAP2PLUS=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
|
||||
CONFIG_DEFAULT_DEVICE_TREE="am335x-baltos"
|
||||
CONFIG_AM33XX=y
|
||||
CONFIG_TARGET_AM335X_BALTOS=y
|
||||
|
@ -12,8 +14,6 @@ CONFIG_SPL=y
|
|||
CONFIG_SPL_FS_FAT=y
|
||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_BOOTCOMMAND="run findfdt; run usbboot;run mmcboot;setenv mmcdev 1; setenv bootpart 1:2; run mmcboot;run nandboot;"
|
||||
|
|
|
@ -4,14 +4,14 @@ CONFIG_ARCH_CPU_INIT=y
|
|||
# CONFIG_SPL_USE_ARCH_MEMSET is not set
|
||||
CONFIG_ARCH_OMAP2PLUS=y
|
||||
CONFIG_TI_COMMON_CMD_OPTIONS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
|
||||
CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack"
|
||||
CONFIG_AM33XX=y
|
||||
CONFIG_CLOCK_SYNTHESIZER=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_ENV_OFFSET_REDUND=0x280000
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
|
||||
CONFIG_TIMESTAMP=y
|
||||
CONFIG_FIT_SIGNATURE=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -2,6 +2,8 @@ CONFIG_ARM=y
|
|||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_OMAP2PLUS=y
|
||||
CONFIG_TI_COMMON_CMD_OPTIONS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
|
||||
CONFIG_ENV_OFFSET=0x100000
|
||||
CONFIG_SPL_DM_SPI=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
|
||||
|
@ -12,8 +14,6 @@ CONFIG_SPL=y
|
|||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
|
||||
CONFIG_TIMESTAMP=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
|
|
|
@ -3,6 +3,8 @@ CONFIG_ARCH_CPU_INIT=y
|
|||
CONFIG_ARCH_OMAP2PLUS=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030fef0
|
||||
CONFIG_ENV_SIZE=0x40000
|
||||
CONFIG_ENV_OFFSET=0x500000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="am335x-guardian"
|
||||
|
@ -21,8 +23,6 @@ CONFIG_SPL_LIBDISK_SUPPORT=y
|
|||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x81000000
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030fef0
|
||||
CONFIG_TIMESTAMP=y
|
||||
CONFIG_BOOTDELAY=0
|
||||
CONFIG_AUTOBOOT_KEYED=y
|
||||
|
|
|
@ -3,17 +3,16 @@ CONFIG_ARCH_CPU_INIT=y
|
|||
CONFIG_ARCH_OMAP2PLUS=y
|
||||
CONFIG_TI_SECURE_DEVICE=y
|
||||
CONFIG_TI_COMMON_CMD_OPTIONS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
|
||||
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
|
||||
CONFIG_SPL_TEXT_BASE=0x40300350
|
||||
CONFIG_AM33XX=y
|
||||
CONFIG_CLOCK_SYNTHESIZER=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
|
||||
CONFIG_TIMESTAMP=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_USE_SPL_FIT_GENERATOR is not set
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_bootcmd"
|
||||
CONFIG_LOGLEVEL=3
|
||||
|
|
|
@ -3,6 +3,8 @@ CONFIG_ARCH_CPU_INIT=y
|
|||
CONFIG_ARCH_OMAP2PLUS=y
|
||||
CONFIG_TI_SECURE_DEVICE=y
|
||||
CONFIG_TI_COMMON_CMD_OPTIONS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
|
||||
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
|
||||
CONFIG_SPL_TEXT_BASE=0x40301950
|
||||
CONFIG_AM33XX=y
|
||||
|
@ -12,11 +14,8 @@ CONFIG_SPL=y
|
|||
# CONFIG_SPL_FS_FAT is not set
|
||||
# CONFIG_SPL_LIBDISK_SUPPORT is not set
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
|
||||
CONFIG_TIMESTAMP=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_USE_SPL_FIT_GENERATOR is not set
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_bootcmd"
|
||||
CONFIG_LOGLEVEL=3
|
||||
|
|
|
@ -4,6 +4,8 @@ CONFIG_ARCH_OMAP2PLUS=y
|
|||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
|
||||
CONFIG_ENV_SIZE=0x18000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="am335x-base0033"
|
||||
CONFIG_AM33XX=y
|
||||
|
@ -14,8 +16,6 @@ CONFIG_SPL=y
|
|||
CONFIG_SPL_FS_FAT=y
|
||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_BOOTCOMMAND="run findfdt;run mmcboot;run nandboot;run netboot;"
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
|
|
|
@ -4,6 +4,8 @@ CONFIG_ARCH_OMAP2PLUS=y
|
|||
CONFIG_SYS_MALLOC_F_LEN=0x1200
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
|
||||
CONFIG_ENV_SIZE=0x4000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="am335x-pdu001"
|
||||
|
@ -16,8 +18,6 @@ CONFIG_SPL_FS_FAT=y
|
|||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
CONFIG_LOCALVERSION="-EETS-1.0.0"
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
|
||||
CONFIG_BOOTDELAY=1
|
||||
CONFIG_AUTOBOOT_KEYED=y
|
||||
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue