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riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"

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There is no need for RISCV_NDS_CACHE config to control cache switches.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
This commit is contained in:
Leo Yu-Chi Liang 2023-02-06 16:10:44 +08:00
parent daf1312b07
commit 55ca747f66
3 changed files with 2 additions and 93 deletions
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10
arch/riscv/cpu/ax25/Kconfig
View file

@ -12,13 +12,3 @@ config RISCV_NDS
help
Run U-Boot on AndeStar V5 platforms and use some specific features
which are provided by Andes Technology AndeStar V5 families.
if RISCV_NDS
config RISCV_NDS_CACHE
bool "AndeStar V5 families specific cache support"
depends on RISCV_MMODE || SPL_RISCV_MMODE
help
Provide Andes Technology AndeStar V5 families specific cache support.
endif

84
arch/riscv/cpu/ax25/cache.c
View file

@ -67,106 +67,26 @@ void invalidate_dcache_range(unsigned long start, unsigned long end)
void icache_enable(void)
{
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
#if CONFIG_IS_ENABLED(RISCV_MMODE)
asm volatile (
"csrr t1, mcache_ctl\n\t"
"ori t0, t1, 0x1\n\t"
"csrw mcache_ctl, t0\n\t"
);
#endif
#endif
#endif
}
void icache_disable(void)
{
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
#if CONFIG_IS_ENABLED(RISCV_MMODE)
asm volatile (
"fence.i\n\t"
"csrr t1, mcache_ctl\n\t"
"andi t0, t1, ~0x1\n\t"
"csrw mcache_ctl, t0\n\t"
);
#endif
#endif
#endif
}
void dcache_enable(void)
{
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
#if CONFIG_IS_ENABLED(RISCV_MMODE)
asm volatile (
"csrr t1, mcache_ctl\n\t"
"ori t0, t1, 0x2\n\t"
"csrw mcache_ctl, t0\n\t"
);
#endif
#ifdef CONFIG_V5L2_CACHE
_cache_enable();
#endif
#endif
#endif
}
void dcache_disable(void)
{
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
#if CONFIG_IS_ENABLED(RISCV_MMODE)
csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
asm volatile (
"csrr t1, mcache_ctl\n\t"
"andi t0, t1, ~0x2\n\t"
"csrw mcache_ctl, t0\n\t"
);
#endif
#ifdef CONFIG_V5L2_CACHE
_cache_disable();
#endif
#endif
#endif
}
int icache_status(void)
{
int ret = 0;
#ifdef CONFIG_RISCV_NDS_CACHE
#if CONFIG_IS_ENABLED(RISCV_MMODE)
asm volatile (
"csrr t1, mcache_ctl\n\t"
"andi %0, t1, 0x01\n\t"
: "=r" (ret)
:
: "memory"
);
#endif
#endif
return ret;
return 0;
}
int dcache_status(void)
{
int ret = 0;
#ifdef CONFIG_RISCV_NDS_CACHE
#if CONFIG_IS_ENABLED(RISCV_MMODE)
asm volatile (
"csrr t1, mcache_ctl\n\t"
"andi %0, t1, 0x02\n\t"
: "=r" (ret)
:
: "memory"
);
#endif
#endif
return ret;
return 0;
}

1
drivers/cache/Kconfig vendored
View file

@ -25,7 +25,6 @@ config L2X0_CACHE
config V5L2_CACHE
bool "Andes V5L2 cache driver"
select CACHE
depends on RISCV_NDS_CACHE
help
Support Andes V5L2 cache controller in AE350 platform.
It will configure tag and data ram timing control from the