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https://github.com/AsahiLinux/u-boot
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video: ti: am335x: restore driver-model code
The commit82f7b869f5
("video: Drop CONFIG_AM335X_LCD") removed not only the LCD legacy implementation but also the code with driver model support. The patch restores the code with driver model support. Fixes:82f7b869f5
("video: Drop CONFIG_AM335X_LCD") Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
parent
a209c3e6b4
commit
f4cf8710a1
8 changed files with 666 additions and 0 deletions
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@ -576,6 +576,8 @@ config ATMEL_HLCD
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help
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HLCDC supports video output to an attached LCD panel.
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source "drivers/video/ti/Kconfig"
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source "drivers/video/exynos/Kconfig"
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config LOGICORE_DP_TX
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@ -26,6 +26,7 @@ obj-${CONFIG_EXYNOS_FB} += exynos/
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obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/
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obj-${CONFIG_VIDEO_STM32} += stm32/
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obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
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obj-y += ti/
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obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
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obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
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8
drivers/video/ti/Kconfig
Normal file
8
drivers/video/ti/Kconfig
Normal file
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@ -0,0 +1,8 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
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#
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config AM335X_LCD
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bool "Enable AM335x video support"
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help
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Supports video output to an attached LCD panel.
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6
drivers/video/ti/Makefile
Normal file
6
drivers/video/ti/Makefile
Normal file
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@ -0,0 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
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#
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obj-$(CONFIG_AM335X_LCD) += tilcdc.o tilcdc-panel.o
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172
drivers/video/ti/tilcdc-panel.c
Normal file
172
drivers/video/ti/tilcdc-panel.c
Normal file
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@ -0,0 +1,172 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* OMAP panel support
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*
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* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
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*/
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#include <common.h>
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#include <backlight.h>
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#include <clk.h>
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#include <display.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <log.h>
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#include <panel.h>
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#include <asm/gpio.h>
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#include <linux/err.h>
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#include "tilcdc.h"
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struct tilcdc_panel_priv {
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struct tilcdc_panel_info info;
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struct display_timing timing;
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struct udevice *backlight;
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struct gpio_desc enable;
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};
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static int tilcdc_panel_enable_backlight(struct udevice *dev)
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{
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struct tilcdc_panel_priv *priv = dev_get_priv(dev);
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if (dm_gpio_is_valid(&priv->enable))
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dm_gpio_set_value(&priv->enable, 1);
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if (priv->backlight)
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return backlight_enable(priv->backlight);
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return 0;
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}
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static int tilcdc_panel_set_backlight(struct udevice *dev, int percent)
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{
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struct tilcdc_panel_priv *priv = dev_get_priv(dev);
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if (dm_gpio_is_valid(&priv->enable))
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dm_gpio_set_value(&priv->enable, 1);
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if (priv->backlight)
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return backlight_set_brightness(priv->backlight, percent);
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return 0;
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}
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int tilcdc_panel_get_display_info(struct udevice *dev,
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struct tilcdc_panel_info *info)
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{
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struct tilcdc_panel_priv *priv = dev_get_priv(dev);
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memcpy(info, &priv->info, sizeof(*info));
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return 0;
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}
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static int tilcdc_panel_get_display_timing(struct udevice *dev,
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struct display_timing *timing)
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{
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struct tilcdc_panel_priv *priv = dev_get_priv(dev);
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memcpy(timing, &priv->timing, sizeof(*timing));
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return 0;
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}
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static int tilcdc_panel_remove(struct udevice *dev)
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{
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struct tilcdc_panel_priv *priv = dev_get_priv(dev);
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if (dm_gpio_is_valid(&priv->enable))
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dm_gpio_free(dev, &priv->enable);
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return 0;
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}
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static int tilcdc_panel_probe(struct udevice *dev)
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{
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struct tilcdc_panel_priv *priv = dev_get_priv(dev);
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int err;
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err = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
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"backlight", &priv->backlight);
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if (err)
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dev_warn(dev, "failed to get backlight\n");
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err = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable,
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GPIOD_IS_OUT);
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if (err) {
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dev_warn(dev, "failed to get enable GPIO\n");
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if (err != -ENOENT)
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return err;
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}
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return 0;
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}
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static int tilcdc_panel_of_to_plat(struct udevice *dev)
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{
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struct tilcdc_panel_priv *priv = dev_get_priv(dev);
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ofnode node;
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int err;
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err = ofnode_decode_display_timing(dev_ofnode(dev), 0, &priv->timing);
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if (err) {
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dev_err(dev, "failed to get display timing\n");
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return err;
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}
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node = dev_read_subnode(dev, "panel-info");
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if (!ofnode_valid(node)) {
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dev_err(dev, "missing 'panel-info' node\n");
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return -ENXIO;
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}
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err |= ofnode_read_u32(node, "ac-bias", &priv->info.ac_bias);
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err |= ofnode_read_u32(node, "ac-bias-intrpt",
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&priv->info.ac_bias_intrpt);
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err |= ofnode_read_u32(node, "dma-burst-sz", &priv->info.dma_burst_sz);
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err |= ofnode_read_u32(node, "bpp", &priv->info.bpp);
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err |= ofnode_read_u32(node, "fdd", &priv->info.fdd);
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err |= ofnode_read_u32(node, "sync-edge", &priv->info.sync_edge);
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err |= ofnode_read_u32(node, "sync-ctrl", &priv->info.sync_ctrl);
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err |= ofnode_read_u32(node, "raster-order", &priv->info.raster_order);
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err |= ofnode_read_u32(node, "fifo-th", &priv->info.fifo_th);
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if (err) {
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dev_err(dev, "failed to get panel info\n");
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return err;
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}
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/* optional */
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priv->info.tft_alt_mode = ofnode_read_bool(node, "tft-alt-mode");
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priv->info.invert_pxl_clk = ofnode_read_bool(node, "invert-pxl-clk");
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dev_dbg(dev, "LCD: %dx%d, bpp=%d, clk=%d Hz\n",
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priv->timing.hactive.typ, priv->timing.vactive.typ,
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priv->info.bpp, priv->timing.pixelclock.typ);
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dev_dbg(dev, " hbp=%d, hfp=%d, hsw=%d\n",
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priv->timing.hback_porch.typ, priv->timing.hfront_porch.typ,
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priv->timing.hsync_len.typ);
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dev_dbg(dev, " vbp=%d, vfp=%d, vsw=%d\n",
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priv->timing.vback_porch.typ, priv->timing.vfront_porch.typ,
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priv->timing.vsync_len.typ);
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return 0;
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}
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static const struct panel_ops tilcdc_panel_ops = {
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.enable_backlight = tilcdc_panel_enable_backlight,
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.set_backlight = tilcdc_panel_set_backlight,
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.get_display_timing = tilcdc_panel_get_display_timing,
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};
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static const struct udevice_id tilcdc_panel_ids[] = {
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{.compatible = "ti,tilcdc,panel"},
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{}
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};
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U_BOOT_DRIVER(tilcdc_panel) = {
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.name = "tilcdc_panel",
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.id = UCLASS_PANEL,
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.of_match = tilcdc_panel_ids,
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.ops = &tilcdc_panel_ops,
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.of_to_plat = tilcdc_panel_of_to_plat,
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.probe = tilcdc_panel_probe,
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.remove = tilcdc_panel_remove,
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.priv_auto = sizeof(struct tilcdc_panel_priv),
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};
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14
drivers/video/ti/tilcdc-panel.h
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14
drivers/video/ti/tilcdc-panel.h
Normal file
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@ -0,0 +1,14 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
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*/
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#ifndef _TILCDC_PANEL_H
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#define _TILCDC_PANEL_H
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#include "tilcdc.h"
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int tilcdc_panel_get_display_info(struct udevice *dev,
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struct tilcdc_panel_info *info);
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#endif /* _TILCDC_PANEL_H */
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425
drivers/video/ti/tilcdc.c
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425
drivers/video/ti/tilcdc.c
Normal file
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@ -0,0 +1,425 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <log.h>
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#include <panel.h>
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#include <video.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/utils.h>
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#include "tilcdc.h"
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#include "tilcdc-panel.h"
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#define LCDC_FMAX 200000000
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/* LCD Control Register */
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#define LCDC_CTRL_CLK_DIVISOR_MASK GENMASK(15, 8)
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#define LCDC_CTRL_RASTER_MODE BIT(0)
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#define LCDC_CTRL_CLK_DIVISOR(x) (((x) & GENMASK(7, 0)) << 8)
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/* LCD Clock Enable Register */
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#define LCDC_CLKC_ENABLE_CORECLKEN BIT(0)
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#define LCDC_CLKC_ENABLE_LIDDCLKEN BIT(1)
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#define LCDC_CLKC_ENABLE_DMACLKEN BIT(2)
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/* LCD DMA Control Register */
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#define LCDC_DMA_CTRL_BURST_SIZE(x) (((x) & GENMASK(2, 0)) << 4)
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#define LCDC_DMA_CTRL_BURST_1 0x0
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#define LCDC_DMA_CTRL_BURST_2 0x1
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#define LCDC_DMA_CTRL_BURST_4 0x2
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#define LCDC_DMA_CTRL_BURST_8 0x3
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#define LCDC_DMA_CTRL_BURST_16 0x4
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#define LCDC_DMA_CTRL_FIFO_TH(x) (((x) & GENMASK(2, 0)) << 8)
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/* LCD Timing_0 Register */
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#define LCDC_RASTER_TIMING_0_HORMSB(x) ((((x) - 1) & BIT(10)) >> 7)
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#define LCDC_RASTER_TIMING_0_HORLSB(x) (((((x) >> 4) - 1) & GENMASK(5, 0)) << 4)
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#define LCDC_RASTER_TIMING_0_HSWLSB(x) ((((x) - 1) & GENMASK(5, 0)) << 10)
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#define LCDC_RASTER_TIMING_0_HFPLSB(x) ((((x) - 1) & GENMASK(7, 0)) << 16)
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#define LCDC_RASTER_TIMING_0_HBPLSB(x) ((((x) - 1) & GENMASK(7, 0)) << 24)
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/* LCD Timing_1 Register */
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#define LCDC_RASTER_TIMING_1_VERLSB(x) (((x) - 1) & GENMASK(9, 0))
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#define LCDC_RASTER_TIMING_1_VSW(x) ((((x) - 1) & GENMASK(5, 0)) << 10)
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#define LCDC_RASTER_TIMING_1_VFP(x) (((x) & GENMASK(7, 0)) << 16)
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#define LCDC_RASTER_TIMING_1_VBP(x) (((x) & GENMASK(7, 0)) << 24)
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/* LCD Timing_2 Register */
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#define LCDC_RASTER_TIMING_2_HFPMSB(x) ((((x) - 1) & GENMASK(9, 8)) >> 8)
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#define LCDC_RASTER_TIMING_2_HBPMSB(x) ((((x) - 1) & GENMASK(9, 8)) >> 4)
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#define LCDC_RASTER_TIMING_2_ACB(x) (((x) & GENMASK(7, 0)) << 8)
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#define LCDC_RASTER_TIMING_2_ACBI(x) (((x) & GENMASK(3, 0)) << 16)
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#define LCDC_RASTER_TIMING_2_VSYNC_INVERT BIT(20)
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#define LCDC_RASTER_TIMING_2_HSYNC_INVERT BIT(21)
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#define LCDC_RASTER_TIMING_2_PXCLK_INVERT BIT(22)
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#define LCDC_RASTER_TIMING_2_DE_INVERT BIT(23)
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#define LCDC_RASTER_TIMING_2_HSVS_RISEFALL BIT(24)
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#define LCDC_RASTER_TIMING_2_HSVS_CONTROL BIT(25)
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#define LCDC_RASTER_TIMING_2_VERMSB(x) ((((x) - 1) & BIT(10)) << 16)
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#define LCDC_RASTER_TIMING_2_HSWMSB(x) ((((x) - 1) & GENMASK(9, 6)) << 21)
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/* LCD Raster Ctrl Register */
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#define LCDC_RASTER_CTRL_ENABLE BIT(0)
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#define LCDC_RASTER_CTRL_TFT_MODE BIT(7)
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#define LCDC_RASTER_CTRL_DATA_ORDER BIT(8)
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#define LCDC_RASTER_CTRL_REQDLY(x) (((x) & GENMASK(7, 0)) << 12)
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#define LCDC_RASTER_CTRL_PALMODE_RAWDATA (0x02 << 20)
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#define LCDC_RASTER_CTRL_TFT_ALT_ENABLE BIT(23)
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#define LCDC_RASTER_CTRL_TFT_24BPP_MODE BIT(25)
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#define LCDC_RASTER_CTRL_TFT_24BPP_UNPACK BIT(26)
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enum {
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LCDC_MAX_WIDTH = 2048,
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LCDC_MAX_HEIGHT = 2048,
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LCDC_MAX_LOG2_BPP = VIDEO_BPP32,
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};
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struct tilcdc_regs {
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u32 pid;
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u32 ctrl;
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u32 gap0;
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u32 lidd_ctrl;
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u32 lidd_cs0_conf;
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u32 lidd_cs0_addr;
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u32 lidd_cs0_data;
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u32 lidd_cs1_conf;
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u32 lidd_cs1_addr;
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u32 lidd_cs1_data;
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u32 raster_ctrl;
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u32 raster_timing0;
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u32 raster_timing1;
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u32 raster_timing2;
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u32 raster_subpanel;
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u32 raster_subpanel2;
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u32 lcddma_ctrl;
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u32 lcddma_fb0_base;
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u32 lcddma_fb0_ceiling;
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u32 lcddma_fb1_base;
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u32 lcddma_fb1_ceiling;
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u32 sysconfig;
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u32 irqstatus_raw;
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u32 irqstatus;
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u32 irqenable_set;
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u32 irqenable_clear;
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u32 gap1;
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u32 clkc_enable;
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u32 clkc_reset;
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};
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struct tilcdc_priv {
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struct tilcdc_regs *regs;
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struct clk gclk;
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struct clk dpll_m2_clk;
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};
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DECLARE_GLOBAL_DATA_PTR;
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static ulong tilcdc_set_pixel_clk_rate(struct udevice *dev, ulong rate)
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{
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struct tilcdc_priv *priv = dev_get_priv(dev);
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struct tilcdc_regs *regs = priv->regs;
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ulong mult_rate, mult_round_rate, best_err, err;
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u32 v;
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int div, i;
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best_err = rate;
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div = 0;
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for (i = 2; i <= 255; i++) {
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mult_rate = rate * i;
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mult_round_rate = clk_round_rate(&priv->gclk, mult_rate);
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if (IS_ERR_VALUE(mult_round_rate))
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return mult_round_rate;
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err = mult_rate - mult_round_rate;
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if (err < best_err) {
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best_err = err;
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div = i;
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if (err == 0)
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break;
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}
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}
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if (div == 0) {
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dev_err(dev, "failed to find a divisor\n");
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return -EFAULT;
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}
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mult_rate = clk_set_rate(&priv->gclk, rate * div);
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v = readl(®s->ctrl) & ~LCDC_CTRL_CLK_DIVISOR_MASK;
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v |= LCDC_CTRL_CLK_DIVISOR(div);
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writel(v, ®s->ctrl);
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rate = mult_rate / div;
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dev_dbg(dev, "rate=%ld, div=%d, err=%ld\n", rate, div, err);
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return rate;
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}
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static int tilcdc_remove(struct udevice *dev)
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{
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struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
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struct tilcdc_priv *priv = dev_get_priv(dev);
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uc_plat->base -= 0x20;
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uc_plat->size += 0x20;
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clk_release_all(&priv->gclk, 1);
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clk_release_all(&priv->dpll_m2_clk, 1);
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return 0;
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}
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static int tilcdc_probe(struct udevice *dev)
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{
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struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
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struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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struct tilcdc_priv *priv = dev_get_priv(dev);
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struct tilcdc_regs *regs = priv->regs;
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struct udevice *panel, *clk_dev;
|
||||
struct tilcdc_panel_info info;
|
||||
struct display_timing timing;
|
||||
ulong rate;
|
||||
u32 reg;
|
||||
int err;
|
||||
|
||||
/* Before relocation we don't need to do anything */
|
||||
if (!(gd->flags & GD_FLG_RELOC))
|
||||
return 0;
|
||||
|
||||
err = uclass_get_device(UCLASS_PANEL, 0, &panel);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to get panel\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
err = panel_get_display_timing(panel, &timing);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to get display timing\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
if (timing.pixelclock.typ > (LCDC_FMAX / 2)) {
|
||||
dev_err(dev, "invalid display clock-frequency: %d Hz\n",
|
||||
timing.pixelclock.typ);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (timing.hactive.typ > LCDC_MAX_WIDTH)
|
||||
timing.hactive.typ = LCDC_MAX_WIDTH;
|
||||
|
||||
if (timing.vactive.typ > LCDC_MAX_HEIGHT)
|
||||
timing.vactive.typ = LCDC_MAX_HEIGHT;
|
||||
|
||||
err = tilcdc_panel_get_display_info(panel, &info);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to get panel info\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
switch (info.bpp) {
|
||||
case 16:
|
||||
case 24:
|
||||
case 32:
|
||||
break;
|
||||
default:
|
||||
dev_err(dev, "invalid seting, bpp: %d\n", info.bpp);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (info.dma_burst_sz) {
|
||||
case 1:
|
||||
case 2:
|
||||
case 4:
|
||||
case 8:
|
||||
case 16:
|
||||
break;
|
||||
default:
|
||||
dev_err(dev, "invalid setting, dma-burst-sz: %d\n",
|
||||
info.dma_burst_sz);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
err = uclass_get_device_by_name(UCLASS_CLK, "lcd_gclk@534", &clk_dev);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to get lcd_gclk device\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
err = clk_request(clk_dev, &priv->gclk);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to get %s clock\n", clk_dev->name);
|
||||
return err;
|
||||
}
|
||||
|
||||
rate = tilcdc_set_pixel_clk_rate(dev, timing.pixelclock.typ);
|
||||
if (IS_ERR_VALUE(rate)) {
|
||||
dev_err(dev, "failed to set pixel clock rate\n");
|
||||
return rate;
|
||||
}
|
||||
|
||||
err = uclass_get_device_by_name(UCLASS_CLK, "dpll_disp_m2_ck@4a4",
|
||||
&clk_dev);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to get dpll_disp_m2 clock device\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
err = clk_request(clk_dev, &priv->dpll_m2_clk);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to get %s clock\n", clk_dev->name);
|
||||
return err;
|
||||
}
|
||||
|
||||
err = clk_set_parent(&priv->gclk, &priv->dpll_m2_clk);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to set %s clock as %s's parent\n",
|
||||
priv->dpll_m2_clk.dev->name, priv->gclk.dev->name);
|
||||
return err;
|
||||
}
|
||||
|
||||
/* palette default entry */
|
||||
memset((void *)uc_plat->base, 0, 0x20);
|
||||
*(unsigned int *)uc_plat->base = 0x4000;
|
||||
/* point fb behind palette */
|
||||
uc_plat->base += 0x20;
|
||||
uc_plat->size -= 0x20;
|
||||
|
||||
writel(LCDC_CLKC_ENABLE_CORECLKEN | LCDC_CLKC_ENABLE_LIDDCLKEN |
|
||||
LCDC_CLKC_ENABLE_DMACLKEN, ®s->clkc_enable);
|
||||
writel(0, ®s->raster_ctrl);
|
||||
|
||||
reg = readl(®s->ctrl) & LCDC_CTRL_CLK_DIVISOR_MASK;
|
||||
reg |= LCDC_CTRL_RASTER_MODE;
|
||||
writel(reg, ®s->ctrl);
|
||||
|
||||
reg = (timing.hactive.typ * timing.vactive.typ * info.bpp) >> 3;
|
||||
reg += uc_plat->base;
|
||||
writel(uc_plat->base, ®s->lcddma_fb0_base);
|
||||
writel(reg, ®s->lcddma_fb0_ceiling);
|
||||
writel(uc_plat->base, ®s->lcddma_fb1_base);
|
||||
writel(reg, ®s->lcddma_fb1_ceiling);
|
||||
|
||||
reg = LCDC_DMA_CTRL_FIFO_TH(info.fifo_th);
|
||||
switch (info.dma_burst_sz) {
|
||||
case 1:
|
||||
reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_1);
|
||||
break;
|
||||
case 2:
|
||||
reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_2);
|
||||
break;
|
||||
case 4:
|
||||
reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_4);
|
||||
break;
|
||||
case 8:
|
||||
reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_8);
|
||||
break;
|
||||
case 16:
|
||||
reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_16);
|
||||
break;
|
||||
}
|
||||
|
||||
writel(reg, ®s->lcddma_ctrl);
|
||||
|
||||
writel(LCDC_RASTER_TIMING_0_HORLSB(timing.hactive.typ) |
|
||||
LCDC_RASTER_TIMING_0_HORMSB(timing.hactive.typ) |
|
||||
LCDC_RASTER_TIMING_0_HFPLSB(timing.hfront_porch.typ) |
|
||||
LCDC_RASTER_TIMING_0_HBPLSB(timing.hback_porch.typ) |
|
||||
LCDC_RASTER_TIMING_0_HSWLSB(timing.hsync_len.typ),
|
||||
®s->raster_timing0);
|
||||
|
||||
writel(LCDC_RASTER_TIMING_1_VBP(timing.vback_porch.typ) |
|
||||
LCDC_RASTER_TIMING_1_VFP(timing.vfront_porch.typ) |
|
||||
LCDC_RASTER_TIMING_1_VSW(timing.vsync_len.typ) |
|
||||
LCDC_RASTER_TIMING_1_VERLSB(timing.vactive.typ),
|
||||
®s->raster_timing1);
|
||||
|
||||
reg = LCDC_RASTER_TIMING_2_ACB(info.ac_bias) |
|
||||
LCDC_RASTER_TIMING_2_ACBI(info.ac_bias_intrpt) |
|
||||
LCDC_RASTER_TIMING_2_HSWMSB(timing.hsync_len.typ) |
|
||||
LCDC_RASTER_TIMING_2_VERMSB(timing.vactive.typ) |
|
||||
LCDC_RASTER_TIMING_2_HBPMSB(timing.hback_porch.typ) |
|
||||
LCDC_RASTER_TIMING_2_HFPMSB(timing.hfront_porch.typ);
|
||||
|
||||
if (timing.flags & DISPLAY_FLAGS_VSYNC_LOW)
|
||||
reg |= LCDC_RASTER_TIMING_2_VSYNC_INVERT;
|
||||
|
||||
if (timing.flags & DISPLAY_FLAGS_HSYNC_LOW)
|
||||
reg |= LCDC_RASTER_TIMING_2_HSYNC_INVERT;
|
||||
|
||||
if (info.invert_pxl_clk)
|
||||
reg |= LCDC_RASTER_TIMING_2_PXCLK_INVERT;
|
||||
|
||||
if (info.sync_edge)
|
||||
reg |= LCDC_RASTER_TIMING_2_HSVS_RISEFALL;
|
||||
|
||||
if (info.sync_ctrl)
|
||||
reg |= LCDC_RASTER_TIMING_2_HSVS_CONTROL;
|
||||
|
||||
writel(reg, ®s->raster_timing2);
|
||||
|
||||
reg = LCDC_RASTER_CTRL_PALMODE_RAWDATA | LCDC_RASTER_CTRL_TFT_MODE |
|
||||
LCDC_RASTER_CTRL_ENABLE | LCDC_RASTER_CTRL_REQDLY(info.fdd);
|
||||
|
||||
if (info.tft_alt_mode)
|
||||
reg |= LCDC_RASTER_CTRL_TFT_ALT_ENABLE;
|
||||
|
||||
if (info.bpp == 24)
|
||||
reg |= LCDC_RASTER_CTRL_TFT_24BPP_MODE;
|
||||
else if (info.bpp == 32)
|
||||
reg |= LCDC_RASTER_CTRL_TFT_24BPP_MODE |
|
||||
LCDC_RASTER_CTRL_TFT_24BPP_UNPACK;
|
||||
|
||||
if (info.raster_order)
|
||||
reg |= LCDC_RASTER_CTRL_DATA_ORDER;
|
||||
|
||||
writel(reg, ®s->raster_ctrl);
|
||||
|
||||
uc_priv->xsize = timing.hactive.typ;
|
||||
uc_priv->ysize = timing.vactive.typ;
|
||||
uc_priv->bpix = log_2_n_round_up(info.bpp);
|
||||
|
||||
err = panel_enable_backlight(panel);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to enable panel backlight\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tilcdc_of_to_plat(struct udevice *dev)
|
||||
{
|
||||
struct tilcdc_priv *priv = dev_get_priv(dev);
|
||||
|
||||
priv->regs = (struct tilcdc_regs *)dev_read_addr(dev);
|
||||
if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
|
||||
dev_err(dev, "failed to get base address\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
dev_dbg(dev, "LCD: base address=0x%x\n", (unsigned int)priv->regs);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tilcdc_bind(struct udevice *dev)
|
||||
{
|
||||
struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
|
||||
|
||||
uc_plat->size = ((LCDC_MAX_WIDTH * LCDC_MAX_HEIGHT *
|
||||
(1 << LCDC_MAX_LOG2_BPP)) >> 3) + 0x20;
|
||||
|
||||
dev_dbg(dev, "frame buffer size 0x%x\n", uc_plat->size);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id tilcdc_ids[] = {
|
||||
{.compatible = "ti,am33xx-tilcdc"},
|
||||
{}
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(tilcdc) = {
|
||||
.name = "tilcdc",
|
||||
.id = UCLASS_VIDEO,
|
||||
.of_match = tilcdc_ids,
|
||||
.bind = tilcdc_bind,
|
||||
.of_to_plat = tilcdc_of_to_plat,
|
||||
.probe = tilcdc_probe,
|
||||
.remove = tilcdc_remove,
|
||||
.priv_auto = sizeof(struct tilcdc_priv)
|
||||
};
|
38
drivers/video/ti/tilcdc.h
Normal file
38
drivers/video/ti/tilcdc.h
Normal file
|
@ -0,0 +1,38 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
|
||||
*/
|
||||
|
||||
#ifndef _TILCDC_H
|
||||
#define _TILCDC_H
|
||||
|
||||
/**
|
||||
* tilcdc_panel_info: Panel parameters
|
||||
*
|
||||
* @ac_bias: AC Bias Pin Frequency
|
||||
* @ac_bias_intrpt: AC Bias Pin Transitions per Interrupt
|
||||
* @dma_burst_sz: DMA burst size
|
||||
* @bpp: Bits per pixel
|
||||
* @fdd: FIFO DMA Request Delay
|
||||
* @tft_alt_mode: TFT Alternative Signal Mapping (Only for active)
|
||||
* @invert_pxl_clk: Invert pixel clock
|
||||
* @sync_edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
|
||||
* @sync_ctrl: Horizontal and Vertical Sync: Control: 0=ignore
|
||||
* @raster_order: Raster Data Order Select: 1=Most-to-least 0=Least-to-most
|
||||
* @fifo_th: DMA FIFO threshold
|
||||
*/
|
||||
struct tilcdc_panel_info {
|
||||
u32 ac_bias;
|
||||
u32 ac_bias_intrpt;
|
||||
u32 dma_burst_sz;
|
||||
u32 bpp;
|
||||
u32 fdd;
|
||||
bool tft_alt_mode;
|
||||
bool invert_pxl_clk;
|
||||
u32 sync_edge;
|
||||
u32 sync_ctrl;
|
||||
u32 raster_order;
|
||||
u32 fifo_th;
|
||||
};
|
||||
|
||||
#endif /* _TILCDC_H */
|
Loading…
Reference in a new issue