Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-28 07:31:15 +00:00
Code Issues Projects Releases Packages Wiki Activity

clk: rockchip: rk3568: add more supported clk rates for sdmmc and emmc

Browse source 
SDHCI driver may attempt to set 26MHz clock, but clk_rk3568
will return error in this case. Apparently, SDHCI silently ignores the
error and as a result eMMC initialization fails.

Add 25 MHz and 26 MHz clk rates for sdmmc and emmc on rk3568 to fix that.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Vasily Khoruzhick 2023-02-23 13:03:32 -08:00 committed by Kever Yang
parent 3a539e0862
commit f0eb365e21
1 changed files with 3 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
drivers/clk/rockchip/clk_rk3568.c
View file

@ -1442,6 +1442,7 @@ static ulong rk3568_sdmmc_set_clk(struct rk3568_clk_priv *priv,
switch (rate) {
case OSC_HZ:
case 26 * MHz:
case 25 * MHz:
src_clk = CLK_SDMMC_SEL_24M;
break;
case 400 * MHz:
@ -1631,6 +1632,8 @@ static ulong rk3568_emmc_set_clk(struct rk3568_clk_priv *priv, ulong rate)
switch (rate) {
case OSC_HZ:
case 26 * MHz:
case 25 * MHz:
src_clk = CCLK_EMMC_SEL_24M;
break;
case 52 * MHz: