Commit graph

22945 commits

Author SHA1 Message Date
Marek Vasut
7e9ce5adf6 net: phy: davicom: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:49 +02:00
Marek Vasut
579f359269 net: phy: cortina: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:48 +02:00
Marek Vasut
227650f0e7 net: phy: ca_phy: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:48 +02:00
Marek Vasut
c00f3f826f net: phy: broadcom: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:48 +02:00
Marek Vasut
761e4060fe net: phy: b53: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:48 +02:00
Marek Vasut
fba31ab92c net: phy: atheros: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:48 +02:00
Marek Vasut
a5fbc10560 net: phy: aquantia: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:48 +02:00
Marek Vasut
4de8644504 net: phy: adin: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:48 +02:00
Marek Vasut
7940a93eb9 net: phy: Iterate over both registered PHYs and struct phy_driver linker list
Introduce U_BOOT_PHY_DRIVER() macro which is used to add struct phy_driver
into a new linker list section containing all compiled in struct phy_driver
drivers. This is so far empty until PHY drivers are converted over to this
macro.

Iterate over both drivers registered using soon to be legacy phy_register()
as well as drivers in the new linker list when looking up a suitable PHY
driver. This way, PHY drivers can be converted over to the new macro one
driver at a time.

The relocation of callbacks for linker list based drivers now happens in
phy_init() call as the drivers are available at that point in time, and
phy_register() is not called for those drivers.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:48 +02:00
Marek Vasut
9d5a38c214 net: phy: Factor manual relocation into separate function
Create separate function to implement manual relocation of PHY driver
functions and make use of that function. This is a preparatory patch
for introduction of PHY driver definition using linker lists.

No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:48 +02:00
Marek Vasut
d1569689c6 net: phy: teranetics: Staticize PHY driver entries
These struct phy_driver ... instances are local to this source code
file, staticize them. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:48 +02:00
Marek Vasut
97c50ab8db net: phy: cortina: Staticize PHY driver entries
These struct phy_driver ... instances are local to this source code
file, staticize them. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:48 +02:00
Marek Vasut
3309c58a0e net: phy: ca_phy: Staticize PHY driver entries
These struct phy_driver ... instances are local to this source code
file, staticize them. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:17:24 +02:00
Marek Vasut
5914bec3f0 net: phy: aquantia: Staticize PHY driver entries
These struct phy_driver ... instances are local to this source code
file, staticize them. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-04-07 14:15:07 +02:00
Rasmus Villemoes
f3bb055ecb serial-uclass: drop redundant code in serial_check_stdout()
As the updated comment says, this is already handled by
fdt_path_offset_namelen() itself.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2023-04-06 19:10:08 -04:00
Heinrich Schuchardt
120ec1dfa9 ata: don't use SYS_SCSI_MAX_SCSI_ID for SATA
CONFIG_SYS_SCSI_MAX_SCSI_ID is not defined if CONFIG_SCSI=n.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-06 19:10:08 -04:00
Heinrich Schuchardt
480c1d6725 ata: fix requirements for CONFIG_AHCI_PCI
Building with CONFIG_AHCI_PCI=y and CONFIG_SCSI_AHCI=n leads to

    drivers/ata/ahci-pci.o: in function `ahci_pci_probe':
    drivers/ata/ahci-pci.c:21: undefined reference to `ahci_probe_scsi_pci'

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-06 19:10:08 -04:00
Corentin Guillevic
1172e258bf spi: Kconfig: add dependency on CONFIG_MPC85xx for FSL_ESPI entry
The Freescale ESPI driver (CONFIG_FSL_ESPI) relies to the MPC85xx platform
(PowerPC) through arch/powerpc/include/asm/immap_85xx.h. The driver can't
compile on another architecture/platform.

Signed-off-by: Corentin Guillevic <corentin.guillevic@smile.fr>
2023-04-06 19:10:08 -04:00
Tobias Waldekranz
762dc78bde blk: blkmap: Add linear device mapping support
Allow a slice of an existing block device to be mapped to a
blkmap. This means that filesystems that are not stored at exact
partition boundaries can be accessed by remapping a slice of the
existing device to a blkmap device.

Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-05 10:54:47 -04:00
Tobias Waldekranz
15d9e99a27 blk: blkmap: Add memory mapping support
Allow a slice of RAM to be mapped to a blkmap. This means that RAM can
now be accessed as if it was a block device, meaning that existing
filesystem drivers can now be used to access ramdisks.

Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-05 10:54:47 -04:00
Tobias Waldekranz
c41e209ea6 blk: blkmap: Add basic infrastructure
blkmaps are loosely modeled on Linux's device mapper subsystem. The
basic idea is that you can create virtual block devices whose blocks
can be backed by a plethora of sources that are user configurable.

This change just adds the basic infrastructure for creating and
removing blkmap devices. Subsequent changes will extend this to add
support for actual mappings.

Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-05 10:54:47 -04:00
Safae Ouajih
bc6413bdd9 drivers: fastboot: zImage flashing is not supported for v3, v4
With vendor boot image introduced in version 3 and 4 of boot
image header, boot information is located in both boot image
and vendor boot image.

Flashing zImage is not supported for version 3 and 4 since this
requires updating vendor boot image and/or generating a new image.

Print an error message when the boot image header version is
greater than 2.

Signed-off-by: Safae Ouajih <souajih@baylibre.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-04-04 14:50:47 -04:00
Safae Ouajih
734cb47d6d android: boot: replace android_image_check_header
With the new vendor boot image introduced in versions 3 and 4
of boot image header, the header check must be done for both boot
image and vendor boot image. Thus, replace android_image_check_header()
by is_android_boot_image_header() to only refer to boot image header check.

Signed-off-by: Safae Ouajih <souajih@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-04-04 14:50:46 -04:00
Safae Ouajih
d71a732af4 android: boot: rename andr_img_hdr -> andr_boot_img_hdr_v0
Android introduced boot header version 3 or 4.
The header structure change with version 3 and 4 to support
the new updates such as:
- Introducing Vendor boot image: with a vendor ramdisk
- Bootconfig feature (v4)

Change andr_img_hdr struct name to maintain support for version v0,
v1 and v2 while introducing version 3 and 4.

Signed-off-by: Safae Ouajih <souajih@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-04-04 14:50:46 -04:00
Tom Rini
02f8486b9f Merge https://source.denx.de/u-boot/custodians/u-boot-usb
- Two USB gadget fixes
2023-04-03 20:49:03 -04:00
Marek Vasut
7f23470885 usb: gadget: f_sdp: Add missing spl_board_prepare_for_boot() call
The spl_board_prepare_for_boot() should be called before jump_to_image_no_args()
to perform board-specific deinitialization before jumping to the next stage.
This board-specific deinitialization can be very much anything, e.g. disable
dcache in case it was enabled, or such.

Add the missing spl_board_prepare_for_boot() call into f_sdp .

Signed-off-by: Marek Vasut <marex@denx.de>
2023-04-04 00:34:42 +02:00
Heinrich Schuchardt
063359444c usb: gadget: missing fallthrough in composite_setup()
Add a missing fallthrough macro. This fixes a -Wimplicit-fallthrough
warning.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-04-04 00:33:32 +02:00
Tom Rini
288fe30a23 Merge branch 'next'
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-04-03 16:45:41 -04:00
Quanyang Wang
d0bb00adcc pinctrl: fix pinctrl_gpio_get_pinctrl_and_offset for gpio-ranges array
Sometimes a multi-element array is used for "gpio-ranges" property in
dts file:

    qe_pio_e: gpio-controller@1460 {
        ......
        gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
        ......
    };

But the function pinctrl_gpio_get_pinctrl_and_offset can't handle this
case because the "index" argument passed to dev_read_phandle_with_args
is fixed to be "0". Use a loop to traverse the array to fix it.

Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
2023-04-03 06:53:53 +12:00
David Sebek
86169cdcb0 rockchip: Fix incorrect constant name in RAM init code
A condition in the rk3399 RAM initialization code used the old
CONFIG_RAM_RK3399_LPDDR4 constant name. This commit changes the
condition to use the correct CONFIG_RAM_ROCKCHIP_LPDDR4 constant.

Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-02 12:57:12 -04:00
Heinrich Schuchardt
854aaf9024 scsi: typo supporedt
%s/supporedt/supported/

Fixes: edca8cf721 ("Convert CONFIG_SCSI_AHCI_PLAT et al to Kconfig")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-01 10:11:50 +02:00
Tom Rini
942ac73afc u-boot-imx-next-20230331 for next
---------------------------------
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/15819
 
 i.MX patches queued for next:
 
 - Conversions to DM_SERIAL
 - Fixes for Toradex boards
 - Gateworks Boards
 - i.MX8ULP
 - EQoS support / fixes, changes in boards
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Merge tag 'u-boot-imx-next-20230331' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next

u-boot-imx-next-20230331 for next
---------------------------------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/15819

i.MX patches queued for next:

- Conversions to DM_SERIAL
- Fixes for Toradex boards
- Gateworks Boards
- i.MX8ULP
- EQoS support / fixes, changes in boards
2023-03-31 12:50:34 -04:00
Jonathan Liu
a47164dfc1 sysreset: gpio: fix gpio_reboot_request return value
It should return -EINPROGRESS if successful otherwise sysreset-uclass
will continue to the next sysreset device.

Signed-off-by: Jonathan Liu <net147@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-31 08:32:52 +13:00
Svyatoslav Ryhel
25df91520e input: button_kbd: make driver complementary to gpio buttons
Remove need of dts binding for button keyboard since it reuses
gpio-keys binding. Select gpio-keys driver if button keyboard
is selected since button keyboard can not operate on its own.

Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-30 15:09:59 -04:00
Chris Packham
0798a1ce0f drivers: rtc: add max313xx series rtc driver
Adding support for Analog Devices MAX313XX series RTCs.

This is ported from the Linux driver and adapted for use in u-boot.
Notable differences are
- handling of tm_year and tm_mon differ
- clock source support is omitted
- hwmon support for the MAX31328 and MAX31343 is omitted
- rtc_ops->reset is added

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-30 15:09:59 -04:00
Rasmus Villemoes
e1c97949ee gpio: allow passing NULL to gpio_request_by_line_name() to search all gpio controllers
The API is more convenient to use if one doesn't have to know upfront
which gpio controller has a line with the name one is searching for,
and arrange to look that device up somehow. Or implement this loop
oneself.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-30 15:09:59 -04:00
Thomas Perrot
fdef6b982f rtc: m41t62: implements read8/write8 operations
These operations are required by dm_rtc_read and
dm_bootcount_get helpers.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-30 15:09:59 -04:00
Stephen Carlson
713db6f6d3 drivers: pci: sandbox: Add stub sandbox PCI MPS support
Reports the sandbox swapcase PCI Express device to support a 256 byte
Maximum Payload Size for MPS tuning tests.

Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-30 15:09:59 -04:00
Rasmus Villemoes
19213d7a65 sysinfo: gpio: fix loop over DT "revisions" array
There can certainly be a lot more elements in the "revisions" (and
"names") arrays than there are gpios used to form the trinary number
we're searching for; we simply don't know the array size up-front.

Nor do we need to, because the loop body already knows to recognize
-EOVERFLOW as "not that many elements present" (and we have a test
that specifically ensures that dev_read_u32_index() returns exactly
that). So just drop the i < priv->gpio_num condition.

While in here, fix the weird placement of the default: keyword.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2023-03-30 15:09:59 -04:00
Tommaso Merciai
f216580b64 clk: imx8mp: add pwm clocks support
Add clocks support for the PWM controllers. This is ported from
Linux v6.3.0-rc1

Signed-off-by: Tommaso Merciai <tomm.merciai@gmail.com>
2023-03-30 13:53:55 +02:00
Marek Vasut
4bdc3524d7 net: fec_mxc: Add board_interface_eth_init() for i.MX8M Mini/Nano/Plus
Implement common board_interface_eth_init() and call it from the FEC
driver to configure IOMUXC GPR[1] register according to the PHY mode
obtained from DT. This supports all three interface modes supported by
the i.MX8M Mini/Nano/Plus FEC and supersedes the current board-side
configuration of the same IOMUX GPR[1] duplicated in the board files.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:47:04 +02:00
Marek Vasut
80a34e4008 net: fec_mxc: Add ref clock setup support for i.MX8M Mini/Nano/Plus
The FEC ref clock frequency on i.MX8M Mini/Nano/Plus was so far configured
via ad-hoc board code. Replace that with DM clock clk_set_rate() instead.
This way, the driver claims all its required clock and sets the ref clock
rate, without any need of architecture specific register fiddling.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:47:04 +02:00
Marek Vasut
f9e950b9bf net: dwc_eth_qos: Add board_interface_eth_init() for i.MX8M Plus
Implement common board_interface_eth_init() and call it from the DWMAC
driver to configure IOMUXC GPR[1] register according to the PHY mode
obtained from DT. This supports all three interface modes supported by
the i.MX8M Plus DWMAC and supersedes current board-side configuration
of the same IOMUX GPR[1] duplicated in the board files.

Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:47:04 +02:00
Marek Vasut
2e9b3014df net: dwc_eth_qos: Add i.MX8M Plus RMII support
With DM clock support in place, it is easy to add RMII support into the
MAC driver. The RMII cannot operate at 1000 Mbps and at 100 and 10 Mbps
the clock frequency is 50 MHz and 5 MHz instead of 25 MHz and 2.5 MHz.

The board DT requires the following adjustments to EQoS node:
  phy-mode = "rmii";
  assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
  			<&clk IMX8MP_SYS_PLL2_100M>,
  			<&clk IMX8MP_SYS_PLL2_50M>;
  assigned-clock-rates = <0>, <100000000>, <50000000>;

Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:47:03 +02:00
Marek Vasut
158456089c net: dwc_eth_qos: Add DM CLK support for i.MX8M Plus
The DWMAC clock in i.MX8M Plus were so far configured via ad-hoc
architecture code. Replace that with DM clock instead. This way,
the driver claims all its required clock, enables and disables
them, and even gets the CSR clock rate and sets the TX clock rate,
without any need of architecture specific register fiddling. Drop
the architecture specific code while at it too.

The adjustment here is modeled after STM32MP15xx clock handling
in this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:47:03 +02:00
Marek Vasut
a79de0808a net: dwc_eth_qos: Set DMA_MODE SWR bit to reset the MAC
The driver currently only waits for DMA_MODE SWR bit to clear itself.
This is insufficient e.g. on i.MX8M Plus, where the MAC must be reset
before IOMUX GPR[1] content is latched into the MAC and used. Without
the proper reset, the i.MX8M Plus MAC variant does not take the value
in IOMUX GPR[1] into account, which makes it impossible e.g. to switch
interface mode from RGMII to any other.

Since proper reset is desired in general to put the block into defined
state, always assert the DMA_MODE SWR bit before waiting for the bit
to clear itself.

Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:47:03 +02:00
Marek Vasut
ac19125f72 net: dwc_eth_qos: Staticize eqos_inval_buffer_tegra186()
This function is only used within the driver, staticize it.

Fixes: 149e80f74b ("net: dwc_eth_qos: public some functions")
Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:47:03 +02:00
Marek Vasut
2e0bade785 net: dwc_eth_qos: Drop unused dm_gpio_free() on STM32
The dm_gpio_free() is never called, because for stm32, the phy_reset_gpio
pointer is never valid. This is because only tegra186 ever claims the
phy_reset_gpio, all other platforms use the PHY framework to reset the
PHY instead. Drop the dm_gpio_free() and dm_gpio_is_valid().

Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:47:03 +02:00
Marek Vasut
895b05ce02 net: dwc_eth_qos: Drop bogus return after goto
The return is never triggered due to the goto just above it.
Drop it. No functional change.

Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:47:03 +02:00
Marek Vasut
6c7e559864 net: Pull board_interface_eth_init() into common code
Move the board_interface_eth_init() into common ethernet uclass code,
since this function could be shared by multiple drivers.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:47:03 +02:00
Marek Vasut
ecb1c37a7b clk: imx8mp: Add EQoS MAC clock
Add clock for the DWMAC EQoS block. This is used among other things
to configure the MII clock via DM CLK.

Acked-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:47:03 +02:00
Jean-Marie Lemetayer
251a3053b1 misc: imx: remove DM dependency for ocotp driver in SPL
The ocotp driver is available for regular and SPL builds using the
(SPL_)MXC_OCOTP configuration. Also, the ocotp driver does not support
the driver model (DM) configuration.

But, for SPL builds, the SPL_MXC_OCOTP configuration depends on
SPL_MISC which implies on SPL_DM.

This commit replaces the dependency on SPL_MISC with SPL_DRIVERS_MISC.
So the only requirement is to have enabled miscellaneous drivers for
the SPL.

Signed-off-by: Jean-Marie Lemetayer <j.lemetayer@kerlink.fr>
2023-03-30 08:40:27 +02:00
Ye Li
69c573ca89 power: pmic: Add NXP PCA9451A PMIC support
PCA9451A uses similar BUCKs and LDO regulators as PCA9450B/C but
has LDO2 and LDO3 removed. So reuse pca9450 PMIC and regulator driver
and add new type for PCA9451A.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-03-30 00:45:39 +02:00
Ye Li
040fc2be78 misc: sentinel: s400_api: Use new command request definitions
Remove legacy command definitions, change to use new ELE_xxx command
request.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29 22:27:38 +02:00
Ye Li
76c184fe3a misc: sentinel: s400_api: Add get_events API
Add get_events API to retrieve any singular events that has occurred
since the FW has started from sentinel

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29 22:27:38 +02:00
Jacky Bai
a29383da72 ddr: imx: Update the ddr init flow on imx8ulp
Update the ddr init flow to support LPDDR3 and PLL bypass mode.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
2023-03-29 20:15:42 +02:00
Ye Li
39f700e801 misc: fuse: Lock 8ULP ECC-protected fuse when programming
The ECC fuse on 8ULP can't be written twice. If any user did it, the
ECC value would be wrong then cause accessing problem to the fuse.
The patch will lock the ECC fuse word to avoid this problem.
For iMX9, the OTP controller automatically prevents an ECC fuse word to
be written twice. So it does not need the setting.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29 20:15:42 +02:00
Ye Li
fff11619a1 misc: fuse: Update fuse mapping for 8ULP S400 API
Since new 8ULP A1 S400 FW (v0.0.8-e329b760) can support to read
more fuses: like PMU trim, Test flow/USB, GP1-5, GP8-10. Update
the u-boot driver for the new mapping.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Alice Guo <alice.guo@nxp.com>
2023-03-29 20:15:42 +02:00
Ye Li
b36756c769 ddr: imx8ulp: Change DRAM timing save area to 0x20055000
To align with ARM trusted firmware's change, adjust DRAM timing
save area to new position 0x20055000. So we can release the space
since 0x2006c000 for the NOBITS region of ARM trusted firmware

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2023-03-29 20:15:42 +02:00
Janne Grunau
6ee2c8ad58 pci: apple: Initialize only enabled ports
The Linux devicetrees for Apple silicon devices are after review
feedback switching from deleting unused PCIe ports to disabling them.

Link: https://lore.kernel.org/asahi/1ea2107a-bb86-8c22-0bbc-82c453ab08ce@linaro.org/
Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
2023-03-29 13:30:29 -04:00
Sinthu Raja
3d0f2e37c5 phy: ti: j721e-wiz: Add support to enable LN23 Type-C swap
The WIZ acts as a wrapper for SerDes and has Lanes 0 and 2 reserved
for USB for type-C lane swap if Lane 1 and Lane 3 are linked to the
USB PHY that is integrated into the SerDes IP. The WIZ control register
has to be configured to support this lane swap feature.

The support for swapping lanes 2 and 3 is missing and therefore
add support to configure the control register to swap between
lanes 2 and 3 if PHY type is USB.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2023-03-29 13:30:29 -04:00
Sinthu Raja
75b6cd97dd phy: ti: j721e-wiz: Manage TypeC lane swap if typec-dir-gpios not specified
It's possible that the Type-C plug orientation on the DIR line will be
implemented through hardware design. In that situation, there won't be
an external GPIO line available, but the driver still needs to address
this since the DT won't use the typec-dir-gpios property.

Add code to handle LN10 Type-C swap if typec-dir-gpios property is not
specified in DT.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2023-03-29 13:30:29 -04:00
Tom Rini
654483d251 First set of u-boot-at91 features for the 2023.07 cycle
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Merge tag 'u-boot-at91-2023.07-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next

First set of u-boot-at91 features for the 2023.07 cycle:

This feature set includes the clock changes required for sam9x60 SoC to
support USB host.
2023-03-28 11:21:29 -04:00
Tom Rini
605bc145f9 Merge branch 'master' into next 2023-03-27 15:19:57 -04:00
Sergiu Moga
c544e8181a clk: at91: sam9x60: Add initial setup of UPLL and USBCK rates
In order for some of the functionalities, such as the USB clocks,
to work properly we need some clocks to be properly initialised
at the very beginning of booting.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2023-03-27 14:27:37 +03:00
Claudiu Beznea
248e41002b clk: at91: pmc: export clock setup to pmc
Clock setup was intended for setting clocks at boot time on SAMA7G5,
e.g. for root clocks like PLLs, that were used to feed IPs needed alive
in u-boot (e.g. Ethernet clock feed by a PLL). Export this functionality
to all at91 clocks as it may be necessary on other SoCs.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2023-03-27 14:27:37 +03:00
Sergiu Moga
c88a925a3a clk: at91: sam9x60: Register the required clocks for USB
Register into DM the clocks required to properly enable USB functionality
within the bootloader.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2023-03-27 14:27:37 +03:00
Sergiu Moga
0a0f0e737b clk: at91: Add support for sam9x60 USB clock
Implement sam9x60 USB clock driver. This clock has
three parents: PLLA, UPLL and MAINXTAL. The driver is
aware of the three possible parents with the help of the
two mux tables provied to the driver during the registration
of the clock.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2023-03-27 14:27:37 +03:00
Tom Rini
78f67f11a9 Merge branch 'rpi-2023.04' of https://source.denx.de/u-boot/custodians/u-boot-raspberrypi
- Fixes for booting newer revs of the SoC in the Raspberry Pi 4
- Propagate some firmware DT properties to the loaded DT
- Update the Zero2W upstream DT name
2023-03-24 17:00:41 -04:00
Vincent Fazio
85bdd28d2b mmc: bcm2835-host: let firmware manage the clock divisor
Newer firmware can manage the SDCDIV clock divisor register, allowing
the divisor to scale with the core as necessary.

Leverage this ability if the firmware supports it.

Adapted from the following raspberrypi Linux kernel commit:

  bcm2835-sdhost: Firmware manages the clock divisor
  08532d242d

Signed-off-by: Vincent Fazio <vfazio@xes-inc.com>
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
2023-03-24 14:43:20 +00:00
Pali Rohár
e6900565b5 ddr: marvell: a38x: Remove unused file seq_exec.h
DDR code does not use seq_exec.h, so remove it.

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-24 13:11:47 +01:00
Vignesh Raghavendra
f8461352b8 dma: ti: k3-udma: Fix channel hang on teardown
Setting RX flow error handling will stall the channel until descriptors
are available to move RX data. Setting this bit causes issues when
tearing down ethernet DMA channel at the end of TFTP transfer as
unrelated network packets can cause teardown to stall indefinitely waiting
for driver to queue add more desc leading to channel hang with error
logs:
udma_stop_dev2mem TIMEOUT !
udma_stop_dev2mem: peer not stopped TIMEOUT !
udma_stop_dev2mem TIMEOUT !

Fix this by clearing rx_error_handling similar to how its done for UDMA
as part of udma_alloc_rchan_sci_req()

This fixes occasional TFTP Failures seen when downloading multiple files
one after the other on AM64/AM62 SoCs.

Fixes: 9a92851c33 ("dma: ti: k3-udma: Add BCDMA and PKTDMA support")
Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-03-22 12:51:15 -04:00
Tom Rini
e37be8484f Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
A single reset controller driver (part of the clock driver) fix
for v2023.04 release.
2023-03-21 11:52:55 -04:00
Marek Vasut
afafaa2a8f clk: renesas: Pack reset identifier before look up
The reset identifier must be processed via MOD_CLK_PACK() before it is
used to look up register and bit within reset_regs or reset_clear_regs
arrays, otherwise completely bogus register and bit is picked from the
arrays, one which may even be out of range.

Fixes: 326e05c5e2 ("clk: renesas: Add and enable CPG reset driver")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-20 02:46:44 +01:00
Johan Jonker
791c7ac792 rockchip: timer: rockchip_timer: fix compatible and driver name
In the binding for the Rockchip timer the compatible string
consists of a SoC orientated string and a fall back string
"rockchip,rk3288-timer", so remove all unneeded ones and
fix driver name.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-03-19 14:12:01 +08:00
Vasily Khoruzhick
2321a991bb rockchip: sdhci: rk3568: bypass DLL when clk <= 52 MHz
For Rockchip platform, DLL bypass bit and start bit need to be set if
DLL is not locked.

With this change applied eMMC in my NanoPi R5S can run at 52 MHz.

Based on linux commit b75a52b0dda3 ("mmc: sdhci-of-dwcmshc: Update DLL
and pre-change delay for rockchip platform")

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-03-19 14:12:00 +08:00
Vasily Khoruzhick
4340771323 clk: rockchip: rk3568: add stubs for CLK_PCIEPHY_REF clocks
Device tree contains assigned-clock-rates property for these,
but default value will work just fine

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2023-03-19 14:12:00 +08:00
Jonas Karlman
d11f0dac30 mmc: rockchip_dw_mmc: Fix get_mmc_clk return value
The get_mmc_clk ops is expected to set a clock rate and return the
configured rate as an unsigned value. However, if clk_set_rate fails,
e.g. using a fixed rate clock, a negative error value is returned.

The mmc core will treat this as a valid unsigned rate and tries to
configure a divider based on this bogus clock rate.

Use 0 as the return value when setting clock rate fails, the mmc core
will configure to use bypass mode instead of using a bogus divider.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-03-19 13:20:21 +08:00
Jonas Karlman
67a1d773e7 clk: rockchip: rk3588: Fix clk_aux16m in clock driver
The rate and error value is not returned for aux16m clocks, fix this.

Fixes: 7a474df740 ("clk: rockchip: Add rk3588 clk support")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-03-19 13:17:28 +08:00
Peter Geis
a67e219d0c clk: rockchip: rk3568: Fix reset handler
The reset handler for rk3568 is missing its private data. This leads to
an abort when a reset is triggered.

  => reset
  resetting ...
  "Synchronous Abort" handler, esr 0x96000045
  elr: 0000000000a2bc04 lr : 0000000000a2bbd4 (reloc)
  elr: 00000000eff9bc04 lr : 00000000eff9bbd4
  x0 : 00000000fdd20000 x1 : 0000000014000001
  x2 : 000000000000fdb9 x3 : 00000000edf77e88
  x4 : 00000000edf50e78 x5 : 00000000edf77530
  x6 : 000000000000001d x7 : 00000000edf8a1d0
  x8 : 00000000ffffffd8 x9 : 0000000000000008
  x10: 000000000000000d x11: 0000000000000006
  x12: 000000000001869f x13: 0000000086c290c5
  x14: 000000009118e878 x15: 0000000000000000
  x16: 00000000eff9bbb8 x17: 0000000012f8c119
  x18: 00000000edf50dc0 x19: 0000000000000000
  x20: 0000000000000001 x21: 0000000000000000
  x22: 00000000edf85900 x23: 0000000000000001
  x24: 00000000effe8bbc x25: 0000000000000000
  x26: 00000000edf85940 x27: 0000000000000000
  x28: 0000000000000000 x29: 00000000edf3c8e0

  Code: d65f03c0 d5033fbf b9400661 529d9502 (b8216802)
  Resetting CPU ...

Add the missing dev_set_priv to the rk3568 clk driver to fix this.

Fixes: 4a262feba3 ("rockchip: rk3568: add clock driver")
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # radxa-cm3
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-03-19 13:17:28 +08:00
Marek Vasut
6254c5f7e1 serial: sh: Make indent consistent
Make the indent of these macro elements consistent with the
rest of this table. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18 12:04:02 +01:00
Marek Vasut
836d1bfffa serial: sh: Add DEBUG_UART support
Add support for debug output very early during boot using the DEBUG_UART
mechanism. This uses a static fixed UART port configuration selected via
Kconfig options and dedicated print functions from debug_uart.h. This is
useful e.g. when debugging problems so early during boot, that not even
the DM is initialized at that point, and thus DM_SERIAL is not available
either.

This functionality is disabled by default. To activate it, define the
following Kconfig options and select SCIF type using CFG_SCI/CFG_SCIF_A/
CFG_HSCIF/<nothing for regular SCIF>:

CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_SCIF=y
CONFIG_DEBUG_UART_BASE=0xe6540000
CONFIG_DEBUG_UART_CLOCK=24000000

The later two options define the SCIF physical base address and SCIF
input clock in Hz. Optionally, to validate DEBUG_UART works, enable
the following as well to get early serial output message by default:

CONFIG_DEBUG_UART_ANNOUNCE=y

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18 12:04:02 +01:00
Marek Vasut
5e12d7d00b serial: sh: Rename CONFIG_SCI and CONFIG_SCIF_USE_EXT_CLK to CFG_ variants
Both CONFIG_SCI and CONFIG_SCIF_USE_EXT_CLK options do not have a
matching Kconfig entry because they are internal to the SCIF driver.
Change their prefix to CFG_, i.e. CFG_SCIF_USE_EXT_CLK and CFG_SCI,
to reflect that and avoid interferring with Kconfig symbols. Since
neither of those options are defined elsewhere, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18 12:04:02 +01:00
Marek Vasut
517f8e8aee pinctrl: renesas: Replace ifdeffery with IS_ENABLED()
Switch ifdef in sh_gpio_get_value() to IS_ENABLED() macro.
The CONFIG_RCAR_GEN3 will never have SPL counterpart, so
the IS_ENABLED() macro is the right one here. No functional
change, except for improved build test coverage.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18 12:02:38 +01:00
Mikhail Lappo
d797a8ccb2 net: ravb: Support fixed PHY in R-Car
Calling old U-Boot API doesn't allow to use fixed PHY.
Searching by mask is the part of new function, after
scanning FDT for a fixed PHY definition

Fixes: e821a7bdb1 ("net: ravb: Detect PHY correctly")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Mikhail Lappo <mikhail.lappo@esrlabs.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
[Hai Pham: Drop phy_connect_dev since it's called in phy_connect]
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Use mask -1 instead of 0 to reinstate the search behavior
        over all PHY addresses. Add Fixes tag, sort the tag list.]
2023-03-18 12:02:38 +01:00
Marek Vasut
495211a489 i2c: rcar_i2c: Sort Kconfig depends list ascending
Sort the list of "depends" symbols in ascending order.
No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2023-03-18 12:02:38 +01:00
Marek Vasut
61eb551f3a i2c: rcar_iic: Sort Kconfig depends list ascending
Sort the list of "depends" symbols in ascending order.
No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2023-03-18 12:02:38 +01:00
Marek Vasut
99c7e03119 clk: renesas: rcar-gen3: Replace SSCG caching with MDSEL/PE caching
Do not cache the single CPG MODE register bit 12, instead cache the
entire register value, and only pick the matching bit from the cached
value when core clock of type MDSEL or PE are used. Both MDSEL and PE
clock type currently define .offset field as 12 on Gen3, which means
this code will use bit 12 on Gen3 again, however there are additional
clock on Gen4 which use different bits, and having this flexibility
in place now will be useful when adding Gen4.

No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18 12:02:38 +01:00
Tom Rini
cefd0449d6 Xilinx changes for v2023.07-rc1
cmd:
 - Print results in hex instead of dec in smc command
 
 firmware:
 - Cover missing ZYNQMP_FIRMWARE dependencies
 
 fpga:
 - fix loads for unencrypted use case
 
 relocation
 - Add support for BE systems
 
 spi:
 - Fix xilinx_spi init reset sequence
 
 arasan nand:
 - Remove hardcoded bbt option
 - Set ofnode value
 
 xilinx:
 - Enable SMC command
 - Fix some sparse issues
 
 zynqmp:
 - Remove cdns,zynq-gem compatible string
 - Add optee node
 - Some DT cleanups
 
 zynq:
 - Some DT cleanups
 
 microblaze
 - Remove MANUAL_RELOC option
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Merge tag 'xilinx-for-v2023.07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2023.07-rc1

cmd:
- Print results in hex instead of dec in smc command

firmware:
- Cover missing ZYNQMP_FIRMWARE dependencies

fpga:
- fix loads for unencrypted use case

relocation
- Add support for BE systems

spi:
- Fix xilinx_spi init reset sequence

arasan nand:
- Remove hardcoded bbt option
- Set ofnode value

xilinx:
- Enable SMC command
- Fix some sparse issues

zynqmp:
- Remove cdns,zynq-gem compatible string
- Add optee node
- Some DT cleanups

zynq:
- Some DT cleanups

microblaze
- Remove MANUAL_RELOC option
2023-03-16 12:18:30 -04:00
Tom Rini
f6546c7822 Revert 9f62a472df ("video: Remove duplicate cursor-positioning function")
This reverts commit 9f62a472df.

The changes here aren't quite right, and on platforms such as Raspberry
Pi where we can have both serial and video output, the change above
causes output to change. This can be seen as the hush tests we have now
fail.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-16 12:17:02 -04:00
Tom Rini
a5faa4a9eb Prepare v2023.04-rc4
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Merge tag 'v2023.04-rc4' into next

Prepare v2023.04-rc4

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-03-14 12:06:35 -04:00
Simon Glass
a76b60f820 video: Clear the vidconsole rather than the video
It is better to clear the console device rather than the video device,
since the console has the text display. We also need to reset the cursor
position with the console, but not with the video device.

Add a new function to handle this and update the 'cls' command to use it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13 13:53:01 +01:00
Simon Glass
9f62a472df video: Remove duplicate cursor-positioning function
There are two functions for positioning the cursor on the console. Remove
one of them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13 13:53:01 +01:00
Simon Glass
315e367977 video: Allow a copy framebuffer with pre-allocated fb
At present it is not possible for the video driver to use a pre-allocated
frame buffer (such as is done with EFI) with the copy framebuffer. This
can be useful to speed up the display.

Adjust the implementation so that copy_size can be set to the required
size, with this being allocated if the normal framebuffer size is 0.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13 13:53:01 +01:00
Simon Glass
f62229227c efi: Support copy framebuffer
Add support for this to EFI in case it becomes useful. At present it just
slows things down. You can enable CONFIG_VIDEO_COPY to turn it on.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13 13:53:01 +01:00
Simon Glass
4f9a8f33f0 efi: Use a fixed value for the timer clock
It is not yet clear how to read the timer via EFI. The current value seems
much too high on a Framework laptop I tried. Adjust it to a lower
hard-coded value for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13 13:53:01 +01:00
Simon Glass
644e61448c efi: Support a 64-bit frame buffer address
The current vesa structure only provides a 32-bit value for the frame
buffer. Many modern machines use an address outside the range.

It is still useful to have this common struct, but add a separate
frame-buffer address as well.

Add a comment for vesa_setup_video_priv() while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13 13:53:01 +01:00
Simon Glass
57fa418224 efi: video: Return mode info for app also
The mode info is currently not initialised for the app. Fix this by
returning it from the function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13 13:53:01 +01:00
Simon Glass
88753816cf efi: video: Move payload code into a function
Put this into a function, as we have done for the app implementation.
Comment both functions. FOr now the app still does not access it
correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13 13:53:01 +01:00
Tom Rini
1247fc7de8 Merge https://source.denx.de/u-boot/custodians/u-boot-usb
Two minimal Kconfig/Makefile fixes for USB.
2023-03-10 19:10:14 -05:00
Tam Nguyen
c8eaebb426 ARM: dts: renesas: Enable sysinfo on R-Car V3H Condor/Condor-I
Add new sysinfo IDs for R-Car V3H Condor/Condor-I .

Enable support for sysinfo on R-Car V3H Condor/Condor-I. The sysinfo is
used e.g. to access and decode board-specific information and then in
turn used by board-info to print those information.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Drop compatible from I2C node, this is in r8a77980.dtsi already.
        Drop status = "okay" from EEPROM node.
	Add dts: tag.
	Update the commit message, note the new sysinfo IDs.
	Fix Kconfig EEPROM address to be 0x50 and match the DT, sync config.]
2023-03-10 17:46:09 +01:00
Tam Nguyen
b791b9cf55 sysinfo: rcar3: Fix Draak and Eagle board code
Correct the board code ID based on the hardware documentation

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10 17:46:09 +01:00
Marek Vasut
ce46817215 pinctrl: renesas: Drop non-existent PFC info table entries
Remove PFC info table entries which are never instantiated,
since there are no drivers for those. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10 17:46:09 +01:00
Marek Vasut
3efdf01fa4 clk: renesas: Always select DM_RESET to prevent inobvious failure of rst_gen3 subdriver
The CLK_RCAR_GEN3 registers two subdrivers, clk_gen3 and rst_gen3.
The former depends on the clock framework, which is always enabled
in this context of clock framework driver, while the later depends
on reset framework which may not always be enabled.

Ensure the reset framework is also always enabled to prevent inobvious
early boot time bind failure of the CPG driver, which leads to system
showing no activity and is difficult to debug.

Note that one possible approach to debug this is to use CONFIG_DEBUG_UART
and add debug printascii()s into the drivers/clk/renesas/clk-rcar-gen3.c .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10 17:46:09 +01:00
Marek Vasut
f20a61af42 mmc: renesas-sdhi: Add proper probe error fail path
In case one of the calls in probe fail, trigger a fail path and
undo all the steps done in probe until the point of failure.
The current implementation failed to stop controller clock and
free claimed clock, so fix that. Furthermore, print return code
in error prints for easier debugging.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10 17:45:47 +01:00
Marek Vasut
6ddffa89cb mmc: renesas-sdhi: Always configure default SDnH clock rate to 800 MHz
The prior stage bootloader might have left the SDnCKCR register in completely
arbitrary state before passing control to U-Boot, which includes the register
being populated with incorrect values. Currently the SDHI driver will attempt
to use clock framework to configure SDn clock, which may fail in case SDnCKCR
contains invalid values for the SDnH clock, because the clock framework would
not be able to determine SDnH clock rate and would get -EINVAL instead, which
in turn would not allow the clock framework to determine the correct SDn clock
divider ratio.

This failure occurs specifically in case SDnCKCR reads back 0x209 .

Correct the problem by first setting default SDnH clock rate to 800 MHz, thus
assuring the SDnCKCR SDnH bits are correct, and only afterward set up the SDn
clock rate to default 200 MHz.

Note that the SDHI driver may reconfigure SDnH clock later based on IOS
settings obtained from the attached card, the 800 MHz set up here is only
the default value.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10 17:45:47 +01:00
Heinrich Schuchardt
4042ce73c8 usb: move CONFIG_USB_HUB_DEBOUNCE_TIMEOUT to USB
This configuration setting is only relevant if the board supports USB.
It should not be in the main menu but in the USB menu.

The setting is only relevant in USB host mode.

Fixes: 5454dea313 ("usb: hub: allow to increase HUB_DEBOUNCE_TIMEOUT")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-03-10 17:31:31 +01:00
Algapally Santosh Sagar
cc24fd7859 xilinx: zynqmp: Add missing prototype for zynqmp_mmio_write
Add missing prototype to fix the sparse warning, warning: no
previous prototype for 'zynqmp_mmio_write' [-Wmissing-prototypes].

Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230301103334.1455-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09 13:15:00 +01:00
Ashok Reddy Soma
1e01769a2d mtd: nand: arasan: Set ofnode value
Ofnode value is not set, so all the DT properties are not being read
and due to this default values are being used.

Find nand node and set chip->flash_node value.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230224050709.30014-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09 13:15:00 +01:00
Ashok Reddy Soma
437d77f16b mtd: nand: arasan: Remove hardcoded bbt option
Bad block table option is hardcoded to read from flash with
NAND_BBT_USE_FLASH option. This decision should be done based on DT
property. Remove this hardcoding, to be able to use DT property.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230224050709.30014-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09 13:15:00 +01:00
Jiajie Chen
4fffbc1108 spi: xilinx_spi: Fix spi reset
It was incorrectly using an old priv->regs pointer, which was
initialized to zero. SPI resets won't happen on first call.

Signed-off-by: Jiajie Chen <c@jia.je>
Link: https://lore.kernel.org/r/20230227150938.211820-1-c@jia.je
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09 13:15:00 +01:00
Neal Frager
749cbcfeac fpga: zynqmppl: fix fpga loads command for unencrypted use case
When using the fpga loads command, the driver is passing the AES encryption
key address is all cases.  However, for the authenticated, but not encrypted
use case, there is no AES encryption key, and this value is 0.

When AES encryption is not used on the fpga bitstream, the pmufw assumes that
the AES key address is a bitstream size value like what is used by the
unsecure fpga load command.

To fix the problem, this patch checks to see if the AES key address is zero.
If the AES key address is zero, it means that AES is not being used on the
bitstream and the bitstream size should be passed instead.  Thus, matching
the fpga load functionality.

Signed-off-by: Neal Frager <neal.frager@amd.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230214131959.40298-1-neal.frager@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09 13:15:00 +01:00
Algapally Santosh Sagar
6d87b1572f arm64: zynqmp: Add missing ZYNQMP_FIRMWARE dependencies
There are missing Kconfig dependencies in the code which is using
firmware interface.
The commit 71efd45a5f ("arm64: zynqmp: Change firmware dependency")
add option to also disable ZYNQMP_FIRMWARE. But not all Kconfig
dependencies were properly described and also sdhci and gem drivers
didn't protect the code properly.
So, add the missing ZYNQMP_FIRMWARE dependencies.

Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230201095553.11219-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09 13:14:59 +01:00
Tom Rini
70ed05ce6c - video console refactoring and optimization
- support for fonts wider than 1 byte
  - use named header for 8x16 font data
  - support multiple fonts configuration
  - move get_font_size() to truetype driver ops
  - support font size configuration at runtime
  - add 16x32 Terminus font from linux
  - add 12x22 Sun font from linux
  - add 12x22 console simple font test
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Merge tag 'next-20230307' of https://source.denx.de/u-boot/custodians/u-boot-video into next

 - video console refactoring and optimization
 - support for fonts wider than 1 byte
 - use named header for 8x16 font data
 - support multiple fonts configuration
 - move get_font_size() to truetype driver ops
 - support font size configuration at runtime
 - add 16x32 Terminus font from linux
 - add 12x22 Sun font from linux
 - add 12x22 console simple font test
2023-03-07 12:54:01 -05:00
Dzmitry Sankouski
0d6c089f84 video console: add 16x32 Terminus font from linux
Modern mobile phones typically have high pixel density.
Bootmenu is hardly readable on those with 8x16 font.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-07 15:59:58 +01:00
Dzmitry Sankouski
e24db8645f video console: add 12x22 Sun font from linux
Modern mobile phones typically have high pixel density.
Bootmenu is hardly readable on those with 8x16 font.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-07 15:59:47 +01:00
Dzmitry Sankouski
e7ee1fd567 video console: allow font size configuration at runtime
Allow font size configuration at runtime for console_simple.c
driver. This needed for unit testing different fonts.

Configuring is done by `font` command, also used for font
selection in true type console.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-07 15:59:35 +01:00
Dzmitry Sankouski
4f6e34811d video console: move vidconsole_get_font_size() logic to driver ops
Since multiple vidconsole drivers exists, vidconsole_get_font_size()
implementation cannot longer live in vidconsole_uclass.c file.

Move current vidconsole_get_font_size logic to truetype driver ops.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-07 15:59:21 +01:00
Dzmitry Sankouski
39c1fa2c21 video console: implement multiple fonts configuration
This needed for unit testing different fonts.

Configured fonts are placed in an array of fonts.
First font is selected by default upon console probe.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[agust: fixed build error when bmp logo disabled]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2023-03-07 15:57:19 +01:00
Dzmitry Sankouski
02db4ec902 video console: add support for fonts wider than 1 byte
Devices with high ppi may benefit from wider fonts.

Current width implementation is limited by 1 byte, i.e. 8 bits.
New version iterates VIDEO_FONT_BYTE_WIDTH times, to process all
width bytes, thus allowing fonts wider than 1 byte.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-07 13:26:08 +01:00
Dzmitry Sankouski
3154725949 video console: refactoring and optimization
- move common code to vidconsole_internal.h and console_core.c
- unite probe functions
- get rid of code duplications in switch across bpp values
- extract common pixel fill logic in two functions one per
horizontal and vertical filling
- rearrange statements in put_xy* methods in unified way
- replace types - uint*_t to u*

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-07 13:26:08 +01:00
Patrick Delaunay
e67b1f4dde mmc: remove SDHCI SPEAR
As the file spear_sdhci.c file is already removed, delete the associated
configuration CONFIG_MMC_SDHCI_SPEAR.

Fixes: c942fc925e ("mmc: spear: remove the entire spear_sdhci.c file")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-03-06 17:03:56 -05:00
Dylan Hung
95f7955384 clk: ast2600: Keep PLL power on
According to the PLL vendor, we should keep the PLL power on, so we
shouldn't toggle the power-down bit during PLL initialization.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
2023-03-06 17:03:56 -05:00
Dylan Hung
45443f6089 ram: ast2600: Keep MPLL power on
According to the PLL vendor, we should keep the PLL power on, so we
shouldn't toggle the power-down bit during PLL initialization.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
2023-03-06 17:03:56 -05:00
Sergei Antonov
2c0bdcacf3 timer: fttmr010: return a previously deleted driver now ported to DM
The fttmr010 timer driver was deleted by
commit 29fc6f2492 ("ARM: remove a320evb board support")
The original source file was: arch/arm/cpu/arm920t/a320/timer.c

Return the driver to the codebase in a DM compatible form.
A platform using fttmr010 will be submitted later.

This hardware is described in the datasheet [1], starting from page 348.
According to the datasheet, there is a Revision Register at offset 0x3C,
which is not present in 'struct fttmr010'. Add it and debug() print
revision in probe function.

[1]
https://bitbucket.org/Kasreyn/mkrom-uc7112lx/src/master/documents/FIC8120_DS_v1.2.pdf

Signed-off-by: Sergei Antonov <saproj@gmail.com>
2023-03-06 17:03:56 -05:00
Tom Rini
d1653548d2 Merge branch '2023-03-02-kconfig-and-CONFIG-cleanups' into next
- Partial merge of a series of mine to select some framework options
  that shouldn't be prompted for (and remove some unused code related to
  that), and a partial merge of a series from Simon to remove some dead
  code and address various CONFIG_IS_ENABLED/IS_ENABLED issues in code.
2023-03-03 12:48:23 -05:00
Simon Glass
fd3753593a dm: Add a TPL symbol for simple-bus
This is used in some x86 code, so add a symbol for it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-03 09:49:02 -05:00
Simon Glass
e6c5205d64 net: Add an SPL config for atheros
Add a new SPL_PHY_ATHEROS to avoid a build error on am335x_evm with split
config.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-03-03 09:49:02 -05:00
Simon Glass
c7d53f027b sandbox: Tidy up I2C options
At present we enable the sandbox I2C driver for all builds. Add a separate
Kconfig option to control this, so that it can be disabled in TPL, where
it is not needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2023-03-02 17:45:58 -05:00
Simon Glass
dd8a29040d sandbox: Tidy up RTC options
At present we enable the sandbox RTC driver for all builds. Add a separate
Kconfig option to control this, so that it can be disabled in TPL, where
it is not needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-02 17:45:58 -05:00
Simon Glass
b51b1a8442 Correct SPL uses of PHY_FIXED
This converts 3 usages of this option to the non-SPL form, since there is
no SPL_PHY_FIXED defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-02 17:45:58 -05:00
Simon Glass
b07be4a8a2 Correct SPL uses of MULTIPLEXER
This converts 3 usages of this option to the non-SPL form, since there is
no SPL_MULTIPLEXER defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-03-02 17:45:58 -05:00
Simon Glass
1be3077e71 Correct SPL uses of DISPLAY_AER_FULL
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_DISPLAY_AER_FULL defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-02 17:45:57 -05:00
Simon Glass
f1692c97ea sh4: Drop unused twl6030 driver
This is not used. Drop the driver and Kconfig option.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-02 17:45:57 -05:00
Simon Glass
83431d1474 mtd: Drop unused kb9202_nand driver
This is not used since time out of mind.

Drop the driver and Kconfig option.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Michael Trimarchi <michael@amarulasolutions.com>
2023-03-02 17:45:57 -05:00
Chunfeng Yun
b2eff0340d usb: xhci-mtk: modify the SOF/ITP interval for mt8195
There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
exclude IP0) have a wrong default SOF/ITP interval which is
calculated from the frame counter clock 24Mhz by default, but
in fact, the frame counter clock is 48Mhz, so we shall set the
accurate interval according to 48Mhz for those controllers.

Note:
The first controller no need set it, but if set it, shall change
tphy's pll at the same time.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-03-02 22:43:43 +01:00
Chunfeng Yun
39b854ae86 phy: phy-mtk-tphy: add support mt8195
The T-PHY controller is designed to use use PLL integer mode, but
in fact use fractional mode for some ones on mt8195 by mistake,
this causes signal degradation (e.g. eye diagram test fail), fix
it by switching PLL to 26Mhz from default 48Mhz to improve signal
quality.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2023-03-02 22:43:43 +01:00
Chunfeng Yun
5241fc8dbf phy: phy-mtk-tphy: remove macros to prepare bitfield value
Prefer to make use of FIELD_PREP() macro to prepare bitfield value,
then no need local macros anymore.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2023-03-02 22:43:43 +01:00
Marek Vasut
e61eaee91c usb: dwc3-meson-g12a: Select PHY instead of imply PHY
Imply means you can turn off the option and expect things to work
- "it's a good idea to have X enabled" is when to use imply
- "you must have X for Y to work" is when to use select

Use "select" here.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-03-02 22:42:27 +01:00
Heinrich Schuchardt
d22c695249 sandbox: fix building with CONFIG_SPL_TIMER=y
Building sandbox_defconfig with CONFIG_SPL_TIMER=y results in an error

    include/dm/platdata.h:63:33: error: static assertion failed:
    "Cannot use U_BOOT_DRVINFO with of-platdata.
    Please use devicetree instead"

Add a missing condition in the sandbox driver.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-01 11:22:40 -07:00
Robert Marko
1de76a4535 arm64: a37xx: pinctrl: probe after binding
Currently, pinctrl drivers are getting probed during post-bind, however
that is being reverted, and on A37XX pinctrl driver is the one that
registers the GPIO driver during the probe.

So, if the pinctrl driver doesn't get probed GPIO-s won't get registered
and thus they cannot be used.

This is a problem on the Methode eDPU as it just uses SB pins as GPIO-s
and without them being registered networking won't work as it only has
one SFP slot and the TX disable GPIO is on the SB controller.

So, lets just add a flag only to A37XX driver to probe after binding
in order for the GPIO driver to always get registered.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-01 11:22:27 -07:00
Pali Rohár
67bd6158d4 arm: mvebu: Add support for generating NAND kwbimage
Add a new Kconfig option CONFIG_MVEBU_SPL_BOOT_DEVICE_NAND which instruct
make to generate kwbimage with NAND header. This image is used for booting
from NAND flash (either SPI or parallel).

Support is very simple, SPL after finishes DDR training returns back to the
BootROM (via CONFIG_SPL_BOOTROM_SUPPORT option) and BootROM then loads and
executes U-Boot proper.

To generate correct kwbimage NAND header, it is required to set following
Kconfig options:

CONFIG_SYS_NAND_PAGE_SIZE
CONFIG_SYS_NAND_BLOCK_SIZE
CONFIG_MVEBU_SPL_NAND_BADBLK_LOCATION

They are used only by make / mkimage when generating final kwbimage.

CONFIG_MVEBU_SPL_NAND_BADBLK_LOCATION is a new mvebu specific Kconfig
option which is set into kwbimage NAND_BADBLK_LOCATION header field.

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Tom Rini
f10905b4b7 TPM auto startup and testing
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Merge tag 'tpm-next-28022023' of https://source.denx.de/u-boot/custodians/u-boot-tpm into next

TPM auto startup and testing:

Due to U-Boot's lazy binding we always relied on command line tools to
initialize the TPM subsystem and devices.  One exception is the EFI
subsystem.  When compiled with TCG2 measured boot support the TPM was
automatically initialized.

However that init was not complete.  The TCG specs [0] (and specifically
§12.3 Self-test modes) describe how self-tests on the device should be
performed.  This PR is adding an extra API function, that can be used to
initialize the TPM2.0 properly.

Simon added the equivalent for TPM1.2 and refactored the DM tests to
include the new funtion.

[0] https://trustedcomputinggroup.org/wp-content/uploads/TPM-Rev-2.0-Part-1-Architecture-01.07-2014-03-13.pdf
2023-02-28 09:50:16 -05:00
Tom Rini
c12fe739ea Pull request for u-boot-nand-20230227
- mark reserved blocks from Ashok Reddy Soma
 - backport BRCMNAND changes from Linux from Linus Walleij
 - fix display of unknown raw ID from Patrice Chotard
 - show reserved block in chip.erase from Michael Trimarchi
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Merge tag 'u-boot-nand-20230227' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash into next

Pull request for u-boot-nand-20230227

- mark reserved blocks from Ashok Reddy Soma
- backport BRCMNAND changes from Linux from Linus Walleij
- fix display of unknown raw ID from Patrice Chotard
- show reserved block in chip.erase from Michael Trimarchi
2023-02-28 09:46:07 -05:00
Vasily Khoruzhick
f0eb365e21 clk: rockchip: rk3568: add more supported clk rates for sdmmc and emmc
SDHCI driver may attempt to set 26MHz clock, but clk_rk3568
will return error in this case. Apparently, SDHCI silently ignores the
error and as a result eMMC initialization fails.

Add 25 MHz and 26 MHz clk rates for sdmmc and emmc on rk3568 to fix that.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:29 +08:00
Jonas Karlman
dd5684b878 rockchip: efuse: Add support for RK3036
Add support for rk3036 compatible.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jonas Karlman
16e8afa802 rockchip: efuse: Add support for RK3128
Add support for rk3128 compatible.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jonas Karlman
b0828cf989 rockchip: efuse: Add support for RK3328
Add support for rk3328 compatible.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jonas Karlman
6f95b3e103 rockchip: efuse: Add support for RK3288 and more
Add support for rk3066a, rk3188, rk322x and rk3288 compatible.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jonas Karlman
433260ac1a rockchip: efuse: Refactor to use driver data and ops
Refactor the driver to use driver data and ops to simplify handling
of SoCs that require a unique read op.

Move handling of the aligned bounce buffer to main read op in order to
keep the SoC unique read op simple.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jonas Karlman
9a850d1fcd rockchip: otp: Add dump_otp debug command
Add a simple debug command to dump the content of the otp.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jonas Karlman
f888098229 rockchip: otp: Add support for RK3588
Add support for rk3588 compatible.

Adjust offset using driver data in main read op.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jonas Karlman
d58d55d242 rockchip: otp: Add support for RK3568
Add support for rk3568 compatible.

Handle allocation of an aligned bounce buffer in main read op in order
to keep the SoC unique read op simple.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jonas Karlman
8fa1870e11 rockchip: otp: Refactor to use driver data and ops
Refactor the driver to use driver data and ops to simplify handling
of SoCs that require a unique read op.

Use readl_poll_sleep_timeout instead of a custom poll loop, and add
validation of input parameter to main read op.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jagan Teki
3b7f29f2c8 ram: rockchip: Add rk3588 ddr driver support
Add ddr driver for rk3588 to get the ram capacity.

Co-developed-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Jagan Teki
b851c006a1 clk: rockchip: pll: Add pll_rk3588 type for rk3588
Add RK3588 pll set and get rate clock support.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Jagan Teki
7a474df740 clk: rockchip: Add rk3588 clk support
Add clock driver support for Rockchip RK3588 SoC.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Chris Morgan
904b8700f8 gpio: gpio-rockchip: parse gpio-ranges for bank id
Use the new devicetree property of gpio-ranges to determine the GPIO
bank ID. Preserve the "old" way of doing things too, so that boards
can be migrated and tested gradually (I only have a 3566 and 3326 to
test).

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Jagan Teki
1977d746aa rockchip: rk3568: add rk3568 pinctrl driver
Add driver supporting pin multiplexing on rk3568 platform.

Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Co-developed-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Jagan Teki
82220526ac drivers: phy: add naneng combphy for rk3568
RK3568 has three combo phys, and PCIe/USB3/SATA/QSGMII controllers
share one pipe interface for each combo phy, here is the diagram
of the complex connection.

+----------------+
|                |     +------+
| USB3 OTG CTRL0 |---->|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |---->| Combo PHY0 |
+----------------+     |      |     |            |
|                |     |      |     +------------+
|   SATA CTRL0   |---->|      |
|                |     +------+
+----------------+

+----------------+
|                |     +------+
| USB3 HOST CTRL1|---->|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |---->| Combo PHY1 |
+----------------+     |      |     |            |
|                |---->|      |     +------------+
|   SATA CTRL1   |  -->|      |
|                |  |  +------+
+----------------+  |
                    |
+----------------+  |
|                |  |  +------+
|  QSGMII CTRL   |---->|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |---->| Combo PHY2 |
+----------------+     |      |     |            |
|                |---->|      |     +------------+
|   SATA CTRL2   |  -->|      |
|                |  |  +------+
+----------------+  |
                    |
+----------------+  |
|                |  |
|  PCIe2 1-Lane  |---
|                |
+----------------+

Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Co-developed-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Manoj Sai
3da15f0b49 phy: rockchip-inno-usb2: Add USB2 PHY for rk3568
RK3568 has two USB 2.0 PHYs, and each PHY has two ports, the OTG port
of PHY0 support OTG mode with charging detection function, they are
similar to previous Rockchip SoCs.

However, there are three different designs for RK3568 USB 2.0 PHY.
1. RK3568 uses independent USB GRF module for each USB 2.0 PHY.
2. RK3568 accesses the registers of USB 2.0 PHY IP directly by APB.
3. The two ports of USB 2.0 PHY share one interrupt.

This patch only PHY1 with necessary attributes required to function
USBPHY1 on U-Boot.

Co-developed-by: Ren Jianing <jianing.ren@rock-chips.com>
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Co-developed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Jagan Teki
d538efb9ad phy: rockchip: inno-usb2: Add support #address_cells = 2
New Rockchip devices have the usb phy nodes as standalone devices.
These nodes have register nodes with #address_cells = 2, but only
use 32 bit addresses.

Adjust the driver to check if the returned address is "0", and adjust
the index in that case.

Derived and adjusted the similar change from linux-next with below
 commit <9c19c531dc98> ("phy: phy-rockchip-inno-usb2: support
 #address_cells = 2")

Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
John Keeping
ea0f766253 mmc: rockchip_dw_mmc: fix DDR52 8-bit mode handling
The RK3288 TRM states that, for 8-bit DDR modes:

	The CLKDIV register should always be programmed with a value
	higher than zero (0); that is, a clock divider should always be
	used for 8-bit DDR mode.

In Linux, the driver applies this logic for all SoCs using the driver
and does not distinguish RK3288, so presumably this requirement is the
same for all other Rockchip SoCs using this IP.

Add the necessary code to double the clock frequency when 8-bit DDR is
selected.  The dw_mmc core already handles setting CLKDIV correctly
given the input clock and desired bus clock.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-28 18:07:26 +08:00
Ilias Apalodimas
87bc11d5e2 tpm: sandbox: Change the return code when device is already open
All the TPM drivers as well as out TCG TIS API for a TPM2.0 device
return -EBUSY if the device has already been opened.  Adjust
the sandbox TPM do return the same error code.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-02-28 09:44:25 +02:00
Tom Rini
5b197eee33 Prepare v2023.04-rc3
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Merge tag 'v2023.04-rc3' into next

Prepare v2023.04-rc3
2023-02-27 17:28:21 -05:00
Michael Trimarchi
d9fa61f54e mtd: nand: Show reserved block in chip.erase
The "nand chip.erase" command always printed as bad blocks even in the
case of reserved blocks. Reserved blocks are used for storing bad block
tables. The patch displays "bbt reserved" when printing reserved blocks in
"nand chip.erase" command.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27 16:30:13 +01:00
Patrice Chotard
4f64a310fc mtd: spinand: Fix display of unknown raw ID
In case ID is not found in manufacturer table, the raw ID is
printed using %*phN format which is not supported by lib/vsprintf.c.
The information displayed doesn't reflect the raw ID return by the
unknown spi-nand.

Use %02x format instead, as done in spi-nor-core.c.

For example, before this patch:
  ERROR: spi-nand: spi_nand flash@0: unknown raw ID f74ec040
after
  ERROR: spi-nand: spi_nand flash@0: unknown raw ID 00 c2 26 03

Fixes: 0a6d6bae03 ("mtd: nand: Add core infrastructure to support SPI NANDs")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Acked-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27 16:30:09 +01:00
Álvaro Fernández Rojas
d346971559 mtd: rawnand: brcmnand: fix OOB R/W with Hamming ECC
Hamming ECC doesn't cover the OOB data, so reading or writing OOB shall
always be done without ECC enabled.
This is a problem when adding JFFS2 cleanmarkers to erased blocks. If JFFS2
clenmarkers are added to the OOB with ECC enabled, OOB bytes will be changed
from ff ff ff to 00 00 00, reporting incorrect ECC errors.

Fixes: 27c5b17cd1b1 ("mtd: nand: add NAND driver "library" for Broadcom STB NAND controller")
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20210224080210.23686-1-noltari@gmail.com
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27 16:30:05 +01:00
Álvaro Fernández Rojas
31b2731863 mtd: rawnand: brcmnand: support v2.1-v2.2 controllers
v2.1: tested on Netgear DGND3700v1 (BCM6368)
v2.2: tested on Netgear DGND3700v2 (BCM6362)

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200522121524.4161539-6-noltari@gmail.com
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27 16:30:01 +01:00
Álvaro Fernández Rojas
3c6ed98c7f mtd: rawnand: brcmnand: rename page sizes
Current pages sizes apply to controllers after v3.4

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200522121524.4161539-4-noltari@gmail.com
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27 16:29:58 +01:00
Álvaro Fernández Rojas
baeb0a8578 mtd: rawnand: brcmnand: fix CS0 layout
Only v3.3-v5.0 have a different CS0 layout.
Controllers before v3.3 use the same layout for every CS.

Fixes: 27c5b17cd1b1 ("mtd: nand: add NAND driver "library" for Broadcom STB NAND controller")
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200522121524.4161539-3-noltari@gmail.com
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27 16:29:53 +01:00
Álvaro Fernández Rojas
7136624a50 mtd: rawnand: brcmnand: rename v4 registers
These registers are also used on v3.3.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200522121524.4161539-2-noltari@gmail.com
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27 16:29:48 +01:00
Álvaro Fernández Rojas
6091939c34 mtd: rawnand: brcmnand: correctly verify erased pages
The current code checks that the whole OOB area is erased.
This is a problem when JFFS2 cleanmarkers are added to the OOB, since it will
fail due to the usable OOB bytes not being 0xff.
Correct this by only checking that data and ECC bytes aren't 0xff.

Fixes: 02b88eea9f9c ("mtd: brcmnand: Add check for erased page bitflips")
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200512082451.771212-1-noltari@gmail.com
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27 16:29:43 +01:00
Kamal Dasu
2de9ff609d mtd: nand: brcmnand: Add support for flash-dma v0
This change adds support for flash dma v0.0.

Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27 16:29:39 +01:00
Claire Lin
8dafc6b88e mtd: rawnand: brcmnand: Fix ecc chunk calculation for erased page bitfips
In brcmstb_nand_verify_erased_page(), the ECC chunk pointer calculation
while correcting erased page bitflips is wrong, fix it.

Fixes: 02b88eea9f9c ("mtd: brcmnand: Add check for erased page bitflips")
Signed-off-by: Claire Lin <claire.lin@broadcom.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27 16:29:34 +01:00
Kamal Dasu
5bf8adc22d mtd: rawnand: brcmnand: Add support for v7.3 controller
This change adds support for brcm NAND v7.3 controller. This controller
uses a newer version of flash_dma engine and change mostly implements
these differences.

Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27 16:29:30 +01:00
Kamal Dasu
79d50f38b2 mtd: rawnand: brcmnand: Refactored code to introduce helper functions
Refactored NAND ECC and CMD address configuration code to use helper
functions.

Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27 16:29:24 +01:00
Ashok Reddy Soma
cfb82f7c12 mtd: nand: Mark reserved blocks
Reserved blocks are used for storing bad block tables. With "nand bad"
command, these reserved blocks are shown as bad blocks. This is leading
to confusion when compared with Linux bad blocks. Hence, display
"bbt reserved" when printing reserved blocks with "nand bad" command.

To acheive this, return 2 which represents reserved from nand_isbad_bbt()
instead of 1 in case of reserved blocks and catch it in cmd/nand.c.

"nand bad" command display's hexadecimal numbers, so add "0x" prefix.

Example log will show up as below.

ZynqMP> nand bad

Device 0 bad blocks:
  0x00400000
  0x16800000
  0x16c00000
  0x17000000
  0x3d800000
  0x3e400000
  0xe8400000
  0xff000000	 (bbt reserved)
  0xff400000	 (bbt reserved)
  0xff800000	 (bbt reserved)
  0xffc00000	 (bbt reserved)
  0x116800000
  0x116c00000
  0x1ff000000	 (bbt reserved)
  0x1ff400000	 (bbt reserved)
  0x1ff800000	 (bbt reserved)
  0x1ffc00000	 (bbt reserved)

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-By: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27 16:28:30 +01:00
Maxim Schwalm
b1de4d7c6e ARM: tegra: provide default USB gadget setup
All Nvidia boards use the same manufacturer, vendor ID and product ID
for the gadgets. Make them the defaults to remove some boilerplate from
the defconfigs.

Inspired by commit e02687bda9 ("sunxi: provide default USB gadget
setup") which did the same for Allwinner boards.

Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Svyatoslav Ryhel
09ca4d8028 spi: tegra20_slink: accept any word length
Original t20 slink could work with commands only
fully divisible by 8. This patch removes such
restriction, so commands of any bitlength now
can be passed and processed.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00
Svyatoslav Ryhel
23d24df34c ARM: tegra: Fix Tegra PWM parent clock
Default parent clock for the PWM on Tegra is a 32kHz clock and
is unable to support the requested PWM period.

Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by
updating the parent clock for the PWM to be the PLL_P.

This commit is equivalent to Linux kernel commit:
https://lore.kernel.org/all/20221010100046.6477-1-jonathanh@nvidia.com/

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # ASUS TF201 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00
Marek Vasut
b684ec8efe usb: dwc3-uniphier: Select PHY
Make sure the PHY subsystem is activated for the uniphier DWC3 glue
logic, as it depends on PHY implementation there.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-02-23 11:33:00 -05:00
Kunihiko Hayashi
ec01e0ba2c usb: dwc3-uniphier: Use dwc3-generic instead of xhci-dwc3
dwc3-uniphier depends on xhci-dwc3 framework, however, it is preferable
to use dwc3-generic.

This driver calls the exported dwc3-generic functions and redefine
the SoC-dependent operations to fit dwc3-generic.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22 19:40:11 +01:00
Kunihiko Hayashi
7a888de4b5 phy: socionext: Add UniPhier USB3 PHY driver
Add USB3 PHY driver support to control clocks and resets needed to enable
PHY. The phy_ops->init() and exit() control PHY clocks and resets only,
and clocks and resets for the controller and the parent logic are enabled
in advance.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22 19:40:11 +01:00
Kunihiko Hayashi
26dd38af85 clk: uniphier: Add missing USB SS-PHY clocks
The USB SS-PHY needs its own clock, however, some clocks don't have
clock gates. Define missing clock entries for the PHY as reference
clock.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22 19:40:11 +01:00
Kunihiko Hayashi
1c866de57b reset: uniphier: Add USB glue reset support
Add reset control support in USB glue logic. This needs to control
the external clocks and resets for the logic before accessing the
glue logic.

The USB dm tree when using dwc3-generic is the following:

   USB glue
     +-- controller       (need controller-reset)
     +-- controller-reset (need syscon-reset)
     +-- phy

The controller needs to deassert "controller-reset" in USB glue before
the controller registers are accessed. The glue needs to deassert
"syscon-reset" before the glue registers are accessed.

The glue itself doesn't have "syscon-reset", so the controller-reset
controls "syscon-reset" instead.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22 19:40:11 +01:00
Kunihiko Hayashi
211a066876 usb: dwc3-generic: Add the size of regs property to glue structure
Add the size of regs property to the glue structure to correctly
specify the register region to map.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22 19:40:11 +01:00
Kunihiko Hayashi
ef2313b8a2 usb: dwc3-generic: Export glue structures and functions
In order to allow external SoC-dependent glue drivers to use dwc3-generic
functions, push the glue structures and export the functions to a header
file.

The exported structures and functions are:

- struct dwc3_glue_data
- struct dwc3_glue_ops
- dwc3_glue_bind()
- dwc3_glue_probe()
- dwc3_glue_remove()

The SoC-dependent glue drivers can only define their own wrapper driver
and specify these functions. The drivers can also add their own compatible
strings and configure functions.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22 19:40:11 +01:00
Kunihiko Hayashi
7c71c684ce usb: dwc3-generic: Add clock initialization in child DT node
Same as the reset cotnrol, should add a clock initialization in child DT
node, if the glue node doesn't have any clocks.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22 19:40:11 +01:00
Kunihiko Hayashi
f7b7c72133 usb: dwc3-generic: Allow different controller DT node pattern
The most of devicetree has the following USB node structure.
The controller node is placed as a child node of the glue node.
Current dwc3-generic driver works on this premise.

    glue {
        /* glue node */
	usb {
            /* controller node */
	};
    };

However, UniPhier original devicetree has the following USB node structure.
The controller node is separately placed from the glue node.

    usb {
        /* controller node */
    };
    glue {
        /* glue node */
    };

In dwc_glue_bind(), this patch provides .glue_get_ctrl_dev() callback to
get such a controller node and binds the driver related to the node.

If this callback isn't defined, dwc_glue_bind() looks for the controller
nodes from the child nodes, as before.

Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22 19:40:11 +01:00
Marek Vasut
c6583354b7 usb: dwc3: Look up reference clock DT phandle in both controller DT nodes
There are currently four disparate placement possibilities of DWC3
reference clock phandle in SoC DTs:
- in top level glue node, with generic subnode without clock (ZynqMP)
- in top level generic node, with no subnode (i.MX8MQ)
- in generic subnode, with other clock in top level node (i.MX8MP)
- in both top level node and generic subnode (Rockchip)

Cover all the possibilities here by looking into both nodes, start
with the top level node as that seems to be used in majority of DTs
to reference the clock.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2023-02-22 19:40:11 +01:00
Venkatesh Yadav Abbarapu
237d1f60b1 usb: dwc3: Use the devm_gpiod_get_optional() API for reset gpio
As the "reset-gpios" property is optional, don't return the
error and just skip the gpio reset sequence.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
2023-02-22 00:28:05 +01:00
Ulf Samuelsson
aa0a8a0be2 cpsw_mdio.c: Use correct reg in cpsw_mdio_get_alive
cpsw_mdio_get_alive reads the wrong register.
See page 2316 in SPRUH73Q AM335x TRM

Signed-off-by: Ulf Samuelsson <ulf@emagii.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-02-17 10:49:41 -05:00
Yu Chien Peter Lin
da24626d14 driver: cache-v5l2: Fix type casting warning on RV32
This patch fixes following warning for the riscv32 toolchain.

drivers/cache/cache-v5l2.c:122:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
  122 |         regs = (struct l2cache *)dev_read_addr(dev);
      |                ^

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-02-17 19:07:48 +08:00
Yu Chien Peter Lin
c1b8819680 riscv: ae350: dts: Update L2 cache compatible string
Update the compatible string of L2 cache.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17 19:07:48 +08:00
Yu Chien Peter Lin
51415fa634 driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform
The L2C configuration register has MAP field to indicate its version
is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver
compatible with both memory-mapped scheme.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17 19:07:48 +08:00
Leo Yu-Chi Liang
55ca747f66 riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"
There is no need for RISCV_NDS_CACHE config to control cache switches.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17 19:07:48 +08:00
Simon Glass
e316fbabbf dm: treewide: Complete migration to new driver model schema
Update various build and test components to use the new schema.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-14 09:43:27 -07:00
Simon Glass
c74e03417b dm: Add support for handling old u-boot,dm- tags
Add a CONFIG option to deal with this automatically, printing a warning
when U-Boot starts up. This can be useful if the device tree comes from
another project.

We will maintain this through the 2023.07 release, providing 6 months
for people to notice.

Signed-off-by: Simon Glass <sjg@chromium.org>
Version 4:
Acked-by: Michal Simek <michal.simek@amd.com>
2023-02-14 09:42:14 -07:00
Pei Yue Ho
f536fda99f i2c: i2c-cdns.c: Update driver to read fifo-depth from device tree
Enable driver to fetch the optional parameter (fifo-depth) from device
tree. If the parameter is not found in the device tree, it will use
the default value declared in the driver.

Signed-off-by: Pei Yue Ho <peiyue.ho@starfivetech.com>
Reviewed-by: Wei Liang Lim <weiliang.lim@starfivetech.com>
Reviewed-by: Eng Lee Teh <englee.teh@starfivetech.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-13 09:58:27 +01:00