Commit graph

8718 commits

Author SHA1 Message Date
Lukasz Majewski
ec1b26973c imx6: iomux: Add generic function to set RGMII IO voltage on IMX6 SoCs
This commit provides generic function to set the RGMII/HSIC IO voltage
level on iMX6 devices.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-11-09 11:32:49 +01:00
Fabio Estevam
b2e6ad451b mx51: Select the ESDHC_A001 erratum
When a high speed card is connected to mx51evk the following error is seen:

U-Boot 2017.11-rc2 (Oct 18 2017 - 13:49:26 -0200)

CPU:   Freescale i.MX51 rev3.0 at 800 MHz
Reset cause: POR
Board: MX51EVK
DRAM:  512 MiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
*** Warning - read failed, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   FEC
Hit any key to stop autoboot:  0
=> saveenv
Saving Environment to MMC...
Writing to MMC(0)... failed

The root cause for the failure is the eSDHC-A001 erratum:

"eSDHC-A001 : Data timeout counter (SYSCTL[DTOCV]) is not reliable for
values of 0x4,0x8, and 0xC" that is listed
on some PowerArchitecture chips:
https://www.nxp.com/files-static/32bit/doc/errata/MPC8379ECE.pdf

Even though eSDHC-A001 is not documented on the i.MX51 errata document,
I have confirmed with the NXP design team that this erratum does affect
i.MX51, so fix the problem by selecting SYS_FSL_ERRATUM_ESDHC_A001
at SoC level.

The i.MX51 ts4800 board already selects this option, but it is better
to move this selection to the i.MX51 SoC level instead.

Successfully tested with a high speed SD card on a mx51evk board.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
2017-11-07 10:13:11 +01:00
Fabio Estevam
5d09c27138 mx25: Select the ESDHC_A001 erratum
When a high speed card is connected to mx25 the following error is seen:

U-Boot 2017.11-rc2-00104-gb79372a (Oct 31 2017 - 11:02:22 -0200)

CPU:   Freescale i.MX25 rev1.2 at 399 MHz
Reset cause: POR
Board: MX25PDK
I2C:   ready
DRAM:  64 MiB
No arch specific invalidate_icache_all available!
MMC:   FSL_SDHC: 0
*** Warning - read failed, using default environment
In:    serial
Out:   serial
Err:   serial
Net:   FEC
Hit any key to stop autoboot:  0
=> saveenv
Saving Environment to MMC...
Writing to MMC(0)... failed

, which prevents any usage of the SD card.

The root cause for the failure is the eSDHC-A001 erratum:

"eSDHC-A001 : Data timeout counter (SYSCTL[DTOCV]) is not reliable for
values of 0x4,0x8, and 0xC" that is listed
on some PowerArchitecture chips:
https://www.nxp.com/files-static/32bit/doc/errata/MPC8379ECE.pdf

Even though eSDHC-A001 is not documented on the i.MX25 errata document,
I have confirmed with the NXP design team that this erratum does affect
i.MX25, so fix the problem by selecting SYS_FSL_ERRATUM_ESDHC_A001
at SoC level.

Successfully tested with a high speed SD card on a mx25pdk board.

Suggested-by: Benoît Thébaudeau <benoit@wsystem.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Tested-by: Otavio Salvador <otavio@ossystems.com.br> # mx25pdk
2017-11-07 10:13:00 +01:00
Fabio Estevam
07df697e14 mx25: Move MX25 selection to Kconfig
The motivation for moving MX25 selection to Kconfig is to be
able to better handle MX25 specific errata, so that an errata option
can be selected at SoC level instead of board level.

This selection method also aligns with the way other i.MX SoCs are
selected in U-Boot.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
2017-11-07 10:12:50 +01:00
Klaus Goger
4f70039b36 rockchip: dts: rk3399: change sd-card io voltage to 3.0V
The VCC_SD and VCC_SDIO rail should only be powered up to 3.0V on RK3399
platforms.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-07 09:16:57 +01:00
Klaus Goger
366812fa26 rockchip: dts: Use defines for pin names in rk3399-puma.dtsi and rk3368-lion.dts
pinctrl/rockchip.h provides defines that map pin numbers to pin names.
Use them to make the dts more human readable.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-07 09:16:57 +01:00
Philipp Tomsich
b1e1ce2cd4 rockchip: dts: rk3399-puma: update USB configuration
This change updates the USB configuration for the RK3399-Q7 in the DTS:
 * fixes the OTG board configuration by enabling it ('okay')
 * improves the speed of 'usb start' by disabling the unused EHCI/OHCI
   controllers

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-11-07 09:16:57 +01:00
Philipp Tomsich
f2a9513168 rockchip: dts: rk3399-puma: update usbhub_enable regulator
To correctly model the usbhub_enable regulator for U-Boot, we need
to change the settings to:
 * the GPIO polarity is GPIO_ACTIVE_LOW
 * should be set to inactive (enable-active-low) when boot-on settings
   are applied
 * it can be changed at runtime (i.e. remove the always-on)

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-11-07 09:16:57 +01:00
Philipp Tomsich
df1e6212f9 rockchip: dts: rk3399-puma: fix the modelling of BIOS_DISABLE
The fixed regulator for overriding BIOS_DISABLE had been modelling
backwards (i.e. the GPIO polarity and the enable-active-low/high
property had both been inverted), causing the 'regulator' command
to always print/expect 'disabled'/'enabled' backwards.

This fixes the mix-up and models it correctly:
 * the GPIO is low-active
 * the regulator should be enabled (enable-active-high) during
   boot-on initialisation

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-11-07 09:16:56 +01:00
Chris Brandt
fc85605018 cosmetic: rmobile: renesas spelled wrong
Renesas was spelled wrong.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
2017-11-06 09:59:03 -05:00
Patrice Chotard
e36591c350 spear: fix STMicroelectronics copyright
Uniformize STMicroelectronics copyrights headers for SPEAR
related code.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-06 09:51:01 -05:00
Patrice Chotard
1537d38619 stv0991: fix STMicroelectronics copyright
Uniformize STMicroelectronics copyrights headers for STV0991
related code.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-06 09:51:01 -05:00
Patrice Chotard
3bc599c956 stm32: fix STMicroelectronics copyright
Uniformize STMicroelectronics copyrights headers for STM32
related code.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-06 09:51:01 -05:00
Patrice Chotard
fb48bc448c sti: fix STMicroelectronics copyright
Uniformize all STMicroelectronics copyrights headers for STi
related code.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-06 09:51:01 -05:00
Dongjin Kim
568197fa03 ARM: dts: exynos: fix property values of LDO15/17 for ODROID-XU3/4
Looking at the schematic, LDO15 and LDO17 are tied as a power source of a
builtin network chipset. The voltage on LDO15 is corrected to 3.3V and the
name of LDO17 is corrected to "vdd_ldo17".

Signed-off-by: Dongjin Kim <tobetter@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2017-11-06 16:59:32 +09:00
Kever Yang
36de37f5ca rockchip: rk3328: fix rockchip_get_cru api
The API for get priv pointer is wrong, fix it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-01 11:21:32 +01:00
Fabio Estevam
e1f0715f64 wandboard: Add support for the MX6QP variant
Add support for the latest MX6QP wandboard variant.

Based on Richard Hu's work from Technexion's U-Boot tree.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-10-31 11:01:38 +01:00
Tom Rini
2d5e6b4aac Merge git://git.denx.de/u-boot-video 2017-10-29 10:11:08 -04:00
Tom Rini
bb3d9ed3a9 Merge git://git.denx.de/u-boot-fsl-qoriq 2017-10-27 21:59:10 -04:00
Sumit Garg
9b3f40ad09 armv8: sec_firmware: Add support for loadables in FIT
Enable support for loadables in SEC firmware FIT image. Currently
support is added for single loadable image.

Brief description of implementation:
  Add two more address pointers (loadable_h, loadable_l) as arguments to
  sec_firmware_init() api.
  Create new api: sec_firmware_checks_copy_loadable() to check if loadables
  node is present in SEC firmware FIT image. If present, verify loadable
  image and copies it to secure DDR memory.
  Populate address pointers with secure DDR memory addresses where loadable
  is copied.

Example use-case could be trusted OS (tee.bin) as loadables node in SEC
firmware FIT image.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:47:14 -07:00
Sumit Garg
9781d9ff5f armv8: layerscape: Allocate 66 MB DDR for secure memory
Change DDR allocated for secure memory from 2 MB to 66 MB. This
additional 64 MB secure memory is required for trusted OS running
in Trusted Execution Environment using ARMv8 TrustZone.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:47:14 -07:00
Ran Wang
d4c746c7b1 armv8: ls1088ardb: Enable USB command RDB qspi-boot
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:47:06 -07:00
Ran Wang
4417e83495 arm64: layerscape: Move CONFIG_HAS_FSL_XHCI_USB to Kconfig
Use Kconfig to select QE-HDLC and USB pin-mux.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:43:57 -07:00
Vasily Khoruzhick
1d7eef3f3f sunxi: video: add LCD support to DE2 driver
Extend DE2 driver with LCD support. Tested on Pinebook which is based
on A64 and has ANX6345 eDP bridge with eDP panel connected to it.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
[agust: rebased v5 on u-boot-video/master]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-10-27 09:44:48 +02:00
Vasily Khoruzhick
79f285ddeb sunxi: video: split out PLL configuration code
It will be reused in new DM LCD driver.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2017-10-27 09:39:19 +02:00
Icenowy Zheng
be5b96f0e4 sunxi: setup simplefb for Allwinner DE2
As the support of EFI boot on Allwinner H3 is broken, we still need to
use simplefb to pass the framebuffer to Linux.

Add code to setup simplefb for Allwinner DE2 driver.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-26 11:57:14 +02:00
Icenowy Zheng
f6bdddc92b video: add an option for video simplefb via DT
Add an option to indicate that the video driver should setup a SimpleFB
node that passes the video framebuffer initialized by U-Boot to the
operating system kernel.

Currently only the Allwinner DE driver uses this option, and the
definition of this option in the sunxi-common.h config header is
converted to an imply of this option from CONFIG_VIDEO_SUNXI.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-26 11:53:39 +02:00
Icenowy Zheng
401a3ca0fb sunxi: change the DE1 video option to CONFIG_VIDEO_SUNXI
The sunxi DE1 video option used to be CONFIG_VIDEO, which has the same
name as the "Enable legacy video support" option in
drivers/video/Kconfig.

Change the option name to CONFIG_VIDEO_SUNXI, which is really used by
Makefile under drivers/video/sunxi/, and defined in sunxi-common.h
when CONFIG_VIDEO is selected before this change. Now CONFIG_VIDEO_SUNXI
selects CONFIG_VIDEO and the usages of CONFIG_VIDEO in sunxi Kconfig and
config headers are all converted to use CONFIG_VIDEO_SUNXI.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2017-10-26 11:48:49 +02:00
Maxime Ripard
819f1e081c sunxi: binman: Add U-Boot binary size check
The U-Boot binary may trip over its actual allocated size in the storage.
In such a case, the environment will not be readable anymore (because
corrupted when the new image was flashed), and any attempt at using saveenv
to reconstruct the environment will result in a corrupted U-Boot binary.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-25 10:05:06 +02:00
Maxime Ripard
ce2e44d836 sunxi: Enable THUMB build for the U-Boot binary
We start to get to the limit of our main U-Boot binary size (with some
boards even crossing it). Enable its build using thumb2 to get some extra
room.

Suggested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-25 10:05:06 +02:00
Maxime Ripard
7514069aa3 sunxi: Add support for the Banana Pi M2-Magic
The Banana Pi M2-Magic is a small board with an Allwinner A33, an eMMC, a
wifi chip and some pin headers. Enable support for it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-25 10:05:06 +02:00
Quentin Schulz
c96f598be7 sunxi: clk: fix N formula for CPUX clocks
As explained in arch/arm/mach-sunxi/clock_sun8i_a83t.c, clk for CPU
clusters is computed as clk = 24*n. However, the current formula is clk
= 24*(n-1).

This results in a clock set to a frequency that isn't specified as
possible for CPUs.

Let's use the correct formula.

Fixes: f542948b1e ("sunxi: clk: add basic clocks for A83T")

Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-10-25 10:05:05 +02:00
Masahiro Yamada
624c0954c7 ARM: uniphier: use pr_*() more where appropriate
Commit dd74b945af ("ARM: uniphier: use pr_() instead of printf()
where appropriate"), but I missed to update this file for some reason.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23 01:09:22 +09:00
Masahiro Yamada
272874879b ARM: dts: uniphier: sync DT with Linux 4.14-rc5
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23 01:02:05 +09:00
Masahiro Yamada
9ac0e7b37a ARM: uniphier: split u-boot,dm-pre-reloc out to uniphier-v7-u-boot.dtsi
UniPhier 32-bit SoCs use CONFIG_SPL_OF_CONTROL.  So, many nodes must
be marked as dm-pre-reloc to prevent fdtgrep from stripping them off.

Sprinkling U-Boot-specific properties all over the place is painful
because DT files are synced with Linux from time to time.

Split u-boot,dm-pre-reloc out to uniphier-v7-u-boot.dtsi, which is
appended to UniPhier V7 DTS before the build.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-10-23 01:02:05 +09:00
Masahiro Yamada
d0df9588e8 ARM: uniphier: remove CONFIG_UNIPHIER_ETH
The option is never enabled by anyone.  Remove the code surrounded
by its ifdef.  This should be handled by the clock/reset drivers.

CONFIG_UNIPHIER_ETH in scripts/config_whitelist.txt will be dropped
by the next resync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23 01:02:05 +09:00
Adam Ford
0a9ef45158 Convert CONFIG_NAND_OMAP_GPMC et al and CONFIG_NAND_MXC to Kconfig
This converts the following to Kconfig:
   CONFIG_NAND_MXC
   CONFIG_NAND_OMAP_GPMC
   CONFIG_NAND_OMAP_GPMC_PREFETCH
   CONFIG_NAND_OMAP_ELM
   CONFIG_SPL_NAND_AM33XX_BCH
   CONFIG_SPL_NAND_SIMPLE
   CONFIG_SYS_NAND_BUSWIDTH_16BIT

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
[trini: Finish migration of CONFIG_SPL_NAND_SIMPLE, fix some build issues,
        add CONFIG_NAND_MXC so we can do CONFIG_SYS_NAND_BUSWIDTH_16BIT]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-20 16:44:07 -04:00
Praneeth Bajjuri
9b46ce8cfc arm: dra76: fastboot: extend cpu type for getvar command
'commit fa24eca1f2 ("omap: Add routine for setting fastboot variables")'
adds initial support and usage of "fastboot getvar" command
for DRA75x and DRA72x devices.

and
'commit 0f9e6aee9d ("arm: dra76: Add support for ES1.0 detection")'
adds initial dra76 device definition

This patch is to extend usage of "fastboot getvar" for DRA76 device.

Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-10-16 09:43:34 -04:00
Vishal Mahaveer
b6df93598c omap-common: fastboot: extend cpu type for DRA71x rev 2.1
DRA71x processors are reduced pin and software compatible
derivative of DRA72 processors. Extend support for this
revision in "getvar cpu" command.

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
[praneeth@ti.com: rebase to u-boot master]
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-10-16 09:43:34 -04:00
Tuomas Tynkkynen
c68c03f52b Drop CONFIG_HAS_DATAFLASH
Last user of this option went away in commit:

fdc7718999 ("board: usb_a9263: Update to support DT and DM")

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2017-10-16 09:42:51 -04:00
Alexander Graf
409f05f259 fdt: update bcm283x device tree sources to Linux 4.14 state
Upstream Linux has received a few device tree updates to the RPi
which we should propagate into the builtin U-Boot one as well to
gain hardware support.

This patch bumps the dts files to their 4.14 Linux counterparts
with the exception of sdhost on 32bit RPi versions. There we stay
with iproc as the sdhost driver is missing in U-Boot.

Signed-off-by: Alexander Graf <agraf@suse.de>
2017-10-16 09:42:51 -04:00
Masahiro Yamada
c7372d61fd ARM: uniphier: adjust ifdefs for new UniPhier DWC3 CONFIG
Now USB 3.0 feature is enabled/disabled by CONFIG_USB_DWC3_UNIPHIER.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15 22:32:25 +09:00
Masahiro Yamada
5e5edca27c ARM: uniphier: change the default of SoC select to UNIPHIER_V7_MULTI
ARCH_UNIPHIER_V8_MULTI depends on !SPL, so the default may be hidden.
Use a clearer default.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15 22:32:25 +09:00
Masahiro Yamada
dd74b945af ARM: uniphier: use pr_() instead of printf() where appropriate
Replace printf() with pr_() to specify proper loglevel.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15 22:32:24 +09:00
Masahiro Yamada
0f72b74b32 ARM: dts: uniphier: update GPIO nodes
Switch to the single node design.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15 22:32:24 +09:00
Tom Rini
26f9184e09 Merge git://git.denx.de/u-boot-fsl-qoriq 2017-10-12 13:36:58 -04:00
Marek Vasut
0a333602df ARM: imx6: Add DHCOM i.MX6 PDK board support
Add support for the DHCOM i.MX6 PDK board. This board has:
- FEC ethernet
- EHCI USB host
- 3x SDMMC

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2017-10-12 18:01:06 +02:00
Diego Dorta
e2000731ae mx6: sys_proto: Add prototypes for imx6_pcie_toggle() functions
When compiling with W=1 errors are observed:

drivers/pci/pcie_imx.c:517:12: warning: no previous prototype for ‘imx6_pcie_toggle_power’ [-Wmissing-prototypes] __weak int imx6_pcie_toggle_power(void)

drivers/pci/pcie_imx.c:528:12: warning: no previous prototype for ‘imx6_pcie_toggle_reset’ [-Wmissing-prototypes] __weak int imx6_pcie_toggle_reset(void)

Remove these warnings by adding the functions prototypes on arch-mx6/sys_proto.

Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
2017-10-12 18:00:18 +02:00
Diego Dorta
342b4b09b1 mx6: clock: Add a prototype for do_mx6_showclocks()
When compiling with W=1 the following warning is observed:

arch/arm/mach-imx/mx6/clock.c:1268:5: warning: no previous prototype for ‘do_mx6_showclocks’ [-Wmissing-prototypes] int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])

Remove this warning by adding the function prototype into arch-mx6/clock.h file.

Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
2017-10-12 18:00:01 +02:00
Ilya Ledvich
6963204c4c arm: imx7d: add support for Compulab cl-som-imx7
Add initial support for Compulab cl-som-imx7 SoM.
The initial support includes:
 - MMC
 - eMMC
 - SPI flash
 - I2C
 - FEC
 - USB
 - Serial console

Signed-off-by: Ilya Ledvich <ilya@compulab.co.il>
2017-10-12 17:31:16 +02:00
Uri Mashiach
c5c6f37a04 imx: mx7: SPL support for i.MX7
Add configuration file and spl_boot_device function for the i.MX7 SPL.

Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
2017-10-12 17:31:16 +02:00
Uri Mashiach
258bad41ac imx: mx7: DDR controller configuration for the i.MX7 architecture
The configuration files imximage.cfg are used for the DDR controller
configuration.
Add DDR configuration function to replace the DDR controller
configuration in the imximage.cfg file. The function can be used for
DDR size detection.

Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
2017-10-12 17:31:16 +02:00
Uri Mashiach
8bf2d77806 imx: mx7: fix the CCM_ macros
The CCM_ macros use the CCM_BASE_ADDRESS macro, which doesn't exist.
Replace the CCM_BASE_ADDRESS macros with CCM_BASE_ADDR.

Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2017-10-12 17:31:16 +02:00
Diego Dorta
c49fa34e5b mx6: soc: Include <asm/bootm.h> header file
When compiling with W=1 the following warning is observed:

arch/arm/mach-imx/mx6/soc.c:213:12: warning: no previous prototype for ‘get_board_rev’ [-Wmissing-prototypes] u32 __weak get_board_rev(void)

Fix the build warning by including <asm/bootm.h>.

Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
2017-10-12 17:31:16 +02:00
Diego Dorta
9f272573b7 imx: sys_proto: Add a prototype for board_mmc_get_env_dev()
When compiling with W=1 the following warning is observed:

board/freescale/mx6sabresd/mx6sabresd.c:266:5: warning:
no previous prototype for ‘board_mmc_get_env_dev’
[-Wmissing-prototypes] int board_mmc_get_env_dev(int devno)

Remove this warning by adding the function prototype into sys_proto.h file.

Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-10-12 17:31:16 +02:00
Anatolij Gustschin
38df370182 imx6: disable clock command and print_cpuinfo code in SPL
We do not use print_cpuinfo and clock command code in SPL,
disable it when building SPL image.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-10-12 17:30:32 +02:00
Tom Rini
2ee87b0c1a Merge branch 'rmobile' of git://git.denx.de/u-boot-sh 2017-10-10 20:14:38 -04:00
Marek Vasut
17cf99a5bb ARM: rmobile: dts: Add SDR104/HS200 to Salvator-X
Add DT nodes to enable SDR104/HS200 modes on Salvator-X boards.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-10-10 08:22:54 +09:00
Tom Rini
74d90d17ee Merge git://git.denx.de/u-boot-video 2017-10-09 13:31:33 -04:00
York Sun
fb97b8621e armv8: layerscape: Enable falcon boot
Add jump_to_image_linux() for arm64. Add "noreturn" flag to
armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon
boot.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
Tested-by: Łukasz Majewski <lukma@denx.de>
2017-10-09 08:48:45 -07:00
York Sun
7eb40f0f9d armv8: fsl-layerscape: Avoid running dram_init_banksize again
gd->ram_size is reduced in this function to reserve secure memory.
Avoid running this function again to further reduce memory size.
This fixes issue for SPL boot with PPA image loaded in which case
secure memory is incorrectly allocated due to repeated calling.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-09 08:48:44 -07:00
York Sun
d1fc0a31b5 spl: fix assignment of board info to global data
Commit 15eb1d43bf ("spl: reorder the assignment of board info to
global data") intended to move assignment of board info earlier,
into board_init_r(). However, function preload_console_init() is
called either from spl_board_init() or from board_init_f(). For the
latter case, the board info assignment is much earlier than proposed
board_init_r(). Create a new function to fill gd->bd and call this
function when needed.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Lokesh Vutla <lokeshvutla@ti.com>
CC: Ravi Babu <ravibabu@ti.com>
CC: Lukasz Majewski <lukma@denx.de>
CC: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-09 08:48:44 -07:00
Sumit Garg
710d0cd79e armv8: fsl-layerscape: Allocate Secure memory from first ddr region
This change is required due to trusted OS (OP-TEE) not being position
independent code, it requires compile time fixed base address.

To take care of this it is assumed that all layerscape armv8 platforms
has minimum 2G ddr in first region. So we can have fixed address
space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from
top of first 2G ddr region and compile trusted OS with this fixed
base address.

But one exception here is ls1012 where we have only 1G (rdb) or 512M
(frdm) ddr memory. For those we can have different fixed compile time
base addresses for trusted OS.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-09 08:48:44 -07:00
Ran Wang
7458c5e65f armv8: Apply workaround for USB erratum A-009007 to LS1088A
Rx Compliance tests may fail intermittently at high jitter
frequencies using default register values.

Program register USB_PHY_RX_OVRD_IN_HI in certain sequence
to make the Rx compliance test pass.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-09 08:36:37 -07:00
Patrice Chotard
d8f69e563b ARM: DTS: stm32: add SDMMC support fo stm32h743-eval
Add pinctrl and sdmmc nodes to add MMC support for
STM32H743 evaluation board.

Evaluation board needs a second pinctrl node
"pinctrl_sdmmc1_level_shifter" to drive a level shifter
on MMC bus.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-08 16:19:56 -04:00
Patrice Chotard
eccac3e120 ARM: DTS: stm32: add SDMMC support for stm32h743 disco
Add pinctrl and sdmmc nodes to add MMC support for
STM32H743 discovery board.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-08 16:19:56 -04:00
Bo Shen
72dee54b4e ARM: stm32f7: fix prescaler calculation of timer
As the timer 2 is on APB1 bus, the maximum of clock frequency of APB1 timer
clock is half of SYSCLK. Then to calculate the timer prescaler for timer 2
which need to be divided by 2.

Signed-off-by: Bo Shen <voice.shen@gmail.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-10-08 16:19:56 -04:00
Patrice Chotard
75d5853ffc serial: stm32x7: remove stm32f7-usart and stm32h7-usart compatible
This patch remove the extra compatibility string "st,stm32h7-usart"
and "st,stm32f7-usart" to avoid confusion, save some time & space.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-10-08 16:19:56 -04:00
zijun_hu
34f9a92583 ARMv8: make master CPU checking logic more clear
macro branch_if_master checks master CPU via (Aff3 & (Aff2:Aff1:Aff0))
it is simple but a little obscure.

fix by checking Affx fields within MPIDR_EL1 directly.

Signed-off-by: zijun_hu <zijun_hu@htc.com>
2017-10-08 16:19:56 -04:00
zijun_hu
7baf952fdb ARMv8: fix error in freeing stack frame
relocate_code() allocates 32 bytes stack frame but only 16 bytes are
freed before return. it will cause errors to possible previous frames
and doesn't make relocate_code() look like a function.

fix by freeing 32 bytes stack space

Signed-off-by: zijun_hu <zijun_hu@htc.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-08 16:19:56 -04:00
zijun_hu
01a8359989 ARMv8: get new GD address from gd->new_gd directly
the new GD address is calculated via board data BD currently
it require the new GD area locates below BD tightly, so a strict
constraint is imposed on memory layout which maybe make special
platform unpleasant.

fix it by getting new GD address from gd->new_gd directly.

Signed-off-by: zijun_hu <zijun_hu@htc.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-08 16:19:56 -04:00
Sam Protsenko
268577669a omap: Fix warning when looking for userdata part
When eMMC was formattaed for Linux partition table, "userdata" partition
is missing. In this case, part_get_info_by_name() iterates over all
registered drivers (which are PART_TYPE_EFI, PART_TYPE_DOS and
PART_TYPE_ISO). And when it comes to PART_TYPE_ISO (which has empty
partition table), we can see next warning in U-Boot output:

    ** First descriptor is NOT a primary desc on 1:1 **

This patch switches to part_get_info_by_name_type() API in order to
check only EFI partitions for "userdata" partitions. This eliminates
mentioned warning.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-06 11:28:17 -04:00
Sam Protsenko
19d141a0f9 omap: Omit fastboot.userdata_size related errors
When using regular $partitions variable (for Linux boot), we can see
some unwanted messages:

> ERROR: cannot find partition: 'userdata'

> at arch/arm/mach-omap2/utils.c:96/omap_mmc_get_part_size()
> Warning: fastboot.userdata_size: unable to calc

Let's remove those, as missing 'userdata' partition is correct behavior
for Linux partition, and we don't want to see some Android-related
messages in this case.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2017-10-06 11:28:16 -04:00
Tuomas Tynkkynen
32f1182926 ARM: Add a new arch + board for QEMU's 'virt' machine
This board builds an U-Boot binary that is bootable with QEMU's 'virt'
machine on ARM. The minimal QEMU command line is:

    qemu-system-arm -machine virt,highmem=off -bios u-boot.bin

(Note that the 'highmem=off' parameter to the 'virt' machine is required for
PCI to work in U-Boot.) This command line enables the following:
    - u-boot.bin loaded and executing in the emulated flash at address 0x0
    - A generated device tree blob placed at the start of RAM
    - A freely configurable amount of RAM, described by the DTB
    - A PL011 serial port, discoverable via the DTB
    - An ARMv7 architected timer
    - PSCI for rebooting the system
    - A generic ECAM-based PCI host controller, discoverable via the DTB

Additionally, QEMU allows plugging a bunch of useful peripherals to the PCI bus.
The following ones are supported by both U-Boot and Linux:

- To add a Serial ATA disk via an Intel ICH9 AHCI controller, pass e.g.:
    -drive if=none,file=disk.img,id=mydisk -device ich9-ahci,id=ahci -device ide-drive,drive=mydisk,bus=ahci.0
- To add an Intel E1000 network adapter, pass e.g.:
    -net nic,model=e1000 -net user
- To add an EHCI-compliant USB host controller, pass e.g.:
    -device usb-ehci,id=ehci
- To add a NVMe disk, pass e.g.:
    -drive if=none,file=disk.img,id=mydisk -device nvme,drive=mydisk,serial=foo

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2017-10-06 11:28:16 -04:00
Jean-Jacques Hiblot
a4d72869f8 omap: detect board before spl_early_init()
In order to be able to select the right DTB, we need to have identified the
board before spl_early_init() is called.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-06 11:27:40 -04:00
Tom Rini
4f42a0d721 Merge git://git.denx.de/u-boot-sunxi 2017-10-05 08:26:36 -04:00
Masahiro Yamada
9b643e312d treewide: replace with error() with pr_err()
U-Boot widely uses error() as a bit noisier variant of printf().

This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:

  # define __compiletime_error(message) __attribute__((error(message)))

This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux.  (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)

Let's convert error() into now treewide-available pr_err().

Done with the help of Coccinelle, excluing tools/ directory.

The semantic patch I used is as follows:

// <smpl>
@@@@
-error
+pr_err
 (...)
// </smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-04 11:59:44 -04:00
Masahiro Yamada
b44b30260f printk: collect printk stuff into <linux/printk.h> with loglevel support
When we import code from Linux, with regular re-sync planned, we want
to use printk() and pr_*().  U-Boot does not support them in a clean
way.  So, people end up with local macros, or compat headers here and
there, then we occasionally see build errors of definition conflicts.

We have include/linux/compat.h, but putting all sorts of unrelated
things into a single header is just a temporal workaround.  Hence this
patch, to find the best home for all printk variants.  If you want to
use printk() and friends, please include <linux/printk.h>.  This header
is self-contained, and pulls in only a few headers.

When I was testing this clean-up, I noticed the image size exceeded
its platform limit on some boards.  This is because all pr_*() that
were previously defined as no-op in include/linux/mtd/mtd.h (unless
CONFIG_MTD_DEBUG is set), are now enabled.

To make such boards happy, this commit also implements CONFIG_LOGLEVEL.
The concept is similar to the kernel parameter "loglevel".  (Actually,
the Kconfig help message was taken from kernel-paremeter.txt of Linux)
Messages with a loglevel smaller than console loglevel will be printed.

The difference is the loglevel is build-time determined.  To save the
image size, lower priority pr_*() are compiled out.  I set the default
of CONFIG_LOGLEVEL to 6, i.e. pr_notice and higher priority messages
are compiled in.

I adjusted CONFIG_LOGLEVEL to avoid build error for some boards.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Add in SPL_LOGLEVEL that is the same as LOGLEVEL]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-04 10:31:17 -04:00
Maxime Ripard
9f35688349 sunxi: usb_phy: invert the USB phy_ctl condition
All the new SoCs from Allwinner since the A33 have had the phy_ctl offset
at 0x410 instead of 0x404 that was used on the previous SoCs.

Instead of adding more and more special cases as the number of SoCs grow,
let's invert the test to have 0x410 by default, and the (hopefully) fixed
number of old SoCs being the exception.

Suggested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Suggested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-10-03 19:12:06 +02:00
Jagan Teki
ea5b1e1efb sun7i: a20: Add Bananapi M1 Plus support
Banana Pi M1 Plus is an open-source single-board computer
that adds more connectivity to the classic board using
Allwinner A20 SOC.

Bananapi M1-Plus features:
- A20 Dual-core 1.0GHz
- 1 GB DDR3 SDRAM
- MicroSD
- 10/100/1000 Ethernet RJ45
- WiFi b/g/n
- 5V DC Micro USB power-supply

For dts file,
Sync with Linux commit f92ca09("Merge branch 'akpm/master'").

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-10-03 19:12:06 +02:00
Chen-Yu Tsai
1328a81621 sunxi: rename Bananapi M3 dts file name
The upstream (Linux) device tree file for the Bananapi M3 follows the
convention of using the well known brand name, instead of the vendor
name, for naming. The file was recently added to upstream in commit
359b5a1e1c2d ("ARM: sun8i: a83t: Add device tree for Sinovoip Bananapi
BPI-M3")

Rename the device tree file in U-boot to match.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:06 +02:00
Maxime Ripard
3c989f3a19 sunxi: Fix USB_GADGET implication
USB_GADGET will fail to compile if USB_MUSB_GADGET is not defined. Make
sure we have that condition right.

Fixes: e0ea88042d51 ("sunxi: Imply USB_ETHER")
Suggested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:06 +02:00
Maxime Ripard
8829076a5b arm: sunxi: Move spl_boot_device in a separate function
U-Boot itself might need to identify the boot device, for example to be
able to tell where to load the kernel from when several options are
possible.

Move the logic of spl_boot_device to a function that is compiled both for
the SPL and the main binary.

Tested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:06 +02:00
Stefan Mavrodiev
6ee9d7be06 sunxi: Add support for A20-OLinuXino-MICRO-eMMC
From rev.J A20-OLinuXino-MICRO has eMMC option. For now this is
only 4GB, but in the future size may increase.

The dts file is the same from mainline kernel.

Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:05 +02:00
Maxime Ripard
a12fb0e368 sunxi: Enable CMD_GPT by default
GPT is pretty common these days and can be useful for things like fastboot.
Add a platform imply, so that users can still opt out if they wish so.

Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:05 +02:00
Maxime Ripard
5ed8239383 sunxi: sina33: Sync the device tree with the kernel
The kernel DT of the SinA33 has evolved quite a bit. Make sure we sync it
and its upstream DTSI to be able to use the OTG. The DTs were taken from
the 4.13 kernel release.

Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:05 +02:00
Maxime Ripard
6e2166c186 sunxi: Imply USB_ETHER
Now that we can enable the usb_ether gadget, do it. This will be especially
useful for boards that don't have any ethernet controller, such as the ones
based on the A13 or A33.

Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:05 +02:00
Maxime Ripard
3a61b080ac musb: sunxi: switch to the device model
The device model was implemented so far using a hook that needed to be
called from the board support, without DT support and only for the host.

Switch to probing both in peripheral and host mode through the DT.

Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:05 +02:00
Maxime Ripard
cfa34996b0 cmd: fastboot: Rework fastboot dependency
Fastboot need a bunch of options to be operating properly, such as the
g_dnl gadget, the fastboot command, and some options that make sense. Since
fastboot is now part of Kconfig, make sure we have them right.

That will also reduce the boilerplate in the defconfigs.

Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:05 +02:00
Maxime Ripard
654b02b18c sunxi: imply USB_GADGET
A good number of our boards have USB_GADGET enabled. Imply it so that all
the boards can benefit from it, and remove some boilerplate from our
defconfigs.

Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:05 +02:00
Maxime Ripard
a95aee6af7 usb: gadget: Make g_dnl USB settings common
The g_dnl USB settings for the vendor ID, product ID and manufacturer are
actually common settings that can and should be shared by all the gadgets.

Make them common by renaming them, and convert all the users.

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:05 +02:00
Paul Burton
8f8e6304df arm: Use asm-generic/io.h
Convert the arm architecture to make use of the new asm-generic/io.h to
provide address mapping functions. As the generic implementations are
suitable for arm this is primarily a matter of removing code.

This has only been build-tested, feedback from architecture maintainers
is welcome.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-02 21:52:20 -04:00
Kever Yang
e19fa89c9d rockchip: enable TPL_SYSRESET for all rockchip SoCs
With Makefiles testing for $(SPL_TPL_)SYSRESET, we need TPL_SYSRESET
for do_reset() in TPL for Rockchip SoCs.

References: 87c16d4 "drivers: spl: consistently use the $(SPL_TPL_)
macro"

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:35 +02:00
Jagan Teki
2ee3021ae1 rk3288: spl: Add dram_init_banksize
Falcon mode, is updating DDR dt node configuration through
spl_fixup_fdt() so add appropriate DDR base and size through
dram_init_banksize.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:35 +02:00
Philipp Tomsich
482cf22333 rockchip: rk3399-puma: add boot-on regulator to override BIOS_DISABLE
The (Qseven) BIOS_DISABLE signal on the RK3399-Q7 (Puma) keeps the
eMMC and SPI in reset initially and we need to write a GPIO to turn
them on before continuing the boot-up.

This adds the DTS entries for the additional regulator and makes
pinctrl and gpio3 available during SPL.  It also adds a hook to the
spl_board_init() to ensure that the regulator gets probed and enabled.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:35 +02:00
Philipp Tomsich
775bd78a11 rockchip: dts: rk3399-puma: add 'same-as-spl' to the front of the boot-order
In the general case, we want to continue booting the full U-Boot
(contained in a discoverable FIT image) from the same device the SPL
stage was loaded from.  This prepends the 'same-as-spl' specifier to
our configurable boot-order to make this the default behaviour.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:35 +02:00
Philipp Tomsich
c55addd360 rockchip: spl: rk3399: implement chip-specific board_spl_was_booted_from()
To support the new "same-as-spl" specifier in the boot-order on the
RK3399, this implements the chip-specific mapping from the information
obtainable from the BROM to a OF path name.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:34 +02:00
Philipp Tomsich
80e9f88e67 rockchip: spl: support a 'same-as-spl'-specifier in the spl-boot-order
It is often desirable to configure the spl-boot-order (i.e. the order
that SPL probes devices to find the FIT image containing a full U-Boot)
such that it contains 'the same device the SPL stage was booted from'
early on.  To support this, we introduce the 'same-as-spl' specifier
for the spl-boot-order property.

This commit adds:
 - documentation for the new board_spl_was_booted_from() function that
   individual SoCs/boards should provide, if they can determine where
   the SPL was booted from
 - implements the new board_spl_was_booted_from() stub function
 - adds support for handling the 'same-as-spl' specifier and calling
   into the per-SoC/per-board support code.

This also updates the documentation for the 'u-boot,spl-boot-order'
property.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:34 +02:00
Philipp Tomsich
dbad01cab5 rockchip: spl: add documentation for spl_node_to_boot_device()
In the expectation that the spl-boot-order code will eventually
gain use outside of mach-rockchip: let's add documentation on the
spl_node_to_boot_device() function, which is likely to become a
publicly exported function.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:34 +02:00
Philipp Tomsich
3b4f87735d rockchip: bootrom: add definitions to retrieve BROM boot-source
The Rockchip BROM allows reading where it booted from from SRAM.
This adds the necessary definitions (as received from Kever) for
the location of this information in the RK3399's SRAM and naming
for the constants used.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:34 +02:00
Philipp Tomsich
fb7406469c rockchip: rk3399: make spl_board_init board-specific
The later-stage spl_board_init (as opposed to board_init_f) should set
up board-specific details: these differ between the EVB-RK3399 and the
RK3399-Q7 (Puma).

This moves spl_board_init back into the individual boards and removes
the unneeded functionality from Puma.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:34 +02:00
Kever Yang
4a18729726 rockchip: rk322x: update the sysreg number for boot mode
The boot mode for rk322x is stored in sysreg 0, update it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:34 +02:00
Elaine Zhang
f9674f5eec rockchip: dts: rk3328-evb: add i2c1 and rk805 nodes
add i2c1 and rk805 nodes to support rk805 init setting.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:33 +02:00
Jagan Teki
532cb7f5ad rk3288: vyasa: Add TPL support
Since the size of SPL can't be exceeded 0x8000 bytes in RK3288,
it is not possible add new SPL features like Falcon mode or etc.

So add TPL stage so-that adding new features to SPL is possible.
- TPL: DRAM init, clocks
- SPL: MMC, falcon, etc

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:33 +02:00
Jagan Teki
a982d5156d armv7: rk3288: Move configure_l2ctlr to common
configure_l2ctlr will be shared between SPL and TPL so
move them into asm/arch/sys_proto.h

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:33 +02:00
Jagan Teki
d9a7dcf5b8 armv7: Move L2CTLR read/write to common
L2CTLR read/write functions are common to armv7 so, move
them in to include/asm/armv7.h and use them where ever it need.

Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Backed out the change to arch/arm/mach-tegra/cache.c:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:33 +02:00
Kever Yang
04e97e48d0 rockchip: rk3036: fix grf macro define
Some of macros definition are not correct, fix them according to TRM.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:32 +02:00
Philipp Tomsich
cbe18f10e6 rockchip: rk3399: spl: convert to using BOOT_DEVICE_BOOTROM
Instead of directly calling into the back-to-bootrom code, the RK3399
common SPL implementation now uses BOOT_DEVICE_BOOTROM to trigger a
transfer back into the bootrom.

With this factored out, the spl_board_init function can not be
customised for each RK3399 board.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:32 +02:00
Kever Yang
ffd1cd67da rockchip: dts: rk3229: remove dram channel info
The dram channel info will be auto detect by the driver,
we do not need it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-10-01 00:33:32 +02:00
Kever Yang
0176399b79 rockchip: rk322x: add sdram driver
Add driver for rk322x to support sdram initialize in SPL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:32 +02:00
Kever Yang
f0768491db rockchip: rk3328: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:31 +02:00
Kever Yang
c9eb7bca4b rockchip: rk3288: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:31 +02:00
Kever Yang
5b67d7010b rockchip: rk3188: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:31 +02:00
Kever Yang
b5934cf67c rockchip: rk3399: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:31 +02:00
Philipp Tomsich
8e8bcccc18 rockchip: imply ADC and SARADC_ROCKCHIP for Rockchip SOCs
Enable the Rockchip SARADC driver for all Rockchip SoCs.

Note that the SARADC peripheral is available on all SoCs except the
RK3036 and RK3228.  However, as this is a DM-driver, enabling by
default will not cause any function problems (and can always be
changed from defconfig, if size is a concern).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: David Wu <david.wu@rock-chips.com>
2017-10-01 00:33:31 +02:00
David Wu
3b4cab15ac rockchip: dts: Enable SARADC for rk3399-evb
Enable the SARADC for download key pressed detect.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:31 +02:00
David Wu
6333a3bad9 rockchip: dts: Enable SARADC for rk3368-sheep
Enable the SARADC for download key pressed detect.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:31 +02:00
David Wu
0ac1ae65ea rockchip: dts: Enable SARADC for rk3368-px5-evb
Enable the SARADC for download key pressed detect.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:30 +02:00
David Wu
f957dec682 rockchip: dts: Enable SARADC for rk3328-evb
Enable the SARADC for download key pressed detect.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:30 +02:00
David Wu
0eaf58bfaa rockchip: dts: Enable SARADC for rk3288-popmetal
Enable the SARADC for download key pressed detect.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:30 +02:00
David Wu
679276bde6 rockchip: dts: Enable SARADC for rv1108-evb
Enable the SARADC for download key pressed detect.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:30 +02:00
David Wu
fdc1eccbd1 rockchip: dts: rv1108: Add SARADC node at dtsi level
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:30 +02:00
David Wu
615514c16d rockchip: clk: Add rk3368 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:30 +02:00
David Wu
2e4ce50d1a rockchip: clk: Add rv1108 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:29 +02:00
Karthik Tummala
8adb6ec885 arm: dts: omap3: sync DTS with Linux 4.14-rc1
This re-syncs omap3 DTS file with current file from
Linux v4.14-rc1 to ensure a consistent configuration. Upstream
Linux removed the redundant Interrupt-parent property from usbhsohci,
usbhsehci, ssi_port1 and ssi_port2 sub nodes.

Signed-off-by: Karthik Tummala <karthik@techveda.org>
2017-09-29 14:07:57 -04:00
Lokesh Vutla
df518f804f ARM: dts: OMAP5+: Enable all gpios in SPL
With DM enabled, gpio numbering is assigned based on the
probed order of gpios, irrespective of the gpio base. So enable
all necessary gpios in SPL.

Fixes: edf25d94d55c (“ARM: dts: OMAP5+: Enable gpio in SPL”)
Reported-by: Gou, Hongmei <h-gou@ti.com>
Tested-by: Aparna Balasubramanian <aparnab@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-29 14:07:56 -04:00
Madan Srinivas
0830d72bb9 arm: am33xx: security: adds auth support for encrypted images
This patch adds support for authentication of both plain
text and encrypted binaries. A new SECDEV package is needed
to enable encryption of binaries by default for AM3x.

The ROM authentication API detects encrypted images at
runtime and automatically decrypts the image if the
signature verification passes.

Addition of encryption on AM3x results in a change in the
image format. On AM4x, AM5x and, on AM3x devices signing
clear test images, the signature is appended to the end of the
binary.

On AM3x, when the SECDEV package is used to create signed
and encrypted images, the signature is added as a header
to the start of the binary. So the binary size calculation
has been updated to reflect this change.

The signing tools and encrypted image format for AM3x
cannot be changed to behave like AM4x and AM5x to
maintain backward compatibility with older Sitara
M-Shield releases.

Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-09-29 14:07:55 -04:00
Adam Ford
b85781c2a8 ARM: omap3: am3517-evm: Add device tree and DM support
With the device tree ported from Linux 4.13, this enables
Driver Model and Device Tree support for the am3517-evm

Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
2017-09-29 14:07:54 -04:00
Adam Ford
a56fd949a5 arm: dts: am3517_evm: Sync DTS files with Linux 4.13-RC5
To keep the DTS and DTSI files clean and in sync with Linux, new
u-boot.dtsi files are added.

There are some spacing issues in the patch, but they appear to be
present in the Linux source files.  I'll try to get to fixing them there,
and do a future re-sync at a later date.

Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
2017-09-29 14:07:54 -04:00
Tom Rini
ff6c3125e7 TI: ARCH_OMAP2PLUS: Enable SPL_STACK_R and provide default value
On ARCH_OMAP2PLUS platforms we know what the DDR layout is going to be,
and that it is safe to use SPL_STACK_R and provide a default value for
it.  select this and re-sync the defconfigs.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-29 14:07:51 -04:00
Adam Ford
c774207f48 ARM: da850-evm: Enable DM_I2C
With DM now enabled with the device tree pulled from Linux, we can
enable DM_I2C in U-Boot.

Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Add DM_I2C_COMPAT to da850_am18xxevm to fix warning]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-29 14:07:18 -04:00
Wenyou Yang
40f3429415 board: at91sam9x5ek: Convert to CONFIG_DM_VIDEO
Convert the board to support the video driver model, add the device
tree node, and remove the unnecessary code.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-29 17:51:56 +02:00
Wenyou Yang
e974b08119 board: sama5d4_xplained: Convert to CONFIG_DM_VIDEO
Convert the board to support the video driver model, add the device
tree node, and remove the unnecessary code.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-29 17:51:22 +02:00
Wenyou Yang
4b0467db53 board: sama5d4ek: Convert to CONFIG_DM_VIDEO
Convert the board to support the video driver model, add the device
tree node, and remove the unnecessary code.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-29 17:50:44 +02:00
Wenyou Yang
fe32c6d159 board: sama5d3xek: Convert to CONFIG_DM_VIDEO
Convert the board to support the video driver model, add the device
tree node, and remove the unnecessary code.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-29 17:50:04 +02:00
Wenyou Yang
d2cd09bb44 board: sama5d2_xplained: Convert to CONFIG_DM_VIDEO
Convert the board to support the video driver model, add the device
tree node, and remove the unnecessary code.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-29 17:48:56 +02:00
Adam Ford
4c70755986 arm: dts: da850: Migrate da850-evm DTS files from Linux 4.13-RC5
A few small additional items are needed to support DM_SPI and
DM_SERIAL, so those were added to da850-evm-u-boot.dtsi

Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-29 10:52:20 -04:00
Baruch Siach
f3a88e2ca1 arm: mvebu: fix boot from UART on ClearFog Base
The ClearFog Base boot from UART when setting the DIP switches to 01001.
Unfortunately, the SPL code sometimes fails to detect the UART boot
method at run-time. Add an alternative SAR UART boot value to fix this.

Note that this alternative value is not documented (Armada 38x Hardware
Specifications, Table 48). But experimentations showed it on the
ClearFog Base.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26 06:53:18 +02:00
Chris Packham
c3ab274444 ARM: mvebu: handle unused DRAM banks with ECC enabled
dram_ecc_scrubbing() had code to skip unused DRAM banks but it would not
work because mvebu_sdram_bs() returns 0 and the code was subtracting 1
before checking the size. Remove the -1 from the bank size and the +1
from the total which will skip unused banks and still calculate the
correct size. Put the -1 where it is needed for scrubbing via the xor
engine.

Reported-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26 06:52:57 +02:00
Chris Packham
0a91e1cce4 ARM: mvebu: add SAR frequency values for 1.8/2.0GHz
The Armada-38x has 1.8GHz and 2.0GHz variants. Add entries for these
variants to the sar_freq_tab.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26 06:51:54 +02:00
Joshua Scott
631407c5c0 ARM: mvebu: add additional information to board_add_ram_info()
Display more information about the current RAM configuration. With these
changes the output on a 88F6820 board is

  SoC:   MV88F6820-A0 at 1600 MHz
  DRAM:  2 GiB (800 MHz, 32-bit, ECC not enabled)

Signed-off-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26 06:51:50 +02:00
Chris Packham
0f8031a333 ARM: mvebu: Add SoC IDs for Marvell's integrated CPUs
These SoCs are network packet processors (switch chips) with integrated
ARMv7 cores. They share a great deal of commonality with the Armada-XP
CPUs.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26 06:51:43 +02:00
Chris Packham
7654f62f4e ARM: mvebu: Convert CONFIG_MVNETA to Kconfig
This converts the following to Kconfig:
   CONFIG_MVNETA

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26 06:51:30 +02:00
Marek Vasut
891ac390b8 ARM: dts: rmobile: Add PHY reset GPIO
The PHY reset GPIOs were missing from the DT, add them.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-24 14:12:07 +09:00
Tom Rini
0929863aff Merge git://git.denx.de/u-boot-socfpga 2017-09-23 17:32:53 -04:00
Masahiro Yamada
5e8c39d4f4 ARM: socfpga: fix duplicate const specifier warning
GCC 7.1 warns:
duplicate ‘const’ declaration specifier [-Wduplicate-decl-specifier]

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-23 15:13:20 +02:00
Sriram Dash
0d7f1ae0fe armv8: fsl: i2c: Put I2C related code under CONFIG_SYS_I2C
I2C code is put under CONFIG_SYS_I2C.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22 12:45:27 -07:00
Sriram Dash
e45ff0ce63 armv8: fsl: ifc: Put IFC related code under CONFIG_FSL_IFC
IFC code is put under CONFIG_FSL_IFC

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22 12:45:17 -07:00
Santan Kumar
77dc01bdc1 board/ls2081ardb: Update QSPI flash type from n25q512a to s25fs512s
As per updated board design, different QSPI flash
is connected on boards, hence change QSPI flash type
from Micron n25q512a device to spansion s25fs512s
device in dts and config.

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22 12:41:54 -07:00
Ashish Kumar
bdbcb52256 armv8: fsl-layerscape: Put SATA code under SATA configs
It is not necessary for every SoC to have 2 SATA controller.
So put SATA1, SATA2 code under respective defines.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22 12:41:24 -07:00
Felix Brack
7cc238f2ee arm: am33xx: Make pin multiplexing functions optional
This patch provides default implementations of the two functions
set_uart_mux_conf and set_mux_conf_regs. Hence boards not using
them do not need to provide their distinct empty definitions.

Signed-off-by: Felix Brack <fb@ltec.ch>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-22 07:40:04 -04:00
Patrice Chotard
246771b184 board: Add stm32h7 SoC, discovery and evaluation boards support
This patch adds support for stm32h7 soc family, stm32h743
discovery and evaluation boards.

For more information about STM32H7 series, please visit:
http://www.st.com/en/microcontrollers/stm32h7-series.html

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:40:03 -04:00
Patrice Chotard
a1e384b4d9 ARM: DTS: stm32: adapt stm32h7 dts files for U-boot
This patch adapts stm32h743 disco and eval dts files to match
with U-boot requirements or add features wich are not yet
upstreamed on kernel side :

_ Add RCC clock driver node and update all clocks phandle
  accordingly.

  By default, on kernel side, all clocks was temporarly
  configured as a phandle to timer_clk waiting for a RCC
  clock driver to be available.
  On U-boot side, we now have a dedicated RCC clock driver, we
  can configured all clocks as phandle to this driver.

  All this binding update will be available soon in a kernel tag,
  as all the bindings have been acked by Rob Herring [1].

  [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html

_ Align STM32H7 serial compatible string with the one which will be
  available in next kernel tag. The bindings has been acked by
  Rob Herring [2].
  This compatible string will be usefull to add stm32h7 specific
  feature for this serial driver.

  [2] https://lkml.org/lkml/2017/7/17/739

_ Add gpio compatible and aliases for stm32h743

_ Add FMC sdram node with associated new bindings value to
  manage second bank (ie bank 1).

_ Add missing HSI and CSI oscillators nodes needed
  by STM32H7 RCC clock driver.

  Clock sources could be:
	_ HSE (High Speed External)
	_ HSI (High Speed Internal)
	_ CSI (Low Power Internal)

  These clocks can be used as clocksource in some configuration.
  By default, HSE is selected as clock source.

_ Set HSE to 25Mhz for stm32h743i-disco and eval board

  By default, the external oscillator frequency is defined at
  25 Mhz in SoC stm32h743.dtsi file.
  It has been set at 125 Mhz in kernel DT temporarly waiting for
  RCC clock driver becomes available.

  As in U-boot we got a RCC clock driver, the real value of HSE
  clock can be used.

_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
  pwrcfg and gpio nodes.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:40:03 -04:00
Patrice Chotard
5fbb2b25ae ARM: DTS: stm32: add stm32h743i-eval files
This file is imported from linux kernel v4.13

Add device tree support for STM32H743 evaluation board.
This board offers :
  _ STM32H743XIH6 microcontroller with 2 Mbytes of
    Flash memory and 1 Mbyte of RAM in TFBGA240+25 package
  _ 5.7” 640x480 TFT color LCD with touch screen
  _ Ethernet compliant with IEEE-802.3-2002
  _ USB OTG HS and FS
  _ I2 C compatible serial interface
  _ RTC with rechargeable backup battery
  _ SAI Audio DAC
  _ ST-MEMS digital microphones
  _ 8-Gbyte (or more) SDIO3.0 interface microSD™ card
  _ 8Mx32bit SDRAM, 1Mx16bit SRAM and 8Mx16bit NOR Flash
  _ 1-Gbit Twin Quad-SPI NOR Flash
  _ Potentiometer
  _ 4 colored user LEDs
  _ Reset, wakeup, tamper or key buttons
  _ Joystick with 4-direction control and selector
  _ Board connectors :
     Power jack
     3 USB with Micro-AB
     RS-232 communications
     Ethernet RJ45
     FD-CAN compliant connection
     Stereo headset jack including analog microphone input
     2 audio jacks for external speakers
     microSD™ card
     JTAG/SWD and ETM trace
   _ Expansion connectors:
     Extension connectors and memory connectors for daughterboard
     or wire-wrap board
   _ Flexible power-supply options: ST-LINK USB VBUS or external
     sources
   _ On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration
     capability: mass storage, virtual COM port and debug port

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:40:03 -04:00
Patrice Chotard
d983a0f008 ARM: DTS: stm32: add stm32h743i-disco files
All these files are imported from linux kernel v4.13

Add device tree support for STM32H743 SoC and discovery
board. This board offers :
  _ STM32H743XIH6 microcontroller with 2 Mbytes of
    Flash memory and 1 Mbyte of RAM in TFBGA240+25 package
  _ 5.7” 640x480 TFT color LCD with touch screen
  _ Ethernet compliant with IEEE-802.3-2002
  _ USB OTG HS
  _ I2 C compatible serial interface
  _ ST-MEMS digital microphones
  _ 8-Gbyte (or more) SDIO3.0 interface microSD™ card
  _ 8Mx32bit SDRAM
  _ 1-Gbit Twin Quad-SPI NOR Flash
  _ Reset, wakeup, or key buttons
  _ Joystick with 4-direction control and selector
  _ Board connectors :
	1 USB with Micro-AB
	Ethernet RJ45
	Stereo headset jack including analog microphone input
	microSD™ card
	RCA connector
	JTAG/SWD and ETM trace
   _ Expansion connectors:
	Arduino Uno compatible Connectors
	2 x PIO connectors (PMOD and PMOD+)
   _ On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration
     capability: mass storage, virtual COM port and debug port

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:40:02 -04:00
Patrice Chotard
bfd7ef110a ARM: dts: STiH410: update ehci and ohci compatible
Update ehci and ohci node's compatible string in order to
use ehci-generic and ohci-generic drivers.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:39:59 -04:00
Patrice Chotard
01d142850e ARM: dts: STiH410: set DWC3 dual role mode to peripheral
On STi 96boards, configure by default the micro USB connector
(managed by DWC3 hardware block) in peripheral mode.
This will allow to use fastboot feature.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:39:59 -04:00
Patrice Chotard
40d1a31e63 usb: dwc3: Add dwc3 glue driver support for STi
This patch adds the ST glue logic to manage the DWC3 HC
on STiH407 SoC family. It configures the internal glue
logic and syscfg registers.

Part of this code been extracted from kernel.org driver
(drivers/usb/dwc3/dwc3-st.c)

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:39:59 -04:00
Patrice Chotard
9ea2fc88dd ARM: dts: stih410-family: Add missing reset_names for mmc1 node
reset-names property is needed to use the reset
API for STi sdhci driver.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:39:57 -04:00
Tom Rini
e884656c2c Merge git://www.denx.de/git/u-boot-imx 2017-09-20 12:32:34 -04:00
Fabio Estevam
511db3bf5a toradex: imx6: Move g_dnl_bind_fixup() into common SPL code
Instead of having every board file to add its own g_dnl_bind_fixup()
implementation, move it to the common imx6 SPL code.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
2017-09-20 15:34:59 +02:00
Tom Rini
975f97b431 Merge git://git.denx.de/u-boot-rockchip 2017-09-18 15:44:57 -04:00
Kever Yang
6e5bd8d6f3 rockchip: ram: rk3399: update reg map for of-platdata
After Simon's patch, the dtoc can work with 64bit address,
so we need to fix reg number for it.
Depend on Simon's patch set:
https://patchwork.ozlabs.org/cover/807266/

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:38 +02:00
Philipp Tomsich
75ff057851 rockchip: dts: rk3368: reduce the number of nodes seen in TPL
The RK3368 TPL stage always returns to the BootROM, so it has no need
for the eMMC, SD and SPI nodes.  This marks those nodes (that should
be included in SPL, but not TPL) as 'u-boot,dm-spl'.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18 20:40:38 +02:00
Philipp Tomsich
46c89c8efa rockchip: dts: rk3399-puma: replace 'rockchip, vbus-gpio' with fixed regulator
On the RK3399-Q7, we need to turn on the on-module USB hub before using the
USB host interfaces (only the OTG interface is directly connected to the edge
connector).  This drops the deprecated 'rockchip,vbus-gpio' property and uses
a fixed regulator to turn on the USB hub.

References: 26a8b80 "usb: host: xhci-rockchip: use fixed regulator to control vbus"
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18 20:40:37 +02:00
Jagan Teki
d55af074e5 rk3288: Add Vyasa initial board support
This patch adds support for Vyasa RK3288 initial board
from Amarula Solutions.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:36 +02:00
Philipp Tomsich
ba1657338b rockchip: rk3399: spl: remove hard-coded addresses for GRF and SGRF
On the RK3399, we will have either OF_PLATDATA or full OF_CONTROL
enabled: this allows the use of syscon to retrieve the addresses of
GRF and SGRF (except for the early debug UART setup, which runs so
early that the device-model is not initialised).

This removes the hard-coded addresses and goes through syscon to
retrieve the base-addresses of GRF and SGRF. After that, we use
the structure definitions to locate the respective registers.

In addition to this, the inclusion of header files is also cleaned up:
- all headers are included at the beginning (there was a spurious
  inclusion of the grf header from within a function)
- all #include statements for unused headers are removed
- the remaining #include statements are sorted (while keeping common.h
  included in front)

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18 20:40:36 +02:00
Philipp Tomsich
f041176c46 rockchip: dts: rk3368-lion: add /chosen/tick-timer
To support bootstage recording, we want to mark our DM timer as the
tick-timer; this triggers the support for 'trying harder' to read the
timer in the Rockchip DM timer driver, even if the device model isn't
ready yet.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:36 +02:00
David Wu
4c94aacd62 rockchip: rk322x: Disable integrated macphy for saving power consuming
Unfortunately, the integrated macphy default is enabled, which will
increase power consuming, if we do not use this PHY. So let's disable
it at first, which will save power consuming. If we really use it, then
enable it in driver level.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:33 +02:00
Kever Yang
c964a0dcae rockchip: rk322x: enable fastboot to set boot mode tag
To support fastboot "fastboot reboot-bootloader" cmd.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:32 +02:00
William Wu
809ec9454f ARM: dts: rockchip: add USB nodes for evb-rv1108
This patch adds USB OTG/EHCI/OHCI nodes for evb-rv1108 USB ports.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:32 +02:00
Eric Nelson
8590786acf imx: imx7d: remove CamelCase from ENET_xMHz macros
Update these macros to use all upper-case to avoid checkpatch
warnings:

	ENET_25MHz,
	ENET_50MHz,
	ENET_125MHz,

Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-09-18 17:15:28 +02:00
Stefan Agner
e203dcf23e imx_common: detect USB serial downloader reliably
The current mechanism using SCR/GPR registers work well when
the serial downloader boot mode has been selected explicitly
(either via boot mode pins or using bmode command). However,
in case the system entered boot ROM due to unbootable primary
boot devices (e.g. empty eMMC), the SPL fails to detect that
it has been downloaded through serial loader and tries to
continue booting from eMMC:
  Trying to boot from MMC1
  mmc_load_image_raw_sector: mmc block read error
  SPL: failed to boot from all boot devices
  ### ERROR ### Please RESET the board ###

The only known way to reliably detect USB serial downloader
is by checking the USB PHY receiver block power state...

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
2017-09-18 17:15:22 +02:00
Stefan Agner
7d289d6239 imx: add macro to detect whether USB PHY is active
This macro allows to detect whether the USB PHY is active. This
is helpful to detect if the boot ROM has previously started the
USB serial downloader.

The idea is taken from the mfgtool support in the NXP U-Boot:
http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/?h=imx_v2016.03_4.1.15_2.0.0_ga&id=a352ed3c5184b95c4c9f7468f5fbb5f43de5e412

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
2017-09-18 16:51:36 +02:00
Masahiro Yamada
a184fb8e96 ARM: uniphier: add GPU(Mali) reset deassert and clk enable
The driver for Linux is out of control of Socionext, so set up
reset / clock in here.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-18 20:26:18 +09:00
Masahiro Yamada
2bf7c86ebb ARM: uniphier: remove bit field macros from sc64-regs.h
Starting from PXs3, the bit fields of  RSTCTRL, CLKCTRL registers
will change every SoC.  There is no more point to define bitfields
in the common header file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-18 20:26:12 +09:00
Masahiro Yamada
81b9bb5fcb ARM: uniphier: merge two defconfig files into uniphier_v7_defconfig
The main difference between Pro4 and PXs2/LD6b is the Denali NAND
IP version.  This is now distinguished by DT.  Merge the two defconfig
files into uniphier_v7_defconfig.

Update the README.uniphier too.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-18 20:26:06 +09:00
Adam Ford
079c92b0a7 ARM: davinci: Remove CONFIG_SOC_DA830
Nothing CONFIG_SOC_DA830 anymore, so let's remove it and
the one remaining source file for it. It appears to have been
abandoned a while ago.

Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-15 12:35:48 -04:00
Jean-Jacques Hiblot
8ce5fac9a0 arm: dts: Add missing u-boot specific dtsi for dra7-evm
commit b63b995 (arm: dts: Add u-boot specific compatibles) separated out
u-boot specific compatibles from dts files.
The u-boot specifics were moved in *-u-boot.dtsi files for all dra7
platforms except dra7-evm.
Without it the SD card is broken on DRA7-evm because the regulator cannot
be enabled.
Fix it by adding the missing dra7-evm-u-boot.dtsi with the needed
properties.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-15 12:35:48 -04:00
Harinarayan Bhatta
a1e4bc65e1 arm: mach-omap2: Relax checks on OP-TEE location to allow pageable image
When the OP-TEE image is built for secure paging the load address may be
in SRAM, remove checks that prevent this.

Signed-off-by: Harinarayan Bhatta <harinarayan@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-15 09:03:16 -04:00
Bin Meng
723b43daec blk: Remove various places that do flush cache after read
All these places seem to inherit the codes from the MMC driver where
a FIXME was put in the comment. However the correct operation after
read should be cache invalidate, not flush.

The underlying drivers should be responsible for the cache operation.
Remove these codes completely.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: York Sun <york.sun@nxp.com>
2017-09-15 08:05:10 -04:00
Suman Anna
2f9455c849 ARM: DRA7: Cleanup old pinctrl macros
Commit 6ae4c3efbd ("ARM: DRA7: Add pinctrl register definitions")
has added new macros for pinmux configuration in line with the kernel
definitions. Cleanup the old pinctrl macros from the common header
file so that they are not used by any new boards.

Signed-off-by: Suman Anna <s-anna@ti.com>
2017-09-14 21:32:56 -04:00
Wenyou Yang
a35c34025e ARM: at91: spl: Add macro CONFIG_XXXX_BOOT support
Use the CONFIG_XXXX_BOOT to indicate the boot media, instead of
the CONFIG_SYS_USE_XXXX option, which is declared by
CONFIG_SYS_EXTRA_OPTIONS option.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-09-14 16:02:47 -04:00
Wenyou Yang
e61ed48ff5 ARM: at91: Remove hardware.h included in configs
As said in READRE.kconfig, include/configs/*.h will be removed
after all options are switched to Kconfig. As the first step,
remove the follow line from include/configs/*.h.

 #include <asm/hardware.h>

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-09-14 16:02:47 -04:00
Wenyou Yang
2269337614 ARM: at91: Add the SoC options to Kconfig
To prepare to remove the SoCs options such as SAMA5D2, SAMA5D3
and SAMA5D4 from the CONFIG_SYS_EXTRA_OPTIONS option which is
deprecated, add the SoC options to Kconfig.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-09-14 16:02:47 -04:00
Wenyou Yang
6553581a81 ARM: at91: Move CONFIG_AT91FAMILY option to Kconfig
Move the CONFIG_AT91FAMILY option from include/mach/<soc>.h header
file to Kconfig.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-09-14 16:02:46 -04:00
Wenyou Yang
ce4054bf82 board: atmel: Add SAMA5D27 SOM1 EK board
The SAMA5D27-SiP (System in Package) integrates the SAMA5D2
with 1Gbit DDR2-SDRAM in a single package.

The SAMA5D27 SOM1 embeds a 64Mbit QSPI flash, KSZ8081 Phy and
Mac-address EEPROM.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14 16:02:46 -04:00
Wenyou Yang
245cbc583d ARM: at91: Get the Chip ID of SAMA5D2 SiP
The SAMA5D2 SiP(System in Package) has different Chip IDs in the
CHIPID and CHIP_EXID registers.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14 16:02:45 -04:00
Wenyou Yang
b5c13daca4 ARM: at91: mach: Add missing defines of MPDDRC
Add missing defines of Multiport DDR-SDRAM Controller (MPDDRC).

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14 16:02:45 -04:00
Wenyou Yang
dfd6d3a9d4 ARM: at91: spl: Add boot device for boot from QSPI
Add the boot device for booting from the QSPI flash.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14 16:02:45 -04:00
Wenyou Yang
2b21cf55cc ARM: at91: spl: Add mck function to lower rate while switching
Refer to the commit 70f8c8316ad(PMC: add new mck function to lower
rate while switching) from AT91Bootstrap.

While switching to a lower clock source, we must switch the clock
source first instead of last. Otherwise, we could end up with
too high frequency on internal bus and peripherals.
This happens on SAMA5D2 as exitting from the ROM code.

Add a function pmc_mck_init_down() to allow this sequence.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14 16:02:44 -04:00
Wenyou Yang
3ceb5118c6 ARM: at91: spl: Adjust switching to oscillator for SAMA5D2
As said in 29.5.7 section of SAMA5D2 datasheet, before switching to
the crystal oscillator, a check must be carried out to ensure that
the oscillator is present and that its freqency is valid.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14 16:02:44 -04:00
Wenyou Yang
82e0646af7 atmel: common: Add function to display via DM_VIDEO's API
Add a function to display the company's logo and board information
via the API from DM_VIDEO. This function can be shared by other
atmel boards, so locate it in board/atmel/common folder.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14 16:02:43 -04:00
Wenyou Yang
56246d1e87 ARM: dts: at91: sama5: Add the sfr node
For sama5d2, add the sfr node with syscon support.

In order to access the SFR_UTMICKTRIM register for the utmi clock
driver, add the phandle property for the utmi node to point to the
sfr node.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-09-14 16:02:43 -04:00
Wenyou Yang
e7c831543a clk: at91: utmi: Set the reference clock frequency
By default, it is assumed that the UTMI clock is generated from
a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ
field of the SFR_UTMICKTRIM has to be updated to generate the UTMI
clock in the proper way.

The UTMI clock has a fixed rate of 480 MHz. In fact, there is no
multiplier we can configure. The multiplier is managed internally,
depending on the reference clock frequency, to achieve the target
of 480 MHz.

The patch is cloned from the patch of mailing-list:
	[PATCH v2] clk: at91: utmi: set the mainck rate

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
[trini: Depend on SPL_DM]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-14 16:02:29 -04:00
Adam Ford
34330a362f Convert CONFIG_EMIF4 et al to Kconfig
This converts the following to Kconfig:
   CONFIG_EMIF4
   CONFIG_SDRC

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-09-13 09:24:27 -04:00
Adam Ford
bf1ddfc026 arm: dts: omap3: Re-sync DTS files with Linux 4.13-RC5
The DTS files had some spacing issues and they needed fixing. This
pull re-sync's the OMAP3xx related DTS files with Linux 4.13-RC5.

To keep the DTS and DTSI files clean and in sync with Linux, new
u-boot.dtsi files are added.

Signed-off-by: Adam Ford <aford173@gmail.com>

V3: The resync broke card detect on MMC1 on Logic PD's Torpedo,
    so we add the cd-invert to the Torpedo's -u-boot.dtsi file.

V2: Add the u-boot.dtsi files for OMAP3, OMAP36xx, and Torpedo
    Remove the need for the second patch in the series
2017-09-13 09:24:26 -04:00
Wenyou Yang
3e9f8f2f51 ARM: dts: ethernut5: Fix the build warning
Fix the building warning as below:
---8<----
Warning (reg_format): "reg" property in /i2c-gpio-0/pcf8563@50 has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /i2c-gpio-0/pcf8563@50
Warning (avoid_default_addr_size): Relying on default #size-cells value for /i2c-gpio-0/pcf8563@50
--->8----

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-13 09:24:25 -04:00
Vishal Mahaveer
ba39608147 ARM: DRA72x: Add support for detection of DRA71x SR 2.1
DRA71x processors are reduced pin and software compatible
derivative of DRA72 processors. Add support for detection
of SR2.1 version of DRA71x family of processors.

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-12 18:02:29 -04:00
Masahiro Yamada
b27af39935 dma: import linux/dma-direction.h to consolidate enum dma_data_direction
Import include/linux/dma-direction.h from Linux 4.13-rc7 and delete
duplicated definitions of enum dma_data_direction.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-09-12 18:02:23 -04:00
Andy Yan
347e30e172 armv8: mmu: add space around operator
Add space around operator "+", make it
match the coding style.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-12 18:00:09 -04:00
Andy Yan
4f84cb980f armv8: mmu: remove unused macro definition
Macro VA_BITS and PTE_BLOCK_BITS are not used
in the code, so remove them.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-12 18:00:08 -04:00
Marek Vasut
e8f86f2bac ARM: rmobile: dts: Add XHCI USB node to r8a7796
The R8A7796 XHCI USB nodes are missing from r8a7796 dtsi, add them.
These nodes don't come from mainline Linux, yet the DT binding is
similar enough to R8A7795 which already has those in mainline and
once the nodes hit mainline, this DT should be resynched.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-12 23:02:30 +02:00
Marek Vasut
1d871465c4 ARM: rmobile: dts: Add EHCI USB nodes to r8a7796
The R8A7796 EHCI USB nodes are missing from r8a7796 dtsi, add them.
These nodes don't come from mainline Linux, yet the DT binding is
similar enough to R8A7795 which already has those in mainline and
once the nodes hit mainline, this DT should be resynched.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-12 19:07:20 +02:00
Marek Vasut
37a7908137 ARM: dts: rmobile: Update DTS to match Linux 4.13
Import the RCar Gen3 DTS and headers from upstream Linux kernel v4.13,
commit 569dbb88e80deb68974ef6fdd6a13edb9d686261 . This includes both M3
and H3 ULCB and Salvator-X boards.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-12 23:01:51 +02:00
Tom Rini
8a33cb8b6b Merge git://git.denx.de/u-boot-fsl-qoriq 2017-09-12 12:02:50 -04:00
Tom Rini
de2ad2c40d Merge git://git.denx.de/u-boot-dm 2017-09-12 09:32:51 -04:00
Simon Glass
3991f42ed2 dm: core: Add ofnode_for_each_subnode()
Add a convenience macro to iterate over subnodes of a node. Make use of
this where appropriate in the code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-09-11 21:43:58 -06:00
Wenyou Yang
fafa440342 board: sama5d4_xplained: Set mac address from eeprom
Add the code to set the ethernet mac address from eeprom by using
the common code from the common folder.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-11 16:23:08 -04:00
Wenyou Yang
34e2819d31 board: sama5d2_xplained: Replace code to set mac address
Replace the code to set the ethernet mac address with the code from
the common folder.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-11 16:23:07 -04:00
Wenyou Yang
d9b23e26f0 board: atmel: Create board/$(VENDOR)/common folder
Create board/$(VENDOR)/common folder to accommodate the common code
shared by other atmel boards, now put the code to set ethernet mac
address from eeprom, which uses the i2c eeprom driver.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-11 16:23:06 -04:00
Lokesh Vutla
8b2551a4db board: ti: am57xx: Add dt support for BeagleBoard-X15 revC
Add support for selecting proper dtb for
am57xx BeagleBoard X15 revC u-boot from FIT

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-11 16:23:04 -04:00
Steve Kipisz
209742fa88 board: ti: am571x: Add 666MHz support for AM571x IDK
AM571x supports DDR running at 666MHz. Right now it is
clocked at 532MHz which is lower than what is supported.
In order to have maximum performance on AM571-IDK,
switch DDR to 666MHz.

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-11 16:22:31 -04:00
Lokesh Vutla
fede942980 board: ti: dra76: Add dt support
Add support for selecting proper dtb for
dra76x u-boot from FIT.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-11 16:22:30 -04:00
Lokesh Vutla
b63b995b16 arm: dts: Add u-boot specific compatibles
Separate out u-boot specific compatibles from dts files.
This will help in syncing dts files in future.
Also these will get deleted eventually once respective drivers
are capable of handling Linux dts files.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-11 16:19:49 -04:00
Lokesh Vutla
4ddaa6ce28 arm: dts: dra7: sync DT with latest Linux
Sync all dra7* specific dts files with the upstream
kernel including changes queued for 4.14

https://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git/log/?h=omap-for-v4.14/dt-v3

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-11 16:19:48 -04:00
Lokesh Vutla
c9a7c17a96 board: ti: dra76-evm: Add DDR data
dra76-evm has the ddr parts connectedi running at 666MHz:
EMIF1: MT41K512M16HA-125 AIT:A  x 2
EMIF2: MT41K512M8RH-125-AAT:E x 4
Add support for configuring the above DDR parts.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-11 16:19:41 -04:00
Keerthy
c247605510 board: ti: dra76-evm: Add the pmic data
dra76-evm uses lp8736 and tps65917 pmic for powering on
various peripherals. Add data for these pmics and register
for dra76-evm.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-11 16:19:40 -04:00
Praneeth Bajjuri
0f9e6aee9d arm: dra76: Add support for ES1.0 detection
dra76 family is a high-performance, infotainment application
device, based on OMAP architecture on a 28-nm technology.
This contains most of the subsystems, peripherals that are
available on dra74, dra72 family. This SoC mainly features
Subsystems:
- 2 x Cortex-A15 with max speed of 1.8GHz
- 2 X DSP
- 2 X Cortex-M4 IPU
- ISS
- CAL
- DSS
- VPE
- VIP
Connectivity peripherals:
- 1 USB3.0 and 3 USB2.0 subsystems
- 1 x SATA
- 2 x PCI Express Gen2
- 3-port Gigabit ethernet switch
- 2 x CAN
- MCAN

Adding CPU detection support for the dra76 ES1.0 soc
and update prcm, control module, dplls data.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-11 16:19:38 -04:00
Lokesh Vutla
0537e097c9 arm: dra7: Kconfig: Select LP87565 related configs
LP87565 is present on dra76-evm. Select it for
TARGET_DRA7XX_EVM.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-11 16:19:37 -04:00
Lokesh Vutla
db4fce8fcd palmas: Add support for powering different ldos
It is not necessary that ldo1 is used to power on mmc.
So, add support for passing ldo registers for powering on mmc.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-11 16:19:37 -04:00
Lokesh Vutla
91d3e90668 arm: omap5+: Add board specific ldo powering
It is not necessary all omap5+ based uses the same PMIC
to poweron mmc. So add support for enabling mmc based on board.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-11 16:19:35 -04:00
York Sun
42f43aa258 armv8: fsl-layerscape: Add back L3 flushing for all exception levels
CCN-504 HPF registers were believed to be accessible only from EL3.
However, recent tests proved otherwise. Remove checking for exception
level to re-enable L3 cache flushing for all levels.

Signed-off-by: York Sun <york.sun@nxp.com>
Tested-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-11 08:02:13 -07:00
Hou Zhiqiang
4c5c87da7b armv8: ls1088a: add PCIe dts node
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:07 -07:00
Hou Zhiqiang
c4787f4b23 armv8: ls1088a: fix the MMU table for pcie config space
The pcie config space of ls1088a is different from ls2080a.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:07 -07:00
York Sun
e9303a4146 armv8: fsl-layerscape: Fix MC reserved memory calculation
In case high region memory doesn't have enough space for Management
Complex (MC), the return value should indicate a failure so the
caller can handle it accordingly.

Signed-off-by: York Sun <york.sun@nxp.com>
Reported-by: Ebony Zhu <ebony.zhu@nxp.com>
2017-09-11 08:01:07 -07:00
Ran Wang
0e8a4264ec armv7: Add workaround for USB erratum A-009007
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values

Program register USB_PHY_RX_OVRD_IN_HI in certain sequence
to make the Rx compliance test pass.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:07 -07:00
Ran Wang
e10d114279 armv7: Add workaround for USB erratum A-008997
Low Frequency Periodic Singaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings

Change config of transmitter signal swings by setting register
PCSTXSWINGFULL to 0x47 to pass compliance tests.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:06 -07:00
Ran Wang
c1853f6f73 armv7: Add workaround for USB erratum A-009798
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receive
Compliance test failure for a 100mV threshold.

Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE
to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:06 -07:00
Ran Wang
83fa71189a armv7: Add workaround for USB erratum A-009008
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature

Optimal eye at TXREFTUNE value to 0x9 is observed, change
set the same value.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:06 -07:00
Ran Wang
15d59b5316 armv8: Add workaround for USB erratum A-009007
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values.

Program register USB_PHY_RX_OVRD_IN_HI in certain sequence
to make the Rx compliance test pass.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:06 -07:00
Ran Wang
9d1cd910f7 armv8: Add workaround for USB erratum A-008997
Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter
settings

Change config of transmitter signal swings by setting register
PCSTXSWINGFULL to 0x47 to pass compliance tests.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:06 -07:00
Ran Wang
2a8a353958 armv8: Add workaround for USB erratum A-009798
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.

Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE
to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:06 -07:00
Ran Wang
2ab1553f08 armv8: Add workaround for USB erratum A-009008
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature

Optimal eye at TXREFTUNE value to 0x9 is observed, change
set the same value.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:06 -07:00
Ran Wang
9a609a8800 armv8: Add scfg_clrsetbits_32(), scfg_clrbits_32()
Some erratum patch might need it to program registers.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:05 -07:00
Ashish Kumar
17d066fc5d armv8: fsl-layerscape: Support to add RGMII for ls1088aqds
This patch adds support for RGMII protocol

NXP's LDPAA2 support RGMII protocol. LS1088A is the
first Soc supporting both RGMII and SGMII.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:05 -07:00
Ashish Kumar
7769776a60 armv8: ls1088aqds: Add support of LS1088AQDS
This patch add support of LS1088AQDS platform.

The LS1088A QorIQTM Development System (QDS) is a high-performance
computing, evaluation, and development platform that supports the
LS1088A QorIQ Architecture processor.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:05 -07:00
Ashish Kumar
e84a324ba7 armv8: ls1088ardb: Add support for LS1088ARDB platform
LS1088A is an ARMv8 implementation. The LS1088ARDB is an evaluatoin
platform that supports the LS1088A family SoCs. This patch add basic
support of the platform.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Disabled NAND in board header file]
Reviewed-by: York Sun <york.sun@nxp.com>

WIP: disable NAND for LS1088ARDB
2017-09-11 08:00:13 -07:00
Ashish Kumar
6d9b82d085 armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:00:13 -07:00
Suresh Gupta
22c51855bf armv8: fsl-layerscape: Fix final MMU table for QSPI and IFC
For QSPI and IFC addresses execution shouldn't be allowed
when u-boot running from DDR. Revise the MMU final table
to enforce execute-never bits.

Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:00:13 -07:00
Ran Wang
5436c6a347 armv8: fsl: Use correct conditional compile for ls1012a
According current code base, CONFIG_LS1012A should be
CONFIG_ARCH_LS1012A, or function fsl_fdt_disable(blob) will be
wrongly called to disable all dwc3 USB nodes on LS1012A, which
cause Linux USB function stop working at all.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:00:13 -07:00
Ashish Kumar
c055cee195 armv8: fsl-lsch3: Make CCN-504 related code conditional
LS2080 family has CCN-504 cache coherent interconnet. Other SoCs
in LSCH3 family may have differnt interconnect.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 07:55:36 -07:00
Udit Agarwal
15e7c681e1 LS2080ARDB: QSPI boot: Secure Boot image validation
Adds header address for PPA to be validated during ESBC phase for
ARCH_LS2088 and QSPI_BOOT. Moves sec_init prior to ppa_init(). It
must be initialized before the PPA.

Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
[YS: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 07:55:36 -07:00
Sumit Garg
06fb06f66c SECURE_BOOT: Unify memory map for Layerscape based platforms
Unify memory map for Layerscape based platforms. This patch includes
changes in bootscript, bootscript header and PPA header addresses
change as per unified memory map.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 07:55:36 -07:00
Ashish Kumar
63b2316c5c fsl-layerscape: Consolidate registers space defination for CCI-400 bus
CoreLink Cache Coherent Interconnect (CCI) provides full cache
coherency between two clusters of multi-core CPUs and I/O coherency
for devices and I/O masters.

This patch add new config option SYS_FSL_HAS_CCI400 and moves
existing register space definaton of CCI-400 bus to fsl_immap to be
shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET
in Kconfig.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: revised commit message, squashed patches for armv8 and armv7]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 07:55:36 -07:00
Chris Packham
f58ad98a62 usb: net: migrate USB Ethernet adapters to Kconfig
This migrates ASIX, ASIX88179, MCS7830, RTL8152 and SMSC95XX to Kconfig.
Update defconfigs.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-08 10:23:00 -04:00
Chris Packham
ae3584498b usb: net: migrate CONFIG_USB_HOST_ETHER to Kconfig
CONFIG_USB_HOST_ETHER is the framework that the drivers are dependent on
USB_HOST_ETHER. Use this as a menu and move the existing LAN75XX and
LAN78XX options under new menu. Finally update the defconfigs that need
CONFIG_USB_HOST_ETHER.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-08 10:21:46 -04:00
Kever Yang
0532ceef30 rockchip: enable SPL_SYSRESET config for all Rockchip SoCs
With Makefiles testing for $(SPL_TPL_)SYSRESET, we need SPL_SYSRESET
for do_reset() in SPL for Rockchip SoCs.

References: 87c16d4 "drivers: spl: consistently use the $(SPL_TPL_) macro"
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-08 11:45:19 +02:00
Kever Yang
e1f6881367 rockchip: rk3328: fix syscon id table
syscon id table need a dummy member as NULL ending, or else system
will panic while try to match a compatible in this table as a list.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-08 11:44:51 +02:00
Tom Rini
08d0c53d6b Merge git://git.denx.de/u-boot-rockchip 2017-09-05 07:11:46 -04:00
Wadim Egorov
40d4f79b81 rockchip: rk3288: Add reset reason detection
Sometimes it's helpful to know the reset reason caused in the SoC.
Add reset reason detection for the RK3288 SoC.
This will set an environment variable which represents the reset reason.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-05 11:04:35 +02:00
Tom Rini
a0e80c97c9 Merge branch 'rmobile' of git://git.denx.de/u-boot-sh 2017-09-04 22:17:59 -04:00
Marek Vasut
0d0915bef7 ARM: rmobile: Add missing IPSR18 bits to R8A7795 PFC
The IPSR18 register bits were missing from the R8A7795 ES2.0+ PFC
tables, which triggered a BUG() in sh_pfc driver. This is because
of an out-of-bounds access to the pinmux_gpios[] array in the PFC
tables, which was too short due to the missing IPSR18 bits.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-05 07:51:39 +09:00
Adam Ford
edd1653f04 Convert CONFIG_SPL_OMAP3_ID_NAND to Kconfig
This converts the following to Kconfig:
   CONFIG_SPL_OMAP3_ID_NAND

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-01 20:45:26 -04:00
Adam Ford
fc760cc6e8 Convert CONFIG_SYS_I2C_BUS_MAX to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_I2C_BUS_MAX

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
[trini: Fix AM43XX drop AM44XX]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-01 20:44:30 -04:00
Adam Ford
ac1d8ac871 Configs: Migrate I2C_BUS_MAX to CONFIG_SYS_I2C_BUS_MAX
For consistency with other platforms and in preparation of Kconfig
migration, let's change Several TI platforms that use I2C_BUS_MAX
to CONFIG_SYS_I2C_BUS_MAX

Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-01 17:56:20 -04:00
Tom Rini
48f6232e58 Kconfig: Migrate all of cmd/fastboot/Kconfig to defconfigs
- Move ANDROID_IMAGE_SUPPORT to top level Kconfig under images as it's
  not strictly part of fastboot.
- Add some defaults for the fastboot buffer location and size
- Migrate all options listed in cmd/fastboot/Kconfig
- Cleanup the README

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-01 16:18:21 -04:00
Tom Rini
0b6e5b2c48 Merge git://git.denx.de/u-boot-sunxi 2017-09-01 13:30:19 -04:00
Dave Prue
6ff005cf19 sunxi: Fix CONFIG_SUNXI_GMAC references
SUNXI_GMAC was still used to configure the code where as the
same has been renamed and moved to Kconfig in below commit
"sunxi: Move SUNXI_GMAC to Kconfig"
(sha1: 4d43d065db)

Signed-off-by: Dave Prue <dave@prue.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
[Tweek commit message, config_whitelist.txt, build-whitelist.sh]
Signed-off-by: Jagan Teki <jagan@openedev.com>
2017-09-01 20:48:27 +05:30
Tom Rini
6aee2ab68c Merge git://git.denx.de/u-boot-imx
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	configs/imx6qdl_icore_mmc_defconfig
	configs/imx6qdl_icore_rqs_defconfig
2017-09-01 10:40:59 -04:00
Tom Rini
4109d70293 Merge git://git.denx.de/u-boot-marvell 2017-09-01 10:33:21 -04:00
Tom Rini
e4adc8ed3c Merge git://git.denx.de/u-boot-uniphier
- add {ofnode,dev}_read_resource_byname
- provide DT probe hook to Denali NAND driver
- update clk/reset driver
- update DT
- misc cleanups
2017-09-01 10:32:35 -04:00
Jagan Teki
46668df5d0 i.MX6Q: spl: Fix falcon to use dram_init_banksize
Memory dt node update introduced by spl_fixup_fdt() in below
commit was making DDR configuration in-appropriate
to boot falcon mode. Hence added dram_init_banksize for
explicit assignment of  proper base and size of DDR.

"boot: fdt: Perform arch_fixup_fdt() on the given device tree for falcon boot"
(sha1: 6e7585bb64)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-30 12:18:26 +02:00
Stefan Agner
624da53ca8 imx: remove SATA boot mode for i.MX 6UL and 6ULL
The NXP i.MX 6UL and 6ULL do not support SATA and have no SATA
boot mode, hence remove it from the boot device detecion. This
fixes a build error introduced with 3bd1642d4d ("imx: fix USB
boot mode detection for i.MX 6UL and 6ULL")

Fixes: 3bd1642d4d ("imx: fix USB boot mode detection for i.MX 6UL and 6ULL")
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-30 12:17:53 +02:00
Chris Packham
dbc3e64fd1 ARM: mvebu: add "spi-flash" compatible string
U-boots spi-nor support is currently considered a work in progress. For
now to avoid issues it is necessary to add a "spi-flash" compatible
string. Eventually the "jedec,spi-nor" will be sufficient when the core
U-boot code is updated to support it.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-30 10:03:35 +02:00
Masahiro Yamada
d8a10e7fac ARM: uniphier: set system bus pinmux for PXs3
The system bus is not enabled by default for NAND, eMMC boot
etc. of PXs3.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
b173c19663 ARM: uniphier: move CONFIG_NAND to defconfig
This imply was added when the option was moved by the moveconfig tool,
but the intention is not clear.  Move it to defconfig.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
31c86aa7fd ARM: dts: uniphier: update PXs3 SoC/board DT
Support PXs3 SoC and its reference development board.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
6c9e46efae ARM: dts: uniphier: sync with Linux
Import updates queued up for Linux 4.14-rc1.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Dai Okamura
4013bbb1f3 ARM: uniphier: fix DSPLL init code for LD20 SoC
Signed-off-by: Dai Okamura <okamura.dai@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:07:04 +09:00
Masahiro Yamada
e0daca7de5 ARM: uniphier: remove ad-hoc pin settings for NAND
This is now set up by the pinctrl driver when the NAND driver is
probed.  Remove the legacy code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:06:57 +09:00
Masahiro Yamada
4914a68de7 ARM: uniphier: add PLL settings for PXs3
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:03:11 +09:00
Masahiro Yamada
a55957b9ad ARM: uniphier: move PLLCTRL register macros to each SoC .c file
The new SoC PXs3 changed the address of PLL, but still uses the
same PLL name.  We can not define SC_*PLLCTRL in the common header.
Move them to per-SoC .c file.  Also, fix some PLL comments.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:03:11 +09:00
Masahiro Yamada
546197b986 ARM: uniphier: replace <common.h> with <linux/delay.h> in pll settings
The #include <common.h> was added for mdelay().  Later, the declaration
of mdelay was moved to <linux/delay.h> by commit 5bc516ed66 ("delay:
collect {m, n, u}delay declarations to include/linux/delay.h").

There is no need to include <common.h> now.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:03:11 +09:00
Anatolij Gustschin
ffc36f57bc imx6: don't include unneeded boot_mode array in SPL
The soc_boot_modes array is only used by bmode command
and not needed in SPL. Don't include it into SPL.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-29 09:49:51 +02:00
Anatolij Gustschin
ae64226dbe imx: timer: don't clear the GPT control register multiple times
There is no need to clear the control register 100 times in a
loop, a single zero write clears the register. I didn't find any
justification why clearing this register in a loop is needed
(no info in i.MX6 errata or GPT timer linux driver, linux driver
uses single write to clear this control register).

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2017-08-29 09:47:28 +02:00
Maxime Ripard
343ff16106 sunxi: Enable MMC new mode for A83T
The eMMC controller for the A83T uses the new operating mode. Enable it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-28 22:36:48 +05:30
Maxime Ripard
de9b1771c3 mmc: sunxi: Support new mode
Almost all of the newer Allwinner SoCs have a new operating mode for the
eMMC clocks that needs to be enabled in both the clock and the MMC
controller.

Details about that mode are sparse, and the name itself (new mode vs old
mode) doesn't give much details, but it seems that the it changes the
sampling of the MMC clock. One side effect is also that it divides the
parent clock rate by 2.

Add support for it through a Kconfig option.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-28 22:36:44 +05:30
Breno Lima
3aa4b703b4 imx: imx6: Move gpr_init() function to soc.c
Since the gpr_init() function is common for boards using MX6S, MX6DL, MX6D,
MX6Q and MX6QP processors move it to the soc.c file.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-08-28 09:48:53 +02:00
Tom Rini
f72b96ec8f Merge branch 'rmobile' of git://git.denx.de/u-boot-sh 2017-08-26 15:10:46 -04:00
Vikas Manocha
1e87f9ced4 spl: stm32: make falcon mode activation configurable
With this change, it will be possible to de-select falcon mode & spl
will only boot U-Boot.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Suggested-by: Bo Shen <voice.shen@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-26 14:56:13 -04:00
Ruchika Gupta
a797f274d7 ARMv8/sec_firmware : Update chosen/kaslr-seed with random number
kASLR support in kernel requires a random number to be passed via
chosen/kaslr-seed propert. sec_firmware generates this random seed
which can then be passed in the device tree node.

sec_firmware reserves JR3 for it's own usage. Node for JR3 is
removed from device-tree.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
2017-08-26 14:56:11 -04:00
Thomas Petazzoni
225bfd3906 arch/arm/cpu/arm926ejs/spear/cpu.c: guard do_switch_ecc() with CONFIG_NAND_FSMC
do_switch_ecc() calls fsmc_nand_switch_ecc(), which is a direct
function call into drivers/mtd/nand/fsmc_nand.c. However, this
function is not guarded by CONFIG_NAND_FSMC, which results to a build
failure if CONFIG_NAND_FSMC is disabled.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2017-08-26 14:56:10 -04:00
Thomas Petazzoni
c25c4fd010 board/spear/common: move code to arch/arm/cpu/arm926ejs/spear/
The code in board/spear/common/ is not board-specific but
SoC-specific. Therefore, boards from other vendors than "spear" may
want to re-use this code, which is currently difficult with the code
being placed in board/spear/common/.

Since this code really is SoC-specific, this commit moves it to
arch/arm/cpu/arm926ejs/spear/, with the rest of the SPEAr related
code.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2017-08-26 14:56:10 -04:00
Wenyou.Yang@microchip.com
fc6adebbc1 board: atmel: Use the new PIT timer driver
Use the Atmel PIT timer driver which supports the driver model
and device tree.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-08-26 14:56:09 -04:00
Wenyou.Yang@microchip.com
47edaea494 driver: timer: Add the Atmel PIT timer driver
Add the new Atmel PIT timer driver, which supports the driver model
and device tree.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-08-26 14:56:08 -04:00
Suniel Mahesh
528f2b66dc arm: dts: am33xx: sync DTS with Linux 4.13-rc4
This re-syncs AM33xx DTS file with current file from
Linux v4.13-rc4 to ensure a consistent configuration. Upstream
Linux removed the redundant Interrupt-parent property from mmc,
mac, lcdc and tscadc sub nodes.

Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-26 14:56:07 -04:00
Marek Vasut
46933dfbe1 ARM: rmobile: Add u-boot, dm-pre-reloc to clock nodes on Gen3
We need the clock available very early, add the u-boot,dm-pre-reloc
DT property on those nodes, so they come up very in the process.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-26 07:04:49 +09:00
Stefan Agner
962c78b1df imx: use BOOT_DEVICE_BOARD instead of UART
i.MX 6 serial downloader is not necessarily booting via UART but can
also boot from USB. In fact only some i.MX chips have serial
downloader support via UART (e.g. 6UL/ULL and Vybrid) but all of
them have serial downloader support via USB. Use the more appropriate
BOOT_DEVICE_BOARD define which is used for ROM provided recovery
mechanisms in general.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2017-08-25 13:31:47 +02:00
Stefan Agner
3bd1642d4d imx: fix USB boot mode detection for i.MX 6UL and 6ULL
Add the reserved boot mode used in the bmode command for i.MX 6UL
and 6ULL as introduced in commit 3fd9579085 ("imx: mx6ull: fix USB
bmode for i.MX 6UL and 6ULL").

Also replace BMODE_UART with BMODE_RESERVED, which is more appropriate.
Commit 96aac843b6 ("imx: Use IMX6_BMODE_* macros instead of numericals")
added macros for boot modes, in the process the reserved boot mode got
named BMODE_UART. We use the reserved boot mode in the bmode command to
let the boot ROM enter serial downloader recovery mode. But this is only
a side effect, the actual boot mode is reserved...

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2017-08-25 13:31:31 +02:00
Stefano Babic
7c09cbf68b imx: fix licensing in i.MX files
Some files for i.MX do not yet have the SPDX ID to reference the correct
license.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Wolfgang Denk <wd@denx.de>
2017-08-23 10:45:45 +02:00
Peng Fan
fa85b0217d imx: mx7: psci: add copyright and license
Add copyright and license header.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2017-08-23 10:45:25 +02:00
Masahiro Yamada
3444d1d40e ARM: dts: uniphier: add dr_mode property to dwc3 node
Since commit 576e3cc700 ("usb: host: xhci-dwc3: Add dual role mode
support from DT"), warning is displayed if dr_mode is not specified.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20 23:07:02 +09:00
Masahiro Yamada
c5161eee38 Revert "ARM: uniphier: fix ROM boot mode for PH1-sLD3"
This reverts commit 82d075e79f.

Commit 82d075e79f ("ARM: uniphier: fix ROM boot mode for PH1-sLD3")
was a workaround for sLD3.  Now the sLD3 SoC support has been removed.

Revert it to allow to simplify the init code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20 23:05:39 +09:00
Masahiro Yamada
0aa8b2c3e0 Revert "ARM: uniphier: move lowlevel debug init code after page table switch"
This reverts commit bcc51c1512.

Commit bcc51c1512 ("ARM: uniphier: move lowlevel debug init code
after page table switch") was intended to support lowlevel debug for
sLD3.  Now the sLD3 SoC support has been removed.

Revert it to allow to enable lowlevel debug earlier.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20 23:05:39 +09:00
Masahiro Yamada
00aa453ebf ARM: uniphier: remove sLD3 SoC support
This SoC is too old.  It is difficult to maintain any longer.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20 23:05:39 +09:00
Masahiro Yamada
213fcabdfd clk: uniphier: fix unmet direct dependencies warning
Since commit f0776a5517 ("spl: dm: Kconfig: SPL_CLK depends on
SPL_DM"), the following warning is displayed:

  $ make uniphier_v8_defconfig
  warning: (ARCH_ZYNQ && ARCH_ZYNQMP && STM32F7 && CLK_UNIPHIER) selects
  SPL_CLK which has unmet direct dependencies (CLK && SPL_DM)

While I am here, I am removing the prompt to make it user-unconfigurable
option so that "select CLK_UNIPHIER" can be omitted.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20 23:05:39 +09:00
Tom Rini
1fdafb2e3d Merge branch 'master' of git://git.denx.de/u-boot-mmc 2017-08-18 18:24:36 -04:00
Kever Yang
a80b3b0378 rockchip: rk322x: update MACRO for mmc clksel reg
The description for eMMC/SDIO/SDMMC src is not correct,
update the CRU_CLKSEL11_CON value definition according to TRM.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-18 17:52:47 +02:00
Kever Yang
44c5ba557b rockchip: rk322x: update dram bank size
The DRAM start address is not 0, so need to update the last bank size
as:
DRAM start addr + DRAM_SIZE - last bank start addr

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-18 16:55:25 +02:00
Philipp Tomsich
a299a4879e rockchip: rk3399: spl: remove unused header inclusion
fdtdec.h is included, but not used in rk3399-board-spl.c: remove the
'#include'-statement.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-18 16:55:15 +02:00
Kever Yang
caa6b3b530 rockchip: dts: rk3399-evb: remove redundant gmac node
There are two same gmac node, remove one.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-18 16:54:39 +02:00
Kever Yang
1ade3a9013 rockchip: dts: rk3399-firefly: update gmac parameter
Update the tx_delay and rx_delay to match the timing for
rk3399-firefly board to improve the stability of gmac data
transfer.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-17 10:11:18 +02:00
Simon Glass
e7881d85a9 dm: mmc: Drop CONFIG_DM_MMC_OPS
All boards which use DM_MMC have now been converted to use DM_MMC_OPS.
Drop the option and good riddance.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:59:55 +09:00
Simon Glass
5ec1f560f3 dm: imx: cm_fx6: Add device tree for cm_fx6
Add this file so we can use device-tree control for cm_fx6. It comes from
linux 4.12.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
7e0712b26e dm: sata: imx: Allow driver model to be used for sata
Update the sata call to work with driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Marek Vasut
a3f0a7d5b5 mmc: sh_sdhi: Fix the ACMD handling
The command handling in this driver is awful, esp. because the driver
depends on command numbers to determine whether this is APPCMD or not.
Also, handling of command RSP response types is totally wrong.

This patch at least plucks out some of the custom command encoding and
fixes the APPCMD handling. The RSP handling still needs work, yet that
might not be needed as it turns out the uniphier-sd.c driver is in much
better shape and supports the same IP, so we might be able to just drop
this driver in favor of the uniphier one.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-17 14:38:02 +09:00
Tom Rini
336aee50cf Merge git://git.denx.de/u-boot-tegra 2017-08-16 18:12:58 -04:00
Tom Rini
ceff355a5f Merge git://git.denx.de/u-boot-sunxi
Update A20-OLinuXino-Lime2-eMMC_defconfig to include CONFIG_SCSI

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-16 18:12:40 -04:00
Tom Rini
470135be27 Merge git://www.denx.de/git/u-boot-imx
Update pfla02 for setenv changes and PHYLIB/etc migration to Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-16 18:12:00 -04:00
Simon Glass
35affd7a2f env: Rename eth_getenv_enetaddr() to eth_env_get_enetaddr()
Rename this function for consistency with env_get().

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:30:44 -04:00
Simon Glass
00caae6d47 env: Rename getenv/_f() to env_get()
We are now using an env_ prefix for environment functions. Rename these
two functions for consistency. Also add function comments in common.h.

Quite a few places use getenv() in a condition context, provoking a
warning from checkpatch. These are fixed up in this patch also.

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:30:24 -04:00
Simon Glass
fd1e959e91 env: Rename eth_setenv_enetaddr() to eth_env_set_enetaddr()
Rename this function for consistency with env_set().

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:23:56 -04:00
Simon Glass
018f530323 env: Rename common functions related to setenv()
We are now using an env_ prefix for environment functions. Rename these
commonly used functions, for consistency. Also add function comments in
common.h.

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:23:32 -04:00
Simon Glass
382bee57f1 env: Rename setenv() to env_set()
We are now using an env_ prefix for environment functions. Rename setenv()
for consistency. Also add function comments in common.h.

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:22:18 -04:00
Peng Fan
e872f27a02 imx: mx7: fix build warning when CONFIG_IMX_RDC not enabled
Fix build warning when CONFIG_IMX_RDC not defined in defconfig.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2017-08-16 12:43:09 +02:00
Peng Fan
9402cafb23 imx: mx6sl: simplify code using setbits_le32
Simplify code by removing set_preclk_from_osc with directly setbits_le32.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2017-08-16 12:43:09 +02:00
Peng Fan
7236297aee imx: mx6sx: select OSC as uart's clk parent
As M4 is sourcing UART clk from OSC, to make UART work
when M4 is enabled, need to select OSC as clk parent,
24M OSC is enough for debug UART in uboot.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2017-08-16 12:43:04 +02:00
Peng Fan
79a57b5ae1 imx: mx6: soc: fix mx6sll settings
There is not LDO_SOC/PU/ARM/MMDC1 on i.MX6SLL, also no need to gate/ungate
all PFDs to make PFD working.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2017-08-16 11:56:22 +02:00
Peng Fan
3d3598d0f6 imx: mx6: select ARM_ERRATA_845369
Select ARM_ERRATA_845369 for i.MX6DQ/DL/QP.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-16 11:51:00 +02:00
Peng Fan
11d94319c3 arm: Implement workaround for Cortex-A9 errata 845369
Under very rare timing circumstances, transitioning into streaming
mode might create a data corruption. Present on Two or more processors
or 1 core with ACP, all revisions. This erratum can be worked round
by setting bit[22] of the undocumented Diagnostic Control Register to 1.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-16 11:50:51 +02:00
Peng Fan
91435cd40d ARM: i.MX6: exclude the ARM errata from i.MX6 UP system
The ARM errata 751472, 794072, 761320 only applied
to the following configuration:

This erratum affects configurations with either:
- One processor if the ACP is present
- Two or more processors

i.MX6 family does not have the ACP and thus only the MPCore system
will be impacted, which are the i.MX6DQ, i.MX6DL, and i.MX6QP.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2017-08-16 11:50:40 +02:00
Sébastien Szymanski
0c7c6fb764 imx: imx6ull: correct get_cpu_speed_grade_hz
i.MX6ULL has different speed grades than i.MX6UL.

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2017-08-16 11:45:10 +02:00
Sébastien Szymanski
44e670532d imx: imx6ul: correct get_cpu_speed_grade_hz on 696MHz SoCs
Return the correct value when the speed grade is 696MHz.

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2017-08-16 11:44:57 +02:00
Anatolij Gustschin
ff3a5fc46d imx6: clock: correct comment for PLL_VIDEO
This appear to be a copy-paste error, clean it up.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-16 11:38:27 +02:00
Anatolij Gustschin
557b9b7250 imx6: use SION macro in SDn_CMD mux mode bitfield arguments
Select SION by appropriate macro instead of constant.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-08-16 11:36:05 +02:00
Simon Glass
01510091de env: Drop saveenv() in favour of env_save()
Use the env_save() function directly now that there is only one
implementation of saveenv().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Denk <wd@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:30 -04:00
Simon Glass
c1c3fe2307 env: Convert CONFIG_ENV_IS_IN... to a choice
At present we support multiple environment drivers but there is not way to
select between them at run time. Also settings related to the position and
size of the environment area are global (i.e. apply to all locations).

Until these limitations are removed we cannot really support more than one
environment location. Adjust the location to be a choice so that only one
can be selected. By default the environment is 'nowhere', meaning that the
environment exists only in memory and cannot be saved.

Also expand the help for the 'nowhere' option and move it to the top since
it is the default.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Move all of the imply logic to default X if Y so it works again]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-15 20:50:01 -04:00
Marcel Ziswiler
33848eb53e apalis_t30/tk1, colibri_t20/t30: fix i2c bus frequencies
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2017-08-15 14:51:18 -07:00
Marcel Ziswiler
8b733af831 apalis-tk1: remove duplicate hdmi_ddc device tree node
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2017-08-15 14:51:18 -07:00
Jagan Teki
585bf8ae6f sun50i: a64: Add A64-OLinuXino initial support
OLimex A64-OLinuXino is an open-source hardware board
using the Allwinner A64 SOC.

OLimex A64-OLinuXino has
- A64 Quad-core Cortex-A53 64bit
- 1GB or 2GB RAM DDR3L @ 672Mhz
- microSD slot and 4/8/16GB eMMC
- Debug TTL UART
- HDMI
- LCD
- IR receiver
- 5V DC power supply

Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-15 11:30:59 +05:30
Jagan Teki
f322657204 sun50i: a64: Add initial NanoPi A64 support
NanoPi A64 is a new board of high performance with low cost
designed by FriendlyElec., using the Allwinner A64 SOC.

Nanopi A64 features
- Allwinner A64, 64-bit Quad-core Cortex-A53@648MHz to 1.152GHz, DVFS
- 1GB DDR3 RAM
- MicroSD
- Gigabit Ethernet (RTL8211E)
- Wi-Fi 802.11b/g/n
- IR receiver
- Audio In/Out
- Video In/Out
- Serial Debug Port
- microUSB 5V 2A DC power-supply

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-08-15 11:30:19 +05:30
Tom Rini
c1b62ba9ca Merge branch 'master' of git://git.denx.de/u-boot-rockchip 2017-08-14 10:40:01 -04:00
Patrice Chotard
bc5d038445 stm32f1: remove stm32f1 support
A few years ago STM32F1 SoCs support has been added :
0144caf22c  gpio: stm32: add stm32f1 support
2d18ef2364  ARMv7M: add STM32F1 support

But neither STM32F1 dedicated defconfig nor board was
associated to these commits.

Got confirmation from Tom Rini and Matt Porter to remove
all this code [1]

[1] http://u-boot.10912.n7.nabble.com/Remove-STM32F1-support-td301603.html

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 15:17:37 -04:00
Nishanth Menon
0459bc30b6 ARM: OMAP5: Enable support for AVS0 for OMAP5 production devices
OMAP5432 did go into production with AVS class0 registers which were
mutually exclusive from AVS Class 1.5 registers.

Most OMAP5-uEVM boards use the pre-production Class1.5 which has
production efuse registers set to 0. However on production devices,
these are set to valid data.

scale_vcore logic is already smart enough to detect this and use the
"Nominal voltage" on devices that do not have efuse registers populated.

On a test production device populated as follows:
MPU OPP_NOM:
=> md.l 0x04A0021C4 1
4a0021c4: 03a003e9                               ....
(0x3e9 = 1.01v) vs nom voltage of 1.06v
MPU OPP_HIGH:
=> md.l 0x04A0021C8 1
4a0021c8: 03400485                               ..@.

MM OPP_NOM:
=> md.l 0x04A0021A4 1
4a0021a4: 038003d4                               ....
(0x3d4 = 980mV) vs nom voltage of 1.025v
MM OPP_OD:
=> md.l 0x04A0021A8 1
4a0021a8: 03600403                               ..`.

CORE OPP_NOM:
=> md.l 0x04A0021D8 1
4a0021d8: 000003cf                               ....
(0x3cf = 975mV) vs nom voltage of 1.040v

Since the efuse values are'nt currently used, we do not regress on
existing pre-production samples (they continue to use nominal voltage).

But on boards that do have production samples populated, we can leverage
the optimal voltages necessary for proper operation.

Tested on:
a) 720-2644-001 OMAP5UEVM with production sample.
b) 750-2628-222(A) UEVM5432G-02 with pre-production sample.

Data based on OMAP5432 Technical reference Manual SWPU282AF (May
2012-Revised Aug 2016)

NOTE: All collaterals on OMAP5432 silicon itself seems to have been
removed from ti.com, though EVM details are still available:
http://www.ti.com/tool/OMAP5432-EVM

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-08-13 15:17:35 -04:00
Nishanth Menon
5796b66651 ARM: OMAP5: Remove OPP_LOW Definitions for ES2.0
ES2.0 descopes OPP_LOW definition. So remove it from macros defined.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-08-13 15:17:35 -04:00
xypron.glpk@gmx.de
d1fe19766b stm32: remove redundant 'else if'
The if in the else branch is superfluous.
We can use a simple if.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-08-13 15:17:28 -04:00
xypron.glpk@gmx.de
a22bbfda6e arm: mvebu: avoid possible NULL dereference
It does not make sense to check if info is NULL after
dereferencing it.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-13 15:17:28 -04:00
xypron.glpk@gmx.de
a5981734a4 armv7m: mpu_config add missing break
For DEVICE_NON_SHARED the newly assigned value of attr
is overwritten due to a missing break.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-08-13 15:17:28 -04:00
xypron.glpk@gmx.de
6def7de37b bcm281xx: clock: avoid possible NULL dereference
It does not make sense first to dereference c and then
to check if it is NULL.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-08-13 15:17:27 -04:00
xypron.glpk@gmx.de
65e8ce29e4 arm: bcm235xx: clk_set_rate avoid possible NULL deref
It does not make sense first to dereference c and then
to check if it is NULL.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-08-13 15:17:27 -04:00
xypron.glpk@gmx.de
b69a0849e7 arm: bcm235xx: avoid possible NULL dereference
It does not make sense to first dereference c and then
check if it is NULL.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-08-13 15:17:26 -04:00
xypron.glpk@gmx.de
9730bcdc2f arm: spear: do not return random value from stack
If the NOR device is not available do not return
a random value from the stack.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-08-13 15:17:26 -04:00
Kever Yang
95ca100ba7 rockchip: rk322x: update max-frequency for mmc node
mmc using 150000000 as max-frequency like what rk3288 sets.
This can speed up the mmc read/write, the actual mmc clock is:
Before this patch: 37.125M
After this patch: 49.5M

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-13 17:15:09 +02:00
Kever Yang
a2a1bfe175 rockchip: dts: rk322x: add sdmmc device node
add node for sdmmc in dts and rk3229-evb.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-13 17:15:08 +02:00
Kever Yang
18d38d3a94 rockchip: rk322x: set the DDR region as non-secure in SPL
Disable the ddr secure region setting in SPL and the ddr memory
becomes non-secure, every one can access it. the trust firmware
like OPTEE should have the correct setting for it after SPL if
there is one.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-13 17:15:08 +02:00
Kever Yang
bf82e200a9 rockchip: rk3288: fix EMMC_DIV_MASK definition in header
It should be '<<' instead of '<' for _MASK definition, fix it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:15:08 +02:00
Philipp Tomsich
e8f9ad94bf rockchip: rk3368: spl: move SPL_LDSCRIPT to Kconfig
With the new way of doing things (i.e. the hierarchical selection of
SPL_LDSCRIPT via Kconfig) in place, this moves the SPL_LDSCRIPT setting
for the RK3368 from defconfig back into Kconfig.

With this done, there should be no lingering cases of SPL_LDSCRIPT
outside of Kconfig files.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:15:08 +02:00
Philipp Tomsich
b529993e02 spl: add hierarchical defaults for SPL_LDSCRIPT
With SPL_LDSCRIPT moved to Kconfig (and this being a 'string' config
node), all the lingering definitions in header files will cause
warnings/errors due to the redefinition of the configuration item.

As we don't want to pollute the defconfig files (and values should
usually be identical for entire architectures), the defaults are moved
into Kconfig.  Kconfig will always pick the first default that
matches, so please keep these values at the end of each file (to allow
any board-specific Kconfig, which will be included earlier) to
override with an unconditional default setting.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:37 +02:00
Philipp Tomsich
96b9082c64 rockchip: rk3188: rock: adjust for SPL/TPL split
With the changes to split SPL/TPL for the RK3368, I apparently missed
some needed adjustments to the RK3188 Kconfig and rock_defconfig.

This fixes build-issues for the rock board after applying the RK3368
enablement (and SPL/TPL) set that resulted from TPL_SERIAL_SUPPORT,
TPL_ROCKCHIP_BACK_TO_BROM and TPL_TINY_MEMSET being separate symbols
now.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:37 +02:00