Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-24 21:54:01 +00:00
Code Issues Projects Releases Packages Wiki Activity

armv7: rk3288: Move configure_l2ctlr to common

Browse source 
configure_l2ctlr will be shared between SPL and TPL so
move them into asm/arch/sys_proto.h

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
Jagan Teki 2017-09-27 23:03:11 +05:30 committed by Philipp Tomsich
parent d9a7dcf5b8
commit a982d5156d
2 changed files with 24 additions and 20 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

23
arch/arm/include/asm/arch-rockchip/sys_proto.h
View file

@ -7,4 +7,27 @@
#ifndef _ASM_ARCH_SYS_PROTO_H
#define _ASM_ARCH_SYS_PROTO_H
#ifdef CONFIG_ROCKCHIP_RK3288
#include <asm/armv7.h>
static void configure_l2ctlr(void)
{
uint32_t l2ctlr;
l2ctlr = read_l2ctlr();
l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
/*
* Data RAM write latency: 2 cycles
* Data RAM read latency: 2 cycles
* Data RAM setup latency: 1 cycle
* Tag RAM write latency: 1 cycle
* Tag RAM read latency: 1 cycle
* Tag RAM setup latency: 1 cycle
*/
l2ctlr |= (1 << 3 | 1 << 0);
write_l2ctlr(l2ctlr);
}
#endif /* CONFIG_ROCKCHIP_RK3288 */
#endif /* _ASM_ARCH_SYS_PROTO_H */

21
arch/arm/mach-rockchip/rk3288-board-spl.c
View file

@ -13,7 +13,6 @@
#include <malloc.h>
#include <ram.h>
#include <spl.h>
#include <asm/armv7.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/bootrom.h>
@ -21,6 +20,7 @@
#include <asm/arch/hardware.h>
#include <asm/arch/periph.h>
#include <asm/arch/sdram.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>
#include <dm/pinctrl.h>
#include <dm/root.h>
@ -81,25 +81,6 @@ u32 spl_boot_mode(const u32 boot_device)
return MMCSD_MODE_RAW;
}
static void configure_l2ctlr(void)
{
uint32_t l2ctlr;
l2ctlr = read_l2ctlr();
l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
/*
* Data RAM write latency: 2 cycles
* Data RAM read latency: 2 cycles
* Data RAM setup latency: 1 cycle
* Tag RAM write latency: 1 cycle
* Tag RAM read latency: 1 cycle
* Tag RAM setup latency: 1 cycle
*/
l2ctlr |= (1 << 3 | 1 << 0);
write_l2ctlr(l2ctlr);
}
#ifdef CONFIG_SPL_MMC_SUPPORT
static int configure_emmc(struct udevice *pinctrl)
{