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https://github.com/AsahiLinux/u-boot
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ARM: DTS: stm32: adapt stm32h7 dts files for U-boot
This patch adapts stm32h743 disco and eval dts files to match with U-boot requirements or add features wich are not yet upstreamed on kernel side : _ Add RCC clock driver node and update all clocks phandle accordingly. By default, on kernel side, all clocks was temporarly configured as a phandle to timer_clk waiting for a RCC clock driver to be available. On U-boot side, we now have a dedicated RCC clock driver, we can configured all clocks as phandle to this driver. All this binding update will be available soon in a kernel tag, as all the bindings have been acked by Rob Herring [1]. [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html _ Align STM32H7 serial compatible string with the one which will be available in next kernel tag. The bindings has been acked by Rob Herring [2]. This compatible string will be usefull to add stm32h7 specific feature for this serial driver. [2] https://lkml.org/lkml/2017/7/17/739 _ Add gpio compatible and aliases for stm32h743 _ Add FMC sdram node with associated new bindings value to manage second bank (ie bank 1). _ Add missing HSI and CSI oscillators nodes needed by STM32H7 RCC clock driver. Clock sources could be: _ HSE (High Speed External) _ HSI (High Speed Internal) _ CSI (Low Power Internal) These clocks can be used as clocksource in some configuration. By default, HSE is selected as clock source. _ Set HSE to 25Mhz for stm32h743i-disco and eval board By default, the external oscillator frequency is defined at 25 Mhz in SoC stm32h743.dtsi file. It has been set at 125 Mhz in kernel DT temporarly waiting for RCC clock driver becomes available. As in U-boot we got a RCC clock driver, the real value of HSE clock can be used. _ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl, pwrcfg and gpio nodes. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Patrice Chotard
Tom Rini
parent
5fbb2b25ae
commit
a1e384b4d9
6 changed files with 294 additions and 28 deletions
88
arch/arm/dts/stm32h7-u-boot.dtsi
Normal file
88
arch/arm/dts/stm32h7-u-boot.dtsi
Normal file
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@ -0,0 +1,88 @@
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/{
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clocks {
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u-boot,dm-pre-reloc;
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};
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soc {
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u-boot,dm-pre-reloc;
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pin-controller {
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u-boot,dm-pre-reloc;
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};
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};
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};
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&clk_hse {
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u-boot,dm-pre-reloc;
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};
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&clk_lse {
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u-boot,dm-pre-reloc;
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};
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&clk_i2s {
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u-boot,dm-pre-reloc;
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};
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&pwrcfg {
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u-boot,dm-pre-reloc;
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};
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&rcc {
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u-boot,dm-pre-reloc;
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};
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&fmc {
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u-boot,dm-pre-reloc;
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};
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&clk_hsi {
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u-boot,dm-pre-reloc;
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};
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&clk_csi {
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u-boot,dm-pre-reloc;
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};
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&gpioa {
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u-boot,dm-pre-reloc;
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};
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&gpiob {
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u-boot,dm-pre-reloc;
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};
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&gpioc {
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u-boot,dm-pre-reloc;
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};
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&gpiod {
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u-boot,dm-pre-reloc;
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};
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&gpioe {
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u-boot,dm-pre-reloc;
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};
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&gpiof {
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u-boot,dm-pre-reloc;
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};
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&gpiog {
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u-boot,dm-pre-reloc;
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};
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&gpioh {
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u-boot,dm-pre-reloc;
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};
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&gpioi {
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u-boot,dm-pre-reloc;
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};
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&gpioj {
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u-boot,dm-pre-reloc;
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};
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&gpiok {
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u-boot,dm-pre-reloc;
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};
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@ -54,88 +54,99 @@
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gpioa: gpio@58020000 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x0 0x400>;
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clocks = <&timer_clk>;
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clocks = <&rcc GPIOA_CK>;
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st,bank-name = "GPIOA";
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};
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gpiob: gpio@58020400 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x400 0x400>;
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clocks = <&timer_clk>;
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clocks = <&rcc GPIOB_CK>;
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st,bank-name = "GPIOB";
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};
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gpioc: gpio@58020800 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x800 0x400>;
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clocks = <&timer_clk>;
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clocks = <&rcc GPIOC_CK>;
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st,bank-name = "GPIOC";
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};
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gpiod: gpio@58020c00 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0xc00 0x400>;
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clocks = <&timer_clk>;
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clocks = <&rcc GPIOD_CK>;
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st,bank-name = "GPIOD";
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};
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gpioe: gpio@58021000 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x1000 0x400>;
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clocks = <&timer_clk>;
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clocks = <&rcc GPIOE_CK>;
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st,bank-name = "GPIOE";
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};
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gpiof: gpio@58021400 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x1400 0x400>;
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clocks = <&timer_clk>;
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clocks = <&rcc GPIOF_CK>;
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st,bank-name = "GPIOF";
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};
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gpiog: gpio@58021800 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x1800 0x400>;
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clocks = <&timer_clk>;
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clocks = <&rcc GPIOG_CK>;
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st,bank-name = "GPIOG";
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};
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gpioh: gpio@58021c00 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x1c00 0x400>;
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clocks = <&timer_clk>;
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clocks = <&rcc GPIOH_CK>;
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st,bank-name = "GPIOH";
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};
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gpioi: gpio@58022000 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x2000 0x400>;
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clocks = <&timer_clk>;
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clocks = <&rcc GPIOI_CK>;
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st,bank-name = "GPIOI";
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};
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gpioj: gpio@58022400 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x2400 0x400>;
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clocks = <&timer_clk>;
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clocks = <&rcc GPIOJ_CK>;
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st,bank-name = "GPIOJ";
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};
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gpiok: gpio@58022800 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x2800 0x400>;
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clocks = <&timer_clk>;
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clocks = <&rcc GPIOK_CK>;
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st,bank-name = "GPIOK";
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};
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@ -164,6 +175,75 @@
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bias-disable;
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};
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};
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fmc_pins: fmc@0 {
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pins {
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pinmux = <STM32H7_PD0_FUNC_FMC_D2_FMC_DA2>,
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<STM32H7_PD1_FUNC_FMC_D3_FMC_DA3>,
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<STM32H7_PD8_FUNC_FMC_D13_FMC_DA13>,
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<STM32H7_PD9_FUNC_FMC_D14_FMC_DA14>,
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<STM32H7_PD10_FUNC_FMC_D15_FMC_DA15>,
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<STM32H7_PD14_FUNC_FMC_D0_FMC_DA0>,
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<STM32H7_PD15_FUNC_FMC_D1_FMC_DA1>,
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<STM32H7_PE0_FUNC_FMC_NBL0>,
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<STM32H7_PE1_FUNC_FMC_NBL1>,
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<STM32H7_PE7_FUNC_FMC_D4_FMC_DA4>,
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<STM32H7_PE8_FUNC_FMC_D5_FMC_DA5>,
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<STM32H7_PE9_FUNC_FMC_D6_FMC_DA6>,
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<STM32H7_PE10_FUNC_FMC_D7_FMC_DA7>,
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<STM32H7_PE11_FUNC_FMC_D8_FMC_DA8>,
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<STM32H7_PE12_FUNC_FMC_D9_FMC_DA9>,
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<STM32H7_PE13_FUNC_FMC_D10_FMC_DA10>,
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<STM32H7_PE14_FUNC_FMC_D11_FMC_DA11>,
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<STM32H7_PE15_FUNC_FMC_D12_FMC_DA12>,
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<STM32H7_PF0_FUNC_FMC_A0>,
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<STM32H7_PF1_FUNC_FMC_A1>,
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<STM32H7_PF2_FUNC_FMC_A2>,
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<STM32H7_PF3_FUNC_FMC_A3>,
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<STM32H7_PF4_FUNC_FMC_A4>,
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<STM32H7_PF5_FUNC_FMC_A5>,
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<STM32H7_PF11_FUNC_FMC_SDNRAS>,
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<STM32H7_PF12_FUNC_FMC_A6>,
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<STM32H7_PF13_FUNC_FMC_A7>,
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<STM32H7_PF14_FUNC_FMC_A8>,
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<STM32H7_PF15_FUNC_FMC_A9>,
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<STM32H7_PG0_FUNC_FMC_A10>,
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<STM32H7_PG1_FUNC_FMC_A11>,
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<STM32H7_PG2_FUNC_FMC_A12>,
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<STM32H7_PG4_FUNC_FMC_A14_FMC_BA0>,
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<STM32H7_PG5_FUNC_FMC_A15_FMC_BA1>,
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<STM32H7_PG8_FUNC_FMC_SDCLK>,
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<STM32H7_PG15_FUNC_FMC_SDNCAS>,
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<STM32H7_PH5_FUNC_FMC_SDNWE>,
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<STM32H7_PH6_FUNC_FMC_SDNE1>,
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<STM32H7_PH7_FUNC_FMC_SDCKE1>,
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<STM32H7_PH8_FUNC_FMC_D16>,
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<STM32H7_PH9_FUNC_FMC_D17>,
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<STM32H7_PH10_FUNC_FMC_D18>,
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<STM32H7_PH11_FUNC_FMC_D19>,
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<STM32H7_PH12_FUNC_FMC_D20>,
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<STM32H7_PH13_FUNC_FMC_D21>,
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<STM32H7_PH14_FUNC_FMC_D22>,
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<STM32H7_PH15_FUNC_FMC_D23>,
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<STM32H7_PI0_FUNC_FMC_D24>,
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<STM32H7_PI1_FUNC_FMC_D25>,
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<STM32H7_PI2_FUNC_FMC_D26>,
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<STM32H7_PI3_FUNC_FMC_D27>,
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<STM32H7_PI4_FUNC_FMC_NBL2>,
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<STM32H7_PI5_FUNC_FMC_NBL3>,
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<STM32H7_PI6_FUNC_FMC_D28>,
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<STM32H7_PI7_FUNC_FMC_D29>,
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<STM32H7_PI9_FUNC_FMC_D30>,
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<STM32H7_PI10_FUNC_FMC_D31>;
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slew-rate = <3>;
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};
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};
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};
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};
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};
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@ -42,45 +42,83 @@
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#include "skeleton.dtsi"
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#include "armv7-m.dtsi"
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#include <dt-bindings/clock/stm32h7-clks.h>
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/ {
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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clock-frequency = <25000000>;
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};
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timer_clk: timer-clk {
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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clock-frequency = <32768>;
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};
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clk_i2s: i2s_ckin {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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};
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soc {
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rcc: rcc@58024400 {
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#clock-cells = <1>;
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#reset-cells = <1>;
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compatible = "st,stm32h743-rcc", "st,stm32-rcc";
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reg = <0x58024400 0x400>;
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clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>, <&clk_hsi>, <&clk_csi>;
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st,syscfg = <&pwrcfg>;
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};
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usart1: serial@40011000 {
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compatible = "st,stm32f7-usart", "st,stm32f7-uart";
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compatible = "st,stm32h7-usart", "st,stm32h7-uart";
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reg = <0x40011000 0x400>;
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interrupts = <37>;
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status = "disabled";
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clocks = <&timer_clk>;
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clocks = <&rcc USART1_CK>;
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};
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usart2: serial@40004400 {
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compatible = "st,stm32f7-usart", "st,stm32f7-uart";
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compatible = "st,stm32h7-usart", "st,stm32h7-uart";
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reg = <0x40004400 0x400>;
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interrupts = <38>;
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status = "disabled";
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clocks = <&timer_clk>;
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clocks = <&rcc USART2_CK>;
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};
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timer5: timer@40000c00 {
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compatible = "st,stm32-timer";
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reg = <0x40000c00 0x400>;
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interrupts = <50>;
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clocks = <&timer_clk>;
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clocks = <&rcc TIM5_CK>;
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};
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pwrcfg: power-config@58024800 {
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compatible = "syscon";
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reg = <0x58024800 0x400>;
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};
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fmc: fmc@52004000 {
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compatible = "st,stm32h7-fmc";
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reg = <0x52004000 0x1000>;
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clocks = <&rcc FMC_CK>;
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <64000000>;
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};
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clk_csi: clk-csi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <4000000>;
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};
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};
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};
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@ -43,6 +43,7 @@
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/dts-v1/;
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#include "stm32h743.dtsi"
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#include "stm32h743-pinctrl.dtsi"
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#include <dt-bindings/memory/stm32-sdram.h>
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/ {
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model = "STMicroelectronics STM32H743i-Discovery board";
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@ -59,15 +60,41 @@
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aliases {
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serial0 = &usart2;
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gpio0 = &gpioa;
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gpio1 = &gpiob;
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gpio2 = &gpioc;
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gpio3 = &gpiod;
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gpio4 = &gpioe;
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gpio5 = &gpiof;
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gpio6 = &gpiog;
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gpio7 = &gpioh;
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gpio8 = &gpioi;
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gpio9 = &gpioj;
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gpio10 = &gpiok;
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};
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};
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&clk_hse {
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clock-frequency = <125000000>;
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};
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&usart2 {
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pinctrl-0 = <&usart2_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&fmc {
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pinctrl-0 = <&fmc_pins>;
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pinctrl-names = "default";
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status = "okay";
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/*
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* Memory configuration from sdram datasheet IS42S32800G-6BLI
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* firsct bank is bank@0
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* second bank is bank@1
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*/
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bank1: bank@1 {
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st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4
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CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>;
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st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2
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TWR_1 TRCD_1>;
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st,sdram-refcount = <1539>;
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};
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};
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@ -43,6 +43,7 @@
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/dts-v1/;
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#include "stm32h743.dtsi"
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#include "stm32h743-pinctrl.dtsi"
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#include <dt-bindings/memory/stm32-sdram.h>
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/ {
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model = "STMicroelectronics STM32H743i-EVAL board";
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@ -59,16 +60,41 @@
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|
||||
aliases {
|
||||
serial0 = &usart1;
|
||||
gpio0 = &gpioa;
|
||||
gpio1 = &gpiob;
|
||||
gpio2 = &gpioc;
|
||||
gpio3 = &gpiod;
|
||||
gpio4 = &gpioe;
|
||||
gpio5 = &gpiof;
|
||||
gpio6 = &gpiog;
|
||||
gpio7 = &gpioh;
|
||||
gpio8 = &gpioi;
|
||||
gpio9 = &gpioj;
|
||||
gpio10 = &gpiok;
|
||||
};
|
||||
};
|
||||
|
||||
&clk_hse {
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
&usart1 {
|
||||
pinctrl-0 = <&usart1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fmc {
|
||||
pinctrl-0 = <&fmc_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* Memory configuration from sdram datasheet IS42S32800G-6BLI
|
||||
* firsct bank is bank@0
|
||||
* second bank is bank@1
|
||||
*/
|
||||
bank2: bank@1 {
|
||||
st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4
|
||||
CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>;
|
||||
st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2
|
||||
TWR_1 TRCD_1>;
|
||||
st,sdram-refcount = <1539>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -18,7 +18,9 @@
|
|||
#define CAS_1 0x1
|
||||
#define CAS_2 0x2
|
||||
#define CAS_3 0x3
|
||||
#define SDCLK_DIS 0x0
|
||||
#define SDCLK_2 0x2
|
||||
#define SDCLK_3 0x3
|
||||
#define RD_BURST_EN 0x1
|
||||
#define RD_BURST_DIS 0x0
|
||||
#define RD_PIPE_DL_0 0x0
|
||||
|
|
@ -26,12 +28,17 @@
|
|||
#define RD_PIPE_DL_2 0x2
|
||||
|
||||
/* Timing = value +1 cycles */
|
||||
#define TMRD_1 (1 - 1)
|
||||
#define TMRD_2 (2 - 1)
|
||||
#define TXSR_1 (1 - 1)
|
||||
#define TXSR_6 (6 - 1)
|
||||
#define TRAS_1 (1 - 1)
|
||||
#define TRAS_4 (4 - 1)
|
||||
#define TRC_6 (6 - 1)
|
||||
#define TWR_1 (1 - 1)
|
||||
#define TWR_2 (2 - 1)
|
||||
#define TRP_2 (2 - 1)
|
||||
#define TRCD_1 (1 - 1)
|
||||
#define TRCD_2 (2 - 1)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue