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https://github.com/AsahiLinux/u-boot
synced 2024-11-28 15:41:40 +00:00
ARM: uniphier: split u-boot,dm-pre-reloc out to uniphier-v7-u-boot.dtsi
UniPhier 32-bit SoCs use CONFIG_SPL_OF_CONTROL. So, many nodes must be marked as dm-pre-reloc to prevent fdtgrep from stripping them off. Sprinkling U-Boot-specific properties all over the place is painful because DT files are synced with Linux from time to time. Split u-boot,dm-pre-reloc out to uniphier-v7-u-boot.dtsi, which is appended to UniPhier V7 DTS before the build. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
This commit is contained in:
parent
d0df9588e8
commit
9ac0e7b37a
16 changed files with 63 additions and 135 deletions
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@ -68,12 +68,3 @@
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&usb1 {
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status = "okay";
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};
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/* for U-Boot only */
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&serial0 {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_uart0 {
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u-boot,dm-pre-reloc;
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};
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@ -50,7 +50,6 @@
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#size-cells = <1>;
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ranges;
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interrupt-parent = <&intc>;
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u-boot,dm-pre-reloc;
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l2: l2-cache@500c0000 {
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compatible = "socionext,uniphier-system-cache";
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@ -295,11 +294,9 @@
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compatible = "socionext,uniphier-ld4-soc-glue",
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"simple-mfd", "syscon";
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reg = <0x5f800000 0x2000>;
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u-boot,dm-pre-reloc;
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pinctrl: pinctrl {
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compatible = "socionext,uniphier-ld4-pinctrl";
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u-boot,dm-pre-reloc;
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};
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};
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@ -70,12 +70,3 @@
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&usb1 {
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status = "okay";
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};
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/* for U-Boot only */
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&serial0 {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_uart0 {
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u-boot,dm-pre-reloc;
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};
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@ -90,12 +90,3 @@
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&usb3 {
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status = "okay";
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};
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/* for U-Boot only */
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&serial0 {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_uart0 {
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u-boot,dm-pre-reloc;
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};
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@ -83,12 +83,3 @@
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&usb1 {
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status = "okay";
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};
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/* for U-Boot only */
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&serial0 {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_uart0 {
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u-boot,dm-pre-reloc;
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};
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@ -85,24 +85,3 @@
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&usb3 {
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status = "okay";
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};
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/* for U-Boot only */
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&serial0 {
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u-boot,dm-pre-reloc;
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};
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&mio_clk {
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u-boot,dm-pre-reloc;
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};
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&emmc {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_uart0 {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_emmc {
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u-boot,dm-pre-reloc;
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};
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@ -58,7 +58,6 @@
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#size-cells = <1>;
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ranges;
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interrupt-parent = <&intc>;
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u-boot,dm-pre-reloc;
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l2: l2-cache@500c0000 {
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compatible = "socionext,uniphier-system-cache";
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@ -224,7 +223,6 @@
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compatible = "socionext,uniphier-pro4-mioctrl",
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"simple-mfd", "syscon";
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reg = <0x59810000 0x800>;
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u-boot,dm-pre-reloc;
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mio_clk: clock {
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compatible = "socionext,uniphier-pro4-mio-clock";
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@ -333,11 +331,9 @@
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compatible = "socionext,uniphier-pro4-soc-glue",
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"simple-mfd", "syscon";
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reg = <0x5f800000 0x2000>;
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u-boot,dm-pre-reloc;
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pinctrl: pinctrl {
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compatible = "socionext,uniphier-pro4-pinctrl";
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u-boot,dm-pre-reloc;
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};
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};
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@ -55,12 +55,3 @@
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&sd {
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status = "okay";
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};
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/* for U-Boot only */
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&serial1 {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_uart1 {
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u-boot,dm-pre-reloc;
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};
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@ -132,7 +132,6 @@
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#size-cells = <1>;
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ranges;
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interrupt-parent = <&intc>;
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u-boot,dm-pre-reloc;
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l2: l2-cache@500c0000 {
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compatible = "socionext,uniphier-system-cache";
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@ -311,7 +310,6 @@
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compatible = "socionext,uniphier-pro5-sdctrl",
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"simple-mfd", "syscon";
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reg = <0x59810000 0x400>;
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u-boot,dm-pre-reloc;
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sd_clk: clock {
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compatible = "socionext,uniphier-pro5-sd-clock";
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@ -344,11 +342,9 @@
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compatible = "socionext,uniphier-pro5-soc-glue",
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"simple-mfd", "syscon";
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reg = <0x5f800000 0x2000>;
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u-boot,dm-pre-reloc;
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pinctrl: pinctrl {
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compatible = "socionext,uniphier-pro5-pinctrl";
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u-boot,dm-pre-reloc;
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};
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};
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@ -66,24 +66,3 @@
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&usb1 {
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status = "okay";
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};
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/* for U-Boot only */
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&serial2 {
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u-boot,dm-pre-reloc;
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};
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&sd_clk {
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u-boot,dm-pre-reloc;
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};
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&emmc {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_uart2 {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_emmc {
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u-boot,dm-pre-reloc;
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};
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@ -49,24 +49,3 @@
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&usb0 {
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status = "okay";
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};
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/* for U-Boot only */
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&serial2 {
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u-boot,dm-pre-reloc;
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};
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&sd_clk {
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u-boot,dm-pre-reloc;
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};
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&emmc {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_uart2 {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_emmc {
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u-boot,dm-pre-reloc;
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};
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@ -120,7 +120,6 @@
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#size-cells = <1>;
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ranges;
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interrupt-parent = <&intc>;
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u-boot,dm-pre-reloc;
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l2: l2-cache@500c0000 {
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compatible = "socionext,uniphier-system-cache";
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@ -297,7 +296,6 @@
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compatible = "socionext,uniphier-pxs2-sdctrl",
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"simple-mfd", "syscon";
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reg = <0x59810000 0x400>;
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u-boot,dm-pre-reloc;
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sd_clk: clock {
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compatible = "socionext,uniphier-pxs2-sd-clock";
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@ -365,11 +363,9 @@
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compatible = "socionext,uniphier-pxs2-soc-glue",
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"simple-mfd", "syscon";
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reg = <0x5f800000 0x2000>;
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u-boot,dm-pre-reloc;
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pinctrl: pinctrl {
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compatible = "socionext,uniphier-pxs2-pinctrl";
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u-boot,dm-pre-reloc;
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};
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};
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@ -72,12 +72,3 @@
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&usb2 {
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status = "okay";
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};
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/* for U-Boot only */
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&serial0 {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_uart0 {
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u-boot,dm-pre-reloc;
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};
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@ -50,7 +50,6 @@
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#size-cells = <1>;
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ranges;
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interrupt-parent = <&intc>;
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u-boot,dm-pre-reloc;
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l2: l2-cache@500c0000 {
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compatible = "socionext,uniphier-system-cache";
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compatible = "socionext,uniphier-sld8-soc-glue",
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"simple-mfd", "syscon";
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reg = <0x5f800000 0x2000>;
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u-boot,dm-pre-reloc;
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pinctrl: pinctrl {
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compatible = "socionext,uniphier-sld8-pinctrl";
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u-boot,dm-pre-reloc;
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};
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};
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61
arch/arm/dts/uniphier-v7-u-boot.dtsi
Normal file
61
arch/arm/dts/uniphier-v7-u-boot.dtsi
Normal file
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@ -0,0 +1,61 @@
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/ {
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soc {
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u-boot,dm-pre-reloc;
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serial@54006800 {
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u-boot,dm-pre-reloc;
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};
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serial@54006900 {
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u-boot,dm-pre-reloc;
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};
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serial@54006a00 {
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u-boot,dm-pre-reloc;
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};
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mioctrl@59810000 {
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u-boot,dm-pre-reloc;
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clock {
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u-boot,dm-pre-reloc;
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};
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};
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sdctrl@59810000 {
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u-boot,dm-pre-reloc;
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clock {
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u-boot,dm-pre-reloc;
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};
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};
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soc-glue@5f800000 {
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u-boot,dm-pre-reloc;
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pinctrl {
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u-boot,dm-pre-reloc;
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emmc_grp {
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u-boot,dm-pre-reloc;
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};
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uart0_grp {
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u-boot,dm-pre-reloc;
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};
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uart1_grp {
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u-boot,dm-pre-reloc;
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};
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uart2_grp {
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u-boot,dm-pre-reloc;
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};
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};
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};
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};
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};
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&emmc {
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u-boot,dm-pre-reloc;
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};
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@ -117,4 +117,6 @@ config CMD_DDRMPHY_DUMP
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The command "ddrmphy" shows the resulting parameters of DDR Multi PHY
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training; it is useful for the evaluation of DDR Multi PHY training.
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config SYS_SOC
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default "uniphier-v7" if ARCH_UNIPHIER_LD4_SLD8 || ARCH_UNIPHIER_V7_MULTI
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endif
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