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https://github.com/AsahiLinux/u-boot
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sunxi: video: split out PLL configuration code
It will be reused in new DM LCD driver. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
This commit is contained in:
Vasily Khoruzhick
Anatolij Gustschin
parent
491041c749
commit
79f285ddeb
3 changed files with 132 additions and 116 deletions
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@ -124,5 +124,8 @@ void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
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void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
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const struct display_timing *mode,
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bool ext_hvsync, bool is_composite);
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void lcdc_pll_set(struct sunxi_ccm_reg * const ccm, int tcon,
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int dotclock, int *clk_div, int *clk_double,
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bool is_composite);
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#endif /* _LCDC_H */
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@ -10,6 +10,7 @@
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/lcdc.h>
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#include <asm/io.h>
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@ -100,7 +101,7 @@ void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
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writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) |
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SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v);
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#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
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#if defined(CONFIG_VIDEO_LCD_IF_PARALLEL) || defined(CONFIG_VIDEO_DE2)
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writel(SUNXI_LCDC_X(mode->hsync_len.typ) |
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SUNXI_LCDC_Y(mode->vsync_len.typ), &lcdc->tcon0_timing_sync);
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@ -207,3 +208,122 @@ void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
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SUNXI_LCDC_MUX_CTRL_SRC0(1));
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#endif
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}
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void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
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int *clk_div, int *clk_double, bool is_composite)
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{
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int value, n, m, min_m, max_m, diff;
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int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
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int best_double = 0;
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bool use_mipi_pll = false;
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if (tcon == 0) {
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#if defined(CONFIG_VIDEO_LCD_IF_PARALLEL) || defined(CONFIG_SUNXI_DE2)
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min_m = 6;
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max_m = 127;
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#endif
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#ifdef CONFIG_VIDEO_LCD_IF_LVDS
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min_m = 7;
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max_m = 7;
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#endif
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} else {
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min_m = 1;
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max_m = 15;
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}
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/*
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* Find the lowest divider resulting in a matching clock, if there
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* is no match, pick the closest lower clock, as monitors tend to
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* not sync to higher frequencies.
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*/
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for (m = min_m; m <= max_m; m++) {
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#ifndef CONFIG_SUNXI_DE2
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n = (m * dotclock) / 3000;
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if ((n >= 9) && (n <= 127)) {
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value = (3000 * n) / m;
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diff = dotclock - value;
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if (diff < best_diff) {
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best_diff = diff;
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best_m = m;
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best_n = n;
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best_double = 0;
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}
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}
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/* These are just duplicates */
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if (!(m & 1))
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continue;
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#endif
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/* No double clock on DE2 */
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n = (m * dotclock) / 6000;
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if ((n >= 9) && (n <= 127)) {
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value = (6000 * n) / m;
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diff = dotclock - value;
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if (diff < best_diff) {
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best_diff = diff;
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best_m = m;
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best_n = n;
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best_double = 1;
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}
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}
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}
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#ifdef CONFIG_MACH_SUN6I
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/*
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* Use the MIPI pll if we've been unable to find any matching setting
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* for PLL3, this happens with high dotclocks because of min_m = 6.
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*/
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if (tcon == 0 && best_n == 0) {
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use_mipi_pll = true;
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best_m = 6; /* Minimum m for tcon0 */
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}
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if (use_mipi_pll) {
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clock_set_pll3(297000000); /* Fix the video pll at 297 MHz */
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clock_set_mipi_pll(best_m * dotclock * 1000);
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debug("dotclock: %dkHz = %dkHz via mipi pll\n",
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dotclock, clock_get_mipi_pll() / best_m / 1000);
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} else
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#endif
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{
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clock_set_pll3(best_n * 3000000);
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debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
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dotclock,
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(best_double + 1) * clock_get_pll3() / best_m / 1000,
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best_double + 1, best_n, best_m);
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}
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if (tcon == 0) {
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u32 pll;
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if (use_mipi_pll)
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pll = CCM_LCD_CH0_CTRL_MIPI_PLL;
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else if (best_double)
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pll = CCM_LCD_CH0_CTRL_PLL3_2X;
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else
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pll = CCM_LCD_CH0_CTRL_PLL3;
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#ifndef CONFIG_SUNXI_DE2
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writel(CCM_LCD_CH0_CTRL_GATE | CCM_LCD_CH0_CTRL_RST | pll,
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&ccm->lcd0_ch0_clk_cfg);
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#else
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writel(CCM_LCD_CH0_CTRL_GATE | CCM_LCD_CH0_CTRL_RST | pll,
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&ccm->lcd0_clk_cfg);
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#endif
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}
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#ifndef CONFIG_SUNXI_DE2
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else {
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writel(CCM_LCD_CH1_CTRL_GATE |
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(best_double ? CCM_LCD_CH1_CTRL_PLL3_2X :
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CCM_LCD_CH1_CTRL_PLL3) |
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CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
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if (is_composite)
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setbits_le32(&ccm->lcd0_ch1_clk_cfg,
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CCM_LCD_CH1_CTRL_HALF_SCLK1);
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}
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#endif
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*clk_div = best_m;
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*clk_double = best_double;
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}
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@ -516,119 +516,6 @@ static void sunxi_composer_enable(void)
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setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
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}
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/*
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* LCDC, what allwinner calls a CRTC, so timing controller and serializer.
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*/
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static void sunxi_lcdc_pll_set(int tcon, int dotclock,
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int *clk_div, int *clk_double)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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int value, n, m, min_m, max_m, diff;
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int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
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int best_double = 0;
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bool use_mipi_pll = false;
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if (tcon == 0) {
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#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
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min_m = 6;
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max_m = 127;
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#endif
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#ifdef CONFIG_VIDEO_LCD_IF_LVDS
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min_m = max_m = 7;
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#endif
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} else {
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min_m = 1;
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max_m = 15;
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}
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/*
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* Find the lowest divider resulting in a matching clock, if there
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* is no match, pick the closest lower clock, as monitors tend to
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* not sync to higher frequencies.
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*/
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for (m = min_m; m <= max_m; m++) {
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n = (m * dotclock) / 3000;
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if ((n >= 9) && (n <= 127)) {
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value = (3000 * n) / m;
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diff = dotclock - value;
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if (diff < best_diff) {
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best_diff = diff;
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best_m = m;
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best_n = n;
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best_double = 0;
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}
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}
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/* These are just duplicates */
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if (!(m & 1))
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continue;
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n = (m * dotclock) / 6000;
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if ((n >= 9) && (n <= 127)) {
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value = (6000 * n) / m;
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diff = dotclock - value;
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if (diff < best_diff) {
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best_diff = diff;
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best_m = m;
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best_n = n;
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best_double = 1;
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}
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}
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}
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#ifdef CONFIG_MACH_SUN6I
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/*
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* Use the MIPI pll if we've been unable to find any matching setting
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* for PLL3, this happens with high dotclocks because of min_m = 6.
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*/
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if (tcon == 0 && best_n == 0) {
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use_mipi_pll = true;
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best_m = 6; /* Minimum m for tcon0 */
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}
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if (use_mipi_pll) {
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clock_set_pll3(297000000); /* Fix the video pll at 297 MHz */
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clock_set_mipi_pll(best_m * dotclock * 1000);
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debug("dotclock: %dkHz = %dkHz via mipi pll\n",
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dotclock, clock_get_mipi_pll() / best_m / 1000);
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} else
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#endif
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{
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clock_set_pll3(best_n * 3000000);
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debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
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dotclock,
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(best_double + 1) * clock_get_pll3() / best_m / 1000,
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best_double + 1, best_n, best_m);
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}
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if (tcon == 0) {
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u32 pll;
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if (use_mipi_pll)
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pll = CCM_LCD_CH0_CTRL_MIPI_PLL;
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else if (best_double)
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pll = CCM_LCD_CH0_CTRL_PLL3_2X;
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else
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pll = CCM_LCD_CH0_CTRL_PLL3;
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writel(CCM_LCD_CH0_CTRL_GATE | CCM_LCD_CH0_CTRL_RST | pll,
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&ccm->lcd0_ch0_clk_cfg);
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} else {
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writel(CCM_LCD_CH1_CTRL_GATE |
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(best_double ? CCM_LCD_CH1_CTRL_PLL3_2X :
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CCM_LCD_CH1_CTRL_PLL3) |
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CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
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if (sunxi_is_composite())
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setbits_le32(&ccm->lcd0_ch1_clk_cfg,
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CCM_LCD_CH1_CTRL_HALF_SCLK1);
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}
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*clk_div = best_m;
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*clk_double = best_double;
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}
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static void sunxi_lcdc_init(void)
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{
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struct sunxi_ccm_reg * const ccm =
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@ -755,6 +642,8 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
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{
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struct sunxi_lcdc_reg * const lcdc =
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(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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int clk_div, clk_double, pin;
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struct display_timing timing;
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@ -774,7 +663,8 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
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#endif
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}
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sunxi_lcdc_pll_set(0, mode->pixclock_khz, &clk_div, &clk_double);
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lcdc_pll_set(ccm, 0, mode->pixclock_khz, &clk_div, &clk_double,
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sunxi_is_composite());
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sunxi_ctfb_mode_to_display_timing(mode, &timing);
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lcdc_tcon0_mode_set(lcdc, &timing, clk_div, for_ext_vga_dac,
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@ -788,6 +678,8 @@ static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
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{
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struct sunxi_lcdc_reg * const lcdc =
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(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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struct display_timing timing;
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sunxi_ctfb_mode_to_display_timing(mode, &timing);
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@ -799,7 +691,8 @@ static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
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sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD_LCD0);
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}
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sunxi_lcdc_pll_set(1, mode->pixclock_khz, clk_div, clk_double);
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lcdc_pll_set(ccm, 1, mode->pixclock_khz, clk_div, clk_double,
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sunxi_is_composite());
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}
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#endif /* CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || CONFIG_VIDEO_COMPOSITE */
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