Commit graph

2339 commits

Author SHA1 Message Date
Dave Liu
6a81978367 fsl-ddr: Fix two bugs in the ddr infrastructure
1. wr_lat
   UM said the total write latency for DDR2 is equal to
   WR_LAT + ADD_LAT, the write latency is CL + ADD_LAT - 1.
   so, the WR_LAT = CL - 1;
2. rd_to_pre
   we missed to add the ADD_LAT for DDR2 case.

Reported-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Dave Liu <daveliu@freescale.com>
2009-03-30 13:33:50 -05:00
Ladislav Michl
89c00fb158 OMAP: use {read,write}l to access timer registers
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
2009-03-30 18:58:41 +02:00
Ladislav Michl
81472d893f OMAP: rename timer divisor
Divisor field is called PTV not PVT.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-30 18:58:41 +02:00
Ladislav Michl
fe672d60b2 OMAP: reindent timer code
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
2009-03-30 18:58:40 +02:00
Jean-Christophe PLAGNIOL-VILLARD
b3f66b0ba0 s3c2410: move nand driver to drivers/mtd/nand
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-30 18:58:40 +02:00
Jean-Christophe PLAGNIOL-VILLARD
d3b6357741 s3c24x0: move i2c driver to drivers/i2c
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-30 18:58:40 +02:00
Jean-Christophe PLAGNIOL-VILLARD
300f99f453 s3c24x0: move serial driver to drivers/serial
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-30 18:58:39 +02:00
Jean-Christophe PLAGNIOL-VILLARD
942ba9969b davinci: move i2c driver to drivers/i2c
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-30 18:58:39 +02:00
Jean-Christophe PLAGNIOL-VILLARD
ee4f3e2765 davinci: move nand driver to drivers/mtd/nand
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-30 18:58:39 +02:00
Jean-Christophe PLAGNIOL-VILLARD
d3e55d0774 imx: move serial driver to drivers/serial
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-30 18:58:38 +02:00
Jean-Christophe PLAGNIOL-VILLARD
a6ef3ddeaf arm720t/clps7111: move serial driver to drivers/serial
add CONFIG_CLPS7111_SERIAL to activate the driver

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-29 23:01:42 +02:00
Jean-Christophe PLAGNIOL-VILLARD
6790c55704 lpc2292: move serial driver to drivers/serial
add CONFIG_LPC2292_SERIAL to activate the driver

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-29 23:01:42 +02:00
Jean-Christophe PLAGNIOL-VILLARD
176a600d0e ks8695: move serial driver to drivers/serial
add CONFIG_KS8695_SERIAL to activate the driver

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-29 23:01:42 +02:00
Jean-Christophe PLAGNIOL-VILLARD
6d27bca15d s3c64xx: move usb driver to drivers/usb
add CONFIG_USB_S3C64XX to activate the driver

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-29 23:01:42 +02:00
Jean-Christophe PLAGNIOL-VILLARD
ecfa8dda2f imx31: move serial driver to drivers/serial
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-29 23:01:41 +02:00
Jean-Christophe PLAGNIOL-VILLARD
9ea91c9fef netarm: move serial driver to drivers/serial
add CONFIG_NETARM_SERIAL to activate the driver

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-29 23:01:41 +02:00
Jean-Christophe PLAGNIOL-VILLARD
412ab70588 sa1100: move serial driver to drivers/serial
add CONFIG_SA1100_SERIAL to activate the driver

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-29 23:01:41 +02:00
Jean-Christophe PLAGNIOL-VILLARD
b2368754a9 s3c44b0: extract cache from cpu.c
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-29 23:01:41 +02:00
Jean-Christophe PLAGNIOL-VILLARD
40fd626223 s3c44b0: move serial driver to drivers/serial
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-29 23:01:41 +02:00
Jean-Christophe PLAGNIOL-VILLARD
5fe1377cc4 s3c44b0: move rtc driver to drivers/rtc
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-29 23:01:40 +02:00
Jean-Christophe PLAGNIOL-VILLARD
50f601cca8 s3c44b0: move i2c driver to drivers/i2c
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-29 23:01:40 +02:00
Jean-Christophe PLAGNIOL-VILLARD
281dfb0c0c s3c4510b: move specific code to soc directory
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-29 23:01:36 +02:00
Heiko Schocher
76756e41cd ppc: cleanup compiler errors/warnings
Current u-boot top of tree builds with warnings/errors for
the following boards:

ads5121 cpci5200 mecp5200 v38b IAD210 MBX MBX860T NX823
RPXClassic debris PN62

following patch solves this.

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2009-03-27 20:23:32 +01:00
Wolfgang Denk
aaa0e0812f Merge branch 'master' of git://git.denx.de/u-boot-at91 2009-03-26 22:27:45 +01:00
Jon Smirl
33e88c557b mpc5200: suppress printf until console initialized
On boards which have the environment in eeprom, i2c_init() is called
before the console and RAM are initialized.
Suppress printfs until the console is initialized.

Signed-off-by: Jon Smirl <jonsmirl@gmail.com>
Acked-by: Heiko Schocher <hs@denx.de>
2009-03-25 22:50:04 +01:00
Mike Frysinger
74398b23f9 Blackfin: put memory into self-refresh before/after programming clocks
When initializing the core clocks, stick external memory into self-refresh.
This gains us a few cool things:
 - support suspend-to-RAM with Linux
 - reprogram clocks automatically when doing "go" on u-boot.bin in RAM
 - make sure settings are stable before flashing new version
 - finally fully unify initialize startup code path between LDR/non-LDR

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-03-23 15:14:55 -04:00
Mike Frysinger
d347d572ab Blackfin: do not program voltage regulator on parts that do not have one
Some newer Blackfins (like the BF51x) do not have an on-chip voltage
regulator, so do not attempt to program the memory as if it does.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-03-23 15:14:55 -04:00
Mike Frysinger
0d4f24b70f Blackfin: setup a sane default EBIU_SDBCTL for SDRAM controllers
If the board config does not specify an explicit EBIU_SDBCTL value, set it
up with sane values based on other configuration options.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-03-23 15:14:54 -04:00
Mike Frysinger
3986e981f5 Blackfin: handle reboot anomaly 432
Workaround anomaly 432:
The bfrom_SysControl() firmware function does not clear the SIC_IWR1
register before executing the PLL programming sequence.  Therefore, any
interrupt enabled in the SIC_IWR1 register prior to the call to
bfrom_SysControl() can prematurely terminate the idle sequence required
for the PLL to relock properly. SIC_IWR0 is properly handled.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-03-23 15:14:54 -04:00
Mike Frysinger
7e1d212b6d Blackfin: kill off LDR jump block
The Boot ROM uses EVT1 as the entry point so set that rather than having
to use a tiny jump block in the default EVT1 location.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-03-23 15:14:54 -04:00
Mike Frysinger
a75fa148d6 Blackfin: simplify symbol_lookup() a bit
No need to skip a byte as the symbol table handles this.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-03-23 15:14:54 -04:00
Mike Frysinger
2decc2a8d1 Blackfin: mark bfin_reset static
The function is only used locally, so mark it static.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-03-23 15:14:52 -04:00
Mike Frysinger
e82b762f29 Blackfin: fix jtag console tstc
The jtag tstc operation was checking the hardware to see if data is
available from it (which is fine for the jtag getc operation), but the
higher layers need to know whether any data is available.  Since we have
to read up to 4 bytes at a time from the hardware, the higher layers need
to know they can consume the cached bytes as well.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-03-23 15:14:52 -04:00
Haavard Skinnemoen
8206bfae3a Merge branch 'mimc200' 2009-03-23 10:22:41 +01:00
Nicolas Ferre
df486b1fa3 at91: Support for the at91sam9g20 : Atmel 400Mhz ARM 926ej-s SOC.
AT91sam9g20 is an evolution of the at91sam9260 with a faster clock speed.

The AT91SAM9G20-EK board is an updated revision of the AT91SAM9260-EK board.
It is essentially the same, with a few minor differences.

Here is the chip page on Atmel website:
http://www.atmel.com/dyn/products/product_card.asp?part_id=4337

Signed-off-by: Justin Waters <justin.waters@timesys.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-22 14:48:16 +01:00
Jean-Christophe PLAGNIOL-VILLARD
e2c0476f95 at91sam9/at91cap: move common macb initialisation to cpu
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-22 13:22:14 +01:00
Jean-Christophe PLAGNIOL-VILLARD
f3f91f886b at91sam9/at91cap: move common usb host initialisation to cpu
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-22 13:22:11 +01:00
Jean-Christophe PLAGNIOL-VILLARD
a484b00b86 at91sam9/at91cap: move common led management to cpu
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-22 13:22:08 +01:00
Jean-Christophe PLAGNIOL-VILLARD
7ebafb7ec1 at91sam9/at91cap: move common spi initialisation to cpu
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-22 13:22:06 +01:00
Jean-Christophe PLAGNIOL-VILLARD
1332a2a069 at91sam9/at91cap: move common serial initialisation to cpu
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-22 13:22:03 +01:00
Grzegorz Bernacki
5c4fa9b474 Add support for the digsy MTC board.
This is the InterControl custom device based on the MPC5200B chip.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
2009-03-20 22:39:14 +01:00
Stefan Roese
9cd690160d ppc4xx: Don't write the MAC address into the internal SoC registers
Remove this code. It's not needed. The 4xx EMAC driver stores the MAC
addresses into the SoC registers instead.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-03-20 22:39:14 +01:00
Graeme Russ
e17ee157ca Add basic relocation to i386 port
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-03-20 22:39:13 +01:00
Graeme Russ
8c63d47651 Implement SC520 timers
Signed-off-by: Graeme Russ <graeme.russ at gmail.com>
2009-03-20 22:39:13 +01:00
Graeme Russ
6d7f610b09 Factor out SC520 sub-features
Moved sub-features of the SC520 code which is currently selectively compiled
using #ifdef out of sc520.c into individual files selectively compiled via
the makefile

Signed-off-by: Graeme Russ <graeme.russ at gmail.com>
2009-03-20 22:39:13 +01:00
Graeme Russ
abf0cd3dff Rewrite i386 interrupt handling
Rewrite interrupt handling functionality for the i386 port. Separated
functionality into separate CPU and Architecture components.

It appears as if the i386 interrupt handler functionality was intended
to allow multiple handlers to be installed for a given interrupt.
Unfortunately, this functionality was not fully implemented and also
had the problem that irq_free_handler() does not allow the passing
of the handler function pointer and therefore could never be used to
free specific handlers that had been installed for a given IRQ.

There were also various issues with array bounds not being fully
tested.

I had two objectives in mind for the new implementation:

1) Keep the implementation as similar as possible to existing
   implementations. To that end, I have used the leon2/3
   implementations as the reference

2) Seperate CPU and Architecture specific elements. All specific i386
   interrupt functionality is now in cpu/i386/ with the high level
   API and architecture specific code in lib_i386. Functionality
   specific to the PC/AT architecture (i.e. cascaded i8259 PICs) has
   been further split out into an individual file to allow for the
   implementation of the PIC architecture of the SC520 CPU (supports
   more IRQs)

Signed-off-by: Graeme Russ <graeme.russ at gmail.com>
2009-03-20 22:39:13 +01:00
Graeme Russ
6d83e3ac61 Rename SC520 Configuration Options
Options are now all uniformly CONFIG_SYS_SC520_<option>

Signed-off-by: Graeme Russ <graeme.russ at gmail.com>
2009-03-20 22:39:12 +01:00
Trent Piepho
f62fb99941 Fix all linker script to handle all rodata sections
A recent gcc added a new unaligned rodata section called '.rodata.str1.1',
which needs to be added the the linker script.  Instead of just adding this
one section, we use a wildcard ".rodata*" to get all rodata linker section
gcc has now and might add in the future.

However, '*(.rodata*)' by itself will result in sub-optimal section
ordering.  The sections will be sorted by object file, which causes extra
padding between the unaligned rodata.str.1.1 of one object file and the
aligned rodata of the next object file.  This is easy to fix by using the
SORT_BY_ALIGNMENT command.

This patch has not be tested one most of the boards modified.  Some boards
have a linker script that looks something like this:

*(.text)
. = ALIGN(16);
*(.rodata)
*(.rodata.str1.4)
*(.eh_frame)

I change this to:

*(.text)
. = ALIGN(16);
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))

This means the start of rodata will no longer be 16 bytes aligned.
However, the boundary between text and rodata/eh_frame is still aligned to
16 bytes, which is what I think the real purpose of the ALIGN call is.

Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
2009-03-20 22:39:12 +01:00
Mike Frysinger
740e8ba7d4 npe: get mac address from environment
The environment is the canonical storage location of the mac address, so
we're killing off the global data location and moving everything to
querying the env directly.

The resulting code can also be simplified even further.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Stefan Roese <sr@denx.de>
CC: Ben Warren <biggerbadderben@gmail.com>
2009-03-20 22:39:11 +01:00
Mike Frysinger
6bacfa6a8e cpu/: get mac address from environment
The environment is the canonical storage location of the mac address, so
we're killing off the global data location and moving everything to
querying the env directly.

The cpus that get converted here:
	at91rm9200
	mpc512x
	mpc5xxx
	mpc8260
	mpc8xx
	ppc4xx

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Ben Warren <biggerbadderben@gmail.com>
CC: John Rigby <jrigby@freescale.com>
CC: Stefan Roese <sr@denx.de>
2009-03-20 22:39:11 +01:00
Anatolij Gustschin
f8853d105d ppc4xx: Fix bug in PCI outbound map configuration for canyonlands
PCI outbound address map configuration doesn't match the
PCI memory address range covered by appropriate TLB entry
configuration for canyonlands causing machine check
exceptions while accessing PCI memory regions. This patch
provides a fix for this issue.

Kazuaki Ichinohe observed and reported this issue while
testing display output with PCI ATI video card on canyonlands.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-03-20 12:58:31 +01:00
Grzegorz Bernacki
6a397ef0e6 mpc52xx: Get rid of board-specific #ifdef's in cpu/mpc5xxx/ide.c
Total5200 and digsy MTC use I2C port 2 pins as a ATA chip select.
To avoid adding board-specific ifdefs to cpu/mpc5xxx/ide.c new
define CONFIG_SYS_ATA_CS_ON_I2C2 was introduced. It is used by
Total5200 and will be used by digsy MTC and other boards with
ATA CS on I2C pins.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
2009-03-18 20:54:56 +01:00
Heiko Schocher
506f391888 8xx, icache: enabling ICache not before running from RAM
with the new CONFIG_SYS_DELAYED_ICACHE config option, ICache
is not enabled before code runs from RAM.

Signed-off-by: Heiko Schocher <hs@denx.de>
2009-03-18 20:48:29 +01:00
TsiChung Liew
42b68af106 ColdFire: PLATFORM_CPPFLAGS updates for new compiler
Update PLATFORM_CPPFLAGS to accept 4.3.x version of
ColdFire compiler.

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
2009-03-17 15:58:37 -06:00
TsiChung Liew
c3a9e63742 ColdFire: Fix M54451 serial boot dram setup
The serial boot dram extended/standard mode register was not
setup and was using default DRAM setup causing the U-boot was
unstable to boot up in serial mode.

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
2009-03-17 15:58:37 -06:00
arun c
32d11d5815 Coldfire: XL Bus minor fixes
According to coldfire manual data timeout > address time out
also use correct macro to program XARB_CFG

Signed-off-by: Arun C <arunedarath@mistralsolutions.com>
2009-03-17 15:58:07 -06:00
Wolfgang Denk
e05825324a Merge branch 'master' of git://git.denx.de/u-boot-sh 2009-03-15 22:15:13 +01:00
Wolfgang Denk
45f93d4e3c Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2009-03-15 22:12:10 +01:00
Wolfgang Denk
06ecf08847 Merge branch 'master' of git://git.denx.de/u-boot-arm 2009-03-15 22:09:18 +01:00
Wolfgang Denk
cd309029f2 Merge branch 'master' of git://git.denx.de/u-boot-pxa 2009-03-15 22:08:07 +01:00
Jerry Van Baren
394d30dd1e mpc83xx: Add bank configuration to FSL spd_sdram.c
The routine assumed 4 bank SDRAMs, enhance to configure for 4 or 8
bank SDRAMs.

Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
Acked-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-03-14 17:44:07 -05:00
Norbert van Bolhuis
b581626c1e mpc83xx: correctly set encryption and I2C bus 0 clock
This patch makes sure the correct mask is applied when setting
the encryption and I2C bus 0 clock in SCCR.
Failing to do so may lead to ENCCM being 0 in which case I2C bus 0
won't function.

Signed-off-by: Norbert van Bolhuis <nvbolhuis@aimvalley.nl>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-03-14 17:43:58 -05:00
Dirk Behme
e6a6a70415 OMAP3: Add support for OMAP3 die ID
Read and store OMAP3 die ID in U-Boot environment.

Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
2009-03-13 23:17:43 +01:00
Nobuhiro Iwamatsu
64f3c0b8ba sh: Add netdev header fixing of warning/build
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2009-03-12 23:58:30 +09:00
Ed Swarthout
0ee84b88b7 Fix mpc85xx ddr-gen3 ddr_sdram_cfg.
Commit e1be0d25, "32bit BUg fix for DDR2 on 8572" prevented other
sdram_cfg bits (such as ecc and self_refresh_in_sleep) from being set.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
2009-03-09 17:46:09 -05:00
Jean-Christophe PLAGNIOL-VILLARD
a922fdb87a PXA: timer use do_div and simplify it
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-09 12:01:32 +01:00
Wolfgang Denk
014c595f12 Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
Conflicts:
	lib_ppc/board.c

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-03-09 00:41:48 +01:00
Heiko Schocher
f70fd13e2f 8360, kmeter1: added bootcount feature.
add CONFIG_BOOTCOUNT_LIMIT feature for 8360 CPU.

The bootcounter uses 8 bytes from the muram,
because no other memory was found on this
CPU for the bootcount feature. So we must
correct the muram size in DTS before booting
Linux.

This feature is actual only implemented for
MPC8360, because not all 83xx CPU have qe,
and therefore no muram, which this feature
uses.

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-03-05 18:21:30 -06:00
Dave Liu
5b0055547f 83xx: Fix some bugs in spd sdram code
1. RD_TO_PRE missed to add the AL, and need min 2 clocks for
  tRTP according to DDR2 JEDEC spec.
2. WRTORD - tWTR need min 2 clocks according to DDR2 JEDEC spec.
3. add the support of DDR2-533,667,800 DIMMs
4. cpo
5. make the AL to min to gain better performance.

The Micron MT9HTF6472CHY-667D1 DIMMs test passed on
MPC837xEMDS platform at 266MHz/333MHz/400MHz data rate.

items 1, 2 and 5:
Acked-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>

Reported-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-03-05 18:20:37 -06:00
Graeme Russ
f5a77a09c9 Moved SC520 Files (fix commit 407976185e)
Fixes commit 407976185e

Signed-off-by: Graeme Russ <graeme.russ at gmail.com>
2009-02-25 11:59:22 +01:00
Anton Vorontsov
50a4d08e8f mpc83xx: PCI: Fix hard-coded first_busno value
We should use pci_last_busno() in pci_init_bus(), otherwise we'll
erroneously re-use PCI0's first_busno for PCI1 hoses.

NOTE: The patch is untested. All MPC83xx FSL boards I have have
PCI1 in miniPCI form, for which I don't have any cards handy.

But looking in cpu/mpc85xx/pci.c:
...
#ifdef CONFIG_MPC85XX_PCI2
        hose = &pci_hose[1];

        hose->first_busno = pci_hose[0].last_busno + 1;

And considering that we do the same for MPC83xx PCI-E support,
I think this patch is correct.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-02-23 15:52:23 -06:00
Anton Vorontsov
a5878d4271 mpc83xx: PCI: Fix bus-range fdt fixups for PCI1 controllers
This patch fixes copy-paste issue: pci_hose[0]'s first and last
busnos were used to fixup pci1's nodes.

We don't see this bug triggering only because Linux reenumerate
buses anyway.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-02-23 15:52:12 -06:00
Anton Vorontsov
b24a99f666 mpc83xx: PCIe: Fix CONFIG_PCI_SCAN_SHOW reporting bogus values
This patch fixes an issue in config space read accessors: we should
fill-in the value even if we fail (e.g. skipping devices), otherwise
CONFIG_PCI_SCAN_SHOW reports bogus values during boot up.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-02-23 15:51:59 -06:00
Anton Vorontsov
e2d72ba543 mpc83xx: PCIe: Don't start bus enumeration at 0
Currently we assign first_busno = 0 for the first PCIe hose, but this
scheme won't work if we have ordinary PCI hose already registered (its
first_busno value is 0 too).

The old code worked fine only because we have PCI disabled on
MPC837XEMDS boards in stand-alone mode (see commit 00f7bbae92
"mpc83xx: fix PCI scan hang on the standalone MPC837xE-MDS boards").
But on MPC837XERDB boards we have PCI and PCIe, so the bug actually
triggers.

So, to fix the issue, we should use pci_last_busno() + 1 for the
first_busno (i.e. last available busno).

Reported-by: Huang Changming <Chang-Ming.Huang@freescale.com>
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-02-23 15:51:35 -06:00
Olav Morken
d8f2aa3298 AVR32: Make cacheflush cpu-dependent
The AT32UC3A series of processors doesn't contain any cache, and issuing
cache control instructions on those will cause an exception. This commit
makes cacheflush.h arch-dependent in preparation for the AT32UC3A-support.

Signed-off-by: Gunnar Rangoy <gunnar@rangoy.com>
Signed-off-by: Paul Driveklepp <pauldriveklepp@gmail.com>
Signed-off-by: Olav Morken <olavmrk@gmail.com>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2009-02-23 10:34:23 +01:00
Haavard Skinnemoen
ea393eb1d6 Merge branch 'cleanups' into next 2009-02-23 10:27:15 +01:00
Wolfgang Denk
9d34d0a0c1 Merge branch 'master' of git://git.denx.de/u-boot-arm 2009-02-22 22:51:25 +01:00
Dirk Behme
6530a8bf8a OMAP3: Add OMAP3 auto detection
This patch adds OMAP3 cpu type auto detection based on OMAP3 register
and removes hardcoded values.

Signed-off-by: Steve Sakoman <sakoman@gmail.com>
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
2009-02-22 18:29:10 +01:00
Mike Frysinger
e1ffaee728 Blackfin: disable syscontrol code for now
Looks like the initcode updates fell out of order during my merges.  The
patch that really fixes up this code is part of power-on overhaul and so
is too large for merging at this point.  Instead, we can disable the code
as no currently in-tree board depends on it.  The next merge window will
fix things up properly.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-02-21 19:23:20 -05:00
Shinya Kuribayashi
35c9e14d80 MIPS: cpu/mips/Makefile: Add a missing START line
In the commit 79b51ff820 ([MIPS] cpu/mips/
Makefile: Split [CS]OBJS onto separate lines), I wrongly deleted a START
line.  This patch puts it back.

Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
2009-02-21 22:03:24 +01:00
Jean-Christophe PLAGNIOL-VILLARD
b03d92e558 pxa: move mmc drivers to drivers/mmc
introduce new macro CONFIG_PXA_MMC to activate it

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-02-20 03:47:50 +01:00
Tom Rix
9490f46564 ARM:PXA Remove redefinition of mmc_cid and mmc_csd.
These structures are defined in the common mmc.h

This was compile checked on cerf250.
2009-02-20 03:47:44 +01:00
Micha Kalfon
94a3312920 pxa: fixing get_timer to return time in miliseconds.
Fixing the get_timer function to return time in miliseconds instead of
ticks. Also fixed PXA boards to use the conventional value of 1000 for
CONFIG_SYS_HZ.

Signed-off-by: Micha Kalfon <smichak.uv@gmail.com>
2009-02-20 03:24:08 +01:00
Wolfgang Denk
44a01a73e8 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2009-02-19 00:50:08 +01:00
Wolfgang Denk
1bba30efe1 Coding style cleanup, update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-02-19 00:41:08 +01:00
Stefan Roese
b4996d6b21 ppc4xx: PCIe: Change 16GB inbound memory to 4GB
This patch fixes a problem recently seen on some 4xx platforms. For
example on Kilauea PCIe slot #0.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-02-18 15:59:20 +01:00
Andy Fleming
e1ac387f46 83xx: Add eSDHC support on 8379 EMDS board
Signed-off-by: Andy Fleming <afleming@freescale.com>
2009-02-16 18:07:43 -06:00
Andy Fleming
80522dc836 85xx: Add eSDHC support for 8536 DS
Signed-off-by: Andy Fleming <afleming@freescale.com>
2009-02-16 18:07:43 -06:00
Andy Fleming
1de97f9856 Eliminated arch-specific mmc header requirement
The current MMC infrastructure relies on the existence of an
arch-specific header file.  This isn't necessary, and a couple
drivers were forced to implement dummy files to meet this requirement.
Instead, we move the stuff in those header files into a more appropriate
place, and eliminate the stubs and the #include of asm/arch/mmc.h

Signed-off-by: Andy Fleming <afleming@freescale.com>
2009-02-16 18:07:41 -06:00
Andy Fleming
abb5466ccf Convert mmc_init to mmc_legacy_init
This is to get it out of the way of incoming MMC framework

Signed-off-by: Andy Fleming <afleming@freescale.com>
2009-02-16 18:07:40 -06:00
Andy Fleming
b2e2ed0233 Eliminate support for using MMC as memory
MMC cards are not memory, so we stop treating them that way.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2009-02-16 18:07:40 -06:00
Poonam_Aggrwal-b10812
e1be0d25ec 32bit BUg fix for DDR2 on 8572
This errata fix is required for 32 bit DDR2 controller on 8572.
May  also be required for P10XX20XX platforms

Signed-off-by: Poonam_Agarwal-b10812 <b10812@lc1106.zin33.ap.freescale.net>
2009-02-16 18:06:03 -06:00
Peter Tyser
a1c8a71926 86xx: Update CPU info output on bootup
- Update style of 86xx CPU information on boot to more closely
  match 85xx boards
- Fix detection of 8641/8641D
- Use strmhz() to display frequencies
- Display L1 information
- Display L2 cache size
- Fixed CPU/SVR version output

== Before ==
Freescale PowerPC
CPU:
    Core: E600 Core 0, Version: 0.2, (0x80040202)
    System: Unknown, Version: 2.1, (0x80900121)
    Clocks: CPU:1066 MHz, MPX: 533 MHz, DDR: 266 MHz, LBC: 133 MHz
    L2: Enabled
Board: X-ES XPedite5170 3U VPX SBC

== After ==
CPU:   8641D, Version: 2.1, (0x80900121)
Core:  E600 Core 0, Version: 2.2, (0x80040202)
Clock Configuration:
       CPU:1066.667 MHz, MPX:533.333 MHz
       DDR:266.667 MHz (533.333 MT/s data rate), LBC:133.333 MHz
L1:    D-cache 32 KB enabled
       I-cache 32 KB enabled
L2:    512 KB enabled
Board: X-ES XPedite5170 3U VPX SBC

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-02-16 18:05:57 -06:00
Peter Tyser
4ef630df77 86xx: Reset update
Update the 86xx reset sequence to try executing a board-specific reset
function.  If the board-specific reset is not implemented or does not
succeed, then assert #HRESET_REQ.  Using #HRESET_REQ is a more standard
reset procedure than the previous method and allows all board
peripherals to be reset if needed.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-02-16 18:05:56 -06:00
Kumar Gala
edf0e2524a fsl-ddr: Allow system to boot if we have more than 4G of memory
Previously if we >=4G of memory and !CONFIG_PHYS_64BIT we'd report
an error and hang.  Instead of doing that since DDR is mapped in the
lowest priority LAWs we setup the DDR controller and the max amount
of memory we report back is what we can map (CONFIG_MAX_MEM_MAPPED)

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Becky Bruce <beckyb@kernel.crashing.org>
2009-02-16 18:05:55 -06:00
Srikanth Srinivasan
8d949aff38 mpc85xx: Add support for the P2020
Added various p2020 processor specific details:
* SVR for p2020, p2020E
* immap updates for LAWs and DDR on p2020
* LAW defines related to p2020

Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-16 18:05:55 -06:00
Kumar Gala
f8523cb081 85xx: Fix how we map DDR memory
Previously we only allowed power-of-two memory sizes and didnt
handle >2G of memory.  Now we will map up to CONFIG_MAX_MEM_MAPPED
and should properly handle any size that we can make in the TLBs
we have available to us

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-16 18:05:51 -06:00
Kumar Gala
1542fbdeec fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controller
If we only have one controller we can completely ignore how
memctl_intlv_ctl is set.  Otherwise other levels of code get confused
and think we have twice as much memory.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-16 18:05:50 -06:00
Kumar Gala
b29dee3c90 85xx: Format cpu freq printing to handle 8 cores
Only print 4 cpu freq per line.  This way when we have 8 cores its a
bit more readable.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-16 18:05:50 -06:00
Carolyn Smith
7369f0e384 ppc4xx: Fix initialization of the SDRAM_CODT register
This fixes the initialization of the SDRAM_CODT register in the ppc4xx DDR2
initialization code. It also removes use of the SDRAM_CODT_FEEDBACK_RCV_SINGLE_END
and SDRAM_CODT_FEEDBACK_DRV_SINGLE_END #define's since they are reserved bits.

Signed-off-by: Carolyn Smith <carolyn.smith@tektronix.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-02-12 06:15:48 +01:00
Adam Graham
c645012aef ppc4xx: Autocalibration can set RDCC to over aggressive value.
The criteria of the AMCC SDRAM Controller DDR autocalibration
U-Boot code is to pick the largest passing write/read/compare
window that also has the smallest SDRAM_RDCC.[RDSS] Read Sample
Cycle Select value.

On some Kilauea boards the DDR autocalibration algorithm can
find a large passing write/read/compare window with a small
SDRAM_RDCC.[RDSS] aggressive value of Read Sample Cycle Select
value "T1 Sample".

This SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of
"T1 Sample" proves to be to aggressive when later on U-Boot
relocates into DDR memory and executes.

The memory traces on the Kilauea board are short so on some
Kilauea boards the SDRAM_RDCC.[RDSS] Read Sample Cycle Select
value of "T1 Sample" shows up as a potentially valid value for
the DDR autocalibratiion algorithm.

The fix is to define a weak default function which provides
the minimum SDRAM_RDCC.[RDSS] Read Sample Cycle Select value
to accept for DDR autocalibration.  The default will be the
"T2 Sample" value.  A board developer who has a well defined
board and chooses to be more aggressive can always provide
their own board specific string function with the more
aggressive "T1 Sample" value or stick with the default
minimum SDRAM_RDCC.[RDSS] value of "T2".

Also put in a autocalibration loop fix for case where current
write/read/compare passing window size is the same as a prior
window size, then in this case choose the write/read/compare
result that has the associated smallest RDCC T-Sample value.

Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-02-12 06:08:07 +01:00
Wolfgang Denk
f15c6515fc Coding style cleanup; update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-02-12 00:08:39 +01:00
Heiko Schocher
255d28e164 8xx serial, smc: Coding-Style cleanup serial SMC driver
Signed-off-by: Heiko Schocher <hs@denx.de>
2009-02-11 23:18:14 +01:00
Heiko Schocher
2b3f12c214 8xx serial, smc: add configurable SMC Rx buffer len
This patch adds the configuration option CONFIG_SYS_SMC_RXBUFLEN.
With this option it is possible to allow the receive
buffer for the SMC on 8xx to be greater then 1. In case
CONFIG_SYS_SMC_RXBUFLEN == 1 this driver works as the
old version.

When defining CONFIG_SYS_SMC_RXBUFLEN also
CONFIG_SYS_MAXIDLE must be defined to setup the maximum
idle timeout for the SMC.

Signed-off-by: Heiko Schocher <hs@denx.de>
2009-02-11 23:18:13 +01:00
ksi@koi8.net
2bc2a8f6dc Fix MPC8260 with ethernet on SCC
This fixes MPC8260 compilation with ethernet on SCC. Probably was a
typo or something...

Signed-off-by: Sergey Kubushyn <ksi@koi8.net>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-02-09 22:47:06 -08:00
Heiko Schocher
ae5d8f613c 82xx serial, smc: Coding-Style cleanup serial SMC driver
Signed-off-by: Heiko Schocher <hs@denx.de>
2009-02-10 00:55:12 +01:00
Heiko Schocher
c92fac91a0 82xx serial, smc: add configurable SMC Rx buffer len
This patch adds the configuration option CONFIG_SYS_SMC_RXBUFLEN.
With this option it is possible to allow the receive
buffer for the SMC on 82xx to be greater then 1. In case
CONFIG_SYS_SMC_RXBUFLEN == 1 this driver works as the
old version.

When defining CONFIG_SYS_SMC_RXBUFLEN also
CONFIG_SYS_MAXIDLE must be defined to setup the maximum
idle timeout for the SMC.

Signed-off-by: Heiko Schocher <hs@denx.de>
2009-02-10 00:54:42 +01:00
Kumar Gala
87c9063963 ppc: Move CONFIG_MAX_MEM_MAPPED to common config.h
Moved CONFIG_MAX_MEM_MAPPED to the asm/config.h so its kept consistent
between the two current users (lib_ppc/board.c, 44x SPD DDR2).

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Stefan Roese <sr@denx.de>
2009-02-10 00:44:13 +01:00
Becky Bruce
c9315e6b4f mpc86xx: Add support to populate addr map based on BATs
If CONFIG_ADDR_MAP is enabled, update the address map
whenever we write a bat.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
2009-02-10 00:29:49 +01:00
Kumar Gala
ff4e66e93c pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity
The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and
can be confusing when reading the code.

Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used
for system memory mapping purposes.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-07 23:50:04 +01:00
Wolfgang Denk
0cfa6a9de6 Merge branch 'master' of git://git.denx.de/u-boot-coldfire 2009-02-07 23:24:38 +01:00
Wolfgang Denk
045639397d Merge branch 'master' of git://git.denx.de/u-boot-blackfin 2009-02-07 22:53:45 +01:00
Wolfgang Denk
e70ef33b6b Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2009-02-07 22:17:19 +01:00
Wolfgang Denk
1b33a62bf9 Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxx 2009-02-07 22:08:53 +01:00
Richard Retanubun
e0db344fab Coldfire: M5271: Allow board header file to specify clock multiplier
M5271 dynamic clock multiplier. It is currently fixed at 100MHz.

Allow the board header file to set their own multiplier and divider.
Added the #define for the multiplier and divider to the cpu header file.

Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
2009-02-06 14:54:47 -07:00
Richard Retanubun
d1ef25dd81 Coldfire: M5271EVB: Remove usage of CONFIG_SYS_FECI2C
Discontinue the use of CONFIG_SYS_FECI2C (only used by M5271EVB).
Use read-modify-write to activate the FEC pins without disabling I2C.

Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
2009-02-06 14:54:47 -07:00
Richard Retanubun
4ffc39050a Coldfire: Fix half-baud UART by adding M5271 to Coldfire v2 core list
Added the CONFIG_M5271 to the list of Coldfire V2 processor. This
was causing the bus clock (not CPU clock) to be declared twice as
fast as it actually is. This causes UARTS to operate at half the
specified baudrate.

Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
2009-02-06 14:54:46 -07:00
Dirk Eibach
59d1bda7f9 ppc4xx: Make PCIE support selectable
On some platforms PCIE support is not required, but would be included
because the cpu supports it. To reduce fooprint it is now configurable
via CONFIG_PCI_DISABLE_PCIE.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-02-06 11:06:19 +01:00
Matthias Fuchs
b129eff5ed ppc4xx: Only fixup opb attached UARTs
This patch updates the fdt UART clock fixup code to
only touch CPU internal UARTs on 4xx systems.
Only these UARTs are definitely clocked by gd->uart_clk.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-02-06 10:53:15 +01:00
Mike Frysinger
f790ef6ff1 Blackfin: dynamically update UART speed when initializing
Previously, booting over the UART required the baud rate to be known ahead
of time.  Using a bit of tricky simple math, we can calculate the new board
rate based on the old divisors.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org>
2009-02-05 21:25:35 -05:00
Mike Frysinger
97f265f14f Blackfin: add support for fast SPI reads with Boot ROM
Newer Blackfin boot roms support using the fast SPI read command rather than
just the slow one.  If the functionality is available, then use it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-02-05 21:25:35 -05:00
Mike Frysinger
67619982bf Blackfin: check for reserved settings in DDR MMRs
Some bits of the DDR MMRs should not be set.  If they do, bad things may
happen (like random failures or hardware destruction).

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-02-05 21:25:35 -05:00
Mike Frysinger
622a8dc095 Blackfin: set default voltage levels for BF538/BF539 parts
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-02-05 21:25:34 -05:00
Mike Frysinger
09dc6b0bbd Blackfin: use on-chip syscontrol() rom function when available
Newer Blackfin's have an on-chip rom with a syscontrol() function that needs
to be used to properly program the memory and voltage settings as it will
include (possibly critical) factory tested bias values.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-02-05 21:25:28 -05:00
Martha Marx
abfbd0ae49 ADS5121 Add IC Ident Module (IIM) support
IIM (IC Identification Module) is the fusebox for the mpc5121.
Use #define CONFIG_IIM to turn on the clock for this module
use #define CONFIG_CMD_FUSE to add fusebox commands.
Fusebox commands include the ability to read
the status, read the register cache, override the register cache,
program the fuses and sense them.

Signed-off-by: Martha Marx <mmarx@silicontkx.com>
Signed-off-by: John Rigby <jrigby@freescale.com>
2009-02-03 15:40:20 -07:00
Mike Frysinger
fdce83c108 Blackfin: rewrite cache handling functions
Take the cache flush functions from the kernel as they use hardware loops in
order to get optimal performance.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-02-02 12:24:44 -05:00
Mike Frysinger
6957a6209b Blackfin: enable --gc-sections
Start building all Blackfin boards with -ffunction-sections/-fdata-sections
and linking with --gc-sections.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-02-02 12:24:40 -05:00
Mike Frysinger
ee1d2001ea Blackfin: dont check baud if it wont actually get used
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-02-02 12:24:31 -05:00
Wolfgang Denk
6c6e042ab3 Merge branch 'master' of git://git.denx.de/u-boot-arm 2009-02-01 21:38:07 +01:00
Wolfgang Denk
ee924e0030 Merge branch 'master' of git://git.denx.de/u-boot-net 2009-02-01 21:31:37 +01:00
Jean-Christophe PLAGNIOL-VILLARD
930590f3e4 ixp: move serial to drivers/serial
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-01-31 10:16:02 +01:00
Jean-Christophe PLAGNIOL-VILLARD
f90c8022f4 ixp: move pci init in arm/board instead of cpu
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-01-31 10:16:01 +01:00
Jean-Christophe PLAGNIOL-VILLARD
8cb79b5f27 ixp: move pci drivers to drivers/pci
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-01-31 10:16:01 +01:00
Jean-Christophe PLAGNIOL-VILLARD
012d5bab09 ixp: Move conditional compilation to Makefile
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-01-31 10:16:01 +01:00
Jean-Christophe PLAGNIOL-VILLARD
f693f501d6 ixp: add missing os define
need by arm-elf toolchains and no impact on the arm-linux one

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-01-31 10:15:58 +01:00
Jean-Christophe PLAGNIOL-VILLARD
b4e2f89dfc ixp: remove the option to include the Microcode
instead the board will have to load it from flash or ram
which will be specified by npe_ucode env var

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-01-31 09:53:39 +01:00
Jean-Christophe PLAGNIOL-VILLARD
1b017baf20 ixp/npe: Move conditional compilation to Makefile
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-01-30 09:45:23 +01:00
Wolfgang Denk
6b7243aa89 Merge branch 'master' of git://git.denx.de/u-boot-usb 2009-01-28 21:09:46 +01:00
Mike Frysinger
c7d703f3f3 usb.h: use standard __LITTLE_ENDIAN from Linux headers
Rather than forcing people to define a custom "LITTLEENDIAN", just use the
__LITTLE_ENDIAN one from the Linux byteorder headers that every arch is
already setting up.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
2009-01-28 19:57:29 +01:00
Mike Frysinger
fe033ad6d0 Blackfin: fixup misc warnings such as printf's and missing casts
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-28 13:27:28 -05:00
Mike Frysinger
7633903bff Blackfin: allow serial console to be disabled
Some devices have no UART device pulled out, so allow people to disable the
driver completely in favor of other methods (like JTAG-console).

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-28 13:26:15 -05:00
Mike Frysinger
36ea8e9ad1 Blackfin: support console-over-JTAG
The Blackfin JTAG has the ability to pass data via a back-channel without
halting the processor.  Utilize that channel to emulate a console.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-28 13:26:15 -05:00
Mike Frysinger
cf8f2efb5f Blackfin: handle new anomalies with reset
Workaround fun new anomalies related to software reset of the processor.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-28 13:26:15 -05:00
Mike Frysinger
b1e9435b64 Blackfin: pass RETX to Linux
Make sure we save the value of RETX at power on and then pass it on to the
kernel so that it can nicely debug a "double-fault-caused-a-reset" crash.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-28 13:26:15 -05:00
Mike Frysinger
b5eba3fafc Blackfin: clarify relocation comment during init
People often ask questions about the init process and when things go
from flash to relocated base, so clarify the comments a bit.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-28 13:26:14 -05:00
Mike Frysinger
95433f6d43 Blackfin: just set SP register directly during init
No need to set the SP register indirectly to the configured value when it
can be set directly.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-28 13:26:14 -05:00
Mike Frysinger
51230e6e35 Blackfin: add portmuxing for UARTs on the BF51x
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-28 13:26:14 -05:00
Mike Frysinger
4f6a313240 Blackfin: respect CONFIG_CLKIN_HALF
As pointed out by Ivan Koryakovskiy, the initialization code was not
actually respecting the CONFIG_CLKIN_HALF option when configuring the
PLL_CTL register.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-28 13:26:14 -05:00
Mike Frysinger
dc2bfb0b58 Blackfin: use common memcpy routine during init
Rather than using a local custom memcpy function, just call the existing
optimized Blackfin version.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-28 13:26:14 -05:00
Mike Frysinger
be853bf86b Blackfin: overhaul i2c driver
The current Blackfin i2c driver does not work properly with certain devices
due to it breaking up transfers incorrectly.  This is a rewrite of the
driver and relocates it to the newer place in the source tree.

Also remove duplicated I2C speed defines in Blackfin board configs and
disable I2C slave address usage since it isn't implemented.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-28 13:26:13 -05:00
Mike Frysinger
05b75e4883 Blackfin: fix dcache handling when doing dma memcpy's
Our dcache invalidate function doesn't just invalidate, it also flushes.
So rename the function accordingly and fix the dma_memcpy() function so it
doesn't inadvertently corrupt the data destination.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-28 13:26:12 -05:00
Mike Frysinger
0332e4df71 Blackfin: minimize time cache is turned off when replacing cplb entries
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-28 13:26:10 -05:00
Peter Tyser
2fb2604d5c Command usage cleanup
Remove command name from all command "usage" fields and update
common/command.c to display "name - usage" instead of
just "usage". Also remove newlines from command usage fields.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-01-28 08:49:52 +01:00
Peter Tyser
62c3ae7c6e Standardize command usage messages with cmd_usage()
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-01-28 08:43:45 +01:00
Wolfgang Denk
49ad480171 Merge branch 'master' of git://git.denx.de/u-boot-mips 2009-01-27 20:55:57 +01:00
Stefan Roese
03d3bfb008 MIPS: Add flush_dcache_range() and invalidate_dcache_range()
This patch adds flush_/invalidate_dcache_range() to the MIPS architecture.
Those functions are needed for the upcoming dcache support for the USB
EHCI driver. I chose this API because those cache handling functions are
already present in the PPC architecture.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2009-01-27 23:06:58 +09:00
Dirk Eibach
3943d2ff6c ppc4xx: Improve DDR autodetect
Added support for a second memory bank to DDR autodetection for 440
platforms.
Made hardcoded values configurable.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-01-26 10:13:11 +01:00
Gary Jennejohn
ba705b5b1a mgcoge make ether_scc.c work with CONFIG_NET_MULTI
This change is needed for mgcoge because it uses two ethernet drivers.

Add a check for the presence of the PIGGY board on mgcoge.  Without this
board networking cannot work and the initialization must be aborted.

Only allocate rtx once to prevent DPRAM exhaustion.

Initialize ether_scc.c and the keymile-specific HDLC driver (to be added
soon) in eth.c.

Signed-off-by: Gary Jennejohn <garyj@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-01-24 20:45:52 -08:00
Nobuhiro Iwamatsu
bd3980cc09 sh: sh_eth: Change new network API
sh_eth used old network API. This patch changed new API.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-01-24 20:45:51 -08:00
Alessandro Rubini
d5254f149d Initial support for Nomadik 8815 development board
The NMDK8815 board is distributed by ST Microelectornics.
Other (proprietary) code must be run to unlock the CPU before
U-Boot runs. doc/README.nmdk8815 outlines the boot sequence.

This is the initial port, with basic infrastructure and
a working serial port.

Signed-off-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Andrea Gallo <andrea.gallo@stnwireless.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-01-24 18:10:37 +01:00
Dirk Behme
91eee54673 OMAP3: Add common board, interrupt and system info
Add common board, interrupt and system info code.

Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
2009-01-24 17:51:21 +01:00
Dirk Behme
5ed3e8659e OMAP3: Add common clock, memory and low level code
Add common clock, memory and low level code

Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
2009-01-24 17:51:21 +01:00
Dirk Behme
0b02b18400 OMAP3: Add common cpu and start code
Add common cpu and start code.

Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
2009-01-24 17:51:21 +01:00
Wolfgang Denk
8f86a3636e Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2009-01-24 02:17:02 +01:00
Wolfgang Denk
1ea0823786 Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2009-01-24 02:08:31 +01:00
Graeme Russ
2b5360eb2b Remove #ifdef CONFIG_SC520 in source code
CONFIG_SC520 is now used for conditional compile

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-01-24 01:14:31 +01:00
Graeme Russ
ead056bc20 Added MMCR reset functionality
Reset function specific to AMD SC520 microcontroller - Is more of a
'hard reset' that the triple fault.

Requires CONFIG_SYS_RESET_SC520 to be defined in config

I would have liked to add this to a new file (cpu/i386/sc520/reset.c)
but ld requires that a object file in a library arhive MUST contain
at least one function which does not override a weak function (and is
called from outside the object file) in order for that object file to
be extracted from the archive. This would be the only function on the
new file, and hence, will never get linked in.

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-01-24 01:13:25 +01:00
Graeme Russ
3f5f18d12d Moved generic (triple fault) reset code
Moved from interrupts.c to cpu.c and made into a weak function to
allow vendor specific override

Vendor specific CPU reset (like the AMD SC520 MMCR reset) can now be
added to the vendor specific code without the need to remember to
#undef usage of the generic method and if you forget to include your
custom reset method, you will always get the default.

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-01-24 01:12:20 +01:00
Graeme Russ
9933d60902 Moved definition of set_vector() to new header file
This allows for future tidy ups and functionality that will require
set_vector ()

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-01-24 01:11:32 +01:00
Graeme Russ
85ffbbd519 Renamed cpu/i386/reset.S to resetvec.S
Brings i386 in line with other CPUs with a reset vector and frees up reset.c
for CPU reset functions

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-01-24 01:06:25 +01:00
Kim Phillips
833d94bcdc Merge branch 'next' 2009-01-23 17:48:24 -06:00
Haiying Wang
2fc7eb0cfc Add secondary CPUs processor frequency for e500 core
This patch updates e500 freqProcessor to array based on CONFIG_NUM_CPUS,
and prints each CPU's frequency separately. It also fixes up each CPU's
frequency in "clock-frequency" of fdt blob.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2009-01-23 17:03:14 -06:00
Dave Liu
b4983e16d1 fsl-ddr: use the 1T timing as default configuration
For light loaded system, we use the 1T timing to gain better
memory performance, but for some heavily loaded system,
you have to add the 2T timing options to board files.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23 17:03:14 -06:00
Dave Liu
22cca7e1cd fsl-ddr: make the self refresh idle threshold configurable
Some 85xx processors have the advanced power management feature,
such as wake up ARP, that needs enable the automatic self refresh.

If the DDR controller pass the SR_IT (self refresh idle threshold)
idle cycles, it will automatically enter self refresh. However,
anytime one transaction is issued to the DDR controller, it will
reset the counter and exit self refresh state.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23 17:03:14 -06:00
Dave Liu
22ff3d0134 fsl-ddr: clean up the ddr code for DDR3 controller
- The DDR3 controller is expanding the bits for timing config
- Add the DDR3 32-bit bus mode support

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23 17:03:13 -06:00
Dave Liu
80ee3ce6d7 fsl-ddr: update the bit mask for DDR3 controller
According to the latest 8572 UM, the DDR3 controller
is expanding the bit mask, and we use the extend ACTTOPRE
mode when tRAS more than 19 MCLK.

Signed-off-by: Dave Liu <daveliu@freescale.com>
2009-01-23 17:03:13 -06:00
Kumar Gala
5f91ef6acd 85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boards
Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead
of _IO_BASE so we are more explicit.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-23 17:03:13 -06:00
Kumar Gala
10795f42cb 85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boards
Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead
of _MEM_BASE so we are more explicit.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23 17:03:13 -06:00
Michal Simek
e7f325be9e microblaze: Use cache functions (especially cache status)
in systems which are configured without flash
2009-01-23 10:40:00 +01:00
Scott Wood
6677876181 83xx: Use the proper sequence for updating IMMR.
This ensures that subsequent accesses properly hit the new window.

The dcbi during the NAND loop was accidentally working around this;
it's no longer necessary, as the cache is not enabled.

Reported-by: Suchit Lepcha <Suchit.Lepcha@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-01-21 18:43:57 -06:00
Anton Vorontsov
fd6646c0b9 mpc83xx: Add support for MPC83xx PCI-E controllers
This patch adds support for MPC83xx PCI-E controllers in Root Complex
mode.

The patch is based on Tony Li and Dave Liu work[1].

Though unlike the original patch, by default we don't register PCI-E
buses for use in U-Boot, we only configure the controllers for future
use in other OSes (Linux). This is done because we don't have enough
of spare BATs to map all the PCI-E regions.

To actually use PCI-E in U-Boot, users should explicitly define
CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And
only then U-Boot will able to access PCI-E, but at the cost of disabled
address translation.

[1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html

Signed-off-by: Tony Li <tony.li@freescale.com>
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-01-21 18:43:49 -06:00
Ira Snyder
75f35209f7 83xx: PCI agent mode fixes for multi-board systems
When running a system with 2 or more MPC8349EMDS boards in PCI agent mode,
the boards will lock up the PCI bus by scanning against each other.

The boards lock against each other by trying to access the PCI bus before
clearing their configuration lock bit. Both boards end up in a loop,
sending and receiving "Target Not Ready" messages forever.

When running in PCI agent mode, the scanning now takes place after the
boards have cleared their configuration lock bit.

Also, add a missing declaration to the mpc83xx.h header file, fixing a
build warning.

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-01-21 18:43:49 -06:00
Ron Madrid
455a46915b mpc83xx: Size optimization of start.S
Currently there are in excess of 100 bytes located at the beginning of the image
built by start.S that are not being utilized.  This patch moves a few functions
into this part of the image.  This will create a greater number of *available*
bytes that can be used by board specific code in NAND builds and will decrease
the size of the assembled code in other builds.

Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-01-21 18:43:49 -06:00
Kieran Bingham
a5b04d00bf sh: Fix up rsk7203 target for out of tree build
Fix up rsk7203 target to build successfully using out-of-tree build.

Signed-off-by: Kieran Bingham <kbingham@mpc-data.co.uk>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2009-01-16 10:22:27 +09:00
Wolfgang Denk
e92c9a860e cpu/mpc824x/Makefile: fix warning with parallel builds
Parallel builds would occasionally issue this build warning:

    ln: creating symbolic link `cpu/mpc824x/bedbug_603e.c': File exists

Use "ln -sf" as quick work around for the issue.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-01-14 22:35:30 +01:00
Wolfgang Denk
5f01ea63a6 Merge branch 'master' of /home/wd/git/u-boot/custodians 2009-01-14 00:27:06 +01:00
Haiying Wang
950264317e Change DDR tlb start entry to CONFIG param for 85xx
So that we can locate the DDR tlb start entry to the value other than 8. By
default, it is still 8.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2009-01-13 16:47:07 -06:00
Wolfgang Denk
a9f3acbcd0 MPC86xx: fix build warnings
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-01-12 14:50:35 +01:00
Jean-Christophe PLAGNIOL-VILLARD
3dd9395a0d at91rm9200: move define from lowlevel_init to header
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-01-06 21:41:59 +01:00
Jean-Christophe PLAGNIOL-VILLARD
d481c80d78 at91rm9200: rename lowlevel init value to CONFIG_SYS_
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-01-06 21:37:39 +01:00
Trent Piepho
ada591d2a0 mpc8[56]xx: Put localbus clock in sysinfo and gd
Currently MPC85xx and MPC86xx boards just calculate the localbus frequency
and print it out, but don't save it.

This changes where its calculated and stored to be more consistent with the
CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock.

The localbus frequency is added to sysinfo and calculated when sysinfo is
set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are.

get_clocks() copies the frequency into the global data, as the other
frequencies are, into a new field that is only enabled for MPC85xx and
MPC86xx.

checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency
from sysinfo, like the other frequencies, instead of calculating it on the
spot.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-19 18:32:49 -06:00
Trent Piepho
9863d6aca1 mpc86xx: Double local bus clock divider
The local bus clock divider should be doubled for both 8610 and 8641.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-19 18:32:48 -06:00
Trent Piepho
446c381e3e mpc8568: Double local bus clock divider
The clock divider for the MPC8568 local bus should be doubled, like the
other newer MPC85xx chips.

Since there are now more chips with a 2x divider than a 1x, and any new
85xx chips will probably be 2x, invert the sense of the #if so that it
lists the 1x chips instead of the 2x ones.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-19 18:32:48 -06:00
Dave Liu
f51f07eb58 85xx: Fix the boot window issue
If one custom board is using the 8MB flash, it is set
as FLASH_BASE = 0xef000000, TEXT_BASE = 0xef780000.
The current start.S code will be broken at switch_as.

It is because the TLB1[15] is set as 16MB page size,
EPN = TEXT_BASE & 0xff000000, RPN = 0xff000000.

For the 8MB flash case, the EPN = 0xefxxxxxx,
RPN = 0xffxxxxxx. Assume the virt address of switch_as
is 0xef7ff18c, the real address of the instruction at
switch_as should be 0xff7ff18c. the 0xff7ff18c is out
of the range of the default 8MB boot LAW window
0xff800000 - 0xffffffff.

So when we switch to AS1 address space at switch_as,
the core can't fetch the instruction at switch_as any
more. It will cause broken issue.

Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-12-19 18:32:48 -06:00
Haiying Wang
181a365011 Set IVPR to kenrel entry point in second core boot page
Assuming the OSes exception vectors start from the base of kernel address, and
the kernel physical starting address can be relocated to an non-zero address.
This patch enables the second core to have a valid IVPR for debugger before
kernel setting IVPR in CAMP mode. Otherwise, IVPR is 0x0 and it is not a valid
value for second core which runs kernel at different physical address other
than 0x0.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2008-12-19 18:32:41 -06:00
Trent Piepho
a5d212a263 mpc8xxx: LCRR[CLKDIV] is sometimes five bits
On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.

In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems.  It
should be safe as the fifth bit was defined as reserved and set to 0.

Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-19 18:20:25 -06:00
Trent Piepho
58ec4866ed mpc8[56]xx: Put localbus clock in device tree
Export the localbus frequency in the device tree, the same way the CPU, TB,
CCB, and various other frequencies are exported in their respective device
tree nodes.

Some localbus devices need this information to be programed correctly, so
it makes sense to export it along with the other frequencies.

Unfortunately, when someone wrote the localbus dts bindings, they didn't
bother to define what the "compatible" property should be.  So it seems no
one was quite sure what to put in their dts files.

Based on current existing dts files in the kernel source, I've used
"fsl,pq3-localbus" and "fsl,elbc" for MPC85xx, which are used by almost all
of the 85xx devices, and are looked for by the Linux code.  The eLBC is
apparently not entirely backward compatible with the pq3 LBC and so eLBC
equipped platforms like 8572 won't use pq3-localbus.

For MPC86xx, I've used "fsl,elbc" which is used by some of the 86xx systems
and is also looked for by the Linux code.  On MPC8641, I've also used
"fsl,mpc8641-localbus" as it is also commonly used in dts files, some of
which don't use "fsl,elbc" or any other acceptable name to match on.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-19 18:20:20 -06:00
Kumar Gala
ecf5b98c7a 85xx: Add support to populate addr map based on TLB settings
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-19 18:20:08 -06:00
Haavard Skinnemoen
cb54732052 Merge branch 'fixes' into cleanups
Conflicts:

	board/atmel/atngw100/atngw100.c
	board/atmel/atstk1000/atstk1000.c
	cpu/at32ap/at32ap700x/gpio.c
	include/asm-avr32/arch-at32ap700x/clk.h
	include/configs/atngw100.h
	include/configs/atstk1002.h
	include/configs/atstk1003.h
	include/configs/atstk1004.h
	include/configs/atstk1006.h
	include/configs/favr-32-ezkit.h
	include/configs/hammerhead.h
	include/configs/mimc200.h
2008-12-17 16:53:07 +01:00
Wolfgang Denk
455ae7e87f Coding style cleanup, update CHANGELOG.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-12-16 01:02:17 +01:00
Timur Tabi
ecf5f077c8 i2c: merge all i2c_reg_read() and i2c_reg_write() into inline functions
All implementations of the functions i2c_reg_read() and
i2c_reg_write() are identical. We can save space and simplify the
code by converting these functions into inlines and putting them in
i2c.h.

Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-By: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-12-15 23:46:21 +01:00
Jean-Christophe PLAGNIOL-VILLARD
3aed3aa2c1 Fix new found CFG_
Also fix some minor typos.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-12-14 10:55:30 +01:00
Sergei Poselenov
0e0c862efe Remove compiler warning: target CPU does not support interworking
This warning is issued by modern ARM-EABI GCC on non-thumb targets.

Signed-off-by: Vladimir Panfilov <pvr@emcraft.com>
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
2008-12-13 23:41:23 +01:00
Wolfgang Denk
3680aed04f Merge branch 'master' of git://git.denx.de/u-boot-mips 2008-12-13 00:34:12 +01:00
Stefan Roese
71fa0714fe MIPS: Flush data cache upon relocation
This patch now adds a flush to the data cache upon relocation. The
current implementation is missing this. Only a comment states that it
should be done. So let's really do it now.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-12-10 23:29:12 +09:00
Stefan Roese
4417434368 MIPS: Add CONFIG_SKIP_LOWLEVEL_INIT
This patch adds the CONFIG_SKIP_LOWLEVEL_INIT option to start.S. This
enables support for boards where the lowlevel initialization is
already done when U-Boot runs (e.g. via OnChip ROM).

This will be used in the upcoming VCTH board support.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-12-10 23:29:09 +09:00
Nobuhiro Iwamatsu
e9d5f35497 sh: Update sh timer function
Change to write/readX function and fix timer problem.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-12-10 23:11:35 +09:00
Ben Warren
2145188bea Fix compile error in building MBX860T.
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-12-10 09:26:42 +01:00
Graeme Russ
1f5070c0c1 Fixed path to sc520 SSI include file
Signed Off By: Graeme Russ <graeme.russ@gmail.com>
2008-12-10 00:34:09 +01:00
Anatolij Gustschin
ee2e9ba917 video: fix FADS823 and RRvision compiling issues
Since commit 561858ee building for FADS823 and RRvision
doesn't work. Let's include version.h and timestamp.h
unconditionally to fix the problem.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2008-12-09 17:52:05 +01:00
Wolfgang Denk
13d36ec849 Merge branch 'master' of git://git.denx.de/u-boot-at91 2008-12-09 01:06:14 +01:00
Trent Piepho
5e3ab68e9a Section name should be ".data", not "data"
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-12-09 00:48:41 +01:00
Peter Tyser
561858ee7d Update U-Boot's build timestamp on every compile
Use the GNU 'date' command to auto-generate a new U-Boot
timestamp on every compile.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2008-12-06 23:36:43 +01:00
Remy Bohmer
83ad179e2f Remove redundant armv4 flag from arm926ejs compile flags
Currently the arm926ejs tree has the armv4 option set during compilation.
This flag does not belong here because a arm926 CPU is always a armv5 CPU.

Signed-off-by: Remy Bohmer <linux@bohmer.net>
2008-12-06 20:34:12 +01:00
Wolfgang Denk
90665e3d97 Merge branch 'master' of git://git.denx.de/u-boot-at91 2008-12-05 00:27:19 +01:00
Kumar Gala
9df59533f7 85xx: init gd as early as possible
Moved up the initialization of GD so C code like set_tlb() can use
gd->flags to determine if we've relocated or not in the future.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
2008-12-04 03:15:43 -06:00
Kumar Gala
aed461af81 85xx: Fix relocation of CCSRBAR
If the virtual address for CCSRBAR is the same after relocation but
the physical address is changing we'd end up having two TLB entries with
the same VA.  Instead we new us the new CCSRBAR virt address + 4k as a
temp virt address to access the old CCSRBAR to relocate it.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
2008-12-04 03:15:43 -06:00
Peter Tyser
9427ccde03 85xx: Add PORDEVSR_PCI1 define
Add define used to determine if PCI1 interface is in PCI or PCIX mode.

Convert users of the old PORDEVSR_PCI constant to use MPC85xx_PORDEVSR_PCI1

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-12-04 03:15:43 -06:00
Ed Swarthout
7008d26a40 fsl ddr skip interleaving if not supported.
Removed while(1) hang if memctl_intlv_ctl is set wrong.
Remove embedded tabs from strings.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
2008-12-03 22:47:19 -06:00
Peter Tyser
a2cd50ed6e 85xx: Add CPU 2 errata workaround to all 8548 boards
All mpc8548-based boards should implement the suggested workaround
to CPU 2 errata. Without the workaround, its possible for the
8548's core to hang while executing a msync or mbar 0 instruction
and a snoopable transaction from an I/O master tagged to make
quick forward progress is present.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2008-12-03 22:46:42 -06:00
Jean-Christophe PLAGNIOL-VILLARD
ed3b18e05c AT91: remove non supported board AT91RM9200DF macro
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-12-02 21:59:29 +01:00
Wolfgang Denk
06efc122a0 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2008-11-25 11:47:41 +01:00
Wolfgang Denk
58c696eed8 AT91RM9200DK: fix broken boot from NOR flash
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-11-24 22:10:07 +01:00
Jens Scharsig
8052352f20 at91rm9200: fix broken boot from nor flash
This patch fix the broken boot from NOR Flash on AT91RM9200 boards, if
CONFIG_AT91RM9200 is defined and nor preloader is used.

Signed-off-by: Jens Scharsig <esw@bus-elektronik.de>
2008-11-24 22:10:04 +01:00
Dave Mitchell
ddf45cc758 ppc4xx: Changed 460EX/GT OCM TLB and internal SRAM initialization
Expanded OCM TLB to allow access to 64K OCM as well as 256K of
internal SRAM.

Adjusted internal SRAM initialization to match updated user
manual recommendation.

OCM & ISRAM are now mapped as follows:
        physical        virtual         size
ISRAM   0x4_0000_0000   0xE300_0000     256k
OCM     0x4_0004_0000   0xE304_0000     64k

A single TLB was used for this mapping.

Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-11-21 11:02:04 +01:00
Dave Mitchell
b14ca4b61a ppc4xx: Added ppc4xx-isram.h for internal SRAM and L2 cache DCRs
Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and
L2 cache DCRs from ppc440.h to this new header.

Also converted these DCR defines from lowercase to uppercase and
modified referencing modules to use them.

Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-11-21 10:52:33 +01:00
Stelian Pop
3e0cda071a AT91: Enable PLLB for USB
At least some (old ?) versions of the AT91Bootstrap do not set up the
PLLB correctly to 48 MHz in order to make USB host function correctly.

This patch sets up the PLLB to the same values Linux uses, and makes USB
work ok on the following CPUs:
	- AT91CAP9
	- AT91SAM9260
	- AT91SAM9263

This patch also defines CONFIG_USB_STORAGE and CONFIG_CMD_FAT for all
the relevant AT91CAP9/AT91SAM9 atmel boards.

Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-11-21 01:41:14 +01:00
Stefan Roese
25fb4eaaea ppc4xx: Clear all potentially pending exceptions in MCSR
This is needed on Canyonlands which still has an exception pending
while running relocate_code(). This leads to a failure after trap_init()
is moved to the top of board_init_r().

Signed-off-by: Stefan Roese <sr@denx.de>
2008-11-20 11:48:53 +01:00
Selvamuthukumar
9b827cf172 Align end of bss by 4 bytes
Most of the bss initialization loop increments 4 bytes
at a time. And the loop end is checked for an 'equal'
condition. Make the bss end address aligned by 4, so
that the loop will end as expected.

Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-11-18 23:13:16 +01:00
Wolfgang Denk
e0b0ec8430 Merge branch 'master' of git://git.denx.de/u-boot-mpc86xx 2008-11-18 21:40:38 +01:00
Becky Bruce
3111d32c49 mpc8641: Support 36-bit physical addressing
This patch creates a memory map with all the devices
in 36-bit physical space, in addition to the 32-bit map.
The CCSR relocation is moved (again, sorry) to
allow for the physical address to be 36 bits - this
requires translation to be enabled.  With 36-bit physical
addressing enabled, we are no longer running with VA=PA
translations.  This means we have to distinguish between
the two in the config file.  The existing region name is
used to indicate the virtual address, and a _PHYS variety
is created to represent the physical address.

Large physical addressing is not enabled by default.
Set CONFIG_PHYS_64BIT in the config file to turn this on.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-11-10 10:10:05 -06:00
Becky Bruce
c759a01a00 mpc8641: Change 32-bit memory map
The memory map on the 8641hpcn is modified to look more like
the 85xx boards; this is a step towards a more standardized
layout going forward. As part of this change, we now relocate
the flash.

The regions for some of the mappings were far larger than they
needed to be.  I have reduced the mappings to match the
actual sizes supported by the hardware.

In addition I have removed the comments at the head
of the BAT blocks in the config file, rather than updating
them.  These get horribly out of date, and it's a simple
matter to look at the defines to see what they are set to
since everything is right here in the same file.

Documentation has been changed to reflect the new map, as this
change is user visible, and affects the OS which runs post-uboot.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-11-10 10:10:04 -06:00
Becky Bruce
bf9a8c3430 mpc86xx: Change early FLASH mapping to 1M at CONFIG_MONITOR_BASE_EARLY
We define CONFIG_MONITOR_BASE_EARLY to define the initial location
of the bootpage in flash.   Use this to create an early mapping
definition for the FLASH, and change the early_bats code to use this.

This  change facilitates the relocation of the flash since the early
mappings are no longer tied to the final location of the flash.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-11-10 10:10:04 -06:00
Becky Bruce
c1e1cf6954 mpc86xx: Use SRR0/1/rfi to enable address translation, not blr
Using a mtmsr/blr means that you have to be executing at the
same virtual address once you enable translation.  This is
unnecessarily restrictive, and is not really how this is
usually done.  Change it to use the more common mtspr SRR0/SRR1
and rfi method.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-11-10 10:10:03 -06:00
Becky Bruce
24bfb48c35 mpc86xx: Move setup_bats into cpu_init_f
In order to later allow for a physical relocation of the
flash, setup_bats, which sets up the final BAT mapping
for the board, needs to happen *after* init_laws().
Otherwise, there will be no window programmed for the flash
at the new physical location at the point when we change
the mmu translation.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-11-10 10:10:02 -06:00
Jon Loeliger
33211469f7 Merge commit 'wd/master' 2008-11-10 10:04:51 -06:00
Ben Warren
25a859066b Moved initialization of PPC4xx EMAC to cpu_eth_init()
Removed initialization of the driver from net/eth.c

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
2008-11-09 21:38:05 -08:00
Ben Warren
4d03a4e20e Moved PPC4xx EMAC driver to drivers/net
Also changed path in all linker scripts that reference this driver

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
2008-11-09 21:38:04 -08:00
Ben Warren
96e21f86e8 Changed PPC4xx EMAC driver to require CONFIG_PPC4xx_EMAC
All in-tree IBM/AMCC PPC4xx boards using the EMAC get this new CONFIG

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
2008-11-09 21:38:04 -08:00
Ben Warren
9eb79bd885 Moved initialization of MPC8XX SCC to cpu_eth_init()
Removed initialization of the driver from net/eth.c

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-11-09 21:38:03 -08:00
Ben Warren
a9bec96d63 Moved initialization of MPC8220 FEC to cpu_eth_init()
Removed initialization of the driver from net/eth.c

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-11-09 21:38:03 -08:00
Ben Warren
0e8454e990 Moved initialization of QE Ethernet controller to cpu_eth_init()
Removed initialization of the driver from net/eth.c

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-11-09 21:38:03 -08:00
Ben Warren
3456a14827 Moved initialization of FCC Ethernet controller to cpu_eth_init
Affected boards:
    Several MPC8xx boards
    Several MPC8260/MPC8272 boards
    Several MPC85xx boards

Removed initialization of the driver from net/eth.c

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-11-09 21:38:02 -08:00
Ben Warren
62e15b497f Fix typo in cpu/mpc85xx/cpu.c
CONFIG_MPC85xx_FEC -> CONFIG_MPC85XX_FEC

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-11-09 21:38:02 -08:00
Shinya Kuribayashi
5dfb3ee3f5 net: Move initialization of Au1x00 SoC ethernet MAC to cpu_eth_init
This patch will move au1x00_eth_initialize from net/eth.c to cpu_eth_init
as a part of ongoing eth_initialize cleanup work.  The function ret value
is also fixed as it should be negative on fail.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-11-09 21:38:02 -08:00
Ben Warren
cc94074eca Moved initialization of IXP4XX_NPE Ethernet controller to cpu_eth_init()
Also, removed the driver initialization from net/eth.c

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-11-09 21:38:02 -08:00
Wolfgang Denk
2e4dcb64d1 Merge branch 'master' of git://git.denx.de/u-boot-arm 2008-11-09 00:33:10 +01:00
Wolfgang Denk
c06d9bbbeb Merge branch 'master' of git://git.denx.de/u-boot-coldfire 2008-11-09 00:01:42 +01:00
Tomohiro Masubuchi
26eecd24f9 Change to use "do_div" macro
Signed-off-by: Tomohiro Masubuchi <tomohiro_masubuchi@tripeaks.co.jp>
2008-11-04 23:40:05 +01:00
Roman Mashak
e352495318 ARM926EJ-S: relocate OMAP specific 'cpuinfo.c' into OMAP directory
OMAP identification is implemented in 'cpuinfo.c' and located in ARM926EJ-S directory.
It makes sense to place this file in OMAP specific subdirectory, i.e. cpu/arm926ejs/omap

Signed-off-by: Roman Mashak <romez777@gmail.com>
2008-11-04 23:40:05 +01:00
Becky Bruce
1266df8877 powerpc: change 86xx SMP boot method
We put the bootpg for the secondary cpus into memory and use
BPTR to get to it.  This is a step towards converting to the
ePAPR boot methodology.  Also, the code is written to
deal properly with more than 4GB of RAM.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-11-04 10:58:50 -06:00
Becky Bruce
104992fc54 powerpc 86xx: Handle CCSR relocation earlier
Currently, the CCSR gets relocated while translation is
enabled, meaning we need 2 BAT translations to get to both the
old location and the new location.  Also, the DEFAULT
CCSR location has a dependency on the BAT that maps the
FLASH region.  Moving the relocation removes this unnecessary
dependency. This makes it easier and more intutive to
modify the board's memory map.

Swap BATs 3 and 4 on 8610 so that all 86xx boards use the same
BAT for CCSR space.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-11-03 11:05:00 -06:00
TsiChung Liew
1b27084422 ColdFire: Fix compilation error
The error was caused by the change for strmhz() in cpu.c.
A few of them were one extra close parenthesis.

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
2008-11-03 09:45:58 -07:00
TsiChung Liew
536e7dac16 ColdFire: Add MCF5301x CPU and M53017EVB support
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
2008-11-03 09:45:58 -07:00
TsiChung Liew
a21d0c2cc9 ColdFire: Add SBF support for M52277EVB
Add serial boot support

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
2008-11-03 09:45:58 -07:00
TsiChung Liew
f3962d3f57 ColdFire: Relocate FEC's GPIO and mii functions protocols
Place FEC pin assignments in cpu_init.c from platform's
mii.c

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
2008-11-03 09:45:58 -07:00
TsiChung Liew
012522fef3 ColdFire: Modules header files cleanup
Consolidate ATA, ePORT, QSPI, FlexCan, PWM, RNG,
MDHA, SKHA, INTC, and FlexBus structures and
definitions in immap_5xxx.h to more unify modules
header files. Append DSPI support for m547x_8x.
SSI cleanup. Remove USB Host structure from immap_539.h.
Apply changes to use FlexBus structures in mcf52x2's
cpu_init.c and platform configuration files.

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
2008-11-03 09:45:58 -07:00
Andy Fleming
20d04774f4 Consolidate MAX/MIN definitions
There were several, now there is one (two if you count the lower-case
versions).

Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-11-02 16:23:46 +01:00
Wolfgang Denk
4cc64742a8 Merge branch 'master' of git://git.denx.de/u-boot-blackfin 2008-11-01 15:59:35 +01:00
Dave Liu
d685b74c64 74xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cache
The patch is following the commit 3924384060

mpc86xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cache

This is needed in unlock_ram_in_cache() because it is called from C and
will corrupt the small data area anchor that is kept in R2.

lock_ram_in_cache() is modified similarly as good coding practice, but
is not called from C.

Signed-off-by: Nick Spence <nick.spence@freescale.com>

also, the r2 is used as global data pointer.

Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-10-31 00:25:08 +01:00
Wolfgang Denk
d344293a5b Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2008-10-30 21:34:40 +01:00
Scott Wood
e053ab1903 mpc83xx pci: Round up memory size in inbound window.
The current calculation will fail to cover all memory if
its size is not a power of two.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-30 15:22:22 -05:00
Wolfgang Denk
a7faab9d11 Merge branch 'master' of git://git.denx.de/u-boot-mpc86xx 2008-10-30 20:57:46 +01:00
Dave Liu
eaa44c5dc8 86xx: remove the redundant r2 global data pointer save
The commit 67256678f0 add
the another global data pointer save, but in fact the
global data pointer will be initialized in the board_init_r,
so remove it such as the 85xx/83xx family.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Kumar Gala <kumar.gala@freescale.com>
2008-10-30 10:31:42 -05:00
Dave Liu
bd888e9544 86xx: remove the unused code for 86xx family
I believe these code was copied from 74xx family, but for
86xx, it is unused.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Kumar Gala <kumar.gala@freescale.com>
2008-10-30 10:31:23 -05:00
Dave Liu
dc2adad85b 86xx: Move the clear_tlbs before MMU turn on
We must invalidate TLBs before MMU turn on, but
currently the code is not, if there are some stale
TLB entry valid in the TLBs, it will cause strange
issue.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Becky Bruce <becky.bruce@freescale.com>
2008-10-30 10:26:37 -05:00
Haiying Wang
4e190b03aa Make Freescale local bus registers available for both 83xx and 85xx.
- Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it
  can be shared by both 83xx and 85xx
- Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards
  files which use lbus83xx_t.
- Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that
  85xx can share them.

Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-10-29 11:12:53 -05:00
Graeme Russ
a369f4a492 i386: Renamed show_boot_progress in assembler code
Renamed show_boot_progress in assembler init phase to
show_boot_progress_asm to avoid link conflicts with C version

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2008-10-28 00:26:35 +01:00
Wolfgang Denk
f8030519bb Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2008-10-27 22:31:32 +01:00
Dave Liu
ae5f943ba8 85xx: Fix the incorrect register used for DDR erratum1
The 8572 DDR erratum1:
DDR controller may enter an illegal state when operating
in 32-bit bus mode with 4-beat bursts.

Description:
When operating with a 32-bit bus, it is recommended that
DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories are used.
This forces the DDR controller to use 4-beat bursts when
communicating to the DRAMs. However, an issue exists that
could lead to data corruption when the DDR controller is
in 32-bit bus mode while using 4-beat bursts.

Projected Impact:
If the DDR controller is operating in 32-bit bus mode with
4-beat bursts, then the controller may enter into a bad state.
All subsequent reads from memory is corrupted.
Four-beat bursts with a 32-bit bus only is used with DDR2 memories.
Therefore, this erratum does not affect DDR3 mode.

Work Arounds:
To work around this issue, software must set DEBUG_1[31] in
DDR memory mapped space (CCSRBAR offset + 0x2f00 for DDR_1
and CCSRBAR offset + 0x6f00 for DDR_2).

Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2
as condition, but it should be DDR_SDRAM_CFG register.

Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-10-24 17:29:37 -05:00
Kumar Gala
0f060c3bf8 85xx: Add basic e500mc core support
Introduce CONFIG_E500MC to deal with the minor differences between
e500v2 and e500mc.

* Certain fields of HID0/1 don't exist anymore on e500mc
* Cache line size is 64-bytes on e500mc
* reset value of PIR is different

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-24 15:10:47 -05:00
Kumar Gala
a38a5b6edd 85xx: Use CONFIG_SYS_CACHELINE_SIZE instead of magic number
Using CONFIG_SYS_CACHELINE_SIZE instead of 31 means we can handle
e500mc's 64-byte cacheline properly when it gets added.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-24 15:10:23 -05:00
Ricardo Ribalda Delgado
1f4d53260e ppc4xx: Generic architecture for xilinx ppc405(v3)
As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx
ppc440 boards, this patch presents a common architecture for all the
xilinx ppc405 boards.

Any custom xilinx ppc405 board can be added very easily with no code
duplicity.

This patch also adds a simple generic board, that can be used on almost
any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h

This patch is prepared to work with the latest version of EDK (10.1)

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-24 17:26:09 +02:00
Mike Frysinger
f177f4250c Blackfin: fix up UART status bit handling
Some Blackfin UARTs are read-to-clear while others are write-to-clear.
This can cause problems when we poll the LSR and then later try and handle
any errors detected.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:51 -04:00
Mike Frysinger
bd33e5c613 Blackfin: small cpu init optimization while setting interrupt mask
Use the sti instruction to set the initial interrupt mask rather than
banging on the core IMASK MMR to save both space and time.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:51 -04:00
Mike Frysinger
960922291c Blackfin: set initial stack correctly according to Blackfin ABI
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:51 -04:00
Mike Frysinger
25cd33d82e Blackfin: make baud calculation more accurate
We should use the algorithm in the Linux kernel so that the UART divisor
calculation is more accurate.  It also fixes problems on some picky UARTs
that have sampling anomalies.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:51 -04:00
Mike Frysinger
0ba1da116e Blackfin: decode hwerrcause/excause when crashing
Having to decode hwerrcause/excause values is a pain, so automate it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:50 -04:00
Mike Frysinger
2de95bb20c Blackfin: fix register dump messages
Make sure we report RETI/IPEND correctly.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:50 -04:00
Mike Frysinger
7133999e6f Blackfin: don't bother displaying reboot msg when crashing
The hang function already tells you to reboot, so no point in showing it
twice.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:50 -04:00
Mike Frysinger
70c4c032ea Blackfin: enable support for nested interrupts
During cpu init, make sure we initialize the CEC properly so that
interrupts can fire and be handled while U-Boot is running.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:50 -04:00
Mike Frysinger
2c1ea9e370 Blackfin: drop unused cache flush code
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:50 -04:00
Mike Frysinger
50f0d21191 Blackfin: unify cache handling code
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:50 -04:00
Mike Frysinger
e4337968e4 Blackfin: only enable hardware error irq by default
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:50 -04:00
Richard Retanubun
4a7f6b750d mpc83xx: Removed #ifdef CONFIG_MPC834X dependency on upmconfig function
This is done to allow other 83XX based platforms which also have UPM
(e.g. 8360) to configure and use their UPM in u-boot.

Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:41:04 -05:00
Anton Vorontsov
6f9cc6608b mpc83xx: serdes: add forgotten shifts for rfcks
The rfcks should be shifted by 28 bits left. We didn't notice the bug
because we were using only 100MHz clocks (for which rfcks == 0).

Though, for SGMII we'll need 125MHz clocks.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:34:01 -05:00
Wolfgang Denk
06c2942218 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2008-10-21 21:19:35 +02:00
Stefan Roese
43cbce69d4 ppc4xx: Correctly setup ranges property in ebc node
Previously only the NOR flash mapping was written into the ranges
property of the ebc node. This patch now writes all enabled chip
select areas into the ranges property.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:35:02 +02:00
Adam Graham
c9c11d751e ppc4xx: Add routine to retrieve CPU number
Provide a weak defined routine to retrieve the CPU number for
reference boards that have multiple CPU's.  Default behavior
is the existing single CPU print output.  Reference boards with
multiple CPU's need to provide a board specific routine.
See board/amcc/arches/arches.c for an example.

Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:34:56 +02:00
Adam Graham
59217bae40 ppc4xx: Add static support for 44x IBM SDRAM Controller
This patch add the capability to configure a PPC440 based IBM SDRAM
Controller with static, compiled-in, values. PPC440 memory subsystem
includes a Memory Queue core.

Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:34:51 +02:00
Wolfgang Denk
8ed44d91c8 Cleanup: fix "MHz" spelling
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-10-21 11:25:39 +02:00
Wolfgang Denk
08ef89ecd1 Use strmhz() to format clock frequencies
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-10-21 11:25:38 +02:00
Markus Klotzbuecher
50bd0057ba Merge git://git.denx.de/u-boot into x1
Conflicts:

	drivers/usb/usb_ohci.c
2008-10-21 09:18:01 +02:00
Wolfgang Denk
f82642e338 Merge 'next' branch
Conflicts:

	board/freescale/mpc8536ds/mpc8536ds.c
	include/configs/mgcoge.h

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-10-18 21:59:44 +02:00
Ed Swarthout
6856b3d022 85xx if NUM_CPUS>1, print cpu number
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
2008-10-18 21:54:05 +02:00
Andy Fleming
0e17f02a8a Have u-boot pass stashing parameters into device tree
Some cores don't support ethernet stashing at all, and some
instances have errata.  Adds 3 properties to gianfar nodes
which support stashing.  For now, just add this support to
85xx SoCs.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-10-18 21:54:05 +02:00
Haiying Wang
1f293b417a Add debug information for DDR controller registers
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2008-10-18 21:54:05 +02:00
Haiying Wang
c9ffd839b1 Check DDR interleaving mode
* Check DDR interleaving mode from environment by reading memctl_intlv_ctl and
ba_intlv_ctl.
* Print DDR interleaving mode information
* Add doc/README.fsl-ddr to describe the interleaving setting

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2008-10-18 21:54:05 +02:00
Haiying Wang
dfb49108e4 Pass dimm parameters to populate populate controller options
Because some dimm parameters like n_ranks needs to be used with the board
frequency to choose the board parameters like clk_adjust etc. in the
board_specific_paramesters table of the board ddr file, we need to pass
the dimm parameters to the board file.

* move ddr dimm parameters header file from /cpu to /include directory.
* add ddr dimm parameters to populate board specific options.
* Fix fsl_ddr_board_options() for all the 8xxx boards which call this function.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2008-10-18 21:54:04 +02:00
Haiying Wang
dbbbb3abef Make DDR interleaving mode work correctly
Fix some bugs:
  1. Correctly set intlv_ctl in cs_config.
  2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
  3. Set base_address and total memory for each ddr controller in memory
     controller interleaving mode.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2008-10-18 21:54:04 +02:00
Kumar Gala
54e091d3b6 85xx: Export invalidate_{i,d}cache and add flush_dcache
Added the ability for C code to invalidate the i/d-cache's and
to flush the d-cache.  This allows us to more efficient change mappings
from cache-able to cache-inhibited.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-18 21:54:04 +02:00
Jean-Christophe PLAGNIOL-VILLARD
6d0f6bcf33 rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-18 21:54:03 +02:00
Kumar Gala
71edc27181 74xx/7xx/86xx: Rename flush_data_cache to flush_dcache to match 85xx version
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-18 21:54:02 +02:00
Heiko Schocher
67b23a3228 I2C: adding new "i2c bus" Command to the I2C Subsystem.
With this Command it is possible to add new I2C Busses,
which are behind 1 .. n I2C Muxes. Details see README.

Signed-off-by: Heiko Schocher <hs@denx.de>
2008-10-18 21:54:02 +02:00
Heiko Schocher
799b784aa0 i2c: add CONFIG_I2C_MULTI_BUS for soft_i2c and mpc8260 i2c driver.
Signed-off-by: Heiko Schocher <hs@denx.de>
2008-10-18 21:54:01 +02:00
richardretanubun
c68a05feeb Adds two more ethernet interface to 83xx
Added as a convenience for other platforms that uses MPC8360 (has 8 UCC).
Six eth interface is chosen because the platform I am using combines
UCC1&2 and UCC3&4 as 1000 Eth and the other four UCCs as 10/100 Eth.

Signed-off-by: Richard Retanubun <RichardRetanubun@RugggedCom.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-10-18 21:54:00 +02:00
Lepcha Suchit
fa7b1c07e9 83xx NAND boot: wait for LTESR[CC]
At least some revisions of the 8313, and possibly other chips, do not
wait for all pages of the initial 4K NAND region to be loaded before
beginning execution; thus, we wait for it before branching out of the
first NAND page.

This fixes warm reset problems when booting from NAND on 8313erdb.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-17 10:39:18 -05:00
Yuri Tikhonov
bf29e0ea0a ppc4xx: PPC44x MQ initialization
Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC
values. This fixes the occasional 440SPe hard locking issues when the 440SPe's
dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver).

Previously the appropriate initialization had been made in Linux, by the
ppc440spe ADMA driver, which is wrong because modifying the MQ configuration
registers after normal operation has begun is not supported and could
have unpredictable results.

Comment from Stefan: This patch doesn't change the resulting value of the
MQ registers. It explicitly sets/clears all bits to the desired state which
better documents the resulting register value instead of relying on pre-set
default values.

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-17 13:02:42 +02:00
Kumar Gala
42653b826a Revert "85xx: Using proper I2C source clock divider for MPC8544"
This reverts commit dffd2446fb.

The fix introduced by this patch is not correct.  The problem is
that the documentation is not correct for the MPC8544 with regards
to which bit in PORDEVSR2 is for the SEC_CFG.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-17 10:50:41 +02:00
Selvamuthukumar
9724555755 mpc83xx: wait till UPM completes the write to array
Reference manual states that MxMR[MAD] increment is the indication
of write to UPM array is complete. Honour that. Also, make the dummy
write explicit.

also fix the comment.

Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-14 18:10:51 -05:00
Remy Bohmer
9dbc366744 The PIPE_INTERRUPT flag is used wrong
At a lot of places in the code the PIPE_INTERRUPT flags and friends
are used wrong. The wrong bits are compared to this flag resulting
in wrong conditions. Also there are macros that should be used for
PIPE_* flags.
This patch tries to fix them all, however, I was not able to test the
changes, because I do not have any of these boards.

Review required!

Signed-off-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Markus Klotzbuecher <mk@denx.de>
2008-10-14 16:43:06 +02:00
Nick Spence
3924384060 mpc86xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cache
This is needed in unlock_ram_in_cache() because it is called from C and
will corrupt the small data area anchor that is kept in R2.

lock_ram_in_cache() is modified similarly as good coding practice, but
is not called from C.

Signed-off-by: Nick Spence <nick.spence@freescale.com>
2008-10-13 13:57:14 +02:00
Kumar Gala
5c7cbcd34d 86xx: remove redudant code with lib_ppc/interrupts.c
For some reason we duplicated the majority of code in lib_ppc/interrupts.c
Not know how that happened, but there is no good reason for it.

Use the interrupt_init_cpu() and timer_interrupt_cpu() since its why
they exist.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-13 13:56:18 +02:00
Stefan Roese
1f6aa622e3 Merge branch 'master' of /home/stefan/git/u-boot/u-boot 2008-10-13 11:17:31 +02:00
Wolfgang Denk
22a871a464 Merge branch 'master' of git://git.denx.de/u-boot-arm 2008-10-12 23:55:12 +02:00
Wolfgang Denk
1f7bab0832 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2008-10-12 23:12:44 +02:00
Wolfgang Grandegger
dffd2446fb 85xx: Using proper I2C source clock divider for MPC8544
Measurements with our MPC8544 board showed that the I2C bus frequency
is wrong by a factor of 1.5. Obviously, the interpretation of the
MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not
correct. There seems to be an error in the 8544 RM.

Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
2008-10-08 14:20:27 -05:00
Guennadi Liakhovetski
1ed7a7f0f5 i.MX31: switch to CFG_HZ=1000
Switch to the standard CFG_HZ=1000 value, while at it, minor white-space
cleanup, remove CFG_CLKS_IN_HZ from config-headers. Tested on mx31ads,
provides 2% or 0.4% precision depending on the
CONFIG_MX31_TIMER_HIGH_PRECISION flag. Measured with stop-watch on 100s
boot-delay.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
2008-10-08 18:59:02 +02:00
Adam Graham
f8a00dea84 ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR change
After changing SDRAM_CLKTR phase value rerun the memory preload
initialization sequence (INITPLR) to reset and relock the memory
DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing
adjustment effects the phase relationship of the internal, to the
PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT.

Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-08 11:36:23 +02:00
Jason Jin
c0391111c3 Fix the incorrect DDR clk freq reporting on 8536DS
On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111),
The display is still sync mode DDR freq. This patch try to fix
this. The display DDR freq is now the actual freq in both
sync and async mode.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2008-10-07 15:37:08 -05:00
Kumar Gala
bac6a1d1fa 85xx: Remove setting of *cache-line-size in device trees
ePAPR says if the *cache-block-size is the same as *cache-line-size
than we don't need the *cache-line-size property.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-07 10:28:59 -05:00
Anton Vorontsov
d26154c9a6 mpc83xx: spd_sdram: fix ddr sdram base address assignment bug
The spd_dram code shifts the base address, then masks 20 bits, but
forgets to shift the base address back. Fix this by just masking the
base address correctly.

Found this bug while trying to relocate a DDR memory at the base != 0.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-09-24 09:58:33 -05:00
Wolfgang Denk
5fdc215f0b Fix DPRAM memory leak when CFG_ALLOC_DPRAM is defined, which
eventually leads to a machine check. This change assures that DPRAM
is allocated only once in that case.

Signed-off-by: Gary Jennejohn <garyj@denx.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-09-22 22:23:06 +02:00
Nobuhiro Iwamatsu
4a065abf92 sh: Add support watchdog for SH4A core
Add support watchdog for SH4A core (SH7763, SH7780 and SH7785).
And fix some compile warning.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-09-19 11:05:22 +09:00
Wolfgang Denk
f12e4549b6 Coding style cleanup, update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-09-13 02:23:05 +02:00
Wolfgang Denk
508eb85db7 Merge branch 'master' of git://git.denx.de/u-boot-nand-flash 2008-09-13 01:45:56 +02:00
Wolfgang Denk
afbc526336 Merge branch 'Makefile-next' of git://git.denx.de/u-boot-arm 2008-09-12 16:13:12 +02:00
Wolfgang Denk
b476b03256 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2008-09-12 15:23:20 +02:00
Stefan Roese
7bf5ecfa50 ppc4xx: Fix SDRAM inititialization of multiple 405 based board ports
This patch fixes a problem introdiced with patch
bbeff30c [ppc4xx: Remove superfluous dram_init() call or replace it by
initdram()].

The boards affected are:
- PCI405
- PPChameleonEVB
- quad100hd
- taihu
- zeus

Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-12 07:12:33 +02:00
Jens Scharsig
3ee9f03f58 at91rm9200: fix errors with CONFIG_CMD_I2C_TREE
This patch prevents linker error on AT91RM9200 boards, if
CONFIG_CMD_I2_TREE is set.
It implements i2c_set_bus_speed and i2c_get_bus_speed as a dummy function.

Signed-off-by: Jens Scharsig <esw@bus-elektronik.de>
2008-09-12 02:20:47 +02:00
Hugo Villeneuve
b5b0344957 ARM DaVinci: Remove duplicate code in cpu/arm926ejs/davinci/dp83848.c
ARM DaVinci: Remove duplicate code in cpu/arm926ejs/davinci/dp83848.c

Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
2008-09-12 02:20:47 +02:00
Andrew Dyer
274737e5eb i.mx change get_timer(base) to return time since base
This patch changes get_timer() for i.MX to return the time since
'base' instead of the time since the counter was at zero.

Symptom seen is flash timeout errors when erasing or programming a
sector using the common cfi flash code.

Signed-off-by: Andrew Dyer <adyer@righthandtech.com>
2008-09-12 02:20:46 +02:00
Andrew Dyer
48fed40575 i.MX use u-boot baud rate and don't assume UART master clock
1) Change the i.MX serial driver to use the baud rate set in the
 u-boot environment

2) don't assume a 16MHz value for PERCLK1 in baud rate calculations

3) don't write a 1 to the RDR bit in the USR2 reg. (bit is not "write
 one to clear" like other status bits in the reg.)

Signed-off-by: Andrew Dyer <adyer@righthandtech.com>
2008-09-12 02:20:46 +02:00
Andrew Dyer
6e1551a870 arm920t fix constant error in start.S
Code in cpu/arm920t/start.S will die with a compilation error if
CONFIG_STACKSIZE + CFG_MALLOC_LEN works out to an invalid constant for
the ARM sub instruction.  Change the code so that each is subtracted
independently to avoid the error.

Signed-off-by: Andrew Dyer <adyer@righthandtech.com>
2008-09-12 02:20:46 +02:00
Adrian Filipi
c455d07396 Set up SD/MMC OCR as comment describes. i.e. 3.2-3.4v.
Signed-off-by: Adrian Filipi <adrian.filipi@eurotech.com>
2008-09-12 01:23:44 +02:00
Magnus Lilja
8c4ebec25b i.MX31: Add reset_timer() and modify get_timer_masked().
This patch adds the reset_timer() function (needed by nand_base.c) and
modifies the get_timer_masked() to work in the same way as the omap24xx
function.

Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
2008-09-12 01:23:43 +02:00
Jean-Christophe PLAGNIOL-VILLARD
0cf4fd3cf8 rename environment.c in env_embedded.c to reflect is functionality
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-09-10 22:48:01 +02:00
Jean-Christophe PLAGNIOL-VILLARD
9314cee691 rename CFG_ENV_IS_IN_NVRAM in CONFIG_ENV_IS_IN_NVRAM
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-09-10 22:47:59 +02:00
Hugo Villeneuve
9b05aa788b ARM DaVinci: Fix broken HW ECC for large page NAND.
Based on original patch by Bernard Blackham <bernard@largestprime.net>

U-boot's HW ECC support for large page NAND on Davinci is completely
broken.  Some kernels, such as the 2.6.10 one supported by
MontaVista for DaVinci, rely upon this broken behaviour as they
share the same code for ECCs. In the existing scheme, error
detection *might* work on large page, but error correction
definitely does not.  Small page ECC correction works, but the
format is not compatible with the mainline git kernel.

This patch adds ECC code that matches what is currently in the
Davinci git repository (since NAND support was added in 2.6.24).
This makes the ECC and OOB layout written by u-boot compatible with
Linux for both small page and large page devices and fixes ECC
correction for large page devices.

The old behaviour can be restored by defining the macro
CFG_DAVINCI_BROKEN_ECC, which is undefined by default.

Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
Acked-by: Sergey Kubushyn <ksi@koi8.net>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-09-10 11:40:30 -05:00
Andrew Klossner
5251469943 Fix printf errors under -DDEBUG
Fix printf format-string/arg mismatches under -DDEBUG.

These warnings occur with DEBUG defined for a platform using
cpu/mpc85xx.  Users of other architectures can unearth similar
problems by adding the line "CFLAGS += -DDEBUG=1" in config.mk right
after "CFLAGS += $(call cc-option,-fno-stack-protector)".

Signed-off-by: Andrew Klossner <andrew@cesa.opbu.xerox.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-09-09 17:02:41 -05:00
Kumar Gala
e0ff3d350d 85xx: Ensure timebase is zero on secondary cores
The e500um says the timebase is volatile out of reset.  To ensure
TB sync works we need to make sure its zero.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-09-09 16:52:45 -05:00
Sergei Poselenov
59f630588e Removed hardcoded MxMR loop value from upmconfig() for MPC85xx.
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
2008-09-09 10:14:32 +02:00
Wolfgang Denk
ab00e7a23e Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
Conflicts:

	Makefile

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-09-09 02:24:51 +02:00
Sergei Poselenov
1bb8b2ef27 ARM: fix warning: target CPU does not support interworking
This patch fixes warnings like this:

start.S:0: warning: target CPU does not support interworking

which come from some ARM cross compilers and are caused by hard-coded
(with "--with-cpu=arm9" configuration option) ARM targets (which
support ARM Thumb instructions), while the ARM target selected from
the command line (with "-march=armv4") doesn't support Thumb
instructions.

This warning is issued by the compiler regardless of the real use of
the Thumb instructions in code.

To fix this problem, we use options according to compiler version
being used.

Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-09-09 02:14:43 +02:00
Sergei Poselenov
4265c35fbc ARM: Use do_div() instead of division for "long long".
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-09-09 02:14:41 +02:00
Stefan Roese
c351575c22 Merge branch 'master' of /home/stefan/git/u-boot/u-boot 2008-09-08 10:35:49 +02:00
Stefan Roese
f071f01fd0 ppc4xx: Remove CONFIG_CS8952_PHY define
Since this define is only used on one board that was never really in
production, removing this compile time option doesn't hurt and makes
the code more readable.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-08 10:27:56 +02:00
Stefan Roese
6ca8646c18 ppc4xx: Fix compilation warning for PIP405
This patch fixes a compilation warning for the PIP405 board. It moves the
#ifndef CONFIG_CS8952_PHY define a little so that the warning doesn't
occur anymore. I am a little unsure if this #ifdef is at the correct
place now or if it could be removed completely. This needs to get
tested on the PIP405 board.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-08 10:27:51 +02:00
Stefan Roese
725b53ac61 ppc4xx: Fix compilation warning for canyonlands & glacier
Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-08 10:27:46 +02:00
Kumar Gala
302e52e0b1 Fix compiler warning in mpc8xxx ddr code
ctrl_regs.c: In function 'compute_fsl_memctl_config_regs':
ctrl_regs.c:523: warning: 'caslat' may be used uninitialized in this function
ctrl_regs.c:523: note: 'caslat' was declared here

Add a warning in DDR1 case if cas_latency isn't a value we know about.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-09-07 01:26:13 +02:00