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https://github.com/AsahiLinux/u-boot
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OMAP: rename timer divisor
Divisor field is called PTV not PVT. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
This commit is contained in:
parent
fe672d60b2
commit
81472d893f
19 changed files with 41 additions and 54 deletions
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@ -49,7 +49,7 @@ int interrupt_init (void)
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/* Start the counter ticking up */
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*((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/
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val = (CONFIG_SYS_PVT << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/
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val = (CONFIG_SYS_PTV << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/
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*((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val; /* start timer */
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reset_timer_masked(); /* init the timestamp and lastinc value */
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@ -51,7 +51,7 @@ int interrupt_init (void)
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/* Start the decrementer ticking down from 0xffffffff */
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*((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
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val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PVT << MPUTIM_PTV_BIT);
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val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PTV << MPUTIM_PTV_BIT);
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*((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val;
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/* init the timestamp and lastdec value */
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@ -52,7 +52,7 @@ int timer_init (void)
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/* Start the decrementer ticking down from 0xffffffff */
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*((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
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val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PVT << MPUTIM_PTV_BIT);
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val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PTV << MPUTIM_PTV_BIT);
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*((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val;
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/* init the timestamp and lastdec value */
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@ -175,7 +175,7 @@ int interrupt_init(void)
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/* start the counter ticking up, reload value on overflow */
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writel(TIMER_LOAD_VAL, &timer_base->tldr);
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/* enable timer */
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writel((CONFIG_SYS_PVT << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
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writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
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&timer_base->tclr);
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reset_timer_masked(); /* init the timestamp and lastinc value */
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@ -138,9 +138,9 @@
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/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
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* This time is further subdivided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
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#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */
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#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
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#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE /* use timer 1 */
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#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
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#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
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/*-----------------------------------------------------------------------
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* Stack sizes
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@ -203,11 +203,9 @@
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* or by 32KHz clk, or from external sig. This rate is divided by a local
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* divisor.
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*/
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#define V_PVT 7 /* use with 12MHz/128 */
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#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2
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#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */
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#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
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#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
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#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
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/*-----------------------------------------------------------------------
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* Stack sizes
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@ -226,8 +226,8 @@
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* This time is further subdivided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE
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#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */
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#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
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#define CONFIG_SYS_PTV 7 /* 2^(pvt+1), divide by 256 */
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#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
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#define OMAP5910_DPLL_DIV 1
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#define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \
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@ -135,9 +135,9 @@
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/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
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* This time is further subdivided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
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#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */
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#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
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#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE /* use timer 1 */
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#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
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#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
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/*-----------------------------------------------------------------------
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* Stack sizes
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@ -131,8 +131,8 @@
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* DPLL1. This time is further subdivided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
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#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */
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#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
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#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
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#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
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/*-----------------------------------------------------------------------
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* Stack sizes
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@ -136,8 +136,8 @@
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* DPLL1. This time is further subdivided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
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#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */
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#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
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#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
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#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
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/*-----------------------------------------------------------------------
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* Stack sizes
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@ -222,14 +222,14 @@
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* 32KHz clk, or from external sig. This rate is divided by a local divisor.
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*/
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#ifdef CONFIG_APTIX
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#define V_PVT 3
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#define V_PTV 3
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#else
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#define V_PVT 7 /* use with 12MHz/128 */
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#define V_PTV 7 /* use with 12MHz/128 */
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#endif
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#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2
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#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */
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#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
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#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2
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#define CONFIG_SYS_PTV V_PTV /* 2^(PTV+1) */
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#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
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/*-----------------------------------------------------------------------
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* Stack sizes
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@ -226,11 +226,9 @@
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* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
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* 32KHz clk, or from external sig. This rate is divided by a local divisor.
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*/
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#define V_PVT 7
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#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
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#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */
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#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT))
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#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
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#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV))
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/*-----------------------------------------------------------------------
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* Stack sizes
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@ -219,11 +219,9 @@
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* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
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* 32KHz clk, or from external sig. This rate is divided by a local divisor.
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*/
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#define V_PVT 7
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#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
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#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */
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#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT))
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#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
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#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV))
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/*-----------------------------------------------------------------------
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* Stack sizes
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@ -213,11 +213,9 @@
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* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
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* 32KHz clk, or from external sig. This rate is divided by a local divisor.
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*/
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#define V_PVT 7
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#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
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#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */
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#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT))
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#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
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#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV))
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/*-----------------------------------------------------------------------
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* Stack sizes
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@ -215,11 +215,9 @@
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* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
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* 32KHz clk, or from external sig. This rate is divided by a local divisor.
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*/
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#define V_PVT 7
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#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
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#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */
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#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT))
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#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
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#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV))
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/*-----------------------------------------------------------------------
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* Stack sizes
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@ -223,11 +223,9 @@
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* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
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* 32KHz clk, or from external sig. This rate is divided by a local divisor.
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*/
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#define V_PVT 7
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#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
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#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */
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#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT))
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#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
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#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV))
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/*-----------------------------------------------------------------------
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* Stack sizes
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@ -140,8 +140,8 @@
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* DPLL1. This time is further subdivided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
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#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */
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#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
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#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
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#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
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/*-----------------------------------------------------------------------
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* Stack sizes
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@ -148,10 +148,9 @@
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* the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a
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* local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
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#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */
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#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
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#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
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#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
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#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
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/*-----------------------------------------------------------------------
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* Stack sizes
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@ -213,9 +213,9 @@
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/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
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* This time is further subdivided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE
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#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */
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#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
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#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE
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#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
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#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
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#define OMAP5910_DPLL_DIV 1
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#define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \
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