Commit graph

4027 commits

Author SHA1 Message Date
Wu, Josh
b2d96dc28f ARM: at91: atmel_nand: pmecc driver will select the galois table by sector size
Define the galois index table offset in chip head file. So user do not need
to set by himself. Driver will set it correctly according to sector_size.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Scott Wood <scottwood@freescale.com>
[rebased on master]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-08-22 16:50:16 +02:00
Bo Shen
e08d6f3aaf arm: atmel: add gmac support for sama5d3xek board
add gmac support for sama5d3xek board, the gmac embedded in:
  - sama5d33, sama5d34, sama5d35

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-08-22 16:49:54 +02:00
Tom Rini
6612ab3395 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2013-08-21 16:27:47 -04:00
Andreas Wass
661edaafd4 ARM: mxs: Added application UART driver
The driver makes it possible to use an application UART as
the U-Boot output console for Freescale i.MX23/i.MX28 devices.

Signed-off-by: Andreas Wass <andreas.wass@dalelven.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
2013-08-21 19:20:28 +02:00
Николай Пузанов
e6394e9e8f Fix for incorrect conversion hex string to number (FMAN firmware address).
Signed-off-by: Николай Пузанов <punzik@gmail.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 11:51:26 -07:00
Shengzhou Liu
424bf94273 powerpc/sec: Add workaround for SEC A-003571
Multiple read/write transactions initiated by security
engine may cause system to hang.
Workaround: set MCFGR[AXIPIPE] to 0 to avoid hang.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 10:47:07 -07:00
Shaohui Xie
1c68d01eea powerpc/t4240: add QSGMII interface support
Also some fix for QSGMII.
1. fix QSGMII configure of Serdes2.
2. fix PHY address of QSGMII MAC9 & MAC10 for each FMAN.
3. fix dtb for QSGMII interface.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 10:46:48 -07:00
Shruti Kanetkar
6b44d9e5b7 powerpcv2: Print hardcoded size like print_size() does
Makes the startup output more consistent

Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 10:38:12 -07:00
Shruti Kanetkar
2f848f97d7 powerpc: Use print_size() where appropriate
Makes the startup output more consistent

Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 10:37:58 -07:00
Prabhakar Kushwaha
997399fa42 powerpc: Fix CamelCase checkpatch warnings
85xx, 86xx PowerPC folders have code variables with CamelCase naming conventions.
because of this code checkpatch script generates "WARNING: Avoid CamelCase".

Convert variables name to normal naming convention and modify board, driver
files with updated the new structure.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 09:57:51 -07:00
Ying Zhang
bb0dc1084f powerpc: mpc85xx: Support booting from SD Card with SPL
The code from the internal on-chip ROM. It loads the final uboot image
into DDR, then jump to it to begin execution.

The SPL's size is sizeable, the maximum size must not exceed the size of L2
SRAM. It initializes the DDR through SPD code, and copys final uboot image
to DDR. So there are two stage uboot images:
	* spl_boot, 96KB size. The env variables are copied to L2 SRAM, so that
	ddr spd code can get the interleaving mode setting in env. It loads
	final uboot image from offset 96KB.
	* final uboot image, size is variable depends on the functions enabled.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 09:47:26 -07:00
Ying Zhang
0151d99d74 powerpc: deleted unused symbol CONFIG_SPL_NAND_MINIMAL and enabled some functionality for common SPL
1. The symbol CONFIG_SPL_NAND_MINIMAL is unused, so deleted it.
2. Some functions were unused in the minimal SPL, but it is useful
in the common SPL. So, enabled some functionality for common SPL.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 09:47:15 -07:00
Matthias Fuchs
3fb8588912 ppc4xx: Remove support for PPC405CR CPUs
This patch removes support for the APM 405CR CPU.
This CPU is EOL and no board uses this chip.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2013-08-20 11:35:24 -04:00
Chunhe Lan
9c3f77eb3b fsl_i2c: add workaround for the erratum I2C A004447
This workaround is for the erratum I2C A004447. Device reference
manual provides a scheme that allows the I2C master controller
to generate nine SCL pulses, which enable an I2C slave device
that held SDA low to release SDA. However, due to this erratum,
this scheme no longer works. In addition, when I2C is used as
a source of the PBL, the state machine is not able to recover.

At the same time, delete the reduplicative definition of SVR_VER
and SVR_REV. The SVR_REV is the low 8 bits rather than the low 16
bits of svr. And we use the CONFIG_SYS_FSL_A004447_SVR_REV macro
instead of hard-code value 0x10, 0x11 and 0x20.

The CONFIG_SYS_FSL_A004447_SVR_REV = 0x00 represents that one
version of platform has this I2C errata. So enable this errata
by IS_SVR_REV(svr, maj, min) function.

Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
2013-08-20 11:15:31 +02:00
Wolfgang Denk
cb3761ea99 SPDX-License-Identifier: convert BSD-3-Clause files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini Don't remove some copyrights by accident]
Signed-off-by: Tom Rini <trini@ti.com>
2013-08-19 15:45:35 -04:00
Wolfgang Denk
46263f2de4 SPDX-License-Identifier: convert PIBS licensed files
This commit adapts the files that were derived from PIBS (PowerPC
Initialization and Boot Software) codeto using SPDX License
Identifiers.

So far, SPDX has not assigned an official License ID for the PIBS
license yet, so this should be considered preliminary.

Note that the following files contained incorrect license information:

	arch/powerpc/cpu/ppc4xx/4xx_uart.c
	arch/powerpc/cpu/ppc4xx/start.S
	arch/powerpc/include/asm/ppc440.h

These files included, in addition to the GPL-2.0 / ibm-pibs dual
license as inherited from PIBS, a GPL-2.0+ license header which was
obviously incorrect.  This has been removed.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>

Conflicts:
	Licenses/README
Acked-by: Stefan Roese <sr@denx.de>
2013-08-19 15:34:14 -04:00
Wolfgang Denk
bcd4d4eb2b SPDX-License-Identifier: fixing some problematic GPL-2.0 files
Unlike the other patches in this series so far, this commit fixes a
ambiguity in the license terms for some OMAP files:  the code was
originally derived from the Linux kernel sources, where it was clearly
marked as GPL-2.0 (i. e. without the "or later" part), but the U-Boot
version had a GPL-2.0+ file header added, apparently without
permission / relicensing from the original authors of the code.

Insert a GPL-2.0 SPDX-License-Identifier to fix this.

Signed-off-by: Wolfgang Denk <wd@denx.de>
cc: Tom Rix <Tom.Rix@windriver.com>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: Tom Rini <trini@ti.com>
2013-08-19 15:34:13 -04:00
Tom Rini
e20cc2ca15 Merge branch 'master' of git://88.191.163.10/u-boot-arm
Fixup an easy conflict over adding the clk_get prototype and USB_OTG
defines for am33xx having moved.

Conflicts:
	arch/arm/include/asm/arch-am33xx/hardware.h

Signed-off-by: Tom Rini <trini@ti.com>
2013-08-18 14:14:34 -04:00
Albert ARIBAUD
9ed887caec Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-08-17 18:24:13 +02:00
TENART Antoine
dcf846d5da Add TI816X support
Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com>
[trini: Fix warnings about vtp things in emif4.c, adapt AM43XX]
Signed-off-by: Tom Rini <trini@ti.com>
2013-08-15 18:38:37 -04:00
TENART Antoine
9ed6e41239 Prepare for TI816X : reuse existing code from TI814X
Rename some CONFIG_TI814X to a more generic CONFIG_TI81XX

Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com>
[trini: Adapt for CONFIG_OMAP_COMMON changes, AM43XX]
Signed-off-by: Tom Rini <trini@ti.com>
2013-08-15 18:38:37 -04:00
Heiko Schocher
9c8deaeeb7 arm, da850: enable the correct uart in arch_cpu_init()
in arch_cpu_init() uart2 is fix enabled, without reference the
setting from CONFIG_SYS_NS16550_COM1. Use the setting from
CONFIG_SYS_NS16550_COM1 for enabling the console.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Christian Riesch <christian.riesch@omicron.at>
2013-08-15 18:38:36 -04:00
Heiko Schocher
78056717e3 arm/davinci/da850: add uart0_pins_rtscts and RMII_MHz_50_CLK in emac_pins_rmii pinmux
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
2013-08-15 18:38:36 -04:00
Tom Rini
ec101fdb8d arm: spl: For Falcon Mode, set a default machid of ~0
With device trees, boards do not always set CONFIG_MACH_TYPE now, so we
must not rely on this define being set.  The kernel uses ~0 to see if we
have a valid machine number or not, so set that as the default, invalid
machine, id and only fix if CONFIG_MACH_TYPE is set.

Acked-by: Dan Murphy <dmurphy@ti.com>
Tested-by: Heiko Schocher <hs@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@ti.com>
2013-08-15 18:38:35 -04:00
Taras Kondratiuk
0474fb0e2b omap: emif: Set initial DDR PHY config first
Commit "OMAP5: emif/ddr: Change emif settings as required for ES1.0 silicon"
(f40107345c)
changed sequence to set final DDR PHY config register value at the beginning.
Looks like it was made by mistake and should be reverted.

Signed-off-by: Taras Kondratiuk <taras@ti.com>
2013-08-15 18:38:35 -04:00
Masahiro Yamada
2f6af82719 ARM: omap24xx: remove remainders of dead board
Since Commit 7f5eef9 removed OMAP2420H4 support,
arm1136/omap24xx has not been used at all.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-08-15 18:38:33 -04:00
Naumann Andreas
a704a6d615 ARM: omap3: Implement dpll5 (HSUSB clk) workaround for OMAP36xx/AM/DM37xx according to errata sprz318e.
In chapter 'Advisory 2.1 USB Host Clock Drift Causes USB Spec Non-compliance in Certain Configurations' of the TI Errata it is recommended to use certain div/mult values for the DPLL5 clock setup.
So far u-boot used the old 34xx values, so I added the errata recommended values specificly for 36xx init only.
Also, the FSEL registers exist no longer, so removed them from init.

Tested this on a AM3703 board with 19.2MHz oscillator, which previously couldnt lock the dpll5 (kernel complained). As a consequence the EHCI USB port wasnt usable in U-Boot and kernel. With this patch, kernel panics disappear and USB working fine in u-boot and kernel.

Signed-off-by: Andreas Naumann <anaumann@ultratronik.de>
[trini: Add extern to <asm/arch-omap3/clock.h>
Signed-off-by: Tom Rini <trini@ti.com>
2013-08-15 09:09:29 -04:00
Lokesh Vutla
571804086f ARM: AM43xx: Add build support
Add AM43xx support in the required places

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-08-15 08:51:10 -04:00
Lokesh Vutla
806d279247 ARM: OMAP: Add CONFIG_OMAP_COMMON
Adding a new CONFIG_OMAP_COMMON which is included by all boards
that needs to build cpu/armv7/omap-common folder.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-08-15 08:51:10 -04:00
Lokesh Vutla
3b34ac13fe ARM: AM43xx: clocks: Add dpll and clock data
Add dpll and clock data for AM43xx

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-08-15 08:51:10 -04:00
Lokesh Vutla
c06e498a16 ARM: AM43xx: Add header files
Adding the following data:
-> Prcm structure
-> Base addresses
-> Pin mux structure.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-08-15 08:51:10 -04:00
Heiko Schocher
0660481a59 ARM: AM33xx: Move s_init to a common place
s_init has the same outline for all the AM33xx based
board. So making it generic.
This also helps in addition of new Soc with minimal changes.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
2013-08-15 08:51:10 -04:00
Lokesh Vutla
95cb69faeb ARM: AM33xx: Cleanup clocks layer
Cleaning up the clocks layer.
This helps in addition of new Soc with minimal
changes.
This is derived from OMAP4 boards.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
2013-08-15 08:51:10 -04:00
Lokesh Vutla
94d77fb656 ARM: AM33xx: Cleanup dplls data
Locking sequence for all the dplls is same.
In the current code same sequence is done repeatedly
for each dpll. Instead have a generic function
for locking dplls and pass dpll data to that function.

This is derived from OMAP4 boards.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
2013-08-15 08:51:10 -04:00
ramneek mehresh
61033367a0 powerpc/usb: Depricate usb_phy_type and usb_dr_mode uboot env variables
Remove getting values of usb mode and phy_type from "usb_dr_mode"
and "usb_phy_type" uboot env variables. Now, these are determined
only from hwconfig string

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-14 10:58:21 -07:00
ramneek mehresh
9dee205d78 fsl/usb: Move USB internal phy definitions to fsl_usb.h
fsl_usb.h file created to share data bewteen usb platform code
and usb ip driver. Internal phy structure definitions moved to
this file

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-14 10:58:01 -07:00
Prabhakar Kushwaha
a4c955bc3b powerpc/mpc85xx:Avoid hardcoded init for serdes block 1 & 2
It is not necessary for all processor to have serdes block 1 & 2.
They may have only one serdes block.

So, put serdes block 1 & 2 related code under defines

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-14 10:57:49 -07:00
Tom Rini
b98d934128 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2013-08-13 09:14:02 -04:00
Tom Rini
67cafc0861 Merge branch 'master' of git://www.denx.de/git/u-boot-mips 2013-08-13 08:58:47 -04:00
Daniel Schwierzeck
4b17645d5d MIPS: bootm: drop obsolete Qemu specific bootm implementation
The Qemu specific bootm implementation was intended for a special
Qemu target in Linux kernel. But this target has been dropped in
v2.6.25-rc1 by commit 302922e5f6901eb6f29c58539631f71b3d9746b8

    Author: Ralf Baechle <ralf@linux-mips.org>
    Date:   Tue Jan 29 10:15:02 2008 +0000

    [MIPS] Qemu: Remove platform.

    The Qemu platform was originally implemented to have an easily supportable
    platform until Qemu reaches a state where it emulates a real world system.
    Since the latest release Qemu is capable of emulating the MIPSsim and
    Malta platforms, so this goal has been reached.  The Qemu plaform is also
    rather underfeatured so less useful than a Malta emulation.

Thus the special bootm implementation is obsolete by now and can be
dropped. The Qemu support in U-Boot is going to be replaced by MIPS Malta
board support.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-08-13 11:58:48 +02:00
Daniel Schwierzeck
b87493f49a MIPS: bootm: add YAMON style Linux preparation/jump code for Qemu Malta
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-08-13 11:58:48 +02:00
Daniel Schwierzeck
6c154552b0 MIPS: bootm: add support for generic relocation of init ramdisks
All linux kernels after v2.6 require a page-aligned location of
an external init ramdisk. Enable CONFIG_SYS_BOOT_RAMDISK_HIGH to
support this with the generic U-Boot relocation code.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-08-13 11:58:48 +02:00
Daniel Schwierzeck
15f8aa9093 MIPS: bootm: refactor initialisation of kernel environment
Move initialisation of Linux environment to separate functions.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-08-13 11:58:48 +02:00
Daniel Schwierzeck
59e8cbdb15 MIPS: bootm: refactor initialisation of kernel cmdline
Move initialisation of Linux command line to separate functions.
Also add support for bootm subcommand 'cmdline'.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-08-13 11:58:48 +02:00
Daniel Schwierzeck
f66cc1e348 MIPS: bootm: add support for LMB
This is required for init ramdisk relocation and device tree
support.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-08-13 11:58:48 +02:00
Daniel Schwierzeck
c4b37847d3 MIPS: bootm: optimize kernel entry call
Fix signature of kernel entry function. Mark the kernel entry
with __noreturn for better code optimisation.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-08-13 11:58:48 +02:00
Daniel Schwierzeck
45bde489e3 MIPS: bootm: fix checkpatch.pl warnings
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-08-13 11:58:48 +02:00
Tom Rini
c15438eaea Merge branch 'master' of git://www.denx.de/git/u-boot-video 2013-08-12 18:06:30 -04:00
York Sun
3aab0cd852 powerpc/mpc85xx: Cleanup license header in source files
Fix the license header introduced by the following patches

Add TWR-P10xx board support
Add T4240EMU target
IDT8T49N222A configuration code
Add C29x SoC support
Add support for C29XPCIE board

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-12 15:04:24 -07:00
Donghwa Lee
9c17a32591 exynos: video: change mipi dsi write function parameters correctly
This patch have changed mipi dsi write functions' parameters correctly
so that type cast operations were removed. And mipi dsi payload is
composed with array of panel commands to improve readability.

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
2013-08-12 22:39:07 +02:00
Marek Vasut
ac8ba84c56 video: Encapsulate font in video_font_data.h
This patch moves all the font configuration values into video_font_data.h
so they are all in the right place with the font. The video_font.h now only
includes video_font_data.h and will allow us to select and include different
font once more fonts are added.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
[agust: fixed build warning for mcc200]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-08-12 22:28:41 +02:00
Tom Rini
66ddf42b0e Merge branch 'master' of git://git.denx.de/u-boot-spi 2013-08-12 08:48:49 -04:00
Michal Simek
39523bef29 zynq: slcr: Wait 100ms till clk is properly setup
If you don't wait you will loose the first sent packet
even all bits in emacps are correctly setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-08-12 08:59:55 +02:00
Michal Simek
148ba55cc6 zynq: Add new ddrc driver for ECC support
The first 1MB is not initialized by first stage bootloader.
Check if memory is setup to 16bit mode and ECC is enabled.
If it is, clear the first 1MB.
Also u-boot should report only the half size of memory.

Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-08-12 08:59:55 +02:00
Heiko Schocher
b424aae4be arm, am33xx: add clk_get prototype
the clk_get() function is needed for the da8xx-fb video driver,
which is used on the am3xx based siemens boards.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Tom Rini <trini@ti.com>
2013-08-10 10:38:06 +02:00
Heiko Schocher
0017f9ee06 video, da8xx: move da8xx-fb.h to drivers/video
the da8xx-fb driver works also on am335x boards. So move
the da8xx-fb.h file from arch/arm/include/asm/arch-davinci
to drivers/video, so this driver can used from am335x
based boards. Also add WVGA panel_type.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Tom Rini <trini@ti.com>
2013-08-10 10:37:48 +02:00
Roy Zang
ce24f87b7b 83xx/pcie: fix build error for 83xx pcie
Fix the following build error caused by patch "powerpc/pcie: add PCIe
version 3.x support":

pcie.c:302:34: error: 'PCI_LTSSM' undeclared (first use in this function)
pcie.c:303:15: error: 'PCI_LTSSM_L0' undeclared (first use in this function)

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:50:56 -07:00
Marek Vasut
69f7345c95 dma: apbh: Add special circular mode for LCD
Add special function that executes a specially crafted circular
DMA descriptor. The function doesn't wait for the descriptor to
finish the transfer, since the descritor never finishes. This is
useful when operating a SmartLCD through the LCDIF interface, as
the LCDIF does not give us any means to have continuous refresh
of the SmartLCD. Instead, the RUN bit in the LCDIF CTRL register
must be triggered manually. This can be worked around by starting
an DMA transfer which continuously sets the RUN bit. This function
allows starting exactly such transfer.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2013-08-09 21:48:34 +02:00
James Yang
c45f5c08b7 powerpc/mpc8xxx: Fix TIMING_CFG_3[EXT_ACTTOPRE]
The TIMING_CFG_3[EXT_ACTTOPRE] register field is 2 bits wide, but
the mask omitted the LSB.  This patch provides a 2-bit wide mask.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:43:32 -07:00
Mingkai Hu
3b75e98273 powerpc/85xx: Add C29x SoC support
The Freescale C29x family is a high performance crypto co-processor.
It combines a single e500v2 core with necessary SEC engine. There're
three SoC types(C291, C292, C293) with the following features:

 - 512K L2 Cache/SRAM and 512 KB platform SRAM
 - DDR3/DDR3L 32bit DDR controller
 - One PCI express (x1, x2, x4) Gen 2.0 Controller
 - Trust Architecture 2.0
 - SEC6.0 engine

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Po Liu <Po.Liu@freescale.com>
2013-08-09 12:41:42 -07:00
Zang Roy-R61911
1218f7eb11 powerpc/pcie: remove PCIe version 3.x define for B4860 and B4420
B4860 and B4420 has PCIe version 2.4 IP instead of 3.x

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
2013-08-09 12:41:42 -07:00
Zang Roy-R61911
7b4e58440f powerpc/pcie: add PCIe version 3.x support
T4240 PCIe IP is version 3.0 and has some update comparing previous
QorIQ products.

1.  Move Freescale specific register define
to
arch/powerpc/include/asm/fsl_pci.h
and update the register offset define for T4240.

2. add the status/control register define
use status/control register to judge the link status

3. The original code uses 'Programming Interface' field to judge if PCIE is
EP or RC mode, however, T4240 does not support this functionality.
According to PCIE specification, 'Header Type' offset 0x0e is used to
indicate header type, so for PCIE controller, the patch changes code to
use 'Header Type' field to identify if the PCIE is RC or EP mode.

This patch fixes  the PCIe card link up issue on T4240QDS.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:41 -07:00
Minghuan Lian
0795eff34c powerpc/rman: fix RMan support for t4240 and b4860
1. Add CONFIG_SYS_DPAA_RMAN macro to t4240 and b4860.
2. Decrease RMan liodn offset number.
SET_RMAN_LIODN() is used to set liodn offset of RMan blocks 0-3.
For t4240 and b4860, RMan liodn base is assigned to 922, the original
offset number is too large that the liodn (base+offset 922+678 = 1600)
is greater than 0x500 the maximum liodn number.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:41 -07:00
Shaveta Leekha
40f398a42b powerpc/asm: Move function declaration of 'serdes_get_prtcl' to fsl_serdes.h
It allows files not in the same path to use this function
as required by B4 board file

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
2013-08-09 12:41:41 -07:00
Shaveta Leekha
6fbe988901 powerpc/mpc85xx: Add defines for serdes RSTCTL register
Also change the define name SRDS_RSTCTL_SDPD to
SRDS_RSTCTL_SDEN, which stands for SerDes enable
as mentioned in SerDes module guide

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
2013-08-09 12:41:41 -07:00
Priyanka Jain
f9d379a707 board/bsc9132qds: Configure DSP DDR controller
BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side
DDR. They are mapped to PowerPC and DSP CCSR space respectively.
BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC
and other to DSP side controller.

Configure DSP DDR controller similar to PowerPC side DDR controller as
memories are exactly similar.

Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:40 -07:00
Priyanka Jain
64501c6698 board/bsc9132qds: Add DSP side tlb and laws
BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a
integrated device that contains two powerpc e500v2 cores and two DSP
starcores.

To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 and M3 memory
-Creating LAW for 1GB DDR which is connected exclusively to DSP-cores

Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:40 -07:00
Liu Gang
17b8614754 powerpc/srio-pcie-boot: Avoid the NOR_BOOT macro when boot from SRIO/PCIE
When a board (slave) boots from SRIO/PCIE, it would get the instructions
from a remote board (master) by SRIO/PCIE interface, and the slave's
u-boot image should be built with the

	SYS_TEXT_BASE=0xFFF80000;

So the u-boot of the slave should avoid the NOR_BOOT branch at the
booting stage.

For example, when a P2041RDB boots from SRIO/PCIE, it will set TLB
entry 15 from base address "CONFIG_SYS_MONITOR_BASE & 0xffc00000",
and with the 4M size as the boot window in NOR_BOOT branch. Because
the CONFIG_SYS_MONITOR_BASE = CONFIG_SYS_TEXT_BASE = 0xFFF80000, so
the TLB entry will be from base address 0xffc00000 and with 4M size.

Then the u-boot will set TLB entry 14 from base address
"CONFIG_SYS_INIT_RAM_ADDR", and with the 16K size as the initial
stack window. For the P2041RDB platform, the CONFIG_SYS_INIT_RAM_ADDR
= 0xffd00000. So the TLB entry 14 and 15 will be in confliction.

There will be right TLB entries configurations when avoid the
NOR_BOOT branch and set the boot window from 0xfff00000 with 1M
size space.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
2013-08-09 12:41:40 -07:00
York Sun
d217a9ad01 powerpc/mpc85xx: Workaround for A-005812
Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can
result in invalid atomic operations. For u-boot, this erratum only impacts
SoCs running in write shadow mode.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:40 -07:00
York Sun
c63e137014 powerpc/mpc8xxx: Add memory reset control
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:39 -07:00
York Sun
b61e061566 powerpc/mpc8xxx: Add x4 DDR device support
On selected platforms, x4 DDR devices can be supported. Using x4 devices may
lower the performance, but generally they are available for higher density.

Tested on MT36JSF2G72PZ-1G9E1 RDIMM.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:39 -07:00
York Sun
d8556db1d4 powerpc/mpc8xxx: Set inactive csn_bnds to 0xffffffff
When chip select interleaving is enabled, cs0_bnds is used for address
binding. Other csn_bnds are not used. When two controllers interleaving is
enabled, cs0_bnds of both controllers are used, other csn_bnds are not.
However, the unused csn_bnds may be used internally for calculating
addresses for calibration. Setting those registers to 0 may confuse
controllers in some cases. Instead, setting them to 0xffffffff together
with normal LAWs will guarantee the address is not mapped to DDR.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:39 -07:00
York Sun
f165bc3528 powerpc/corenet: Move RCW print to cpu.c
The RCW print is common for all corenet platforms. Not necessary to ducplicate
in each board file.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:38 -07:00
York Sun
cb93071bb6 mpc85xx: Base emulator support
Prepare for emulator support for mpc85xx parts.
Disable DDR training and skip wrlvl_cntl_2 and wrlvl_cntl_3 registers.
These two registers improve stability but not supported by emulator.
Add CONFIG_FSL_TBCLK_EXTRA_DIV for possible adjustment to time base.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:38 -07:00
York Sun
d2ab4bbc7b powerpc/corenet: Move CONFIG_FSL_CORENET out of board header file
Move CONFIG_FSL_CORENET define to config_mpc85xx.h. It is not board
specific feature and belongs to SoC header.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:38 -07:00
Liu Gang
08047937b4 powerpc/t4: Correct LIODN assignment for SRIO
For T4 platform, the SRIO LIODN registers are in SRIO address space
and not in GUTs.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
2013-08-09 12:41:38 -07:00
Liu Gang
32f38ee3ed powerpc/b4860: Correct LIODN assignment for SRIO
For B4, the SRIO LIODN registers are in SRIO address space and not
in GUTs.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
2013-08-09 12:41:37 -07:00
Liu Gang
b383102040 powerpc/srio: Update the SRIO LIODN registers and ID table macro
For some PowerPC platforms, LIODN registers for SRIO ports are
in SRIO register address space. So the ccsr_rio structure should
be updated for those LIODN registers.

In addition, add a new macro "SET_SRIO_LIODN_BASE" to create
the SRIO LIODN ID table based on the SRIO LIODN register address.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:37 -07:00
ken kuo
9f128bcc07 nds32: introduce DMA allocation API
U-Boot does not compile for the adp-ag101 boards since
commit a8f9cd1893
(net: update FTGMAC100 for MMU/D-cache support)

The driver assumes that the DMA allocation API are provided by all
architectures. This is not the case for nds32 and it causes a
build error. This patch adds DMA allocation API to avoid the errors.

Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com>
Cc: Macpaul Lin <macpaul@gmail.com>
Cc: Andes <uboot@andestech.com>
Signed-off-by: Andes <uboot@andestech.com>
2013-08-09 01:51:11 +08:00
Michal Simek
07a16f2a9c microblaze: Call spi_init function
Initialization spi.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Stephan Linz <linz@li-pro.net>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-08-08 18:58:11 +05:30
Jagannadha Sutradharudu Teki
1465d055f9 spi: Add zynq spi controller driver
Zynq spi controller driver supports 2 buses and
3 chipselects on each bus.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-08-07 01:09:47 +05:30
Stephen Warren
065202803d config: don't define CONFIG_ARCH_DEVICE_TREE
Now that nothing uses CONFIG_ARCH_DEVICE_TREE, stop defining it.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2013-08-02 18:30:11 -04:00
Stefano Babic
326ea986ac Merge git://git.denx.de/u-boot-arm
Conflicts:
	board/freescale/mx6qsabrelite/Makefile
	board/freescale/mx6qsabrelite/mx6qsabrelite.c
	include/configs/mx6qsabrelite.h

Signed-off-by: Stefano Babic <sbabic@denx.de>
2013-07-31 11:30:38 +02:00
Axel Lin
53086befe8 blackfin: Fix using gd->baudrate before setting its value
Current code uses gd->baudrate before setting its value.
Besides, I got below build warning which is introduced by
commit ddb5c5be "blackfin: add baudrate to bdinfo".

board.c:235:3: warning: passing argument 1 of 'simple_strtoul' makes pointer from integer without a cast [enabled by default]
include/vsprintf.h:27:7: note: expected 'const char *' but argument is of type 'unsigned int'

This patch ensures we get the baudrate setting before using it.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-07-31 16:56:04 +08:00
Axel Lin
9868b14263 blackfin: gpio: Use proper mask for comparing function
The function return from P_FUNCT2MUX(per) takes 2 bits, however
for BF537_FAMILY with offset != 1 the function is 1 bit.

Also has small refactor for better readability.
In portmux_setup(), it looks odd having "muxreg &= ~(3 << 1);"
while in current code we do muxreg |= (function << offset);.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
2013-07-31 16:56:03 +08:00
Axel Lin
5460b8d469 blackfin: gpio: Unreserve gpio in special_gpio_free()
In special_gpio_free(), call unreserve() rather than reserve() to release gpio.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-07-31 16:56:03 +08:00
Steve Kipisz
c5c7a7c32d am335x_evm: Add support to boot from NOR.
NOR requires that s_init be within the first 4KiB of the image so that
we can perform the rest of the required pinmuxing to talk with the rest
of NOR that we are found on.  When NOR_BOOT is set we save our
environment in NOR at 512KiB and a redundant copy at 768KiB.  We avoid
using SPL for this case and u-boot.bin is written directly to the start
of NOR.

We enclose the DMM-related parts of arch/arm/cpu/armv7/am33xx/emif4.c
with TI81xx checks as at this time U-Boot does not discard unused
sections in the main build and this code relies on functions specific to
(and only provided in) ti81xx-related code.

Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-30 09:21:41 -04:00
Steve Kipisz
cd8845d7a4 am335x_evm: Add support for the NOR module on the memory cape
This patch adds support for the NOR module that attaches
to the memory cape for a Beaglebone board. This does not
add booting support; only support so that you can boot from
SD/MMC and see the NOR module so that it can be programmed.

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
[trini: Clean up config changes slightly]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-30 09:21:41 -04:00
Tom Rini
392bba4ad0 am33xx: Correct gpmc_cfg->irqstatus/enable
Based on our usage of the GPMC, either with NOR or NAND we do not need
to be setting the irqstatus or irqenable bits and should clear them like
we have historically.

Signed-off-by: Tom Rini <trini@ti.com>
2013-07-30 09:21:41 -04:00
Robert Winkler
10f779da54 imx: nitrogen6x: mx6qsabrelite: Add support for DVI monitors
A little background is probably appropriate for this patch.

Since "the beginning" of usage of the SABRE Lite and Nitrogen6x
boards, DVI detection has been somewhat broken.

Some (most) DVI monitors don't produce the "HPD" bit in
the PHY_STAT0 register, but do show proper toggling of the
RX_SENSE0..3 bits.

Creating a new the bit-mask to include all five bits and
modifying the 'hdmidet' command and internal detection
routines allows these monitors to function properly in U-Boot.

A related patch to our kernels allows things to work under
Linux:
        7d8752905c

Signed-off-by: Robert Winkler <robert.winkler@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-07-27 10:52:42 +02:00
Pardeep Kumar Singla
5ea7f0e328 mx6: Factor out common HDMI setup code
Instead of duplicating HDMI setup code for every mx6 board, factor out the common code

Signed-off-by: Pardeep Kumar Singla <b45784@freescale.com>
Acked-By: Eric Nelson <eric.nelson@boundarydevices.com>
2013-07-27 10:49:36 +02:00
Mugunthan V N
b1e26e3bfb ARM: DRA7xx: Add CPSW support to DRA7xx EVM
Adding support for CPSW Ethernet support found in DRA7xx EVM

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2013-07-26 16:39:11 -04:00
Mugunthan V N
f986d97208 ARM: DRA7xx: Enable GMAC clock control
Enabling CPSW module by enabling GMAC clock control

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2013-07-26 16:39:11 -04:00
Lokesh Vutla
65e9d56fb9 ARM: DRA7xx: Lock DPLL_GMAC
Locking DPLL_GMAC

[mugunthanvnm@ti.com:Configure only if CPSW is selected]

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2013-07-26 16:39:11 -04:00
Andreas Bießmann
c4ec281822 omap3/sys_info: fix printout of OMAP36XX L3 freqency
The OMAP36xx/OMAP37xx family uses L3 frequency of 200MHz instead of 165MHz
used by OMAP34xx/OMAP35xx.

Also fix checkpatch warning about alignment.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-07-26 16:39:10 -04:00
Stefan Roese
bf0e86606d arm: omap3: spl: Fix problem with 8bit NAND devices
Currently in OMAP3 SPL, the GPMC for NAND is configured for 16bit
access. This patch adds support for 8bit NAND devices as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
2013-07-26 16:39:10 -04:00
Albert ARIBAUD
8b485ba12b Merge branch 'u-boot/master' into u-boot-arm/master 2013-07-25 17:57:46 +02:00
Tom Rini
aaf5e82560 Merge branch 'master' of git://git.denx.de/u-boot-nds32 2013-07-25 08:51:51 -04:00
Tom Rini
230187ce26 Merge branch 'master' of git://git.denx.de/u-boot-mips
Conflict over SPDX changes means that one change was effectively dropped
as it was fixing typos in a removed hunk of text.

Conflicts:
	arch/mips/cpu/mips64/start.S

Signed-off-by: Tom Rini <trini@ti.com>
2013-07-25 08:51:48 -04:00
ken kuo
c54fd3efa4 nds32: Enable FPU if the version of CPU supported
Some version of Andes core support FPU coprocessor,
if this is the case, and toolchain support FPU instruction set,
we should enable it at low level initialization time.

Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com>
Cc: Macpaul Lin <macpaul@gmail.com>
2013-07-25 16:54:19 +08:00
Tom Rini
99ca91b6d7 nds32: Update <asm/io.h> and <asm/setup.h> with SPDX license identifiers
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-25 16:54:18 +08:00
ken kuo
951344b778 nds32: Convert Makefiles to use COBJS-y style
Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com>
Cc: Macpaul Lin <macpaul@gmail.com>
2013-07-25 16:54:18 +08:00
Rob Herring
0f7cf3803f ARM: highbank: avoid bss write in timer_init
The timer_init function is called before relocation and writes to bss data
were corrupting relocation data. Fix this by removing the call to
reset_timer_masked. The initial timer count should be 0 or near 0 anyway,
so initializing the variables are not needed.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-07-25 08:15:44 +02:00
Rob Herring
714d1f5da5 ARM: highbank: set timer prescaler to 256
The 150MHz clock rate gives u-boot time functions problems and there's no
benefit to a fast clock, so lower the rate.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-07-25 08:15:33 +02:00
Rob Herring
ec0e413f93 ARM: highbank: fix get_tbclk value to timer rate
get_tbclk should return the timer's frequency, not CONFIG_SYS_HZ.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-07-25 08:15:25 +02:00
Rob Herring
0f5141e9c5 ARM: move interrupt_init to before relocation
interrupt_init also sets up the abort stack, but is not setup before
relocation. So any aborts during relocation will hang and not print out
any useful information. Fix this by moving the interrupt_init to after
the stack setup in board_init_f.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-07-25 08:14:28 +02:00
Gabor Juhos
db2c86d7d7 MIPS: mips32/cache.S: use v1 register for indirect function calls
Synchronize the code with mips64/cache.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:07 -04:00
Gabor Juhos
ee8b1e2959 MIPS: mips32/cache.S: store cache line size in t8 register
Synchronize the code with mips64/cache.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:07 -04:00
Gabor Juhos
c325916563 MIPS: mips32/cache.S: save return address in t9 register
Synchronize the code with mips64/cache.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:06 -04:00
Gabor Juhos
d707e5b713 MIPS: xburst/start.S: rework relocation info check
Make it similar to the code in mips{32,64}/start.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:06 -04:00
Gabor Juhos
e5c868a208 MIPS: xburst/start.S: use t8 register for dynamic relocation
Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:06 -04:00
Gabor Juhos
f01d693535 MIPS: xburst/start.S: save gd in s0 register
Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:06 -04:00
Gabor Juhos
ba9cf07122 MIPS: xburst/start.S: save relocation offset in s1 register
Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:06 -04:00
Gabor Juhos
9a28e0d177 MIPS: xburst/start.S: save relocation address in s2 register
Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:05 -04:00
Gabor Juhos
691995f9ab MIPS: mips32/start.S: rework relocation info check
Make it similar to the code in mips64/start.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:05 -04:00
Gabor Juhos
680cb2dc3a MIPS: mips32/start.S: use t8 register for dynamic relocation
Synchronize the code with mips64/start.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:05 -04:00
Gabor Juhos
da84f33b04 MIPS: mips32/cache.S: remove superfluous register assignment
The t4 register already holds the cache
line size, and the value of the register
is not changed in mips_init_icache.

Get the cache line size value from t4 for
mips_init_dcache as well and remove the
superfluous assignment of t5 register.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
2013-07-24 09:51:05 -04:00
Gabor Juhos
b1591ec246 MIPS: mips64/interrupt.c: remove superfluous include
Nothing is used from asm/mipsregs.h.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:05 -04:00
Gabor Juhos
c3e4901fc6 MIPS: mips32/time.c: fix checkpatch errors/warnings
Checking mips32/time.c with checkpatch.pl shows this:

  arch/mips/cpu/mips32/time.c:30: WARNING: line over 80 characters
  arch/mips/cpu/mips32/time.c:57: ERROR: return is not a function, parentheses are not required
  total: 1 errors, 1 warnings, 0 checks, 85 lines checked

Fix the code to make checkpatch.pl happy.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:04 -04:00
Gabor Juhos
ac12984de8 MIPS: qemu-malta: setup GT64120 registers as done by YAMON
Move the GT64120 register base to 0x1be00000
and setup PCI BAR registers as done by the
original YAMON bootloader.

This is needed for running Linux kernel.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:04 -04:00
Gabor Juhos
52caee0f36 MIPS: qemu-malta: enable flash support
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:04 -04:00
Gabor Juhos
015643152a MIPS: qemu-malta: add reset support
The MIPS Malta board has a SOFTRES register. Writing a
magic value into that register initiates a board reset.

Use this feature to implement reset support.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:03 -04:00
Gabor Juhos
5a4dcfac1e MIPS: qemu-malta: add support for emulated MIPS Malta board
Add minimal support for the MIPS Malta CoreLV board
emulated by Qemu. The only supported peripherial is
the UART.

This is enough to boot U-Boot to the command prompt
both in little and big endian mode.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:03 -04:00
Gabor Juhos
843a76b66b MIPS: start.S: emulate REVISION register for qemu-malta
On the origial Malta boards the REVISION register is
accessible at the 0x1fc00010 address. The contents of
this register gives information about the revision
of the Malta and Core Boards.

This register is used by the Linux kernel to identify
the actual board it is running on. However the register
is not emulated properly by Qemu, so put a hardcoded
value into the flash to make Linux work.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:03 -04:00
Tom Rini
518d438537 MIPS: mips64: fix typos in copyright text of start.S
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

Conflicts:

	arch/mips/cpu/mips64/start.S

Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:50:52 -04:00
Tom Rini
c2120fbfbc Merge branch 'master' of git://git.denx.de/u-boot-i2c
The sandburst-specific i2c drivers have been deleted, conflict was just
over the SPDX conversion.

Conflicts:
	board/sandburst/common/ppc440gx_i2c.c
	board/sandburst/common/ppc440gx_i2c.h

Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:50:24 -04:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Axel Lin
4fc9670513 nds32: ag101/ag102: Fix setting lastdec and now values
The timer3 counter unit for lastdesc and now values are inconsistent in current
code. The unit of "readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2)" is
second. However, CONFIG_SYS_HZ is defined as 1000 in board config file.
This means the accuracy of "lastdec" and "now" should be in millisecond,
thus fix the equation to set lastdec and now variables accordingly.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
2013-07-24 11:50:28 +08:00
ken kuo
e3c58b0292 nds32: Enable the function of passing parameters to Linux
Add a header file, setup.h, which copy from Linux source code,
this file contain structures are used to pass initialisation parameters
to Linux. Enable this function on adp-ag101/adp-ag101p target

Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com>
Cc: Macpaul Lin <macpaul@gmail.com>
2013-07-24 11:50:28 +08:00
ken kuo
3c016704d9 nds32: Enable two banks of SDRAM on Andes board
The original adp-ag101/adp-ag101p initialize only one bank(64MB)
by default at boot time, but it is not enough for some application,
so increasing to two banks(128M).

Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com>
Cc: Macpaul Lin <macpaul@gmail.com>
2013-07-24 11:50:28 +08:00
Gabor Juhos
bea2868f5e nds32: introduce macros for bit manipulation
U-Boot does not compile for the adp-ag101 boards since
commit f6c3b34697 (mmc:
update Faraday FTSDC010 for rw performance)

The driver assumes that the bit manipulation macros
are provided by all architectures. This is not the
case for nds32 and it causes a build error like this:

  ftsdc010_mci.c: In function 'ftsdc010_clkset':
  ftsdc010_mci.c:118: warning: implicit declaration of function 'setbits_le32'
  ftsdc010_mci.c:123: warning: implicit declaration of function 'clrbits_le32'
  drivers/mmc/libmmc.o: In function `ftsdc010_request':
  /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:234: undefined reference to `setbits_le32'
  /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:243: undefined reference to `clrbits_le32'
  /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:234: undefined reference to `clrbits_le32'
  drivers/mmc/libmmc.o: In function `ftsdc010_clkset':
  /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:118: undefined reference to `clrbits_le32'
  /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:118: undefined reference to `clrbits_le32'
  /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:121: undefined reference to `setbits_le32'
  /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:123: undefined reference to `setbits_le32'
  /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:123: undefined reference to `setbits_le32'

The patch adds bit manipulation macros for the
nds32 architecture to avoid the errors. The macros
are copied from the ARM implementation.

Compile tested only.

Cc: Kuo-Jung Su <dantesu@faraday-tech.com>
Cc: Macpaul Lin <macpaul@andestech.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
2013-07-24 11:49:16 +08:00
Alison Wang
1221b3d74a vf610: Add I2C support for Vybrid VF610 platform
This patch adds I2C support for Vybrid VF610 platform and adds
I2C0 support to VF610TWR board.

Signed-off-by: Alison Wang <b18965@freescale.com>
2013-07-23 08:34:57 +02:00
Dirk Eibach
880540decf i2c, ppc4xx_i2c: switch to new multibus/multiadapter support
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2013-07-23 08:34:56 +02:00
Heiko Schocher
9a2accb44f i2c, multibus: get rid of CONFIG_I2C_MUX
CONFIG_I2C_MUX is replaced through the new i2c multibus/multiadapter
framework, configured through CONFIG_SYS_I2C. As CONFIG_I2C_MUX
is only used on the keymile boards, and they are now completely
moved to the new framework, remove CONFIG_I2C_MUX.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Holger Brunck <holger.brunck@keymile.com>
Tested-By: Holger Brunck <holger.brunck@keymile.com>
2013-07-23 08:34:53 +02:00
Heiko Schocher
00f792e0df i2c, fsl_i2c: switch to new multibus/multiadapter support
- added to fsl_i2c driver new multibus/multiadpater support
- adapted all config files, which uses this driver

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
2013-07-23 08:34:53 +02:00
Heiko Schocher
ea818dbbcd i2c, soft-i2c: switch to new multibus/multiadapter support
- added to soft_i2c driver new multibus/multiadpater support
- adapted all config files, which uses this driver

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
2013-07-23 05:54:29 +02:00
Heiko Schocher
3f4978c713 i2c: common changes for multibus/multiadapter support
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Cc: Henrik Nordström <henrik@henriknordstrom.net>
2013-07-23 05:54:28 +02:00
Prabhakar Kushwaha
2a6936059a powerpc/mpc85xx:Disable Debug TLB entry for non-minimal SPL
CONFIG_SPL_BUILD creates debug TLB entry, so disable it before init_tlbs.

CONFIG_SPL_INIT_MINIMAL never creates any debug TLB entry, so no need
of disable_tlb().

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-07-16 17:44:30 -05:00
Dirk Eibach
b8eee4354f Build arch/$ARCH/lib/bootm.o depending on CONFIG_CMD_BOOTM
MAKEALL is fine for ppc4xx and mpc85xx.
Run checks were done on our controlcenterd hardware.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-07-16 17:44:30 -05:00
Łukasz Majewski
f4eaf88e6d arm:exynos:fix: Fix clock calculation for Exynos4210 based targets.
Provide proper setting for the APLL fout frequency calculation for
Exynos4 based targets (especially Exynos4210 - Trats board).

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2013-07-16 09:20:16 -04:00
Tom Rini
fbbbc86e8e Merge branch 'master' of git://git.denx.de/u-boot-arm
Fix a trivial conflict in arch/arm/dts/exynos5250.dtsi about gpio and
serial.

Conflicts:
	arch/arm/dts/exynos5250.dtsi

Signed-off-by: Tom Rini <trini@ti.com>
2013-07-12 10:36:48 -04:00
Simon Glass
7af26b1669 blackfin: x86: bootm: Handle PREP stage of bootm
The OS function is now always called with the PREP stage. Adjust the
remaining bootm OS functions to deal with this correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-07-12 10:32:39 -04:00
Jim Lin
7e44d9320e ARM: Tegra: USB: EHCI: Add support for Tegra30/Tegra114
Tegra30 and Tegra114 are compatible except PLL parameters.

Tested on Tegra30 Cardhu, and Tegra114 Dalmore
platforms. All works well.

Signed-off-by: Jim Lin <jilin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-07-11 14:15:15 -07:00
Jim Lin
56867d88c4 ARM: Tegra: FDT: Add USB EHCI function for T30/T114
Add DT node for USB EHCI function.
Add support for T30-Cardhu, T30-Beaver, T114-Dalmore boards.

Signed-off-by: Jim Lin <jilin@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-07-11 14:15:15 -07:00
Albert ARIBAUD
630aacb085 Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2013-07-10 20:40:47 +02:00
Simon Glass
a5266d6b5d bootm: Clean up bootz_setup() function
This function has no prototype in the headers and passes void * around, thus
requiring several casts. Tidy this up.

- Add new patch to clean up bootz_setup() function

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-07-10 09:15:14 -04:00
Minkyu Kang
e161f60f4d arm: exynos: fix clock calculation
There are differnce with clock calcuation by cpu variations.
This patch will fix it according to user manual.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
2013-07-09 16:15:30 +09:00
Rajeshwari Shinde
643be9c07e EXYNOS: Move files from board/samsung to arch/arm
This patch performs the following:

1) Convert the assembly code for memory and clock initialization to C code.
2) Move the memory and clock init codes from board/samsung to arch/arm
3) Creat a common lowlevel_init file across Exynos4 and Exynos5. Converted
   the common lowlevel_init from assembly to C-code
4) Made spl_boot.c and tzpc_init.c common for both exynos4 and exynos5.
5) Enable CONFIG_SKIP_LOWLEVEL_INIT as stack pointer initialisation is already
   done in _main.
6) exynos-uboot-spl.lds made common across SMDKV310, Origen and SMDK5250.

TEST: Tested SD-MMC boot on SMDK5250 and Origen.
      Tested USB and SPI boot on SMDK5250
      Compile tested for SMDKV310.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-07-05 17:06:55 +09:00
Rajeshwari Shinde
198a40b9f6 EXYNOS4210: Configure GPIO for uart
This patch configures the gpio values for UART
on Origen and SMDKV310 using pinmux

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-07-05 17:06:55 +09:00
Rajeshwari Shinde
dc20fdd76a EXYNOS: Add API for power reset and exit wakeup
This patch adds APIs to get power reset status and exit the wakeup condition for
both exynos5 and exynos4

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-07-05 17:06:54 +09:00
Axel Lin
87bd05d78f ARM: OMAP: GPIO: Fix valid range and enable usage of all GPIOs on OMAP5
The omap_gpio driver is used by AM33XX, OMAP3/4, OMAP54XX and DRA7XX SoCs.
These SoCs have different gpio count but currently omap_gpio driver uses hard
coded 192 which is wrong.

This patch fixes this issue by:
1. Move define of OMAP_MAX_GPIO to all arch/arm/include/asm/arch-omap*/gpio.h.
2. Update gpio bank settings and enable GPIO modules 7 & 8 clocks for OMAP5.

Thanks for Lubomir Popov to provide valuable comments to fix this issue.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Acked-by: Heiko Schocher <hs@denx.de>
2013-07-02 09:21:16 -04:00
Lokesh Vutla
e3f53104e2 ARM: OMAP4+: Fix MA detection during SDRAM_AUTO_DETECTION
During SDRAM_AUTO_DETECTION MA is not configured.
For Soc's > OMAP4460 MA is present. So populating
MA for the same.

Tested on OMAP4430 PANDA, OMAP4460 PANDA.

Reported-by: Dan Murphy <dmurphy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-07-02 09:21:16 -04:00
Ilya Ledvich
58c86c7d1d am33xx: fix the ddr_cmdtctrl structure
Fix the wrong mapping between the DDR I/O control registers on AM33XX
SoCs and the software representation in the SPL code.
The most recent public TRM defines the following DDR I/O control registers
offsets:
 * ddr_cmd0_ioctrl : offset 0x44E11404
 * ddr_cmd1_ioctrl : offset 0x44E11408
 * ddr_cmd2_ioctrl : offset 0x44E1140C
 * ddr_data0_ioctrl: offset 0x44E11440
 * ddr_data1_ioctrl: offset 0x44E11444

While the struct ddr_cmdtctrl has also some reserved bits in the beginning.
The struct is mapped to the address 0x44E11404. As a result "cm0ioctl" points
to the ddr_cmd1_ioctrl register, "cm1ioctl" to the ddr_cmd2_ioctrl and etc.
Registers ddr_cmd0_ioctrl and ddr_data0_ioctrl are never configured because
of this mapping mismatch.

Signed-off-by: Ilya Ledvich <ilya@compulab.co.il>
Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk>
2013-07-02 09:21:16 -04:00
Andreas Bießmann
2cb0e55a3c avr32/m68k/microblaze/nds32/nios2/openrisc/sh/sparc: fix do_bootm_linux
Commit 35fc84fa1f broke bootm on avr32. It
requires to call do_bootm_linux() with flag set to BOOTM_STATE_OS_PREP before
calling it again with flag set to BOOTM_STATE_OS_GO.
Fix this by allowing flag set to BOOTM_STATE_OS_PREP, this however will
require a complete refactoring later on.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
[trini: Apply to m68k, microblaze, nds32, nios2, openrisc, sh and sparc]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-02 09:17:17 -04:00
Stefan Roese
ed12b5b9da Fix bootm to work on powerpc again (compressed uImage)
Patch 35fc84fa1 [Refactor the bootm command to reduce code duplication]
breaks booting Linux (compressed uImage with fdt) on powerpc.

boot_jump_linux() mustn't be called before boot_prep_linux() and
boot_body_linux() have been called. So remove the superfluous call
to boot_jump_linux() in arch/powerpc/lib/bootm.c as its called later on
in this function.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@ti.com>
2013-06-28 16:26:52 -04:00
Albert ARIBAUD
e6c7f86f03 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-06-28 17:51:13 +02:00
Rajeshwari Shinde
493c073ff4 SMDK5250: Remove reduntant code
enum boot_mode is defined twice once in spl.h and also in
spl_boot.c, hence removing the same from spl_boot.c and including
the header file.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-06-28 09:19:38 +09:00
Jason Jin
1b9591c237 ColdFire: Update the arch_global_date changes for mcf5441x
Update inp_clk, vco_clk and flb_clk for mcf5441x as those
items were moved to arch_global_data.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2013-06-27 08:44:00 +08:00
Steve deRosier
08dbd6ccd5 Fix MCF5235 SDRAM base address macro
SDRAMC_DARCn_BA() macro worked fine when the BA is 0x00000000 even
though the macro is incorrect. It causes the BA to be set incorrctly
for other base addresses. This patch fixes the macro so that base
addresses other than zero can be used with the MCF5235.

Signed-off-by: Steve deRosier <derosier@gmail.com>
2013-06-27 08:31:17 +08:00
Jens Scharsig (BuS Elektronik)
aea5eee126 m68k: fix debug call befor serial init
There is a debug call in board.c befor serial interface was initialized.
This moves the debug code behind serial_initialize call.

Signed-off-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
2013-06-27 08:31:16 +08:00
trem
79713f0ad8 mx27: add i2c clock
Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
2013-06-26 17:34:21 +02:00
trem
6247c4653b mx27: add function enable_caches
Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
2013-06-26 17:34:21 +02:00
Pierre Aubert
87d720e0c2 imx: Complete the pin definitions for the i.MX6DL / i.MX6Solo
Signed-off-by: Pierre Aubert <p.aubert@staubli.com>
CC: Stefano Babic <sbabic@denx.de>
2013-06-26 16:47:30 +02:00
Pierre Aubert
7aa1e8bb1b imx6: fix GPR2 wrong definition
Signed-off-by: Pierre Aubert <p.aubert@staubli.com>
CC: Stefano Babic <sbabic@denx.de>
Acked-by: Dirk Behme <dirk.behme@gmail.com>
2013-06-26 16:28:54 +02:00
Simon Glass
d8819f94d5 x86: Support tracing function
Some changes are needed to x86 timer functions to support tracing. Add
these so that the feature works correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26 10:18:56 -04:00
Simon Glass
ca35a0cdf2 exynos: Avoid function instrumentation for microsecond timer
For tracing to work it has to be able to access the microsecond timer
without causing a recursive call to the function entry/exit handlers.
Add attributes to the relevant functions to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26 10:18:56 -04:00
Simon Glass
bce1b92aa1 arm: Implement the 'fake' go command
Implement this feature on ARM for tracing.

It would be nice to have generic bootm support so that it is easily
implemented on any arch.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-06-26 10:18:56 -04:00
Simon Glass
983c72f479 Clarify bootm OS arguments
At present the arguments to bootm are processed in a somewhat confusing
way. Sub-functions must know how many arguments their calling functions
have processed, and the OS boot function must also have this information.
Also it isn't obvious that 'bootm' and 'bootm start' provide arguments in
the same way.

Adjust the code so that arguments are removed from the list before calling
a sub-function. This means that all functions can know that argv[0] is the
first argument of which they need to take notice.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26 10:16:41 -04:00
Simon Glass
e2ee100fd8 sandbox: Support trace feature
Support tracing on sandbox by adding suitable CONFIG options. To enable it,
compile U-Boot with FTRACE=1.

The timer functions are marked to skip tracing, since these are called from
the tracing code itself, and we want to avoid an infinite loop.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26 10:16:41 -04:00
Simon Glass
bdc7d5cda3 x86: Correct missing local variable in bootm
Enabling FIT produces a compile error. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26 10:16:41 -04:00
Hung-ying Tyan
60744a1187 cros: exynos: add cros-ec device nodes to exynos5250-snow.dts
This patch adds cros-ec related device nodes to exynos5250-snow.dts.
It also adds a gpio node to exynos5250.dtsi.

Signed-off-by: Hung-ying Tyan <tyanh@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2013-06-26 10:14:34 -04:00
Rajeshwari Shinde
4603e8cf8b EXYNOS5: FDT: Add serial device node values
This patch adds the device node required for serial driver

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-06-24 20:47:41 +09:00
Mike Dunn
9dc8fef258 pxa: fix memory coherency problem after relocation
On the xscale, the icache must be invalidated and the write buffers drained
after writing code over the data bus, even if the caches are disabled.  Tested
on the pxa270.

Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
2013-06-22 15:25:28 +02:00
Mike Dunn
84c617beb2 pxa: use -mcpu=xscale compiler option
Pass '-mcpu=xscale' to the compiler instead of march and mtune.  This will cause
gcc to define the __XSCALE__ macro.

Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
2013-06-22 15:25:28 +02:00
Mike Dunn
097d86d098 pxa: turn icache off in cpu_init_crit()
The comment in the low-level initialization function cpu_init_crit() says that
the caches are being disabled, but (oddly) the icache is actually turned on.
This is probably not a good idea prior to relocating code, so this patch turns
it off.  Tested on the pxa270.

Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
2013-06-22 15:25:28 +02:00
Tom Rini
348e47f766 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-06-22 07:38:12 -04:00
Albert ARIBAUD
fbf87b1823 arm: optimize relocate_code routine
Use section symbols directly
Drop support for R_ARM_ABS32 record types
Eliminate unneeded intermediate registers
Optimize relocation table iteration

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-21 23:05:50 +02:00
Albert ARIBAUD
47bd65ef05 arm: make __rel_dyn_{start, end} compiler-generated
This change is only done where needed: some linker
scripts may contain relocation symbols yet remain
unchanged.

__rel_dyn_start and __rel_dyn_end each requires
its own output section; putting them in relocation
sections changes their flags and breaks relocation.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-21 23:05:29 +02:00
Albert ARIBAUD
d026dec875 arm: make __image_copy_{start, end} compiler-generated
This change is only done where needed: some linker
scripts may contain __image_copy_{start,end} yet
remain unchanged.

Also, __image_copy_end needs its own section; putting
it in relocation sections changes their flags and makes
relocation break.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-21 23:05:05 +02:00
Albert ARIBAUD
df84502edf arm: generalize lib/bss.c into lib/sections.c
File arch/arm/lib/bss.c was initially defined for BSS only,
but is now going to also contain definitions for other
section-boundary-related symbols, so rename it for better
accuracy.

Also, remove useless 'used' attributes.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-21 23:04:43 +02:00
Albert ARIBAUD
09d81184e1 remove all references to .dynsym
Discard all .dynsym sections from linker scripts
Remove all __dynsym_start definitions from linker scripts
Remove all __dynsym_start references from the codebase

Note: this touches include/asm-generic/sections.h, which
is not ARM-specific, but actual uses of __dynsym_start
are only in ARM, so this patch can safely go through
the ARM repository.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-21 23:04:05 +02:00
Albert ARIBAUD
c37980c31a arm: ensure u-boot only uses relative relocations
Add a Makefile target ('checkarmreloc') which
fails if the ELF binary contains relocation records
of types other than R_ARM_RELATIVE.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-21 22:59:20 +02:00
Chunhe Lan
5707233880 powerpc/85xx: Add P1023RDB board support
P1023RDB Specification:
-----------------------
Memory subsystem:
   512MB DDR3 (Fixed DDR on board)
   64MB NOR flash
   128MB NAND flash

Ethernet:
   eTSEC1: Connected to Atheros AR8035 GETH PHY
   eTSEC2: Connected to Atheros AR8035 GETH PHY

PCIe:
   Three mini-PCIe slots

USB:
   Two USB2.0 Type A ports

I2C:
   AT24C08 8K Board EEPROM (8 bit address)

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:53 -05:00
Prabhakar Kushwaha
bd7c023e48 powerpc/mpc85xx:Disable Debug TLB entry before init_tlbs
init_tlbs() initialize all the TLB entries required for the system.

So disable DEBUG TLB entry before TLB entries initialization.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:53 -05:00
Axel Lin
e51e47d38e powerpc: mpc85xx/mpc86xx: Fix off-by-one boundary checking with ARRAY_SIZE
If a variable is used as array subscript, it's valid value range is
0 ... ARRAY_SIZE -1.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:51 -05:00
Ying Zhang
67ad0d52df powerpc/mpc85xx: modify the functionality clear_bss and aligning the end address of the BSS
There will clear the BSS in the function clear_bss(), the reset address of
the BSS started from the __bss_start, and increased by four-byte increments,
finally stoped depending on the address is equal to the _bss_end. If the end
address __bss_end is not alignment to 4byte, it will be an infinite loop.

1. The reset action stoped depending on the reset address is greater
than or equal the end address of the BSS.
2. The end address of the BSS should be 4byte aligned. Because the reset unit
is 4 Bytes.

This patch is on top of the patch "powerpc/mpc85xx: support application
without resetvec segment in the linker script".

Signed-off-by: Ying Zhang <b40530@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:50 -05:00
Ying Zhang
5df572f013 powerpc/mpc85xx: support application without resetvec segment in the linker script
For SD/SPI 2-stage bootloader, the On-Chip Rom code loads the SPL into L2 SRAM,
then jump to it to begin execution. After that, the SPL loads the final uboot
image into DDR, then jump to it to begin execution. The segment .resetvec in
the SPL and in final U-boot is useless.

So, add new symbols CONFIG_SYS_MPC85XX_NO_RESETVEC for this application.
If CONFIG_SYS_MPC85XX_NO_RESETVEC is set, the segment .resetvec is excluded
and the segment .bootpg is placed in the previous 4K of the segment .text.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:50 -05:00
Scott Wood
8212519254 powerpc/mpc85xx: work around erratum A-006593
Erratum A-006593 is "Atomic store may report failure but still allow
the store data to be visible".

The workaround is: "Set CoreNet Platform Cache register CPCHDBCR0 bit
21 to 1'b1.  This may have a small impact on synthetic write bandwidth
benchmarks but should have a negligible impact on real code."

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:49 -05:00
Mingkai Hu
362ee04b79 fsl_ifc: add support for different IFC bank count
Calculate reserved fields according to IFC bank count

1. Move csor_ext register behind csor register and fix res offset
2. Move ifc bank count to config_mpc85xx.h to support 8 bank count
3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile
   error on some devices that does not have IFC controller.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:49 -05:00
Liu Gang
69fdf90010 powerpc/t4qds: Slave module for boot from SRIO and PCIE
When a T4 board boots from SRIO or PCIE, it needs to finish these processes:
	1. Set all the cores in holdoff status.
	2. Set the boot location to one PCIE or SRIO interface by RCW.
	3. Set a specific TLB entry for the boot process.
	4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
	5. Set a specific TLB entry in order to fetch ucode and ENV from
	   master.
	6. Set a LAW entry with the TargetID one of the PCIE ports for
	   ucode and ENV.
	7. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIO_PCIE_BOOT_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:49 -05:00
Liu Gang
5870fe44b2 powerpc/b4860qds: Slave module for boot from SRIO and PCIE
When a b4860qds board boots from SRIO or PCIE, it needs to finish these
processes:
	1. Set all the cores in holdoff status.
	2. Set the boot location to one PCIE or SRIO interface by RCW.
	3. Set a specific TLB entry for the boot process.
	4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
	5. Set a specific TLB entry in order to fetch ucode and ENV from
	   master.
	6. Set a LAW entry with the TargetID one of the PCIE ports for
	   ucode and ENV.
	7. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIO_PCIE_BOOT_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:48 -05:00
Liu Gang
c8b281524b powerpc/boot: Change the macro of Boot from SRIO and PCIE master module
Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable
the master module of Boot from SRIO and PCIE on a platform. But this
is not a silicon feature, it's just a specific booting mode based on
the SRIO and PCIE interfaces. So it's inappropriate to put the macro
into the file arch/powerpc/include/asm/config_mpc85xx.h.

Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to
"CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from
arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros
in configuration header file of each board which can support the
master module of Boot from SRIO and PCIE.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:48 -05:00
Andy Fleming
8bd00c9494 85xx: Change case of MPC85XX_PORBMSR_ROMLOC_SHIFT
All the other constants use lowercase 'x' in "MPC85xx", so we
duplicate that here.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 16:09:09 -05:00
Fabio Estevam
6770c5e2e8 powerpc: Use lower case for the core names
Freescale documentation presents the PowerPC core names in lower case, such as
"e300", "e500", "e600", etc.

Change the upper case occurrences into lower case so that the core names
reported in U-boot can match the ones from the documentation.

While at it also fix a checkpatch error:

ERROR: space prohibited before that close parenthesis ')'
#53: FILE: arch/powerpc/cpu/mpc86xx/cpu.c:81:
+	printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0 );

Reported-by: Heinz Wrobel <heinz.wrobel@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 16:09:09 -05:00
York Sun
061ffedaaf powerpc/BSC9132: Add IFC bank count
BSC9132 has 3 IFC banks.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 16:09:09 -05:00
Priyanka Jain
765b0bdb89 board/bsc9131rdb: Add DSP side tlb and laws
BSC9131RDB is a Freescale Reference Design Board for
BSC9131 SoC which is a integrated device that contains
one powerpc e500v2 core and one DSP starcore.

To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 memory

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 16:09:08 -05:00
Prabhakar Kushwaha
3a88179d03 powerpc/mpc85xx: new SPL support for IFC NAND
Linker script is not able find start.o binary. So add its absolute path in
u-boot-spl.lds. This change is similar to u-boot-nand.lds

common/Makefile: Avoid compiling unnecssary files

fsl_ifc_spl.c : It is is responsible for reading u-boot binary from
NAND flash and copying into DDR. It also transfer control from NAND SPL
to u-boot image present in DDR.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 16:08:58 -05:00
Prabhakar Kushwaha
74fa22ed73 powerpc/mpc85xx:No NOR boot, do not compile IFC errata A003399
IFC errata A003399 is valid for IFC NOR boot i.e.if no on-board NOR flash or
no NOR boot, do not compile its workaround.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 13:51:24 -05:00
Mingkai Hu
76d354f411 powerpc/mpc85xx: explicit cast the SDRAM size to type phys_size_t
To avoid sign extension problem, use explicit casting to cast
the SDRAM size to type phys_size_t, or else, if the SDRAM size
is 2G(0x80000000), it will be extended to 0xffffffff80000000
when phys_size_t is type 'unsigned long long'.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 13:51:24 -05:00
Andy Fleming
7dd09b546d 85xx: Change clock-frequency compatible to 2.0
Accidentally applied an earlier version of the patch, which set
the compatible to "fsl,qoriq-clockgen-2", lacking the final
".0".

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
2013-06-20 13:51:04 -05:00
Albert ARIBAUD
c2543a21df Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2013-06-19 23:58:01 +02:00
Albert ARIBAUD
69f14dc2fd Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'
Conflicts:
	spl/Makefile
2013-06-19 12:53:59 +02:00
Heiko Schocher
7ea7f689ca arm, am33xx: move uart soft reset code to common place
move uart soft reset code to common place and call
this function from board code, instead of copy and paste
this code for every board.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Matt Porter <mporter@ti.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Tom Rini <trini@ti.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Acked-by: Tom Rini <trini@ti.com>
[trini: Fix igep0033 build, remove 'regval' on pcm051]
Signed-off-by: Tom Rini <trini@ti.com>
2013-06-18 10:40:06 -04:00
Heiko Schocher
7b9c5d0bfd arm, am335x: make mpu pll config configurable
upcoming support for siemens boards switches mpu pll clk in board
code. So make this configurable.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
2013-06-18 09:18:46 -04:00
Heiko Schocher
49f7836500 arm, am33xx: move rtc32k_enable() to common place
move rtc32k_enable() to common place so all am33xx boards can use it.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Matt Porter <mporter@ti.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Tom Rini <trini@ti.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
2013-06-18 09:12:38 -04:00
Tom Rini
41341221d1 Merge branch 'master' of git://git.denx.de/u-boot-arm
Small conflict over DRA7XX updates and adding SRAM_SCRATCH_SPACE_ADDR

Conflicts:
	arch/arm/include/asm/arch-omap5/omap.h

Signed-off-by: Tom Rini <trini@ti.com>
2013-06-13 15:16:15 -04:00
Naveen Krishna Chatradhi
1149ca005a power: exynos-tmu: fix warnings and clean up code
This patch does the folowing
1. change the data types for unsigned int variable to unsigned
2. change the tmu_base type to struct exynos5_tmu_reg *
3. Add timer functionality for get_cur_temp()
4. error handling in the get_tmu_fdt_values()
5. Add check for curr_temp reading
6. some cosmotic changes.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-06-13 17:53:37 +09:00
Amar
2b81c26b7c EXYNOS5: DWMMC: Initialise the local variable to avoid unwanted results.
This patch initialises the local variable 'shift' to zero.
The uninitialised local variable 'shift' had garbage value and was
resulting in unwnated results in the functions exynos5_get_mmc_clk()
and exynos4_get_mmc_clk().

Signed-off-by: Amar <amarendra.xt@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-06-13 17:35:14 +09:00
Amar
a082a2dde0 EXYNOS5: DWMMC: Added FDT support for DWMMC
This patch adds FDT support for DWMMC, by reading the DWMMC node data
from the device tree and initialising DWMMC channels as per data
obtained from the node.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Amar <amarendra.xt@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-06-13 17:35:14 +09:00
Amar
07eb5f9ce7 EXYNOS5: FDT: Add DWMMC device node data
This patch adds DWMMC device node data for exynos5.
This patch also adds binding file for DWMMC device node.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Amar <amarendra.xt@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-06-13 17:35:13 +09:00
Sergey Yanovich
847e6693cc arm: pxa: config option for PXA270 turbo mode
PXA270 CPU has turbo mode. The mode is 2.5 times faster than the
default run mode. Activating the mode early significantly speeds
up boot process.

Signed-off-by: Sergey Yanovich <ynvich@gmail.com>
2013-06-12 22:24:12 +02:00
Scott Wood
a166fbca20 powerpc: fix 8xx and 82xx type-punning warnings with GCC 4.7
C99's strict aliasing rules are insane to use in low-level code such as a
bootloader, but as Wolfgang has rejected -fno-strict-aliasing in the
past, add a union so that 16-bit accesses can be performed.

Compile-tested only.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Wolfgang Denk <wd@denx.de>
2013-06-11 22:01:45 +02:00
Masahiro Yamada
58bb8f5f61 cosmetic: arm: fix comments in arch/arm/lib/crt0.S
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-06-10 21:24:22 +02:00
Vishwanathrao Badarkhe, Manish
68cd4a4c9f arm: da830: moved pinmux configurations to the arch tree
Move pinmux configurations for the DA830 SoCs from board file
to the arch tree so that it can be used for all da830 based devices.
Also, avoids duplicate pinmuxing in case of NAND.

Signed-off-by: Vishwanathrao Badarkhe, Manish <manishv.b@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Acked-by: Christian Riesch <christian.riesch@omicron.at>
2013-06-10 08:54:46 -04:00
Lubomir Popov
ee28edac43 OMAP5: Enable access to auxclk registers
auxclk0 and auxclk1 are utilized on some OMAP5 boards.
Define the infrastructure needed for accessing them
without using magic numbers.

Also remove unrelated TPS62361 defines from clocks.h

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
2013-06-10 08:54:46 -04:00
Tom Rini
7f5eef93af arm: Remove OMAP2420H4 and all omap24xx support
The omap2420H4 was the only mainline omap24xx board.  Prior to being
fixed by Jon Hunter in time for v2013.04 it had been functionally broken
for a very long time.  Remove this board as there's not been interest in
it in U-Boot for quite a long time.

Signed-off-by: Tom Rini <trini@ti.com>
2013-06-10 08:43:19 -04:00
Sricharan R
92b0482c17 ARM: DRA7xx: EMIF: Change settings required for EVM board
DRA7 EVM board has the below configuration. Adding the
settings for the same here.

   2Gb_1_35V_DDR3L part * 2 on EMIF1
   2Gb_1_35V_DDR3L part * 4 on EMIF2

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:10 -04:00
Lokesh Vutla
97405d843e ARM: DRA7xx: clocks: Update PLL values
Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
2013-06-10 08:43:10 -04:00
Lokesh Vutla
7f36c88f64 ARM: DRA7xx: Update pinmux data
Updating pinmux data as specified in the latest DM

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Balaji T K <balajitk@ti.com>
2013-06-10 08:43:10 -04:00
Balaji T K
a5d439c2d3 mmc: omap_hsmmc: Update pbias programming
Update pbias programming sequence for OMAP5 ES2.0/DRA7

Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:10 -04:00
Sricharan R
81ede187c3 ARM: DRA7xx: Correct SRAM END address
NON SECURE SRAM is 512KB in DRA7xx devices.
So fixing it here.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:10 -04:00
Sricharan R
f9b814a8e9 ARM: DRA7xx: Correct the SYS_CLK to 20MHZ
The sys_clk on the dra evm board is 20MHZ.
Changing the configuration for the same.
And also moving V_SCLK, V_OSCK defines to
arch/clock.h for OMAP4+ boards.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:10 -04:00
Lokesh Vutla
e9d6cd042d ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc's
Slew rate compensation cells are not present for DRA7xx
Soc's. So return from function srcomp_enable() if soc is not
OMAP54xx.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:10 -04:00
Nishanth Menon
18c9d55ac6 ARM: OMAP5: DRA7xx: support class 0 optimized voltages
DRA752 now uses AVS Class 0 voltages which are voltages in efuse.

This means that we can now use the optimized voltages which are
stored as mV values in efuse and program PMIC accordingly.

This allows us to go with higher OPP as needed in the system without
the need for implementing complex AVS logic.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:10 -04:00
Lokesh Vutla
3332b24421 ARM: DRA7xx: clocks: Fixing i2c_init for PMIC
In DRA7xx Soc's voltage scaling is done using GPI2C.
So i2c_init should happen before scaling. I2C driver
uses __udelay which needs timer to be initialized.
So moving timer_init just before voltage scaling.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:09 -04:00
Lokesh Vutla
63fc0c775c ARM: DRA7xx: power Add support for tps659038 PMIC
TPS659038 is the power IC used in DRA7XX boards.
Adding support for this and also adding pmic data
for DRA7XX boards.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:09 -04:00
Lokesh Vutla
4de28d7921 ARM: DRA7xx: Add control id code for DRA7xx
The registers that are used for device identification
are changed from OMAP5 to DRA7xx.
Using the correct registers for DRA7xx.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:09 -04:00
Lokesh Vutla
4ca94d8186 ARM: OMAP4+: pmic: Make generic bus init and write functions
Voltage scaling can be done in two ways:
-> Using SR I2C
-> Using GP I2C
In order to support both, have a function pointer in pmic_data
so that we can call as per our requirement.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:09 -04:00
Lokesh Vutla
af1d002f89 ARM: OMAP2+: Rename asm/arch/clocks.h asm/arch/clock.h
To be consistent with other ARM platforms,
renaming asm/arch-omap*/clocks.h to asm/arch-omap*/clock.h

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:09 -04:00
Sricharan R
bcdd8f72f3 ARM: OMAP5: clocks: Do not enable sgx clocks
SGX clocks should be enabled only for OMAP5 ES1.0.
So this can be removed.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:09 -04:00
Lokesh Vutla
9239f5b625 ARM: OMAP4+: Cleanup header files
After having the u-boot clean up series, there are
many definitions that are unused in header files.
Removing all those unused ones.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:09 -04:00
Lubomir Popov
e0a8c99e61 OMAP5: Fix bug in omap5_es1_prcm struct
The newly introduced function setup_warmreset_time(), called
from within prcm_init(), tries to write to the prm_rsttime
OMAP5 register. The struct member holding this register's
address is however initialized for OMAP5 ES2.0 only. On ES1.0
devices this uninitialized value causes a second (warm) reset
at startup.

Add .prm_rsttime address init to the ES1.0 struct.

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
Acked-by: Tom Rini <trini@ti.com>
2013-06-10 08:43:09 -04:00
Andrii Tseglytskyi
e69c585d76 OMAP5: add ABB setup for MPU voltage domain
Patch adds a call of abb_setup() function, and proper registers
definitions needed for ABB setup sequence. ABB is initialized
for MPU voltage domain.

Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
2013-06-10 08:43:09 -04:00
Andrii Tseglytskyi
4d0df9c1e9 OMAP3+: introduce generic ABB support
Adaptive Body Biasing (ABB) modulates transistor bias voltages
dynamically in order to optimize switching speed versus leakage.
Adaptive Body-Bias ldos are present for some voltage domains
starting with OMAP3630. There are three modes of operation:

* Bypass - the default, it just follows the vdd voltage
* Foward Body-Bias - applies voltage bias to increase transistor
  performance at the cost of power.  Used to operate safely at high
  OPPs.
* Reverse Body-Bias - applies voltage bias to decrease leakage and
  save power.  Used to save power at lower OPPs.

Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
2013-06-10 08:43:09 -04:00
Daniel Schwierzeck
e1208c2fe5 MIPS: asm/errno.h: switch to asm-generic/errno.h
This fixes several warnings like

In file included from ./u-boot/include/linux/mtd/mtd.h:13:0,
                 from env_onenand.c:37:
./u-boot/build/vct_platinumavc_onenand_small/include2/asm/errno.h:52:0: warning: "ENOMSG" redefined [enabled by default]

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-06-08 23:10:10 +02:00
Gabor Juhos
f0550f87f4 MIPS: fix __raw_* IO accessors
The purpose of the __raw* IO accessors is to provide
IO access in native-endian order. However in the current
MIPS implementation, the 16 and 32 bit variants of the
__raw accessors are swapping the values on big-endian
systems if the CONFIG_SWAP_IO_SPACE option is enabled.

The patch changes the IO accessor macros to fix this
broken behaviour.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-06-08 23:10:10 +02:00
Albert ARIBAUD
10e167329b Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Conflicts:
	drivers/serial/Makefile
2013-06-08 14:35:10 +02:00
Tom Warren
dbc000bfb5 ARM: tegra: only enable SCU on Tegra20
The non-SPL build of U-Boot on Tegra only runs on a single CPU, and
hence there is no need to enable the SCU when running U-Boot. If an
SMP OS is booted, and it needs the SCU enabled, it will enable the SCU
itself. U-Boot doing so is redundant.

The one exception is Tegra20, where an enabled SCU is required for some
aspects of PCIe to work correctly.

Some Tegra SoCs contain CPUs without a software-controlled SCU. In this
case, attempting to turn it on actively causes problems. This is the case
for Tegra114. For example, when running Linux, the first (or at least
some very early) user-space process will trigger the following kernel
message:

Unhandled fault: imprecise external abort (0x406) at 0x00000000

This is typically accompanied by that process receving a fatal signal,
and exiting. Since this process is usually pid 1, this causes total
system boot failure.

Signed-off-by: Tom Warren <twarren@nvidia.com>
[swarren, fleshed out description, ported to upstream chipid APIs]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-06-06 09:12:32 -07:00
Tom Rini
edfcf85a0a am33xx/omap4+: Move SRAM_SCRATCH_SPACE_ADDR to <asm/arch/omap.h>
The location of valid scratch space is dependent on SoC, so move that
there.  On OMAP4+ we continue to use SRAM_SCRATCH_SPACE_ADDR.  On
am33xx/ti814x we want to use what the ROM defines as "public stack"
which is the area after our defined download image space.  Correct the
comment about and location of CONFIG_SPL_TEXT_BASE.

Signed-off-by: Tom Rini <trini@ti.com>
2013-06-06 08:57:45 -04:00
Tom Rini
4596dcc1d4 am33xx/omap: Move save_omap_boot_params to omap-common/boot-common.c
We need to call the save_omap_boot_params function on am33xx/ti81xx and
other newer TI SoCs, so move the function to boot-common.  Only OMAP4+
has the omap_hw_init_context function so add ifdefs to not call it on
am33xx/ti81xx.  Call save_omap_boot_params from s_init on am33xx/ti81xx
boards.

Reviewed-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2013-06-05 08:46:49 -04:00
Tom Rini
320d9746d3 am33xx: Correct NON_SECURE_SRAM_START/END
Prior to Sricharan's cleanup of the boot parameter saving code, we
did not make use of NON_SECURE_SRAM_START on am33xx, so it wasn't a
problem that the address was pointing to the middle of our running SPL.
Correct to point to the base location of the download image area.
Increase CONFIG_SPL_TEXT_BASE to account for this scratch area being
used.  As part of correcting these tests, make use of the fact that
we've always been placing our stack outside of the download image area
(which is fine, once the downloaded image is run, ROM is gone) so
correct the max size test to be the ROM defined top of the download area
to where we link/load at.

Signed-off-by: Tom Rini <trini@ti.com>

---
Changes in v2:
- Fix typo noted by Peter Korsgaard
2013-06-04 16:32:31 -04:00
Tom Rini
0ac6db2631 omap-common/hwinit-common.c: Mark omap_rev_string as static
Only called in this file, mark as static.

Signed-off-by: Tom Rini <trini@ti.com>
2013-06-04 16:32:31 -04:00
Inderpal Singh
b5f9756f7f exynos: update tzpc to make it common for exynos4 and exynos5
This requires that cpu_is_exynos4/5 should be made available before tzpc_init.
Hence this patch also makes necessary changes to have cpu_info in spl and
invokes arch_cpu_init before tzpc_init in low_level_init.S for smdk5250.

Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-06-04 15:23:17 +09:00
Inderpal Singh
72af2fc850 exynos: move tzpc_init to armv7/exynos
tzpc_init is common for all exynos5 boards, hence move it to
armv7/exynos so that all other boards can use it.

Also update the smdk5250 Makefile and config file.

Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-06-04 15:22:10 +09:00
Marek Vasut
86fb7b3d5b arm: mxs: Fix vectoring table crafting
The vectoring table has to be placed at 0x0, but U-Boot on MX23/MX28
starts from RAM, so the vectoring table at 0x0 is not present. Craft
code that will be placed at 0x0 and will redirect interrupt vectoring
to proper location of the U-Boot in RAM.

Signed-off-by: Marek Vasut <marex@denx.de>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-06-03 12:49:50 +02:00
Alison Wang
24e8bee508 arm: vf610: Add Vybrid VF610 CPU support
This patch adds generic codes to support Freescale's Vybrid VF610 CPU.

It aligns Vybrid VF610 platform with i.MX platform. As there are
some differences between VF610 and i.MX platforms, the specific
codes are in the arch/arm/cpu/armv7/vf610 directory.

Signed-off-by: Alison Wang <b18965@freescale.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-03 10:56:53 +02:00
Alison Wang
cfd701b5f3 arm: vf610: Add IOMUX support for Vybrid VF610
This patch adds the IOMUX support for Vybrid VF610 platform.

There is a little difference for IOMUXC module between VF610 and i.MX
platform, the muxmode and pad configuration share one 32bit register on
VF610, but they are two independent registers on I.MX platform. A
CONFIG_IOMUX_SHARE_CONFIG_REG was introduced to fit this difference.

Signed-off-by: Alison Wang <b18965@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-03 10:56:53 +02:00
Albert ARIBAUD
3da0e5750b arm: factorize relocate_code routine
Replace all relocate_code routines from ARM start.S files
with a single instance in file arch/arm/lib/relocate.S.
For PXA, this requires moving the dcache unlocking code
from within relocate_code into c_runtime_cpu_setup.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Simon Glass <sjg@chromium.org>
2013-05-30 20:24:38 +02:00
Albert ARIBAUD
fa6c7413d1 arm: do not compile relocate_code() for SPL builds
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Simon Glass <sjg@chromium.org>
2013-05-30 20:24:07 +02:00
Albert ARIBAUD
a19b0dd62d Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	common/cmd_fpga.c
	drivers/usb/host/ohci-at91.c
2013-05-30 14:45:06 +02:00