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ppc4xx: Remove support for PPC405CR CPUs

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This patch removes support for the APM 405CR CPU.
This CPU is EOL and no board uses this chip.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
This commit is contained in:
Matthias Fuchs 2013-08-07 12:10:38 +02:00 committed by Tom Rini
parent fb8f4fd3af
commit 3fb8588912
13 changed files with 18 additions and 135 deletions
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10
arch/powerpc/cpu/ppc4xx/4xx_uart.c
View file

@ -17,7 +17,7 @@
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
#if defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_405EX) || defined(CONFIG_440)
@ -68,7 +68,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define UDIV_SUBTRACT 0
#define UART0_SDR SDR0_UART0
#define UART1_SDR SDR0_UART1
#else /* CONFIG_405GP || CONFIG_405CR */
#else /* CONFIG_405GP */
#define CR0_MASK 0x00001fff
#define CR0_EXTCLK_ENA 0x000000c0
#define CR0_UDIV_POS 1
@ -173,7 +173,7 @@ int get_serial_clock(void)
* Let's handle this in some #ifdef's for the SoC's.
*/
#if defined(CONFIG_405CR) || defined(CONFIG_405GP)
#if defined(CONFIG_405GP)
reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
@ -200,7 +200,7 @@ int get_serial_clock(void)
#else
clk = CONFIG_SYS_BASE_BAUD * 16;
#endif
#endif /* CONFIG_405CR */
#endif
#if defined(CONFIG_405EP)
{
@ -265,4 +265,4 @@ int get_serial_clock(void)
return clk;
}
#endif /* CONFIG_405GP || CONFIG_405CR */
#endif /* CONFIG_405GP */

18
arch/powerpc/cpu/ppc4xx/cpu.c
View file

@ -320,25 +320,9 @@ int checkcpu (void)
puts("405GP Rev. D");
break;
#ifdef CONFIG_405GP
case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
case PVR_405GP_RE:
puts("405GP Rev. E");
break;
#endif
case PVR_405CR_RA:
puts("405CR Rev. A");
break;
case PVR_405CR_RB:
puts("405CR Rev. B");
break;
#ifdef CONFIG_405CR
case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
puts("405CR Rev. C");
break;
#endif
case PVR_405GPR_RB:
puts("405GPr Rev. B");

2
arch/powerpc/cpu/ppc4xx/cpu_init.c
View file

@ -326,7 +326,7 @@ cpu_init_f (void)
* External Bus Controller (EBC) Setup
*/
#if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
#if (defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_405EX) || defined(CONFIG_405))
/*

4
arch/powerpc/cpu/ppc4xx/speed.c
View file

@ -21,7 +21,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#if defined(CONFIG_405GP) || defined(CONFIG_405CR)
#if defined(CONFIG_405GP)
void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
{
@ -1184,7 +1184,7 @@ ulong get_bus_freq (ulong dummy)
{
ulong val;
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
#if defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_405EX) || defined(CONFIG_405) || \
defined(CONFIG_440)

4
arch/powerpc/cpu/ppc4xx/start.S
View file

@ -794,7 +794,7 @@ _start:
#endif /* CONFIG_440 */
/*****************************************************************************/
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
#if defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_405EX) || defined(CONFIG_405)
/*----------------------------------------------------------------------- */
@ -1064,7 +1064,7 @@ _start:
#endif /* CONFIG_NAND_SPL */
#endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
#endif /* CONFIG_405GP || CONFIG_405 || CONFIG_405EP */
/*----------------------------------------------------------------------- */

92
arch/powerpc/include/asm/ppc405cr.h
View file

@ -1,92 +0,0 @@
/*
* (C) Copyright 2010
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _PPC405CR_H_
#define _PPC405CR_H_
#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
/* Memory mapped register */
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
/* DCR's */
#define DCP0_CFGADDR 0x0014 /* Decompression controller addr reg */
#define DCP0_CFGDATA 0x0015 /* Decompression controller data reg */
#define OCM0_ISCNTL 0x0019 /* OCM I-side control reg */
#define OCM0_DSARC 0x001a /* OCM D-side address compare */
#define OCM0_DSCNTL 0x001b /* OCM D-side control */
#define CPC0_PLLMR 0x00b0 /* PLL mode register */
#define CPC0_CR0 0x00b1 /* chip control register 0 */
#define CPC0_CR1 0x00b2 /* chip control register 1 */
#define CPC0_PSR 0x00b4 /* chip pin strapping reg */
#define CPC0_EIRR 0x00b6 /* ext interrupt routing reg */
#define CPC0_SR 0x00b8 /* Power management status */
#define CPC0_ER 0x00b9 /* Power management enable */
#define CPC0_FR 0x00ba /* Power management force */
#define CPC0_ECR 0x00aa /* edge conditioner register */
#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
#define PLLMR_FWD_DIV_BYPASS 0xE0000000
#define PLLMR_FWD_DIV_3 0xA0000000
#define PLLMR_FWD_DIV_4 0x80000000
#define PLLMR_FWD_DIV_6 0x40000000
#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
#define PLLMR_FB_DIV_1 0x02000000
#define PLLMR_FB_DIV_2 0x04000000
#define PLLMR_FB_DIV_3 0x06000000
#define PLLMR_FB_DIV_4 0x08000000
#define PLLMR_TUNING_MASK 0x01F80000
#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
#define PLLMR_CPU_PLB_DIV_1 0x00000000
#define PLLMR_CPU_PLB_DIV_2 0x00020000
#define PLLMR_CPU_PLB_DIV_3 0x00040000
#define PLLMR_CPU_PLB_DIV_4 0x00060000
#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
#define PLLMR_OPB_PLB_DIV_1 0x00000000
#define PLLMR_OPB_PLB_DIV_2 0x00008000
#define PLLMR_OPB_PLB_DIV_3 0x00010000
#define PLLMR_OPB_PLB_DIV_4 0x00018000
#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
#define PLLMR_PCI_PLB_DIV_1 0x00000000
#define PLLMR_PCI_PLB_DIV_2 0x00002000
#define PLLMR_PCI_PLB_DIV_3 0x00004000
#define PLLMR_PCI_PLB_DIV_4 0x00006000
#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
#define PLLMR_EXB_PLB_DIV_2 0x00000000
#define PLLMR_EXB_PLB_DIV_3 0x00000800
#define PLLMR_EXB_PLB_DIV_4 0x00001000
#define PLLMR_EXB_PLB_DIV_5 0x00001800
/* definitions for PPC405GPr (new mode strapping) */
#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
#define PSR_PLL_FWD_MASK 0xC0000000
#define PSR_PLL_FDBACK_MASK 0x30000000
#define PSR_PLL_TUNING_MASK 0x0E000000
#define PSR_PLB_CPU_MASK 0x01800000
#define PSR_OPB_PLB_MASK 0x00600000
#define PSR_PCI_PLB_MASK 0x00180000
#define PSR_EB_PLB_MASK 0x00060000
#define PSR_ROM_WIDTH_MASK 0x00018000
#define PSR_ROM_LOC 0x00004000
#define PSR_PCI_ASYNC_EN 0x00001000
#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
#define PSR_PCI_ARBIT_EN 0x00000400
#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
#endif /* _PPC405CR_H_ */

6
arch/powerpc/include/asm/ppc4xx-ebc.h
View file

@ -14,12 +14,12 @@
* Within this group there is a slight variation concerning the bit field
* position of the EMPL and EMPH fields:
*/
#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \
#if defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define CONFIG_EBC_PPC4xx_IBM_VER1
#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \
#if defined(CONFIG_405GP) || \
defined(CONFIG_405EP)
#define EBC_CFG_EMPH_POS 8
#define EBC_CFG_EMPL_POS 6
@ -32,7 +32,7 @@
/*
* Define the max number of EBC banks (chip selects)
*/
#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \
#if defined(CONFIG_405GP) || \
defined(CONFIG_405EZ) || \
defined(CONFIG_440GP) || defined(CONFIG_440GX)
#define EBC_NUM_BANKS 8

4
arch/powerpc/include/asm/ppc4xx.h
View file

@ -8,10 +8,6 @@
/*
* Include SoC specific headers
*/
#if defined(CONFIG_405CR)
#include <asm/ppc405cr.h>
#endif
#if defined(CONFIG_405EP)
#include <asm/ppc405ep.h>
#endif

3
arch/powerpc/include/asm/processor.h
View file

@ -894,9 +894,6 @@
#define PVR_405GP_RC 0x40110082
#define PVR_405GP_RD 0x401100C4
#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */
#define PVR_405CR_RA 0x40110041
#define PVR_405CR_RB 0x401100C5
#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */
#define PVR_405EP_RA 0x51210950
#define PVR_405GPR_RB 0x50910951
#define PVR_405EZ_RA 0x41511460

1
arch/powerpc/include/asm/u-boot.h
View file

@ -67,7 +67,6 @@ typedef struct bd_info {
unsigned int bi_baudrate; /* Console Baudrate */
#if defined(CONFIG_405) || \
defined(CONFIG_405GP) || \
defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || \
defined(CONFIG_405EZ) || \
defined(CONFIG_405EX) || \

6
common/cmd_bdinfo.c
View file

@ -92,7 +92,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
print_num("immr_base", bd->bi_immr_base);
#endif
print_num("bootflags", bd->bi_bootflags);
#if defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
#if defined(CONFIG_405EP) || \
defined(CONFIG_405GP) || \
defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
@ -106,7 +106,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
defined(CONFIG_440SPE) || defined(CONFIG_XILINX_405)
print_mhz("pci_busfreq", bd->bi_pci_busfreq);
#endif
#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */
#else /* ! CONFIG_405GP, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */
#if defined(CONFIG_CPM2)
print_mhz("vco", bd->bi_vco);
print_mhz("sccfreq", bd->bi_sccfreq);
@ -117,7 +117,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
print_mhz("cpmfreq", bd->bi_cpmfreq);
#endif
print_mhz("busfreq", bd->bi_busfreq);
#endif /* CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */
#endif /* CONFIG_405GP, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */
#ifdef CONFIG_ENABLE_36BIT_PHYS
#ifdef CONFIG_PHYS_64BIT

1
include/asm-generic/u-boot.h
View file

@ -69,7 +69,6 @@ typedef struct bd_info {
unsigned int bi_baudrate; /* Console Baudrate */
#if defined(CONFIG_405) || \
defined(CONFIG_405GP) || \
defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || \
defined(CONFIG_405EZ) || \
defined(CONFIG_405EX) || \

2
include/serial.h
View file

@ -26,7 +26,7 @@ extern struct serial_device serial_smc_device;
extern struct serial_device serial_scc_device;
extern struct serial_device *default_serial_console(void);
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
#if defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_405EX) || defined(CONFIG_440) || \
defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \