mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-03-17 23:37:01 +00:00
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
This commit is contained in:
commit
c2543a21df
13 changed files with 164 additions and 176 deletions
|
@ -149,3 +149,43 @@ int arch_misc_init(void)
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#endif
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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void rtc32k_enable(void)
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{
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struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
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/*
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* Unlock the RTC's registers. For more details please see the
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* RTC_SS section of the TRM. In order to unlock we need to
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* write these specific values (keys) in this order.
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*/
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writel(0x83e70b13, &rtc->kick0r);
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writel(0x95a4f1e0, &rtc->kick1r);
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/* Enable the RTC 32K OSC by setting bits 3 and 6. */
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writel((1 << 3) | (1 << 6), &rtc->osc);
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}
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#define UART_RESET (0x1 << 1)
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#define UART_CLK_RUNNING_MASK 0x1
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#define UART_SMART_IDLE_EN (0x1 << 0x3)
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void uart_soft_reset(void)
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{
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struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
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u32 regval;
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regval = readl(&uart_base->uartsyscfg);
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regval |= UART_RESET;
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writel(regval, &uart_base->uartsyscfg);
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while ((readl(&uart_base->uartsyssts) &
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UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
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;
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/* Disable smart idle */
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regval = readl(&uart_base->uartsyscfg);
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regval |= UART_SMART_IDLE_EN;
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writel(regval, &uart_base->uartsyscfg);
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}
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#endif
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|
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@ -246,7 +246,7 @@ static void enable_per_clocks(void)
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;
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}
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static void mpu_pll_config(void)
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void mpu_pll_config_val(int mpull_m)
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{
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u32 clkmode, clksel, div_m2;
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@ -260,7 +260,7 @@ static void mpu_pll_config(void)
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;
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clksel = clksel & (~CLK_SEL_MASK);
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clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
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clksel = clksel | ((mpull_m << CLK_SEL_SHIFT) | MPUPLL_N);
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writel(clksel, &cmwkup->clkseldpllmpu);
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div_m2 = div_m2 & ~CLK_DIV_MASK;
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@ -274,6 +274,11 @@ static void mpu_pll_config(void)
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;
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}
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static void mpu_pll_config(void)
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{
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mpu_pll_config_val(CONFIG_SYS_MPUCLK);
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}
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static void core_pll_config(void)
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{
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u32 clkmode, clksel, div_m4, div_m5, div_m6;
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@ -32,6 +32,7 @@ extern struct ctrl_stat *cstat;
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u32 get_device_type(void);
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void save_omap_boot_params(void);
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void setup_clocks_for_console(void);
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void mpu_pll_config_val(int mpull_m);
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void ddr_pll_config(unsigned int ddrpll_M);
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void sdelay(unsigned long);
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@ -41,4 +42,7 @@ void gpmc_init(void);
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void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
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u32 size);
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void omap_nand_switch_ecc(uint32_t, uint32_t);
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void rtc32k_enable(void);
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void uart_soft_reset(void);
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#endif
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|
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@ -36,37 +36,13 @@
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DECLARE_GLOBAL_DATA_PTR;
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static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
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#ifdef CONFIG_SPL_BUILD
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static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
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#endif
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/* MII mode defines */
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#define RMII_MODE_ENABLE 0x4D
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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/* UART Defines */
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#ifdef CONFIG_SPL_BUILD
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#define UART_RESET (0x1 << 1)
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#define UART_CLK_RUNNING_MASK 0x1
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#define UART_SMART_IDLE_EN (0x1 << 0x3)
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static void rtc32k_enable(void)
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{
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struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
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/*
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* Unlock the RTC's registers. For more details please see the
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* RTC_SS section of the TRM. In order to unlock we need to
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* write these specific values (keys) in this order.
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*/
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writel(0x83e70b13, &rtc->kick0r);
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writel(0x95a4f1e0, &rtc->kick1r);
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/* Enable the RTC 32K OSC by setting bits 3 and 6. */
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writel((1 << 3) | (1 << 6), &rtc->osc);
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}
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static const struct ddr_data ddr3_data = {
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.datardsratio0 = K4B2G1646EBIH9_RD_DQS,
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.datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
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@ -131,23 +107,9 @@ void s_init(void)
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/* Enable RTC32K clock */
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rtc32k_enable();
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/* UART softreset */
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u32 regval;
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enable_uart0_pin_mux();
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regval = readl(&uart_base->uartsyscfg);
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regval |= UART_RESET;
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writel(regval, &uart_base->uartsyscfg);
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while ((readl(&uart_base->uartsyssts) &
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UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
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;
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/* Disable smart idle */
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regval = readl(&uart_base->uartsyscfg);
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regval |= UART_SMART_IDLE_EN;
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writel(regval, &uart_base->uartsyscfg);
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uart_soft_reset();
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gd = &gdata;
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preloader_console_init();
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|
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@ -39,9 +39,6 @@
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DECLARE_GLOBAL_DATA_PTR;
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static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
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#ifdef CONFIG_SPL_BUILD
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static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
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#endif
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/* MII mode defines */
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#define MII_MODE_ENABLE 0x0
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@ -50,31 +47,11 @@ static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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/* UART defines */
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#ifdef CONFIG_SPL_BUILD
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#define UART_RESET (0x1 << 1)
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#define UART_CLK_RUNNING_MASK 0x1
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#define UART_SMART_IDLE_EN (0x1 << 0x3)
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/* DDR RAM defines */
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#define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */
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static void rtc32k_enable(void)
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{
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struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
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/*
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* Unlock the RTC's registers. For more details please see the
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* RTC_SS section of the TRM. In order to unlock we need to
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* write these specific values (keys) in this order.
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*/
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writel(0x83e70b13, &rtc->kick0r);
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writel(0x95a4f1e0, &rtc->kick1r);
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/* Enable the RTC 32K OSC by setting bits 3 and 6. */
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writel((1 << 3) | (1 << 6), &rtc->osc);
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}
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static const struct ddr_data ddr3_data = {
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.datardsratio0 = MT41J256M8HX15E_RD_DQS,
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.datawdsratio0 = MT41J256M8HX15E_WR_DQS,
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@ -141,22 +118,8 @@ void s_init(void)
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/* Enable RTC32K clock */
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rtc32k_enable();
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/* UART softreset */
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u32 regval;
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enable_uart0_pin_mux();
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regval = readl(&uart_base->uartsyscfg);
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regval |= UART_RESET;
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writel(regval, &uart_base->uartsyscfg);
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while ((readl(&uart_base->uartsyssts) & UART_CLK_RUNNING_MASK)
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!= UART_CLK_RUNNING_MASK)
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;
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/* Disable smart idle */
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regval = readl(&uart_base->uartsyscfg);
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regval |= UART_SMART_IDLE_EN;
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writel(regval, &uart_base->uartsyscfg);
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uart_soft_reset();
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gd = &gdata;
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|
|
|
@ -38,9 +38,6 @@
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DECLARE_GLOBAL_DATA_PTR;
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static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
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#ifdef CONFIG_SPL_BUILD
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static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
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#endif
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/* MII mode defines */
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#define MII_MODE_ENABLE 0x0
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@ -126,28 +123,7 @@ static int read_eeprom(void)
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return 0;
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}
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/* UART Defines */
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#ifdef CONFIG_SPL_BUILD
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#define UART_RESET (0x1 << 1)
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#define UART_CLK_RUNNING_MASK 0x1
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#define UART_SMART_IDLE_EN (0x1 << 0x3)
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static void rtc32k_enable(void)
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{
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struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
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/*
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* Unlock the RTC's registers. For more details please see the
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* RTC_SS section of the TRM. In order to unlock we need to
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* write these specific values (keys) in this order.
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*/
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writel(0x83e70b13, &rtc->kick0r);
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writel(0x95a4f1e0, &rtc->kick1r);
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/* Enable the RTC 32K OSC by setting bits 3 and 6. */
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writel((1 << 3) | (1 << 6), &rtc->osc);
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}
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static const struct ddr_data ddr2_data = {
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.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
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(MT47H128M16RT25E_RD_DQS<<20) |
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|
@ -330,9 +306,6 @@ void s_init(void)
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/* Enable RTC32K clock */
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rtc32k_enable();
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/* UART softreset */
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u32 regVal;
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#ifdef CONFIG_SERIAL1
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enable_uart0_pin_mux();
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#endif /* CONFIG_SERIAL1 */
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@ -352,17 +325,7 @@ void s_init(void)
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enable_uart5_pin_mux();
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#endif /* CONFIG_SERIAL6 */
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regVal = readl(&uart_base->uartsyscfg);
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regVal |= UART_RESET;
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writel(regVal, &uart_base->uartsyscfg);
|
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while ((readl(&uart_base->uartsyssts) &
|
||||
UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
|
||||
;
|
||||
|
||||
/* Disable smart idle */
|
||||
regVal = readl(&uart_base->uartsyscfg);
|
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regVal |= UART_SMART_IDLE_EN;
|
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writel(regVal, &uart_base->uartsyscfg);
|
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uart_soft_reset();
|
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|
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gd = &gdata;
|
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|
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|
|
|
@ -37,6 +37,11 @@
|
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#endif
|
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|
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#define PANDA_ULPI_PHY_TYPE_GPIO 182
|
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#define PANDA_BOARD_ID_1_GPIO 101
|
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#define PANDA_ES_BOARD_ID_1_GPIO 48
|
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#define PANDA_BOARD_ID_2_GPIO 171
|
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#define PANDA_ES_BOARD_ID_3_GPIO 3
|
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#define PANDA_ES_BOARD_ID_4_GPIO 2
|
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|
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DECLARE_GLOBAL_DATA_PTR;
|
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|
||||
|
@ -66,6 +71,73 @@ int board_eth_init(bd_t *bis)
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return 0;
|
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}
|
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|
||||
/*
|
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* Routine: get_board_revision
|
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* Description: Detect if we are running on a panda revision A1-A6,
|
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* or an ES panda board. This can be done by reading
|
||||
* the level of GPIOs and checking the processor revisions.
|
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* This should result in:
|
||||
* Panda 4430:
|
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* GPIO171, GPIO101, GPIO182: 0 1 1 => A1-A5
|
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* GPIO171, GPIO101, GPIO182: 1 0 1 => A6
|
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* Panda ES:
|
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* GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 0 1 1 => B1/B2
|
||||
* GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 1 1 1 => B3
|
||||
*/
|
||||
int get_board_revision(void)
|
||||
{
|
||||
int board_id0, board_id1, board_id2;
|
||||
int board_id3, board_id4;
|
||||
int board_id;
|
||||
|
||||
int processor_rev = omap_revision();
|
||||
|
||||
/* Setup the mux for the common board ID pins (gpio 171 and 182) */
|
||||
writew((IEN | M3), (*ctrl)->control_padconf_core_base + UNIPRO_TX0);
|
||||
writew((IEN | M3), (*ctrl)->control_padconf_core_base + FREF_CLK2_OUT);
|
||||
|
||||
board_id0 = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
|
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board_id2 = gpio_get_value(PANDA_BOARD_ID_2_GPIO);
|
||||
|
||||
if ((processor_rev >= OMAP4460_ES1_0 &&
|
||||
processor_rev <= OMAP4460_ES1_1)) {
|
||||
/*
|
||||
* Setup the mux for the ES specific board ID pins (gpio 101,
|
||||
* 2 and 3.
|
||||
*/
|
||||
writew((IEN | M3), (*ctrl)->control_padconf_core_base +
|
||||
GPMC_A24);
|
||||
writew((IEN | M3), (*ctrl)->control_padconf_core_base +
|
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UNIPRO_RY0);
|
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writew((IEN | M3), (*ctrl)->control_padconf_core_base +
|
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UNIPRO_RX1);
|
||||
|
||||
board_id1 = gpio_get_value(PANDA_ES_BOARD_ID_1_GPIO);
|
||||
board_id3 = gpio_get_value(PANDA_ES_BOARD_ID_3_GPIO);
|
||||
board_id4 = gpio_get_value(PANDA_ES_BOARD_ID_4_GPIO);
|
||||
|
||||
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
setenv("board_name", strcat(CONFIG_SYS_BOARD, "-es"));
|
||||
#endif
|
||||
board_id = ((board_id4 << 4) | (board_id3 << 3) |
|
||||
(board_id2 << 2) | (board_id1 << 1) | (board_id0));
|
||||
} else {
|
||||
/* Setup the mux for the Ax specific board ID pins (gpio 101) */
|
||||
writew((IEN | M3), (*ctrl)->control_padconf_core_base +
|
||||
FREF_CLK2_OUT);
|
||||
|
||||
board_id1 = gpio_get_value(PANDA_BOARD_ID_1_GPIO);
|
||||
board_id = ((board_id2 << 2) | (board_id1 << 1) | (board_id0));
|
||||
|
||||
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
if ((board_id >= 0x3) && (processor_rev == OMAP4430_ES2_3))
|
||||
setenv("board_name", strcat(CONFIG_SYS_BOARD, "-a4"));
|
||||
#endif
|
||||
}
|
||||
|
||||
return board_id;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief misc_init_r - Configure Panda board specific configurations
|
||||
* such as power configurations, ethernet initialization as phase2 of
|
||||
|
@ -82,11 +154,7 @@ int misc_init_r(void)
|
|||
if (omap_revision() == OMAP4430_ES1_0)
|
||||
return 0;
|
||||
|
||||
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
if (omap_revision() >= OMAP4460_ES1_0 ||
|
||||
omap_revision() <= OMAP4460_ES1_1)
|
||||
setenv("board_name", strcat(CONFIG_SYS_BOARD, "-es"));
|
||||
#endif
|
||||
get_board_revision();
|
||||
|
||||
gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO);
|
||||
phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
|
||||
|
@ -106,7 +174,7 @@ int misc_init_r(void)
|
|||
auxclk |= AUXCLK_ENABLE_MASK;
|
||||
|
||||
writel(auxclk, &scrm->auxclk3);
|
||||
} else {
|
||||
} else {
|
||||
/* ULPI PHY supplied by auxclk1 derived from PER dpll */
|
||||
debug("ULPI PHY supplied by auxclk1\n");
|
||||
|
||||
|
@ -151,9 +219,9 @@ void set_muxconf_regs_essential(void)
|
|||
|
||||
if (omap_revision() >= OMAP4460_ES1_0)
|
||||
do_set_mux((*ctrl)->control_padconf_wkup_base,
|
||||
wkup_padconf_array_essential_4460,
|
||||
sizeof(wkup_padconf_array_essential_4460) /
|
||||
sizeof(struct pad_conf_entry));
|
||||
wkup_padconf_array_essential_4460,
|
||||
sizeof(wkup_padconf_array_essential_4460) /
|
||||
sizeof(struct pad_conf_entry));
|
||||
}
|
||||
|
||||
void set_muxconf_regs_non_essential(void)
|
||||
|
@ -165,14 +233,14 @@ void set_muxconf_regs_non_essential(void)
|
|||
|
||||
if (omap_revision() < OMAP4460_ES1_0)
|
||||
do_set_mux((*ctrl)->control_padconf_core_base,
|
||||
core_padconf_array_non_essential_4430,
|
||||
sizeof(core_padconf_array_non_essential_4430) /
|
||||
sizeof(struct pad_conf_entry));
|
||||
core_padconf_array_non_essential_4430,
|
||||
sizeof(core_padconf_array_non_essential_4430) /
|
||||
sizeof(struct pad_conf_entry));
|
||||
else
|
||||
do_set_mux((*ctrl)->control_padconf_core_base,
|
||||
core_padconf_array_non_essential_4460,
|
||||
sizeof(core_padconf_array_non_essential_4460) /
|
||||
sizeof(struct pad_conf_entry));
|
||||
core_padconf_array_non_essential_4460,
|
||||
sizeof(core_padconf_array_non_essential_4460) /
|
||||
sizeof(struct pad_conf_entry));
|
||||
|
||||
do_set_mux((*ctrl)->control_padconf_wkup_base,
|
||||
wkup_padconf_array_non_essential,
|
||||
|
@ -181,9 +249,9 @@ void set_muxconf_regs_non_essential(void)
|
|||
|
||||
if (omap_revision() < OMAP4460_ES1_0)
|
||||
do_set_mux((*ctrl)->control_padconf_wkup_base,
|
||||
wkup_padconf_array_non_essential_4430,
|
||||
sizeof(wkup_padconf_array_non_essential_4430) /
|
||||
sizeof(struct pad_conf_entry));
|
||||
wkup_padconf_array_non_essential_4430,
|
||||
sizeof(wkup_padconf_array_non_essential_4430) /
|
||||
sizeof(struct pad_conf_entry));
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
|
||||
|
|
|
@ -37,49 +37,16 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
|
||||
static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
|
||||
#endif
|
||||
|
||||
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
|
||||
|
||||
/* UART Defines */
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define UART_RESET (0x1 << 1)
|
||||
#define UART_CLK_RUNNING_MASK 0x1
|
||||
#define UART_SMART_IDLE_EN (0x1 << 0x3)
|
||||
|
||||
static void rtc32k_enable(void)
|
||||
{
|
||||
struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
|
||||
|
||||
/*
|
||||
* Unlock the RTC's registers. For more details please see the
|
||||
* RTC_SS section of the TRM. In order to unlock we need to
|
||||
* write these specific values (keys) in this order.
|
||||
*/
|
||||
writel(0x83e70b13, &rtc->kick0r);
|
||||
writel(0x95a4f1e0, &rtc->kick1r);
|
||||
|
||||
/* Enable the RTC 32K OSC by setting bits 3 and 6. */
|
||||
writel((1 << 3) | (1 << 6), &rtc->osc);
|
||||
}
|
||||
|
||||
static void uart_enable(void)
|
||||
{
|
||||
u32 regVal;
|
||||
|
||||
/* UART softreset */
|
||||
regVal = readl(&uart_base->uartsyscfg);
|
||||
regVal |= UART_RESET;
|
||||
writel(regVal, &uart_base->uartsyscfg);
|
||||
while ((readl(&uart_base->uartsyssts) &
|
||||
UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
|
||||
;
|
||||
|
||||
/* Disable smart idle */
|
||||
regVal = readl(&uart_base->uartsyscfg);
|
||||
regVal |= UART_SMART_IDLE_EN;
|
||||
writel(regVal, &uart_base->uartsyscfg);
|
||||
uart_soft_reset();
|
||||
}
|
||||
|
||||
static void wdt_disable(void)
|
||||
|
|
|
@ -60,7 +60,7 @@
|
|||
"rdaddr=0x81000000\0" \
|
||||
"bootdir=/boot\0" \
|
||||
"bootfile=uImage\0" \
|
||||
"fdtfile=\0" \
|
||||
"fdtfile=undefined\0" \
|
||||
"console=ttyO0,115200n8\0" \
|
||||
"optargs=\0" \
|
||||
"mtdids=" MTDIDS_DEFAULT "\0" \
|
||||
|
@ -145,8 +145,9 @@
|
|||
"if test $board_name = A33515BB; then " \
|
||||
"setenv fdtfile am335x-evm.dtb; fi; " \
|
||||
"if test $board_name = A335X_SK; then " \
|
||||
"setenv fdtfile am335x-evmsk.dtb; fi\0" \
|
||||
|
||||
"setenv fdtfile am335x-evmsk.dtb; fi " \
|
||||
"if test $fdtfile = undefined; then " \
|
||||
"echo WARNING: Could not determine device tree to use; fi; \0"
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
|
|
|
@ -41,4 +41,7 @@
|
|||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_SYS_OMAP_ABE_SYSCK
|
||||
|
||||
#define CONSOLEDEV "ttyO0"
|
||||
|
||||
#endif /* __CONFIG_DRA7XX_EVM_H */
|
||||
|
|
|
@ -150,6 +150,7 @@
|
|||
"console=ttyO2,115200n8\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"fdtaddr=0x80f80000\0" \
|
||||
"fdtfile=undefined\0" \
|
||||
"bootpart=0:2\0" \
|
||||
"bootdir=/boot\0" \
|
||||
"bootfile=zImage\0" \
|
||||
|
@ -177,8 +178,12 @@
|
|||
"setenv fdtfile omap4-sdp.dtb; fi; " \
|
||||
"if test $board_name = panda; then " \
|
||||
"setenv fdtfile omap4-panda.dtb; fi;" \
|
||||
"if test $board_name = panda-a4; then " \
|
||||
"setenv fdtfile omap4-panda-a4.dtb; fi;" \
|
||||
"if test $board_name = panda-es; then " \
|
||||
"setenv fdtfile omap4-panda-es.dtb; fi; \0" \
|
||||
"setenv fdtfile omap4-panda-es.dtb; fi;" \
|
||||
"if test $fdtfile = undefined; then " \
|
||||
"echo WARNING: Could not determine device tree to use; fi; \0" \
|
||||
"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
|
|
|
@ -136,9 +136,10 @@
|
|||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"loadaddr=0x82000000\0" \
|
||||
"console=ttyO2,115200n8\0" \
|
||||
"console=" CONSOLEDEV ",115200n8\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"fdtaddr=0x80f80000\0" \
|
||||
"fdtfile=undefined\0" \
|
||||
"bootpart=0:2\0" \
|
||||
"bootdir=/boot\0" \
|
||||
"bootfile=zImage\0" \
|
||||
|
@ -166,7 +167,11 @@
|
|||
"bootz ${loadaddr} - ${fdtaddr}\0" \
|
||||
"findfdt="\
|
||||
"if test $board_name = omap5_uevm; then " \
|
||||
"setenv fdtfile omap5-uevm.dtb; fi;\0 " \
|
||||
"setenv fdtfile omap5-uevm.dtb; fi; " \
|
||||
"if test $board_name = dra7xx; then " \
|
||||
"setenv fdtfile dra7-evm.dtb; fi;" \
|
||||
"if test $fdtfile = undefined; then " \
|
||||
"echo WARNING: Could not determine device tree to use; fi; \0" \
|
||||
"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
|
|
|
@ -53,7 +53,9 @@
|
|||
#define CONFIG_PARTITION_UUIDS
|
||||
#define CONFIG_CMD_PART
|
||||
|
||||
#define CONFIG_SYS_PROMPT "OMAP5430 EVM # "
|
||||
#define CONFIG_SYS_PROMPT "OMAP5432 uEVM # "
|
||||
|
||||
#define CONSOLEDEV "ttyO2"
|
||||
|
||||
#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296
|
||||
#endif /* __CONFIG_OMAP5_EVM_H */
|
||||
|
|
Loading…
Add table
Reference in a new issue