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powerpc/boot: Change the macro of Boot from SRIO and PCIE master module
Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable the master module of Boot from SRIO and PCIE on a platform. But this is not a silicon feature, it's just a specific booting mode based on the SRIO and PCIE interfaces. So it's inappropriate to put the macro into the file arch/powerpc/include/asm/config_mpc85xx.h. Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to "CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros in configuration header file of each board which can support the master module of Boot from SRIO and PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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5a516748a8
commit
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9 changed files with 13 additions and 13 deletions
3
README
3
README
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@ -3975,6 +3975,9 @@ Low Level (hardware related) configuration options:
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- CONFIG_SRIO2:
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Board has SRIO 2 port available
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- CONFIG_SRIO_PCIE_BOOT_MASTER
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Board can support master function for Boot from SRIO and PCIE
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- CONFIG_SYS_SRIOn_MEM_VIRT:
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Virtual Address of SRIO port 'n' memory region
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@ -564,7 +564,7 @@ skip_l2:
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#ifdef CONFIG_SYS_SRIO
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srio_init();
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#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
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#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
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char *s = getenv("bootmaster");
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if (s) {
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if (!strcmp(s, "SRIO1")) {
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@ -24,7 +24,7 @@
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#include <asm/fsl_srio.h>
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#include <asm/errno.h>
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#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
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#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
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#define SRIO_PORT_ACCEPT_ALL 0x10000001
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#define SRIO_IB_ATMU_AR 0x80f55000
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#define SRIO_OB_ATMU_AR_MAINT 0x80077000
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@ -299,7 +299,7 @@ void srio_init(void)
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}
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}
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#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
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#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
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void srio_boot_master(int port)
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{
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struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
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@ -337,7 +337,6 @@
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#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
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#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
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#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
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#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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@ -371,7 +370,6 @@
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#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
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#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
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#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
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#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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@ -413,7 +411,6 @@
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#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
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#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
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#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
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#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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@ -449,7 +446,6 @@
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#define CONFIG_SYS_FSL_ERRATUM_USB14
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#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
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#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
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#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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@ -211,7 +211,7 @@ static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
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return 1;
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}
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#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
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#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
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static void fsl_pcie_boot_master(pit_t *pi)
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{
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/* configure inbound window for slave's u-boot image */
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@ -388,7 +388,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
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/* see if we are a PCIe or PCI controller */
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pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
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#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
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#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
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/* boot from PCIE --master */
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char *s = getenv("bootmaster");
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char pcie[6];
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@ -624,7 +624,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
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if (fsl_is_pci_agent(hose)) {
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fsl_pci_config_unlock(hose);
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hose->last_busno = hose->first_busno;
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#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
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#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
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} else {
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/* boot from PCIE --master releases slave's core 0 */
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char *s = getenv("bootmaster");
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@ -77,6 +77,7 @@
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#define CONFIG_SYS_SRIO
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#define CONFIG_SRIO1 /* SRIO port 1 */
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#define CONFIG_SRIO2 /* SRIO port 2 */
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#define CONFIG_SRIO_PCIE_BOOT_MASTER
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#define CONFIG_SYS_DPAA_RMAN /* RMan */
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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@ -40,7 +40,7 @@
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#define CONFIG_SYS_SRIO
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#define CONFIG_SRIO1 /* SRIO port 1 */
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#define CONFIG_SRIO2 /* SRIO port 2 */
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#define CONFIG_SRIO_PCIE_BOOT_MASTER
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#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
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#include "corenet_ds.h"
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@ -36,7 +36,7 @@
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#define CONFIG_SYS_SRIO
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#define CONFIG_SRIO1 /* SRIO port 1 */
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#define CONFIG_SRIO2 /* SRIO port 2 */
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#define CONFIG_SRIO_PCIE_BOOT_MASTER
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#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */
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#include "corenet_ds.h"
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@ -41,7 +41,7 @@
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#define CONFIG_SYS_SRIO
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#define CONFIG_SRIO1 /* SRIO port 1 */
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#define CONFIG_SRIO2 /* SRIO port 2 */
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#define CONFIG_SRIO_PCIE_BOOT_MASTER
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#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
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#include "corenet_ds.h"
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