Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-11 07:34:31 +00:00
Code Issues Projects Releases Packages Wiki Activity

ARM: DRA7xx: Lock DPLL_GMAC

Browse source 
Locking DPLL_GMAC

[mugunthanvnm@ti.com:Configure only if CPSW is selected]

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
This commit is contained in:
Lokesh Vutla 2013-07-08 16:04:39 +05:30 committed by Tom Rini
parent 454ac63525
commit 65e9d56fb9
4 changed files with 32 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

18
arch/arm/cpu/armv7/omap-common/clocks-common.c
View file

@ -196,6 +196,18 @@ static const struct dpll_params *get_ddr_dpll_params
return &dpll_data->ddr[sysclk_ind];
}
#ifdef CONFIG_DRIVER_TI_CPSW
static const struct dpll_params *get_gmac_dpll_params
(struct dplls const *dpll_data)
{
u32 sysclk_ind = get_sys_clk_index();
if (!dpll_data->gmac)
return NULL;
return &dpll_data->gmac[sysclk_ind];
}
#endif
static void do_setup_dpll(u32 const base, const struct dpll_params *params,
u8 lock, char *dpll)
{
@ -398,6 +410,12 @@ static void setup_dplls(void)
params = get_ddr_dpll_params(*dplls_data);
do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
params, DPLL_LOCK, "ddr");
#ifdef CONFIG_DRIVER_TI_CPSW
params = get_gmac_dpll_params(*dplls_data);
do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params,
DPLL_LOCK, "gmac");
#endif
}
#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL

11
arch/arm/cpu/armv7/omap5/hw_data.c
View file

@ -247,6 +247,16 @@ static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
{665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
};
static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
{250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */
{250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */
{119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */
};
struct dplls omap5_dplls_es1 = {
.mpu = mpu_dpll_params_800mhz,
.core = core_dpll_params_2128mhz_ddr532,
@ -283,6 +293,7 @@ struct dplls dra7xx_dplls = {
.iva = iva_dpll_params_2330mhz_dra7xx,
.usb = usb_dpll_params_1920mhz,
.ddr = ddr_dpll_params_2128mhz,
.gmac = gmac_dpll_params_2000mhz,
};
struct pmic_data palmas = {

1
arch/arm/cpu/armv7/omap5/prcm-regs.c
View file

@ -798,6 +798,7 @@ struct prcm_regs const dra7xx_prcm = {
.cm_ssc_deltamstep_dpll_ddrphy = 0x4a00522c,
.cm_clkmode_dpll_dsp = 0x4a005234,
.cm_shadow_freq_config1 = 0x4a005260,
.cm_clkmode_dpll_gmac = 0x4a0052a8,
/* cm1.mpu */
.cm_mpu_mpu_clkctrl = 0x4a005320,

2
arch/arm/include/asm/omap_common.h
View file

@ -73,6 +73,7 @@ struct prcm_regs {
u32 cm_ssc_deltamstep_dpll_ddrphy;
u32 cm_clkmode_dpll_dsp;
u32 cm_shadow_freq_config1;
u32 cm_clkmode_dpll_gmac;
u32 cm_mpu_mpu_clkctrl;
/* cm1.dsp */
@ -483,6 +484,7 @@ struct dplls {
const struct dpll_params *iva;
const struct dpll_params *usb;
const struct dpll_params *ddr;
const struct dpll_params *gmac;
};
struct pmic_data {