Commit graph

3979 commits

Author SHA1 Message Date
Biju Das
40ac794524 arm: dts: rmobile: r8a774e1: Synchronize DTs with Linux 5.11
Synchronize r8a774e1 device trees with Linux 5.11,
commit f40ddce88593482919 ("Linux 5.11").

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
2021-03-16 20:09:29 +01:00
Biju Das
2141203f58 arm: dts: rmobile: r8a774b1: Synchronize DTs with Linux 5.11
Synchronize r8a774b1 device trees with Linux 5.11,
commit f40ddce88593482919 ("Linux 5.11")

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
2021-03-16 20:09:29 +01:00
Tom Rini
e8a10a02bd - Add WATCHDOG_RESET() in MTD framework and STM32 QSPI driver
- stm32mp1_trusted_defconfig rely on SCMI support
 - Remove the nand MTD configuration for NOR boot in stm32mp1 board
 - STM32programmer update
 - Bsec: manage clock when present in device tree
 - stm32mp15: move bootdelay configuration in defconfig
 - Update for stm32 dsi and dw_mipi_dsi
 - STM32 MCU's cleanup
 - Fix compilation issue depending on SYS_DCACHE_OFF and SYS_ICACHE_OFF flags
 - Update stm32mp1 doc
 -----BEGIN PGP SIGNATURE-----
 
 iQJQBAABCgA6FiEEXyrViUccKBz9c35Jysd4L3sz/6YFAmBLfA8cHHBhdHJpY2Uu
 Y2hvdGFyZEBmb3NzLnN0LmNvbQAKCRDKx3gvezP/pkNnD/4hQrwBdaJMz9YXL4Tp
 0W7kpCcTkG+gINY06BONNnKzBHq62SkWMo/lw9iF0nlcNKSOHzrz6ttm+e54ngs0
 qe/dn0yjgImDfr5p5JRMTG1m7/XwQpucZ8wowSZAwt5f/DDh9eta9AyST0ev+iXI
 Eqgbk5HsF2OCOK6h74FJidZUdLMLw+uQkIwPhglx3ZaxxFfXHAdWtXtJ9Fky2adU
 BC0PltvJ6KYl1LTUGCQvrCST1sNe1PXPHrcsUpsQnqUSZ65tGKgeH2On9Exsw6cE
 eA5v0aiQSMmAH2pYXrJwxhSW9b03yt3NdBQd09Du2YUuFe7yZeoWIFy8mM9jRaov
 QDe88aJ9ZjxB+TvYQPToEL0EIyBGkN3HnX05BtKzKLf+E2+wP6gEf/6Sob7fBf6n
 3n2Eud0COfe06hNiocYOHm8n/8bZxdmuEgMA8LU0PZETbH33NlvJtrjyBxY4OHOV
 G+RG6J8idpVWWQ69g2TqfsVhXSjF893nvLOu0+KjuNrZWG4BVxGjylVUSvayk7bG
 TI++ZKlbdvJGweZ3uUPcNLH4VaX47P/nZS/6vX1uL7NtRNvv3jLHN5z4t6zKI9rh
 3iTJxxVv3zilWcY1WsoSdUvK56RTubnNwUlpjriabdRwMDjMN0isL9N06PvOELoi
 jU1IkKBLtMvPbb2XfLRIjvQjTQ==
 =nIJc
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-stm32-20210312' of https://source.denx.de/u-boot/custodians/u-boot-stm

- Add WATCHDOG_RESET() in MTD framework and STM32 QSPI driver
- stm32mp1_trusted_defconfig rely on SCMI support
- Remove the nand MTD configuration for NOR boot in stm32mp1 board
- STM32programmer update
- Bsec: manage clock when present in device tree
- stm32mp15: move bootdelay configuration in defconfig
- Update for stm32 dsi and dw_mipi_dsi
- STM32 MCU's cleanup
- Fix compilation issue depending on SYS_DCACHE_OFF and SYS_ICACHE_OFF flags
- Update stm32mp1 doc
2021-03-15 08:43:19 -04:00
Etienne Carriere
3d15245502 ARM: dts: stm32mp1: explicit clock reference needed by RCC clock driver
Define in the RCC clock provider node which root clocks the driver
depends on. These are root oscillators, which may be present or
not, upon FDT content.

This update binding is introduced in Linux kernel device tree by patch
"ARM: dts: stm32: move clocks/resets to SCMI resources for stm32mp15"

This patch is a preliminary step for SCMI support of stm32mp15
boards with trusted boot chain, based on TF-A or OP-TEE.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-03-11 17:03:19 +01:00
Siew Chin Lim
ae99131bf4 arm: socfpga: dts: soc64: Update filename in binman node of FIT image with VAB support
FIT image of Vendor Authentication Coot (VAB) contains signed images.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-03-08 10:59:10 +08:00
Tim Harvey
03bf8436a3 board: gateworks: imx8mm: Add Gateworks Venice board support
Add initial support for Gateworks Venice product family based on the
i.MX 8M Mini SoC

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-03-03 14:15:02 +01:00
Tim Harvey
5db93abe33 arm: dts: imx8mm: add Gateworks i.MX8 Mini Dev kits
Add Gateworks i.MX 8M Mini Development kits from Linux-5.12-rc1

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-03-03 14:15:02 +01:00
Fabio Estevam
5d42ea5535 ARM: dts: imx8mq-evk: Remove u-boot,off-on-delay-us property
Commit 247bbeb74c ("ARM: dts: imx8m: increase off-on delay on the SD Vcc
regulator") caused the imx8mq-evk board to not be able to store the
environment variables in the SD card.

Remove the u-boot,off-on-delay-us property to fix the regression.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
2021-03-01 10:21:36 +01:00
Ye Li
f19d1a946c arm: dts: imx8mp-evk: Add FEC PHY reset timing
Add phy-reset-duration and phy-reset-post-delay to FEC node for PHY
reset, otherwise the PHY does not work correctly.

Signed-off-by: Ye Li <ye.li@nxp.com>
2021-03-01 10:21:36 +01:00
Fabio Estevam
23013aa961 mx23evk: Convert to driver model
Make the conversion to driver model as it is mandatory.

Successfully tested booting Linux from the SD card.

Dropped splash screen support as this needs to be properly
converted to DM and tested.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2021-03-01 10:21:36 +01:00
Fabio Estevam
c6f2b4cabf mx23-evk: Import devicetree file from Linux
Import the imx23-evk devicetree files from Linux kernel
version 5.11.

This is in preparation for converting the mx23evk_defconfig
target to driver model.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2021-03-01 10:21:36 +01:00
Fabio Estevam
07fc671d7e mx51evk: Convert to driver model
Make the conversion to driver model as it is mandatory.

Tested booting the Linux kernel from the SD card.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2021-03-01 10:21:36 +01:00
Fabio Estevam
1f3b3e7919 imx51-babbage: Import devicetree files from Linux
Import the imx51-babbage devicetree files from Linux kernel
version 5.11-rc7.

This is in preparation for converting the mx51evk_defconfig
target to driver model.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2021-03-01 10:21:36 +01:00
Fabio Estevam
21755161b2 ARM: dts: imx53-qsb: Describe the esdhc1 card detect pin
The micro SD card slot uses GPIO3_13 as card detect pin, so describe
it in the devicetree.

This was noticed when converting imx53-qsb board to driver model
in U-Boot as the micro SD card was not getting detected.

After this change it is possible to load the dtb and zImage
from the SD card and boot Linux.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2021-03-01 10:21:36 +01:00
Fabio Estevam
5c8db4922d mx53loco: Convert to driver model
Make the conversion to driver model as it is mandatory.

Remove the SATA support for now as the i.MX53 support has not
been added yet.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2021-03-01 10:21:36 +01:00
Fabio Estevam
a48c22bc52 imx53-qsb: Import devicetree files from Linux
Import the imx53-qsb devicetree files from Linux kernel
version 5.11-rc7.

This is in preparation for converting the mx53loco_defconfig
target to driver model.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2021-03-01 10:21:36 +01:00
Oleksandr Suvorov
91026456f4 board: toradex: move RGMII delays to PHY side
The RGMII link delays can be set on either MAC or PHY side. Set the
rgmii-id PHY mode for FEC and remove FEC_ENET_ENABLE_.XC_DELAY
setting, so that these definitions aren't used anymore throughout
the U-Boot.

Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-03-01 10:21:36 +01:00
Tom Rini
a3c6d287ba - Add USB host boot support in stm32mp1 config
- Enable uefi related commands for STMicroelectronics STM32MP15 boards
 - Remove duplicate uart nodes in stm32mp15 device tree
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCgAdFiEE56Yx6b9SnloYCWtD4rK92eCqk3UFAmA5DRwACgkQ4rK92eCq
 k3WKtQf+Nk2N8XzhKgoz4dfg+A/uZ1ppKiuuYfHWitvw9OLrjGO61MnYOc6Dh7De
 LchPExBYnatj3lxu3IEaaNUGJRujnt9n3W8JNQTGB81MI1TO2oITEhAyDqpMGtqt
 pvr1NaoxhZM4B7n/HoQnVB+XtlP08w45SQiEXjjaO82hWRk45sAZ7WGFSs60iVck
 ocqhrJ/2AraG98JQPxWfvdqr+24gl1Gt++KT/cdHS//IeYJJYuiCD3m9vOj8TatH
 gDVbfR6tquZ5HLvKr/orRz3smaCuutWdHcDwcjs3kFK1rBHSYFZhG3qHQ3ZqNm+w
 T/7JIqz4W366o7QZXXlCoi56w2tpug==
 =f/Cg
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-stm32-20210226' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- Add USB host boot support in stm32mp1 config
- Enable uefi related commands for STMicroelectronics STM32MP15 boards
- Remove duplicate uart nodes in stm32mp15 device tree
2021-02-26 12:41:06 -05:00
Patrick Delaunay
1a1a47cdba arm: dts: stm32mp15: remove duplicate uart nodes
Remove duplicated uart nodes introduced with commit 62f95af92a
("ARM: dts: stm32mp1: DT alignment with Linux kernel v5.9-rc4"),
because the uart nodes wasn't correctly ordered in alphabetic order.

Only cosmetic: the generated device tree don't change.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-02-26 15:44:58 +01:00
Marek Behún
2ca5b190c3 ARM: dts: armada-385-turris-omnia: rename node in -u-boot.dtsi file
The SPI NOR flash node name in main device tree for Turris Omnia is
called `spi-nor@0`.

Rename node spi-flash@0 in Turris Omnia's -u-boot.dtsi file to spi-nor@0
so that U-Boot does not try to probe the same SPI NOR device multiple
times.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Pali Rohár <pali@kernel.org>
2021-02-26 10:22:29 +01:00
Tom Rini
bced796e2d Merge tag 'ti-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti
- Fix ethernet on J721e
- Sync am335x DT nodes from Linux 5.9-rc7
- Minor Clock fixes
2021-02-22 09:12:04 -05:00
Dario Binacchi
252ee3c5b9 arm: dts: sync am33xx-clocks with Linux 5.9-rc7
The commit 6337d53fdf ("arm: dts: sync am33xx with Linux 5.9-rc7")
synchronized the am33xx-clocks.dtsi file with Linux 5.9-rc7 with the
exception of two nodes. I think I was wrong and it is better to keep
the two files similar and possibly make changes to the *-u-boot.dtsi
files.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-02-22 11:39:48 +05:30
Alex Marginean
cc32fd911a arm: dts: ls1028a: Add Ethernet switch node and dependencies
The definition follows the DSA binding in kernel and describes the switch,
its ports and PHYs.  The switch node has the same structure as in Linux
and this patch enables it (and relevant ports) for the LS1028A RDB board.

ENETC PF6 is the 2nd Eth controller linked to the switch on LS1028A, it is
not used in U-Boot and was disabled.  Ethernet port aliases were also
added to better manage the multitude of ports available now.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
2021-02-16 12:38:36 -05:00
Dario Binacchi
f43d9e904d arm: dts: sync am33xx gpio nodes with Linux 5.9-rc7
Move gpio controller nodes from am33xx.dtsi to am33xx-l4.dtsi. Now both
files are more similar to those found in Linux 5.9-rc7. To be fully
operational as before it was also necessary to fix the am33xx-clock.dtsi
file. It too is now almost the same as the Linux kernel.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-02-16 10:30:11 +05:30
Vignesh Raghavendra
1e8f246563 ARM: dts: k3-j7200-common-proc-board-u-boot: Fix broken ethernet
Since commit 6239cc8c4e ("arm: dts: k3-j7200: Sync Linux v5.11-rc6 dts
into U-Boot") ranges have been added to CPSW node which results in
U-Boot CPSW driver failing to acquire phy_gmii_sel register range and
thus failing to configure GMII mode correctly.

Fix this by deleting ranges in -u-boot-dtsi just like its done for other
K3 platforms.

Fixes: 6239cc8c4e ("arm: dts: k3-j7200: Sync Linux v5.11-rc6 dts into U-Boot")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-02-16 10:29:57 +05:30
Tom Rini
22924317be arm: Remove db-88f6281-bp board
This board has not been converted to CONFIG_DM_MMC by the deadline of
v2019.04, which is almost two years ago.  In addition there are other DM
migrations it is also missing.  Remove it.

Cc: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Chris Packham <judge.packham@gmail.com>
2021-02-15 10:11:38 -05:00
Tom Rini
7c82e12cc4 First set of u-boot-atmel fixes for 2021.04 cycle
-----BEGIN PGP SIGNATURE-----
 
 iQFQBAABCgA6FiEEqxhEmNJ6d7ZdeFLIHrMeAg6sL8gFAmAmOowcHGV1Z2VuLmhy
 aXN0ZXZAbWljcm9jaGlwLmNvbQAKCRAesx4CDqwvyGEpB/oD2ZQdqY/kfu0SlKE6
 2Qor+MSwDA8yQlAKfiX2J3x0sAaGNkeUPQrWLxutACd34MJsjG41sr6uvLwu4E9f
 bc91Gk1Xv/kmySi7JPfpctb01Bd1GVpzuHELIumGgYRkNSwAFFaXrqVPxr/9cN3t
 dEcfbKX0p4qXUv/TDw3tE1D63dYPIJC3yX0/4n/n824AKeqRyTMVC34rjfEOoE/r
 0w6YSxwQ8hlh23xwc2tyEMSKR4jNp8mAtQcl03Gi/6xiaqgH6lQ6ardSblr3qvjW
 6Ev1nd3f9d8i0CzipbLH6PL4G31Ft+ZG/Z/z8wqA6w15h29wu7CfV8yC0aBV0g0/
 N1ko
 =7ddr
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-atmel-fixes-2021.04-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel

First set of u-boot-atmel fixes for 2021.04 cycle:

This small PR includes just two fixes but very important: one revert in
the clk subsystem which fixes the boot on many old boards
(sama5d2_xplained, sama5d4_xplained), which currently crash at boot; and
one small fix related to debug serial on sama7g5ek board.
2021-02-12 09:09:10 -05:00
Eugen Hristev
5dc68b07e7 ARM: dts: at91: sama7g5ek: enable pull-up for serial debug line
If the serial tx/rx are floating, it can happen that bogus characters
are detected on the line at boot time. This leads to U-boot accidentally
thinking someone pressed a key to stop autoboot, thus stopping booting process.
This can happen if the serial cable is not connected. There are hardware
pull-ups on the board connected to serial cable VBUS.
To solve this when the cable is not plugged, enable internal pull-ups as well
for the tx/rx lines.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-02-11 09:26:40 +02:00
Patrick Delaunay
db8fb2ffc4 usb: dwc2: change compatible st,stm32mp1-hsotg to st,stm32mp15-hsotg
The Linux kernel v5.7-rc1 introduced the compatible "st,stm32mp15-hsotg".

See Linux kernel commit d49850110434 ("dt-bindings: usb: dwc2: add
support for STM32MP15 SoCs USB OTG HS and FS")

This patch updates the supported compatible in DWC2 driver,
removes the add-on done in U-Boot dtsi and keeps the compatible
defined in SOC dtsi arch/arm/dts/stm32mp151.dtsi:

usbotg_hs: usb-otg@49000000 {
	compatible = "st,stm32mp15-hsotg", "snps,dwc2";
	reg = <0x49000000 0x10000>;
...
};

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-02-10 22:23:35 +01:00
Tom Rini
c7182c02ce - Add configuration helpers for MIPI D-PHY
- generic-phy: add configure op
 - Add Amlogic AXG MIPI D-PHY driver & MIPI PCIe Analog PHY driver
 - odroid: add runtime detection of the N2/N2+/C4/HC4 variants
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAmAjoVAACgkQd9zb2sjI
 SdELKxAAjFUrK6TmfTwiEFXZyZxl7BPvGCRmlvS/lomWu2LRbV3kqE759Spe9SsQ
 e/xm7tmM3M+R2SP71dPkc9glyopSIR7OjsAkJgfp/XI1pQDJwo4D1RWFEFwPevLo
 APA5OznivUyN0nKMCttYlbdq0PefpNOJ6HKAWBW2IZCMmMo4IspcvEyZsQcynqQU
 J6ftHFLK+uCEGErnePJgHenE8sjnx5ZX/dbupbiHvnQAvul0WxZSr3ENON13DYid
 smcTBeGxdJvLEcfkwvBKvgr2oQHJWq+9X3hGhjp19KfNz/cEz2TJKLn2usSNgTM4
 UhZFYPVuQEuCvrP+ckjd9vHBxDRTb/13xB61X/QaqK6QwkAfqjTJTvMKdBZJl2jI
 6J/52CppxGbvpckh4gNcfAvaonqMWSyVWk6lR+IX2ir4w/f8e2Yj3DlwtgzLj7s3
 ORqc/l/uPXC7JffpJon1pooPHRK6e2eyQKgggWkimaMmC0NJsTG2nKOpN/EQ+fpW
 /+g9G8bLu1/lrAtV6U81NenHvvoQi6OmKQ78PJDfAoGifvGwm0172PT55v5VABcI
 KRi9leX01x2IvlJurgZGPCjgk97sn/nOWreYC/Kfrnn7U/5kg8a1joSXLt3Uicup
 Ag3xIjX3Ux1h1KTB7fc7Xu2nLS45wmiLto0j1BDxikJI2MVdbME=
 =5X7F
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-amlogic-20210210' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- Add configuration helpers for MIPI D-PHY
- generic-phy: add configure op
- Add Amlogic AXG MIPI D-PHY driver & MIPI PCIe Analog PHY driver
- odroid: add runtime detection of the N2/N2+/C4/HC4 variants
2021-02-10 07:56:57 -05:00
Marek Szyprowski
8bc780106c board: amlogic: odroid: add runtime detection of the N2/N2+/C4/HC4 variants
Use the ADC channel 1 to check the hardware revision of the board and
detect the N2 vs. N2+ and the C4 vs. HC4 variants. Each of them use
different dtb file, so adjust fdtfile environment variable to the
detected variant.

The ADC min/max values for each variant are taken from the vendor code,
adjusted to the 12-bit ADC driver operation mode (vendor code use 10-bit
mode).

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-02-10 10:00:51 +01:00
Patrick Delaunay
f050e3fe45 arm: dts: stm32mp15: alignment with v5.11-rc2
Device tree alignment with Linux kernel v5.11-rc2
- fix DCMI DMA features on stm32mp15 family
- Add alternate pinmux for FMC EBI bus
- Harmonize EHCI/OHCI DT nodes name on stm32mp15
- update sdmmc IP version for STM32MP15
- Add LP timer irqs on stm32mp151
- Add LP timer wakeup-source on stm32mp151
- enable HASH by default on stm32mp15
- enable CRC1 by default on stm32mp15
- enable CRYP by default on stm32mp15
- set bus-type in DCMI endpoint for stm32mp157c-ev1 board
- reorder spi4 within stm32mp15-pinctrl
- add STUSB1600 Type-C using I2C4 on stm32mp15xx-dkx
- fix mdma1 clients channel priority level on stm32mp151
- fix dmamux reg property on stm32mp151
- adjust USB OTG gadget fifo sizes in stm32mp151
- update stm32mp151 for remote proc synchronization support
- support child mfd cells for the stm32mp1 TAMP syscon

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-02-09 10:56:06 +01:00
Fabrice GIRARDOT
2220c2e84d ARM: dts: stm32: Fix cosmetic typo: use 'kHz' as kilohertz abbreviation
The kilohertz unit abbreviation should read 'kHz'.
Note to STM32 team: modified files were generated, it may be worth
to fix STM32CubeMX tool.

Signed-off-by: Fabrice GIRARDOT <fabrice.girardot@flowbird.group>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-02-09 10:35:39 +01:00
Tom Rini
a10d06add7 Merge git://git.denx.de/u-boot-fsl-qoriq
Layerscape: Enable gpio
Bug fixes & updates related to dspi, qspi, pciep, SVR mask,
stream-id, env variables, mdio for LAyerscape Platforms
Add SATA, network variant 1, 2 support on sl28
powerpc: T1042: drop CONFIG_VIDEO, Add kmcent2 board supporrt, keymile
Bug fixes and updates for keymile, Kontron
2021-02-08 10:55:28 -05:00
Biwen Li
eeeab2750e arm64: dts: ls208xa: add gpio node
Add gpio node for SoC LS208xA

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:20 +05:30
Biwen Li
d62cbea84a arm64: dts: ls1088a: add gpio node
Add gpio node for SoC LS1088A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:20 +05:30
Biwen Li
b7ddedfab5 arm64: dts: ls1046a: add gpio node
Add gpio node for SoC LS1046A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:20 +05:30
Biwen Li
b609f1ad04 arm64: dts: ls1043a: add gpio node
Add gpio node for SoC LS1043A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:20 +05:30
Biwen Li
f9428d761b arm64: dts: ls1028a: add gpio node
Add gpio node for SoC LS1028A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:19 +05:30
Biwen Li
5609300521 arm64: dts: ls1012a: add gpio node
Add gpio node for SoC LS1012A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:19 +05:30
Biwen Li
2b3393cb3c arm: dts: ls1021a: add gpio node
Add gpio node for SoC LS1021A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:19 +05:30
Michael Walle
805b2423b4 board: sl28: add SATA support
Enable SATA support. Although not supported by the usual SATA pins on
the SMARC baseboard connector, SATA mode is supported on a PCIe lane.
This way one can use a mSATA card in a Mini PCI slot.

We need to invert the received data because in this mode the polarity of
the SerDes lane is swapped. Provide a fixup in board_early_init_f() for
the SPL. board_early_init_f() is then not common between SPL and u-boot
proper anymore, thus common.c is removed, as it just contained said
function.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:16 +05:30
Michael Walle
b463010be0 board: sl28: add network variant 2 support
Although this variant has two external network ports, they are not (yet)
supported by the bootloader because they are connected via an internal
network switch. Otherwise its the same as the other variants.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:16 +05:30
Michael Walle
4029d356e6 board: sl28: add network variant 1 support
This variant has one network port connected via RGMII and doesn't have
any TSN capabilities out-of-the-box. Instead it has all four SerDes
lanes available for customer use.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:15 +05:30
Michael Walle
feed9008b3 board: sl28: move ethernet aliases to variant specific dtsi
The variants differ in their network configuration. Move the first two
network aliases to the proper variant device tree includes. This is in
prepartion for variant 1 and 2 support which has a different network
port mapping. The network aliases for the two internal ports will stay
in the common dtsi because they are present on all board variants.

This might leave a hole if there is no ethernet1 alias. This is
intended.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:15 +05:30
Zhao Qiang
905c8e649e armv8: dts: fsl-lx2162a: add dspi node into qds dts
Add dspi node into lx2162aqds device tree

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:15 +05:30
Wasim Khan
cbfa8f7c7a armv8: lx2162aqds: disable non existing pcie controllers
disable non existing pcie controllers on lx2162aqds

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:15 +05:30
Adam Ford
0099dfd5e5 ARM: rmobile: Add Beacon EmbeddedWorks RZG2H Dev Kit
The Beacon EmbeddedWorks kit is based on the R8A774E1 SoC also
known as the RZ/G2H.

The kit consists of a SOM + Baseboard and supports microSD,
eMMC, Ethernet, a couple celular radios, two CAN interfaces,
Bluetooth and WiFi.  It shares much of the same design as
the RZ/G2M and RZ/G2N dev kits.

Signed-off-by: Adam Ford <aford173@gmail.com>
2021-02-07 21:12:57 +01:00
Adam Ford
6001b49920 ARM: rmobile: Add Beacon EmbeddedWorks RZG2N Dev Kit
The Beacon EmbeddedWorks kit is based on the R8A774B1 SoC also
known as the RZ/G2N.

The kit consists of a SOM + Baseboard and supports microSD,
eMMC, Ethernet, a couple celular radios, two CAN interfaces,
Bluetooth and WiFi.  It shares much of the same design as
the RZ/G2M dev kit.

Signed-off-by: Adam Ford <aford173@gmail.com>
2021-02-07 21:12:57 +01:00
Adam Ford
2b6cf2e94d arm: dts: r8a774b1: Import DTS queued for Linux 5.12-rc1
Update the RZ/G2N dtsi from Renesas repo destined to become 5.12-rc1.

Signed-off-by: Adam Ford <aford173@gmail.com>
2021-02-07 21:12:57 +01:00
Adam Ford
70266e1c18 arm: dts: r8a774e1: Import DTS queued for Linux 5.12-rc1
Update the RZ/G2H dtsi from Renesas repo destined to become 5.12-rc1.

Signed-off-by: Adam Ford <aford173@gmail.com>
2021-02-07 21:12:57 +01:00
Adam Ford
b2c86f596c arm: dts: r8a774a1: Import DTS queued for Linux 5.12-rc1
Update the RZ/G2M dtsi and r8a774a1-beacon-rzg2m-kit kit
from Renesas repo destined to become 5.12-rc1.

Signed-off-by: Adam Ford <aford173@gmail.com>
2021-02-07 21:12:57 +01:00
Lokesh Vutla
6239cc8c4e arm: dts: k3-j7200: Sync Linux v5.11-rc6 dts into U-Boot
Sync all J7200 related v5.11-rc6 Linux kernel dts into U-Boot.
MCU R5F nodes are not yet added in Linux kernel yet but were added
in U-Boot. In order to avoid regressions, r5f nodes are kept intact.
These will be added in kernel in future.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-02-04 20:37:57 +05:30
Lokesh Vutla
70e167495a arm: dts: k3-j721e: Sync Linux v5.11-rc6 dts into U-Boot
Sync all J721e related v5.11-rc6 Linux kernel dts into U-Boot.
HBMC nodes are not yet added in Linux kernel yet but were added
in U-Boot. In order to avoid any regressions, hbmc nodes are kept
intact. These will be added in kernel in future.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-02-04 20:37:57 +05:30
Lokesh Vutla
e497876343 arm: dts: k3-am65: Sync Linux v5.11-rc6 dts into U-Boot
Sync all AM65 related v5.11-rc6 Linux kernel dts into U-Boot.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-02-04 20:37:57 +05:30
Faiz Abbas
9aa4302c02 arm: dts: k3-am654-base-board: Limit Sd card to High speed modes
There's an issue with the base board in which the power cycle
circuit takes way longer to power down than expected by mmc core.
code. This prevents the card from enumerating in UHS modes.

Disable UHS modes for this board until a new board revision fixes
the issue.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-02-04 20:37:57 +05:30
Faiz Abbas
0758e9fe3f arm: dts: k3-am65-main: Add itapdly and clkbuf-sel values
Add the appropriate itapdly and clkbuf-sel values required for
some lower speed modes.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-02-04 20:37:57 +05:30
Faiz Abbas
b4e85ca0ba arm: dts: k3-j7200-common-proc-board: Enable support for UHS modes
Add support for UHS modes by adding the regulators to power cycle
and voltage switch the card. Also add pinmuxes required for each
node

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-02-04 20:37:57 +05:30
Faiz Abbas
f695347066 arm: dts: k3-j7200-main: Add support for gpio0
Add support for the main_gpio0 node

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-02-04 20:37:57 +05:30
Faiz Abbas
f0a496a3d2 arm: dts: k3-j721e-common-proc-board: Add support for UHS modes for SD card
Add support for regulators to power cycle and switch IO voltage to the
SD card. This enables support for UHS modes.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-02-04 20:37:57 +05:30
Faiz Abbas
52de3c324d arm: dts: k3-j721e-main: Update otap-delay values
Update otap delay values to match with the latest Data Manual[1].

[1] https://www.ti.com/lit/gpn/dra829v

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-02-04 20:37:57 +05:30
Faiz Abbas
2121c7e2d5 arm: dts: k3-am65: Fix mmc nodes
Because of fundamental interface issues in am65x pg1, only the
initial sdhci1 node at 25 MHz was added in the u-boot.dtsi
from which both the base-board.dts and r5-base-board.dts
inherit the node. Move the node out to k3-am65-main.dtsi
where it belongs and add the board specific properties
in base-board.dts and r5-base-board.dts

This ensures dts compatibility with the kernel dts in the
base-board.dts and enables the SD card interface at 50 MHz
and High Speed mode

While we are here, also fix the main_mmc0_pins_default
property to be included and inherit from the base-board.dts
instead of the u-boot.dtsi

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-02-04 20:37:57 +05:30
Suman Anna
468ec2f3ef remoteproc: k3_r5: Sync to upstreamed kernel DT property names
The K3 R5F remoteproc driver in U-Boot was upstreamed prior to the
equivalent remoteproc driver in the Linux kernel. Some of the DT
properties used in U-Boot got upstreamed using different names
in Linux kernel.

The modified property names include the R5F cluster mode configuration
property "lockstep-mode"; and three different individual R5F core config
properties - "atcm-enable", "btcm-enable" and "loczrama". The property
names were updated as follows:
  lockstep-mode => ti,cluster-mode
  atcm-enable   => ti,atcm-enable
  btcm-enable   => ti,btcm-enable
  loczrama      => ti,loczrama

Update the K3 R5F remoteproc driver, the corresponding binding, and
all the existing usage in AM65x, J721E and J7200 dts files all at
once to use the new properties and to not break any bisectability.

Signed-off-by: Suman Anna <s-anna@ti.com>
2021-02-04 20:37:56 +05:30
Biju Das
32568ee5b9 arm: dts: rmobile: r8a774a1: Synchronize DTs with Linux 5.10
DTS files apart from r8a774a1-hihope-rzg2m-u-boot.dts and
r8a774a1-u-boot.dtsi have been imported from linux 5.10
commit 2c85ebc57b3e1817 ("Linux 5.10").

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
2021-01-31 14:08:45 +01:00
SkyLake.Huang
3f1250a9e2 arm: dts: enable MTK SPI NOR controller driver
1. Enable MTK SPI NOR controller driver on mt7622 & mt7629.
2. Enable quad mode for read and single mode for write.

Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
2021-01-29 10:35:14 -05:00
Tom Rini
8b195f4b71 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Espressobin: Disable slot when emmc is not present (Pali)
- DS414; config header cleanup (Phil)
- PCI: auto-config enhancement (Phil)
- pci_mvebu: Also map IO region (Phil)
- serial: a3720: Implement pending method for output direction (Pali)
- turris_mox: Enable a few commands (Marek)
- helios4 & ClearFog changes (Dennis)
- Plus some minor misc changes
2021-01-27 11:39:31 -05:00
Alex Nemirovsky
c34a927566 board: presidio-asic: Add CAxxxx Ethernet support
Add CAxxxx Ethernet support for the Cortina Access
Presidio Engineering Board

Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
CC: Tom Rini <trini@konsulko.com>
2021-01-27 10:47:52 -05:00
Dennis Gilmore
827bed4456 ARM: mvebu: helios4 dts changes to enable SPI
Move all aliases defintions into the main dts file
Add u-boot definiton to i2c0 based on clearfog
set spi1 status to okay

Signed-off-by: Dennis Gilmore <dennis@ausil.us>
2021-01-27 07:25:39 +01:00
Jernej Skrabec
38be6b8387 sunxi: Add support for OrangePi Zero2
OrangePi Zero2 is SBC based on Allwinner H616 with 1 GiB of RAM, SD card
support, gigabit ethernet, micro HDMI, WIFI, Bluetooth and 1 USB 2.0
port. It also has two GPIO headers which allows further peripherals to
be used.

The devicetree file is taken from v3 of the OrangePi Zero2 Linux
submission [1], which it's not yet merged.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2021-January/632084.html

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-25 21:52:01 +00:00
Jernej Skrabec
80b2c65bc2 arm: sunxi: add initial H616 DTSI and headers
This commit introduces H616 DTSI file and dt-bindings headers needed for
device tree files.

Files are taken from v3 Linux H616 support submission[1], as the
H616 .dtsi file is not merged upstream yet.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2021-January/632082.html

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-25 21:52:01 +00:00
Jernej Skrabec
8ec293e063 sunxi: Add support for H616 SoC
H616 is very similar to H6 so most of the infrastructure can be reused.
However, two big differences are that it doesn't have functional SRAM A2
which is usually used for TF-A and it doesn't have ARISC co-processor.
It also needs bigger SPL size - 48 KiB.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-25 21:52:01 +00:00
Andre Heider
c81877a919 sunxi: Add support for Orange Pi 3
dts file is taken from Linux 5.11-rc1 tag.

The Bluetooth controller of this device ships with a default address,
use the new CONFIG_FIXUP_BDADDR option to fix it up.

Signed-off-by: Andre Heider <a.heider@gmail.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
[Updated OrangePi 3 DT, rebase and config update]
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-25 21:52:00 +00:00
Jernej Skrabec
a54b2925a6 sunxi: Add support for Tanix TX6
This commit adds support for Tanix TX6 TV box, based on H6. It's low end
H6 board, with 3 GiB of RAM, eMMC, fast ethernet, USB, IR and other
peripherals.

DT file is taken from Linux 5.11-rc1 release.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-25 21:52:00 +00:00
Jernej Skrabec
750cabc87b ARM: dts: sunxi: h6: Update DT files
Updated H6 DT files are based on Linux 5.11-rc1 release.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-25 21:52:00 +00:00
Tom Rini
4057b98ff2 Changes for 2020.04
-------------------
 
 - new board:
 	Phytec phyCORE-i.MX8MP
 	i.MX8MN Beacon EmbeddedWorks devkit
 
 - Fixes:
 	several nanbcb fixes
 	fix for imx8mm_beacon
 - further switch to distro boot commands
 - DM:
 	DM Ether for MX6UL
 
 CI:
 
 https://gitlab.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/6013
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQS2TmnA27QKhpKSZe309WXkmmjvpgUCYA7Oxw8cc2JhYmljQGRl
 bnguZGUACgkQ9PVl5Jpo76bFkACePFxGqlRiC88QcA42wgCbCEmsdtEAnR4TgXQ4
 aMH4tzrcK9Qvs7ULooDL
 =IZtF
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20210125' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Changes for 2020.04
-------------------

- new board:
	Phytec phyCORE-i.MX8MP
	i.MX8MN Beacon EmbeddedWorks devkit

- Fixes:
	several nanbcb fixes
	fix for imx8mm_beacon
- further switch to distro boot commands
- DM:
	DM Ether for MX6UL

CI:

https://gitlab.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/6013
2021-01-25 09:02:35 -05:00
Tom Rini
aee5bcce35 Second set of u-boot-atmel features for 2021.04 cycle
-----BEGIN PGP SIGNATURE-----
 
 iQFQBAABCgA6FiEEqxhEmNJ6d7ZdeFLIHrMeAg6sL8gFAmAOkP8cHGV1Z2VuLmhy
 aXN0ZXZAbWljcm9jaGlwLmNvbQAKCRAesx4CDqwvyKedCACiDHgP71VKSOiYnEU4
 vHD/ANmfMXqnsL71PpSdagnBRAl4vpm46CnD+Mq7RtchxGDNufX6tWJSI04Ci0bC
 mfmIfVEjePOnuUayylJ55OlrtJVpBqJFPqxM6MFcIF7nRja1r5thV1jTLNu+b4sm
 gg2sk1mC/531Lxbk8S7x+diPymNRArEm3IEw+xEqUhsNVQCKjOEcxi/BWIB2prR3
 NxRSGdW3j4CKdBqt7uOL1bqApeQQ9m0/gm1tE3hMXUo09I7uXmb7U52aKb5cV8L+
 8ZOlbav6yaPACe3p9npp4K0ByXMmYHjeo1NZW4cvAoKfzragdu0Cv7f0ssVCgrlR
 p1e3
 =xS6A
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-atmel-2021.04-b' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel

Second set of u-boot-atmel features for 2021.04 cycle

This feature set includes macb updates for all interfaces and new
sama7g5 variant support; micrel ksz9031 DLL support; a new board from
Giant based on Adafruit feather form factor which contains a SAMA5D27
SoC; several fixes regarding the NAND flash PMECC block; and pincontrol
drive strength support for pio4 controller.
2021-01-25 09:01:28 -05:00
Adam Ford
8e95883e46 imx: Add support for i.MX8MN Beacon EmbeddedWorks devkit.
Beacon EmbeddedWorks is releasing a devkit based on the i.MX8M
Nano SoC consisting of baseboard + SOM.

The kit is based on the same design as the Beacon dev kit with
the i.MX8M Mini.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2021-01-23 14:01:49 +01:00
Adam Ford
3796ab8fac arm64: dts: imx8mm-beacon: Resync imx8mm-beacon-som with 5.11-rc4
In order to support the QSPI chip on the SOM, the Flexspi bus
needs to be configured to talk with the SPI chip.
Resync the som device tree with 5.11-rc4

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2021-01-23 13:40:29 +01:00
Teresa Remmet
c661c511e9 board: phytec: imx8mp: Add PHYTEC phyCORE-i.MX8MP support
Add initial support PHYTEC phyCORE-i.MX8MP SOM.

    Supported features:
     - 2GB LPDDR4 RAM
     - eMMC
     - external SD
     - debug UART2
     - watchdog

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
2021-01-23 11:30:32 +01:00
Marc Ferland
9452d58e10 arm: dart6ul: enable DM_ETH for the dart6ul
This patch converts the dart6ul ethernet support to DM_ETH and cleans
up the legacy ethernet code. The clean up, more specifically:

* moves the fec2 node and pin definition to the carrier board DTS
  since the phy associated with it is on the carrier board and not on
  the SoM;
* add the reset pin associated to each phy;
* separate the ethernet, mdio and reset pins of each fec so that they
  are easier to reference;
* add clock properties to the phy nodes since they are connected to the
  50Mhz ENET[12]_TX_CLK clock of the SoC;
* remove CONFIG_BOARD_EARLY_INIT_F since the function is now empty.

Signed-off-by: Marc Ferland <ferlandm@amotus.ca>
2021-01-23 11:30:31 +01:00
Peng Fan
54bd9ddf21 arm: dts: imx8mq: sync dts from Linux Kernel
Sync dts from Linux Kernel
commit f838f8d2b694cf9d524dc("mfd: ab8500-debugfs: Remove extraneous seq_putc")

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-01-23 11:30:31 +01:00
Peng Fan
8d3e37ceb8 arm: dts: imx8mm: sync dts from Linux Kernel
Sync dts from Linux Kernel
commit f838f8d2b694cf9d524dc("mfd: ab8500-debugfs: Remove extraneous seq_putc")

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-01-23 11:30:31 +01:00
Peng Fan
cf8842bc29 arm: dts: imx8mp: sync dts from Linux Kernel
Sync dts from Linux Kernel
commit f838f8d2b694cf9d524dc("mfd: ab8500-debugfs: Remove extraneous seq_putc")

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-01-23 11:30:31 +01:00
Peng Fan
50d0953127 arm: dts: imx8mn: sync dts from Linux Kernel
Sync dts from Linux Kernel
commit f838f8d2b694cf9d524dc("mfd: ab8500-debugfs: Remove extraneous seq_putc")

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-01-23 11:30:30 +01:00
Peng Fan
48b90f86c5 imx: imx8mp_evk: enable eth support
Add board code to configure the network interface
Add net defconfig

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-01-23 11:30:30 +01:00
Greg Gallagher
9119800591 board: atmel: Add SAMA5D27 giant board
Giant board is a tiny SBC based on the Adafruit Feather form factor,
created by groboards it contains a SAMA5D2 processor (SAMA5D27),
128 MB of RAM and a microSD card for storage.

Signed-off-by: Greg Gallagher <greg@embeddedgreg.com>
2021-01-22 15:09:59 +02:00
David Bauer
b821e0db46 rockchip: rk3328: Add support for FriendlyARM NanoPi R2S
This adds support for the NanoPi R2S from FriendlyArm.

Rockchip RK3328 SoC
1GB DDR4 RAM
Gigabit Ethernet (WAN)
Gigabit Ethernet (USB3) (LAN)
USB 2.0 Host Port
MicroSD slot
Reset button
WAN - LAN - SYS LED

Signed-off-by: David Bauer <mail@david-bauer.net>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2021-01-21 11:58:35 +08:00
Peter Robinson
5972c57780 arm: dts: rockchip: rk3399: enable rng at the SoC level
The rng is embedded in the SoC so enable it in the device tree
universally, the use of it can be controlled by enabling/disabling
at the device config level.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2021-01-21 11:55:59 +08:00
Kever Yang
09b053c970 rockchip: leez-rk3399: Provide init voltage
Add missing regulator-init-microvolt property to vdd_log regulator.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2021-01-21 11:54:24 +08:00
Kever Yang
ec0f08c779 rockchip: firefly-rk3399: Provide init voltage
Add missing regulator-init-microvolt property to vdd_log regulator.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2021-01-21 11:54:24 +08:00
Kever Yang
2a6eb3b8f0 rockchip: evb-rk3399: Provide init voltage
Add missing regulator-init-microvolt property to vdd_center regulator.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2021-01-21 11:54:24 +08:00
Hugh Cole-Baker
a2ca3c6032 rockchip: puma-haikou: default to SPI bus 1 for SPI-flash
SPI flash on this machine is located on bus 1, default to using bus 1
for SPI flash and stop aliasing it to bus 0. Formerly the alias spi1
pointed to &spi5, use an alias spi5 for this instead.

Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Suggested-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2021-01-21 11:53:36 +08:00
Hugh Cole-Baker
acc57ecf05 rockchip: rk3399-roc-pc: default to SPI bus 1 for SPI-flash
SPI flash on this board is located on bus 1, default to using bus 1 for
SPI flash on both rk3399-roc-pc and -mezzanine, and stop aliasing it to
bus 0.

Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Suggested-by: Simon Glass <sjg@chromium.org>
Fixes: c4cea2bb ("rockchip: Enable building a SPI ROM image on bob")
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2021-01-21 11:53:25 +08:00
Weijie Gao
ac7a51c0e4 dts: mt7622: use accurate clock source fot mtk_timer
The input system clock for mt7622 timer is 10MHz and can be retrieved
through the clk driver.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-18 15:23:06 -05:00
Chia-Wei, Wang
ec55a1df39 ARM: dts: aspeed: Add AST2600 SoC support
AST2600 is the 7th generation of Aspeed SoC designated for
Interated Remote Management Processor.

AST2600 has significant performance improvement by integrating
1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the
controllers are also improved with more features and better
performance than preceding AST24xx/AST25xx.

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-01-18 15:23:06 -05:00
Kate Liu
34a5addb7b board: presidio: Add Parallel NAND support
Set environment for Nand flash (U-boot 2020.04):
- add nand flash in the device tree
- add new default configuration file for G3 using parallel Nand
- set nand parameters in presidio_asic.h

Signed-off-by: Kate Liu <kate.liu@cortina-access.com>
Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
CC: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2021-01-18 15:14:37 -05:00
Fabien Parent
3dbff96256 arm: dts: mt8516-pumpkin: enable usb port
Enable the USB port for MT8516 Pumpkin Board.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
2021-01-18 14:59:19 -05:00
Fabien Parent
9fe7493b80 arm: dts: mt8516: add support for USB
Add support for USB on mt8516 based SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
2021-01-18 14:59:19 -05:00
Lad Prabhakar
67704d6dfb ARM: dts: renesas: Remove leading 0x from rpc node
Remove the leading "0x" from rpc node to fix the below dtc warning:

Warning (simple_bus_reg): Node /soc/rpc@0xee200000 simple-bus unit
address format error, expected "ee200000"

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2021-01-18 13:29:12 +01:00
Siew Chin Lim
c87496add0 arm: socfpga: dts: soc64: Add binman node of FIT image with ATF support
Add binman node to device tree to generate the FIT image for u-boot
(u-boot.itb) and OS kernel (kernel.itb).

u-boot.itb contains arm trusted firmware (ATF), u-boot proper and
u-boot device tree for ATF u-boot flow.

kernel.itb contains Linux Image and Linux device tree.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-01-15 17:48:38 +08:00
Tom Rini
ab1a425524 - Enable logging features for stm32mp15 boards
- Update MAINTAINERS emails for STI and STM32
 - Activate OF_LIVE for ST stm32mp15 boards
 - Switch to MCO2 for PHY 50 MHz clock for DHCOM boards
 - Correction in stm32prog command on uart: always flush DFU on start command
 - Update USB-C power detection algorithm on DK boards
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCgAdFiEE56Yx6b9SnloYCWtD4rK92eCqk3UFAl/+yLkACgkQ4rK92eCq
 k3X/Fgf/d/11WyQrVzvpr+nN+4Wl7J+ASmoUz0yKa6ri+lbvhLgh+JXbCRKgRPWu
 vNnI07pSoX/QeaMpGBU8Ztg/Onb9/pvffz4WMk1411GoyCpDFuuK3cVSIoqkPfu+
 XmgSX0u4BXtve1+ZdWfVBWXawUSEDMmGR3tmz1708c/s/oYpnVeRDcqiqzJ94cWE
 yt+SpMPVqMUVQ/rAGkE8ToSMxX7FusEa7SvCg4U2ikoRWs3kPpr/73+tRWlmgGxL
 sW8SXSKiOmFyheSBx3d2B9n00kDYTTrQmbW9hlMilZmji7CwZYxgTCMdX0x4DeFP
 RDajT2Yju1JmeM+Z8+Ke2tupzvy6QA==
 =oK8C
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-stm32-20210113' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- Enable logging features for stm32mp15 boards
- Update MAINTAINERS emails for STI and STM32
- Activate OF_LIVE for ST stm32mp15 boards
- Switch to MCO2 for PHY 50 MHz clock for DHCOM boards
- Correction in stm32prog command on uart: always flush DFU on start command
- Update USB-C power detection algorithm on DK boards
2021-01-13 15:00:53 -05:00
Tom Rini
795f8fd0b5 - sync amlogic GX & AXG DT to Linux 5.10
- Add new MESON_EE driver support for GXBB & AXG
 - Add support for Libretech-CC v2, Wetek Core2, Beelink GT-King/Pro boards
 - add driver for TDO tl070wsh30 panel driver
 - meson: isolate loading of socinfo
 - Add soc_rev to environment
 - Enable G12A support for saradc
 - Add correct mmcdev on VIM3(L) & Odroid-N2(C4)
 - Read MAC from fuses for VIM3 & VIM3L boards
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAl/9rV0ACgkQd9zb2sjI
 SdFE0xAAtXzW98pKmC4C3a1FWcGSuBZK2gzUgKc8oTqBWodMTVLSmDGNbIpaES/+
 UySXSR0KJ5Qmu3jEZN2NYUKuABzylmIyT+5/sj1yN0zgxU2NB2//18uELNVKC4b+
 wtLna+SSebl8ofGuVzfYYCfbBS0S2Y+n9g2+WVu3s+D03WG5wrqEZy5RqKRf4OMZ
 MoQiDoLFms1GS6iLoidg/RMNme6efODAOTOVklHre2zeN3rjGei2URHdVtIeXcdG
 G3Wz9GVwR96UWTGY6JuXEGVpI459vHc4AcswnVcKNnILS/50tpSA9Gc0e0lXaDwT
 29DPehnoBkdbtIQ4szrAthGBITWhhgp2ksHaY5jyg38mVGF1/uu76kPUlCLxY5fL
 //3j/t+qaA3iwJq36tvZSKbprjA8sINN8Hsmi9+2Bzyv90sLfxY/x/DpeTVfWUQf
 UireG3iCYBkP5Mxr1kO+eJUoPAEe8BDJ+3AyVCjlMvKdomGFGCY0C/2LY54G8WS+
 el2Sj8XkTgtZQA/HXuXg1y2Cw54FWN6SXMVFXqZW5bu/w2GmeSOMEkFs3aFieCB7
 5UP+PiA3aM9Z6oXJReNnwc7iy+de8peZ/gpNCqWxr/jxg/C5d+Lg3kgbr961MyhU
 e97xab9p3f9raVOrYCAP7jVqAfTS39ZtAzSZlSJcK3Pls9wVxJI=
 =iIWq
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-amlogic-20210112' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- sync amlogic GX & AXG DT to Linux 5.10
- Add new MESON_EE driver support for GXBB & AXG
- Add support for Libretech-CC v2, Wetek Core2, Beelink GT-King/Pro boards
- add driver for TDO tl070wsh30 panel driver
- meson: isolate loading of socinfo
- Add soc_rev to environment
- Enable G12A support for saradc
- Add correct mmcdev on VIM3(L) & Odroid-N2(C4)
- Read MAC from fuses for VIM3 & VIM3L boards
2021-01-13 07:32:02 -05:00
Patrice Chotard
7ccaa31380 MAINTAINERS: Update STi and STM32 maintainers emails in remaining files
A previous series already update STMicroelectronics emails maintainers
but some files have been omitted (Makefile, .dts, .dtsi and .rst files).
Update Patrick and my email address with the one dedicated to upstream
activities.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-01-13 09:52:58 +01:00
Marek Vasut
69ea30e688 ARM: dts: stm32: Switch to MCO2 for PHY 50 MHz clock
The LAN8710i PHY currently uses 50 MHz clock direct from PLL4P.
To permit PLL4P to run at faster frequency, use MCO2 as a divider.
The PLL4P runs at 100 MHz, supplies MCO2 which divides it by 2 to
50MHz, and supplies the PHY with 50 MHz via pin PG2. The feedback
clock are fed back in via pin PA1.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ia9bf7119785d49b633a3ae761c3dc4a30b92628a
2021-01-13 09:52:58 +01:00
Tom Rini
ee6726be4f Merge tag 'ti-v2021.04-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti
- DM support for OMAP PWM backlight
- USB host mode support for AM654
- Minor SPI fixes
- Add support k2g ice board with 1GHz silicon
- Fix GTC programming for K3 devices
2021-01-12 09:32:48 -05:00
Tom Rini
996f217ea3 First set of u-boot-atmel features for 2021.04 cycle
-----BEGIN PGP SIGNATURE-----
 
 iQFQBAABCgA6FiEEqxhEmNJ6d7ZdeFLIHrMeAg6sL8gFAl/8S/0cHGV1Z2VuLmhy
 aXN0ZXZAbWljcm9jaGlwLmNvbQAKCRAesx4CDqwvyKFkB/9NBJq/+sgHZXRaMlAu
 ULNwOPoNsQxHQGwF88B1lC+H8LJjM+2gJ8MfJdWvHNlcSdtJjbWk0aQL+5LKSlyz
 G7l3BZ+AIYMOeTXay5mNUKnekXIr7c8tLoX8FH/Ih+bHFPt57qL0bbfznV66UCOp
 /o/yM8daPa9Kx1vPEpT2dC9bYXLXeQv6R+RMxwoc4Bk+R3OK7zoZ3Wdx0q9HvBwj
 iWHM49X2fBqqi5RS+ZI37AUzi8iysD3fOq0kWTJcCNaci8i8RZdzSyoaDuXhA63I
 EZJ7v9fUkW/bwTONVE9n2BX4xF9X/6R7P46l9dQISXAxsOBwsNRQPt8Ro7mCoc4K
 392o
 =LIK7
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-atmel-2021.04-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel

First set of u-boot-atmel features for 2021.04 cycle

This feature set includes the new board SAMA7G5 EK, the new evaluation
kit for Microchip AT91 SAMA7G5 SoC . The current board support includes
two configurations for booting from eMMC (SDMMC0), SD-Card (SDMMC1), and
support for two Ethernet interfaces.
2021-01-12 09:32:20 -05:00
Nishanth Menon
965db9fb0c arm: dts: k3-*-r5-*-board: Add GTC clock
Add GTC Clock definition as index 0 clock so that we can use the clock
node in the driver later on.

Signed-off-by: Nishanth Menon <nm@ti.com>
2021-01-12 10:59:04 +05:30
Dario Binacchi
ff94c15a3c video: omap: add panel driver
The previous version of am335x-fb.c contained the functionalities of two
drivers that this patch has split. It was a video type driver that used
the same registration compatible string that now registers a panel type
driver. The proof of this is that two compatible strings were referred
to within the same driver.
There are now two drivers, each with its own compatible string,
functions and API.
Furthermore, the panel driver, in addition to decoding the display
timings, is now also able to manage the backlight.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-12 10:58:27 +05:30
Dario Binacchi
8322fdcedf arm: dts: am335x: enable scm_clocks auto binding
Adding the 'simple-bus' compatible string to the scm_clocks node will
allow its automatic binding.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-01-12 10:58:05 +05:30
Dario Binacchi
abdf1a3571 arm: dts: am335x: enable prcm_clocks auto binding
Adding the 'simple-bus' compatible string to the prcm_clocks node will
allow its automatic binding.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-01-12 10:58:04 +05:30
Dario Binacchi
c28baf6c70 arm: dts: am335x: include am33xx-u-boot.dtsi
Include the SoC U-boot DTS in each am335x-<board>-u-boot.dtsi.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-01-12 10:58:04 +05:30
Dario Binacchi
6337d53fdf arm: dts: sync am33xx with Linux 5.9-rc7
There have been several changes to the am33xx.dtsi, so this patch
re-syncs it with Linux.

Let's add proper interconnect hierarchy for l4 interconnect instances
with the related ti-sysc interconnect module data as documented in
Documentation/devicetree/bindings/bus/ti-sysc.txt of the Linux kernel.
With l4 interconnect hierarchy and ti-sysc interconnect target module
data in place, we can simply move all the related child devices to their
proper location and enable probing using ti-sysc.

The am33xx-clock.dtsi file is the same as that of the Linux kernel,
except for the reg property of the node l4-wkup-clkctrl@0.
As for the am33xx.dtsi file, all the devices with drivers not yet
implemented and those I was able to test with this patch have been moved
to am33xx-l4.dtsi. In case of any regressions, problem devices can be
reverted by moving them back and removing the related interconnect
target module node.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-01-12 10:58:04 +05:30
Praneeth Bajjuri
9c789fec10 arm: dts: k3-j721e: ddr: Update to 0.5.0 version of DDR config tool
Update the ddr settings to use the DDR reg config tool rev 0.5.0.
This enables 4266MTs DDR configuration.

Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: Kevin Scholz <k-scholz@ti.com>
2021-01-12 10:21:41 +05:30
Aswath Govindraju
62be2367f5 arm: dts: am654-base-board-uboot: Add aliases for USB subsystems
The sequence number assigned for USB subsystem in a uclass is dependent on
the order of occurrence in the device tree. If the dr_mode of USB3SS0
controller is varied then the sequence number of USB3SS1 controller also
changes. If aliases are added then sequence numbers are assigned using the
alias number. This makes the sequence number of USB3SS1 controller
independent of USB3SS0 controller's dr_mode.

Therefore, add aliases to fix the sequence number assigned to the USB
subsystems.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-01-12 10:21:40 +05:30
Aswath Govindraju
d3af9e3772 arm: dts: am654-base-board-uboot: Set USB0 dr_mode to host
USB3SS0 controller is to be used as a host in U-boot. Fix it by changing
the dr_mode to host.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-01-12 10:21:40 +05:30
Icenowy Zheng
ab3b53f30f sunxi: add PineCube board
PineCube is an IP camera development kit released by Pine64.

It comes with the following compoents:

- A mainboard with Sochip S3 SoC, a 16MByte SPI Flash, AXP209 PMIC,
a power-only microUSB connector, a USB Type-A connector, a 10/100Mbps
Ethernet port and FPC connectors for camera and daughter board.
- An OV5640-based camera module which is connected to the parallel CSI
bus of the mainboard.
- A daughterboard with several buttons, a SD slot, some IR LEDs, a
microphone and a speaker connector.

As the device tree is synchronized in a previous commit, just add it to
Makefile, create a new MAINTAINER item and provide a defconfig.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-11 23:19:33 +00:00
Tom Rini
d71be19902 Merge branch 'next'
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-01-11 13:55:03 -05:00
Christian Hewitt
ca62ed2dac ARM: dts: import Beelink GT-King/Pro DTs from Linux 5.10
Import the Beelink GT-King/Pro and supporting meson-g12b-w400.dtsi file
from Linux 5.10.

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-01-11 14:59:54 +01:00
Christian Hewitt
d45dba838a ARM: dts: import WeTek Core2 DTs from Linux 5.10
Import the WeTek Core2 and supporting meson-gx-p23x-q20x.dtsi files
from Linux 5.10.

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-01-11 14:59:54 +01:00
Jerome Brunet
ade0100a91 arm64: meson: add support for libretech-cc v2
Add support for the Amlogic based libretech cc version 2.
As version 1, it is based on the s905x SoC.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
[narmstrong: Fixed libretech-cc.rst bullet points]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-01-11 14:59:54 +01:00
Jerome Brunet
4ac6946bac arm64: dts: import libretech-cc-v2 from linux v5.10-rc1
Sync the libretech cc v2 device tree from Linux v5.10-rc1
commit 3650b228f83a ("Linux 5.10-rc1")

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-01-11 14:59:54 +01:00
Neil Armstrong
ee73135365 ARM: dts: sync Amlogic GX & AXG from Linux 5.10-rc1
Synced from Linux commit 3650b228f83a ("Linux 5.10-rc1")

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-01-11 14:59:54 +01:00
Hugh Cole-Baker
92cb207af1 rockchip: pinebook-pro: default to SPI bus 1 for SPI-flash
SPI flash on this machine is located on bus 1, default to using bus 1
for SPI flash and stop aliasing it to bus 0.

Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Suggested-by: Simon Glass <sjg@chromium.org>
Fixes: c4cea2bb ("rockchip: Enable building a SPI ROM image on bob")
2021-01-08 08:40:43 -05:00
Nicolas Ferre
aeaef07c51 ARM: dts: sama7g5ek: fix TXC pin configuration
TXC line is directly connected from the SoC to the KSZ9131 PHY. There
is a transient state on this signal, before configuring it to RGMII,
which leads to packet transmit being blocked.
Keeping a pull-up when muxing this pin as function A (G0_TXCK) fixes
the issue.

Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2021-01-07 09:44:16 +02:00
Eugen Hristev
9b614c87bb ARM: dts: sama7g5ek: add i2c1 bus and eeproms
Add node for flx1 i2c1 subnode (and alias to bus 0)
This bus has two eeprom devices connected.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-07 09:44:16 +02:00
Eugen Hristev
1c629fd033 ARM: dts: at91: sama7g5: add flexcom1 and i2c subnode
Add flexcom1 and i2c subnode.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-07 09:44:16 +02:00
Eugen Hristev
7f4c89cc5c ARM: dts: at91: sama7g5ek: enable sdmmc0 with pinctrl
Enable sdmmc0 on this board. A non-removable eMMC is connected on this
block.
Configure pincontrol accordingly.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-07 09:44:16 +02:00
Eugen Hristev
523c10c1fd ARM: dts: at91: sama7g5: add node for sdmmc0
Add node for sdmmc0 block.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-07 09:44:16 +02:00
Eugen Hristev
9b6f157e19 ARM: dts: at91: sama7g5: add assigned clocks for sdmmc1
SDMMC1 requires clock specification with assigned-clocks, such that
the PMC will know which parent to assign and the initial start-up frequency.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-07 09:44:16 +02:00
Claudiu Beznea
3e5853e6a1 ARM: dts: sama7g5: add GMAC1
Add GMAC1.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07 09:44:15 +02:00
Claudiu Beznea
e95af87e9b ARM: dts: sama7g5: add GMAC0
Add GMAC0.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07 09:44:15 +02:00
Eugen Hristev
7d41a8da84 ARM: dts: at91: sama7g5ek: add pinctrl for sdmmc1 and flx3
Add pinctrl for sdmmc1 and flx3.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-07 09:44:15 +02:00
Eugen Hristev
47a13af586 ARM: dts: at91: sama7g5: add pinctrl node
Add pioA pinctrl node.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-07 09:44:15 +02:00
Claudiu Beznea
b032230f87 ARM: dts: sama7g5: add pit64b support
Add DT bindings for PIT64B driver.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07 09:44:15 +02:00
Claudiu Beznea
13f986b748 ARM: dts: sama7g5: add CPU bindings
Add CPU DT bindings.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07 09:44:15 +02:00
Claudiu Beznea
394f520709 ARM: dts: sama7g5: switch to PMC bindings
Get rid of software defined MCK and switch to PMC bindings
for IPs currently present in device tree.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07 09:44:15 +02:00
Claudiu Beznea
33fa0b6cef ARM: dts: sama7g5: add PMC bindings
Add DT bindings for PMC driver.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07 09:44:15 +02:00
Claudiu Beznea
09f19f7770 ARM: dts: sama7g5: add slow clock bindings
Add DT bindings for slow clock driver.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07 09:44:15 +02:00
Claudiu Beznea
072c975940 ARM: dts: sama7g5: add u-boot,dm-pre-reloc bindings for xtals
Add dm-pre-reloc DT binding property for cristals.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07 09:44:15 +02:00
Claudiu Beznea
5e19ade9e5 ARM: dts: sama7g5: add slow rc and main rc oscillators
Add slow rc and main rc oscillators to dtsi.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07 09:44:15 +02:00
Claudiu Beznea
3b86096a59 ARM: dts: sama7g5: move clock frequencies for xtals in board file
Move clock frequencies for crystals on board specific files.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07 09:44:15 +02:00
Eugen Hristev
1d463d6735 board: atmel: sama7g5ek: add initial support for sama7g5ek
Add initial support for sama7g5 evaluation kit board.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-07 09:44:15 +02:00
Eugen Hristev
626879b794 ARM: dts: sama7g5: add initial DT for sama7g5 SoC
Add initial basic devicetree for sama7g5 SoC

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-07 09:44:15 +02:00
Tom Rini
bc0b99bd8b Xilinx changes for v2021.04
arm64:
 - DT updates
 
 microblaze:
 - Add support for NOR device support
 
 spi:
 - Fix unaligned data write issue
 
 nand:
 - Minor code change
 
 xilinx:
 - Fru fix in limit calculation
 - Fill git repo link for all Xilinx boards
 
 video:
 - Add support for seps525 spi display
 
 tools:
 - Minor Vitis file support
 
 cmd/common
 - Minor code indentation fixes
 
 serial:
 - Uartlite debug uart initialization fix
 -----BEGIN PGP SIGNATURE-----
 
 iFsEABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCX/ROlgAKCRDKSWXLKUoM
 IRC5AIkBzg4Sz8fQgdCiOK89k7tdFKMAnA9SYhgm4TSCzffZCJwnm78QoGAC
 =4FnY
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2021.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2021.04

arm64:
- DT updates

microblaze:
- Add support for NOR device support

spi:
- Fix unaligned data write issue

nand:
- Minor code change

xilinx:
- Fru fix in limit calculation
- Fill git repo link for all Xilinx boards

video:
- Add support for seps525 spi display

tools:
- Minor Vitis file support

cmd/common
- Minor code indentation fixes

serial:
- Uartlite debug uart initialization fix
2021-01-06 07:57:33 -05:00
Marek Vasut
ec4efd5ae7 ARM: dts: stm32: Fix GPIO hog flags on DHCOM DRC02
The GPIO hog flags are ignored by gpiolib-of.c now, set the flags to 0.
Since GPIO_ACTIVE_HIGH is defined as 0, this change only increases the
correctness of the DT.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-01-06 11:01:31 +01:00
Marek Vasut
1a6de002e5 ARM: dts: stm32: Fix GPIO hog flags on DHCOM PicoITX
The GPIO hog flags are ignored by gpiolib-of.c now, set the flags to 0.
Due to a change in gpiolib-of.c, setting flags to GPIO_ACTIVE_LOW and
using output-low DT property leads to the GPIO being set high instead.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-01-06 11:01:31 +01:00
Tom Rini
720620e691 Prepare v2021.01-rc5
-----BEGIN PGP SIGNATURE-----
 
 iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAl/0YVIACgkQFHw5/5Y0
 tywtEwv/cJWlKgcSnYjuJrxwuJdauUTfXdbUgtCxOtBw/BP4dsKkbGTJPw5q5M+4
 LJJSKyksmJVTX26h1dpkzQjOpWtTDnWqm5CTIxD52oQD7pxK+zCQ9T6S+QbQD0Se
 ogHmZluzFoluxbNgo8tiO52xvMhDO3TVAzxsNDdGfkd5/tAXOHClPc34RmAkdRHU
 VsR89AKdT2q543fiUfrRZYDzdctaNWhRGXMDcJ4+QU/8hQhrpcr8EtHbF+3mWX4K
 pA01pDz150Rn4UI6S2xKEWrjSTHe55fxVj/Qj0rq9z2E/+NqGXemf5s13AR0G/z3
 PqHdVLHzDe64pbOvmyU1pVQ0aMb8vMJUnqx68SQZY3On2c+MjRWQ+7aVVaKOcPGp
 uatk6QMrggHp3Li+3yZrLBE0qPr/sNMVb7mUesdZb6lFd2VIs8siwhfeGXMS+nDI
 xePzsR43Fnn5Q5KIqqvcWUb+TTTqUDUff0wyAU8NBgCaIBIZK8h2ppS1jjnbms0I
 mr8Er2vb
 =Dfum
 -----END PGP SIGNATURE-----

Merge tag 'v2021.01-rc5' into next

Prepare v2021.01-rc5

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-01-05 16:20:26 -05:00
Harini Katakam
0e3a7aa7a9 arm64: zynqmp: Add Ethernet node for zcu1285 revA
This patch add ethernet node gem1 to zcu1285 RevB.
GMII to RGMII converter sits between MAC and external
phy connected over GMII to MAC and RGMMI to external phy

Signed-off-by: Harini Katakam <harini.katakam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-01-05 11:54:53 +01:00
Siva Durga Prasad Paladugu
59fbd5c1f8 arm64: zynqmp: Add ethernet node for zcu1275 revB
This patch add ethernet node gem1 to zcu1275 RevB.
GMII to RGMII converter sits between MAC and external
phy connected over GMII to MAC and RGMMI to external phy.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-01-05 11:54:44 +01:00
Michal Simek
2d381d2fe2 arm64: zynqmp: Sync DT with Linux kernel
All changes are recorded in lore.kernel.org. Here are links to that patches
for the record.
Link: https://lore.kernel.org/r/f59a63d8cb941592de6d2dee8afa6f120b2e40c8.1601379794.git.michal.simek@xilinx.com
Link: https://lore.kernel.org/r/68f20a2b2bb0feee80bc3348619c2ee98aa69963.1598263539.git.michal.simek@xilinx.com
Link: https://lore.kernel.org/r/f767fe007e446a2299fda9905e75b723c650a424.1605021644.git.michal.simek@xilinx.com
Link: https://lore.kernel.org/r/cc294ae1a79ef845af6809ddb4049f0c0f5bb87a.1598259551.git.michal.simek@xilinx.com
Link: https://lore.kernel.org/r/20200629081744.13916-1-krzk@kernel.org

And there are other minor changes (just moving things around).

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-01-04 10:51:27 +01:00
Tom Rini
ab865a8ee5 Fixes for 2021.1
----------------
 
 CI: https://gitlab.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/5680
 
 - fixes for Variscite dart6ul
 - imx8mp : increase malloc area
 - fixes for bx50v3
 - imx8m: HS400ES and UHS for EVK
 - imx8qm-rom7720: fix phy bind
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQS2TmnA27QKhpKSZe309WXkmmjvpgUCX+nFGQ8cc2JhYmljQGRl
 bnguZGUACgkQ9PVl5Jpo76byvwCcDhQjWcDIHvNkxD4PVjieTVH4VSsAnifKj0td
 C8L36yASIlBRxHH4gpGE
 =39D3
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20201227' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Fixes for 2021.1
----------------

CI: https://gitlab.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/5680

- fixes for Variscite dart6ul
- imx8mp : increase malloc area
- fixes for bx50v3
- imx8m: HS400ES and UHS for EVK
- imx8qm-rom7720: fix phy bind
2020-12-28 07:44:03 -05:00
Stefan Roese
ce040932b5 arm: mvebu: armada-xp-gp.dts: Add spi0 alias
For correct spi bus detection the spi0 alias is needed in the DT.
Otherwise this error will ocurr in U-Boot:

Invalid bus 0 (err=-19)
Failed to initialize SPI flash at 0:0 (error -19)

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Dennis Gilmore <dgilmore@redhat.com>
Tested-by: Dennis Gilmore <dgilmore@redhat.com>
2020-12-28 09:42:06 +01:00
Stefan Roese
33fc6fc105 arm: mvebu: Add armada-xp-gp-u-boot.dtsi for U-Boot properties
Add some missing "u-boot,dm-pre-reloc;" properties to UART0, SPI
controller and SPI NOR flash node to enable usage in SPL. Otherwise
these devices will not be available.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Dennis Gilmore <dgilmore@redhat.com>
Tested-by: Dennis Gilmore <dgilmore@redhat.com>
2020-12-28 09:42:06 +01:00
Marc Ferland
37648b600c arm: dart6ul: read and print SoM info from eeprom on startup
The dart6ul has an i2c eeprom at 0x50 which contains, among other
things, the manufacturing/revision/options info of the SoM. This patch
replaces the current checkboard() implementation with a more
exhaustive one based on the content of the eeprom.

Since this code uses the new driver model, some changes were also
required in the DTS to make the nodes related to i2c available before
relocation.

This code was inspired from the supported u-boot code from Variscite
which can be found here:

https://github.com/varigit/uboot-imx/tree/imx_v2018.03_4.14.78_1.0.0_ga_var02

New output example:

Board: PN: VSM-6UL-705B, Assy: AS1812142257, Date: 2019 Feb 17
       Storage: eMMC, Wifi: yes, DDR: 1024 MiB, Rev: 2.4G

Signed-off-by: Marc Ferland <ferlandm@amotus.ca>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-12-26 14:56:09 +01:00
Marc Ferland
d4d7b663b8 arm: dart6ul: change compatible string for eeprom
The eeprom at address 0x50 is a BR24G04NUX-3TTR. It has a
4Kbit (512x8) capacity, change the compatible string to reflect this
fact.

Also, add an alias to easily refer to this eeprom with
fdt_path_offset() which will be in another commit.

Signed-off-by: Marc Ferland <ferlandm@amotus.ca>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-12-26 14:56:09 +01:00
Sebastian Reichel
717bf50f4b board: ge: bx50v3: cleanup phy config
The current PHY rework does the following things:

1. Configure 125MHz clock
2. Setup the TX clock delay (RX is enabled by default),
3. Setup reserved bits to avoid voltage peak

The clock delays are nowadays already configured by the
PHY driver (in ar803x_delay_config). The code for that
can simply be dropped. The clock speed can also be
configured by the PHY driver by adding the device tree
property "qca,clk-out-frequency".

What is left is setting up the undocumented reserved bits
to avoid the voltage peak problem. I slightly improved its
documentation while updating the board's PHY rework code.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
2020-12-26 14:56:09 +01:00
Andrey Zhizhikin
50b1a69cee ARM: dts: imx8m: add UHS or HS400/HS400ES properties
i.MX8M series provide support for high speed grades in their
usdhc controllers, which has eMMC and SDHC connected to them.

Enable this support across the entire i.MX8M family by providing quirks
to usdhc controllers designated by storage media connected to them.

Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
2020-12-26 12:36:35 +01:00
Andrey Zhizhikin
247bbeb74c ARM: dts: imx8m: increase off-on delay on the SD Vcc regulator
Some SD Card controller and power circuitry has increased capacitance,
which keeps the internal logic remains powered after regulator is switch
off. This is generally the case when card is switched to SD104 mode,
where a power cycle should be performed. In case if the card internal
logic remains powered, it causes a subsequent failure of mode
transition, effectively leading to failed enumeration.

Introduce a delay of 20 msec in order to provide a possibility for
internal card circuitry to drain voltages and perform a power cycle
correctly.

Similar fix is done in commit c49d0ac38a ("ARM: dts: rmobile: Increase
off-on delay on the SD Vcc regulator") targeted Renesas SOCs.

Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Stefano Babic <sbabic@denx.de>
2020-12-26 12:36:19 +01:00
Adam Ford
1170d2b759 arm64: dts: imx8mm-beacon: Re-sync dts file with Linux 5.10-rc6
There have been some updates to the device trees, so re-sync.

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2020-12-26 12:35:58 +01:00
Adam Ford
15d79fcac0 arm: dts: imx8mm: sync dts from Linux Kernel 5.10-rc6
There have been some updates to the device tree since 5.6.
This also includes some clocks, and makes it easier to keep
board device tree files in sync with Linux

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2020-12-26 12:35:49 +01:00
Oliver Graute
2055103f08 ARM: dts: imx: imx8qm-rom7720: Fix AR8031 phy-mode
Fixed wrong PHY Interface Mode

    As per kernel commit 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode)
    the correct phy-mode should be "rgmii-id", so fix it accordingly
    to fix the Ethernet regression.

    This problem has been exposed by commit:

    commit 13114f38e2

    Fix the phy-mode accordingly to fix the regression.

Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Vladimir Oltean <vladimir.oltean@nxp.com>
2020-12-26 12:35:25 +01:00
Michael Walle
e668bec96a board: kontron: sl28: reorder mmc devices
Since linux commit 2e6cde96873253fd9eb0f20afd8ffd18278cff75 ("arm64:
dts: ls1028a: make the eMMC and SD card controllers use fixed indices")
mmc0 is the eMMC and mmc1 is the SD card. Also swap it in u-boot to
avoid any confusion by the user and to be aligned with linux.

Signed-off-by: Michael Walle <michael@walle.cc>
2020-12-20 16:53:25 -05:00
Tom Rini
549e7cb708 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spi 2020-12-18 13:06:02 -05:00
Marek Szyprowski
21a1bc6a90 ARM: dts: meson: switch TFLASH_VDD_EN pin to open drain on Odroid-C4
For the proper reboot Odroid-C4 board requires to switch TFLASH_VDD_EN
pin to the high impedance mode, otherwise the board is stuck in the
middle of loading early stages of the bootloader from SD card.

This can be achieved by using the OPEN_DRAIN flag instead if the
ACTIVE_HIGH, what will leave the pin in input to achieve high state (pin
has the pull-up) and solve the issue.

Suggested-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-12-18 11:50:27 +01:00
Sean Anderson
237e5880f8 spi: dw: Add SoC-specific compatible strings
This adds SoC-specific compatible strings to all users of the designware
spi device. This will allow for the correct driver to be selected for each
device. Where it is publicly documented, a compatible string for the
specific device version has also been added. Devices without
publicly-documented device versions include MSCC SoCs, and Arc Socs. All
compatible strings except those for SoCFPGAs and some of the versioned
strings have been taken from Linux.

Since SSI_MAX_XFER_SIZE is determined at runtime, this is not strictly
necessary. However, it is a good cleanup and brings things closer to Linux.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:37 +05:30
Tom Rini
5a1a8a63be Second set of u-boot-atmel fixes for 2021.01 cycle
-----BEGIN PGP SIGNATURE-----
 
 iQFQBAABCgA6FiEEqxhEmNJ6d7ZdeFLIHrMeAg6sL8gFAl/TlVUcHGV1Z2VuLmhy
 aXN0ZXZAbWljcm9jaGlwLmNvbQAKCRAesx4CDqwvyK8eB/9mIJCgCiDue2ytkUg+
 fyJHHtHf+rFIbvLiR+iVy/2rXlsjfXwNVyJTswJOCucit0cf+F7fh6vi/AnOoDnE
 Zezj9ngm+25fvffQjt0T74V2w+GhT5OXqR7ctpIcrmKun2UTujSA9NQqRaLFDI9x
 RQlUXsCzLypFZRXvyOCo34Nz7MZ1QvIAKxEJyYb7ft/qnbtILDr0p54xxjlK5B/W
 s+MP05qaRmup9rk33JwfLmeyjTmDBuri0rBh/2XKFtszJBm5CdgXJEqNY+22JzJF
 xlqfobmdPn77+JH36B/KJgDmrrL05vv+RyvOPoBNzm6BEKtlflcSf9NnTKlSud4y
 w/50
 =r687
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-atmel-fixes-2021.01-b' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel

Second set of u-boot-atmel fixes for 2021.01 cycle

This set includes very important fixes for: MMC booting on several
boards, drive strength on sam9x60ek mmc lines, compile issues for
timer.c old driver, removal of unwanted access to sam9x60 bit for
oscillator bypass mode, and eeproms read on sama5d2_icp.
2020-12-11 15:55:17 -05:00
Eugen Hristev
bb5eedbc7f ARM: dts: at91: sama5d2_icp: fix i2c eeprom compatible
The correct compatible for this eeproms is microchip,24aa02e48
The previous compatible string was working up to U-boot 2020.04.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Tested-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
2020-12-11 17:47:21 +02:00
Meenakshi Aggarwal
9ed303dfa9 armv8: lx2162aqds: Add support for LX2162AQDS platform
This patch add base support for LX2162AQDS board.
LX2162AQDS board supports LX2162A family SoCs.
This patch add basic support of platform.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Signed-off-by: hui.song <hui.song_1@nxp.com>
Signed-off-by: Manish Tomar <manish.tomar@nxp.com>
Signed-off-by: Vikas Singh <vikas.singh@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10 13:56:39 +05:30
Wasim Khan
4c72d2d53b arm: dts: ls1028a: add label to pcie nodes in dts
Add label to pcie nodes in dts so that these nodes
are easy to refer.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10 13:56:39 +05:30
Wasim Khan
04c2d93d36 arm: dts: ls1043a: add label to pcie nodes in dts
Add label to pcie nodes in dts so that these nodes
are easy to refer.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10 13:56:39 +05:30
Wasim Khan
6ba8b6a8f8 arm: dts: ls1012a: add label to pcie nodes in dts
Add label to pcie nodes in dts so that these nodes
are easy to refer.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10 13:56:39 +05:30
Wasim Khan
7dfc20ab1d arm: dts: ls1088a: add label to pcie nodes in dts
Add label to pcie nodes in dts so that these nodes
are easy to refer.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10 13:56:39 +05:30
Wasim Khan
ba45dd21f3 arm: dts: ls2080a: add label to pcie nodes in dts
Add label to pcie nodes in dts so that these nodes
are easy to refer.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10 13:56:39 +05:30
Wasim Khan
2adb7970cb arm: dts: ls1046a: add label to pcie nodes in dts
Add label to pcie nodes in dts so that these nodes
are easy to refer.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10 13:56:39 +05:30
Wasim Khan
6519ccd282 arm: dts: lx2160a: add label to pcie nodes in dts
Add label to pcie nodes in dts so that these nodes
are easy to refer.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10 13:56:38 +05:30
Tom Rini
2a42de6df1 - Manage CONFIG_ENV_EXT4_DEVICE_AND_PART in stm32mp1 board
- Update ARM STI and ARM STM STM32MP Arch maintainers emails
 - Enable internal pull-ups for SDMMC1 on DHCOM SoM
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCgAdFiEE56Yx6b9SnloYCWtD4rK92eCqk3UFAl/Q5aAACgkQ4rK92eCq
 k3XuqAgAifJcb3NxKmWa4eFDbZpWZ1R8h6FPp6vlmvyC4C3otRHEe5WrYCsAeqy1
 Gs311dtdluc4y5Ltmf54OcN7ICfLsSiOvye85f5myhPj1v4d1F1Z70X0FDo/o9hE
 7TEZfWBQtNjXI4F23+vaDT4jCvUZV1LR6Lab/zLLw1/uLUxxS799kcFiWgHLuEoH
 8Cv0JbgzLuuVk5lyLJ+DFZOcntwWu5+Qm+l5eS46armbKphMFh5KPJ9PG81eJE3N
 zsCpavEs4nuQl7wGF8HPfDWxz5Xef6ip3A4Owh92t3WQWKxp1bSUKqDeKZTkhIyS
 LSJKe9CQ9+zCS3m3Utoi1pVt1EbFrQ==
 =cgbE
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-stm32-20201209' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- Manage CONFIG_ENV_EXT4_DEVICE_AND_PART in stm32mp1 board
- Update ARM STI and ARM STM STM32MP Arch maintainers emails
- Enable internal pull-ups for SDMMC1 on DHCOM SoM
2020-12-09 11:36:41 -05:00
Marek Vasut
9b36b7dc96 ARM: dts: stm32: Add USB OTG ID pin on DH AV96
Add USB OTG ID pin mux and switch the USB OTG port
from peripheral to OTG mode.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2020-12-09 10:57:50 +01:00
Marek Vasut
1399be91cb ARM: dts: stm32: Enable SDMMC3 on DH DRC02
The DH DRC02 board has an on-board microSD slot,
add DT properties to enable the slot.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2020-12-09 10:57:50 +01:00
Marek Vasut
75df748b87 ARM: dts: stm32: Disable SDMMC1 CKIN feedback clock
The STM32MP1 DHCOM SoM can be built with either bus voltage level shifter
or without one on the SDMMC1 interface. Because the SDMMC1 interface is
limited to 50 MHz and hence SD high-speed anyway, disable the SD feedback
clock to permit operation of the same U-Boot image on both SoM with and
without voltage level shifter.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2020-12-09 10:57:50 +01:00
Marek Vasut
845c6720ec ARM: dts: stm32: Enable internal pull-ups for SDMMC1 on DHCOM SoM
The default state of SD bus and clock line is logical HI. SD card IO is
open-drain and pulls the bus lines LO. Always enable the SD bus pull ups
to guarantee this behavior on DHCOM SoM. Note that on SoMs with SD bus
voltage level shifter, the pull ups are built into the level shifter,
however that has no negative impact.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2020-12-09 10:57:50 +01:00
Tom Rini
19ea606109 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-imx 2020-12-08 09:53:03 -05:00
Pali Rohár
135973967b arm: mvebu: Espressobin: Add support for emmc into dts file
To simplify setup, configuration and compilation of u-boot, define emmc
node for all Espressobin boards. Espressobin boards without populated emmc
works correctly, just detection and initialization of emmc obviously fails.

Code for emmc is extracted from commit f1a43c84a9 ("arm64: dts: a3720:
add support for espressobin with populated emmc").

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Gérald Kerma <gerald@gk2.net>
2020-12-07 07:11:37 +01:00
Pali Rohár
c5c4b69857 Revert "arm64: dts: a3720: add support for espressobin with populated emmc"
This reverts commit f1a43c84a9.
2020-12-07 07:11:37 +01:00
Pali Rohár
338c5ee26a Revert "arm64: dts: armada-3720-espressobin: split common parts to .dtsi"
This reverts commit 03bb6a9b1e.
2020-12-07 07:11:37 +01:00
Igor Opaniuk
3d1103cefc ARM: dts: fsl-imx8qxp-apalis: add initial device tree
Introduce initial hierarchy of device trees for Apalis iMX8X
System on Module.

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Acked-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-12-06 15:31:37 +01:00
Max Krummenacher
caafc6c497 ARM: dts: imx8mm-verdin: follow changed pmic
The used PMIC has been changed from RHOM BD71837 to NXP PCA9450A.
Adjust the device tree accordingly.
Remove the old ADC node as the ADC has been changed and has no longer
a separate power rail.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-12-06 15:31:37 +01:00
Ian Ray
559aaa2526 board: ge: reduce VPD EEPROM partition size
Reduce vital product data size to match the latest specification.

Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
2020-12-06 15:31:37 +01:00
Heiko Schocher
68163c3bf0 arm: dts: aristainetos: sync with changes in linux
sync with comaptible changes in linux from
Krzysztof Kozlowski.

https://patchwork.kernel.org/project/linux-arm-kernel/patch/20200930190143.27032-12-krzk@kernel.org/

Signed-off-by: Heiko Schocher <hs@denx.de>
2020-12-06 15:07:35 +01:00
Heiko Schocher
015c026f7a imx6: add support for aristainetos2c_cslb board variant
add support for aristainetos2c_cslb board variant.

Signed-off-by: Heiko Schocher <hs@denx.de>
2020-12-06 15:07:06 +01:00
Heiko Schocher
3cf02f5ffa imx6: remove not longer supported aristainetos boards
Removed aristainetos2, 2b, 2b-csl. This boards have been
recalled and destroyed.

Adapt board code to remove stuff not needed anymore.

Fix checkpatch warning, remove fdt_high and initrd_high
from default environment.

Signed-off-by: Heiko Schocher <hs@denx.de>
zu remove
2020-12-06 15:06:16 +01:00
Michael Walle
4c450daf7d board: sl28: add OP-TEE Trusted OS support (bl32)
Add support to load the OP-TEE Trusted OS by the SPL.

Signed-off-by: Michael Walle <michael@walle.cc>
2020-12-04 16:09:06 -05:00
Michael Walle
e057760f38 board: sl28: add ATF support (bl31)
Add support to load the bl31 part of the ARM Trusted Firmware by the
SPL.

Signed-off-by: Michael Walle <michael@walle.cc>
2020-12-04 16:09:06 -05:00
Michael Walle
ea22783f40 board: sl28: remove u-boot from loadable DT node
It is not needed. Remove it.

Signed-off-by: Michael Walle <michael@walle.cc>
2020-12-04 16:09:06 -05:00
Eugen Hristev
1a5c5b716c ARM: dts: at91: sam9x60: enable slewrate/high drive for sdhci0 pinout
Align the pin setup for sdhci0 with linux kernel.
This means to have slew rate enable and high drive strength.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-26 10:12:47 +02:00
Patrick Delaunay
5a536dfe33 remoteproc: stm32: use reset for hold boot
Use the reset function to handle the hold boot bit in RCC
with device tree handle with MCU_HOLD_BOOT identifier.

This generic reset allows to remove the two specific properties:
- st,syscfg-holdboot
- st,syscfg-tz

This patch prepares alignment with kernel device tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Fabien DESSENNE <fabien.dessenne@st.com>
Cc: Arnaud POULIQUEN <arnaud.pouliquen@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-11-25 11:32:31 +01:00
Marek Vasut
34d573fdab ARM: dts: stm32: Drop QSPI CS2 on DHCOM
The QSPI CS2 is not used on DHCOM, remove the pinmux and flash@1.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-25 10:52:09 +01:00
Marek Vasut
64af7c3110 ARM: dts: stm32: Fix uSD card-detect GPIO on DHCOM
The uSD slot card-detect GPIO is connected to PG1, fix it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-25 10:50:44 +01:00
Marek Vasut
7d5164425b ARM: dts: stm32: Add DHCOM based PicoITX board
Add DT for DH PicoITX unit, which is a bare-bones carrier board for
the DHCOM. The board has ethernet port, USB, CAN, LEDs and a custom
board-to-board expansion connector.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-25 10:43:46 +01:00
Patrice Chotard
d5b0511391 ARM: dts: stm32: Fix typo in stm32h7-u-boot.dtsi
Fix typo "firsct"

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-25 10:29:23 +01:00
Patrice Chotard
183362947c ARM: dts: stm32: Fix timer initialization for stm32 MCU's board
Commit 4b2be78ab6 ("time: Fix get_ticks being non-monotonic")
puts in evidence that get_ticks is called before timer initialization.
Fix it by initializing timer before relocation.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-25 10:29:23 +01:00
Patrice Chotard
61c88ace4b ARM: dts: stm32: DT sync with kernel v5.10-rc1 for MCU's boards
Device tree alignment with kernel v5.10-rc1.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-25 10:29:23 +01:00
Patrice Chotard
63185b0a32 ARM: dts: sync armv7-m.dtsi with kernel v5.10-rc1
Since kernel v4.8-rc1, commit 05b23ebc2bd9 ("ARM: dts: armv7-m: remove skeleton.dtsi include"),
skeleton.dtsi file is no more included.

This synchronization is needed to avoid to get 2 memory node
in DTB file if, in DTS file, memory node is declared with the correct
syntax as following:

	memory@90000000 {
 		device_type = "memory";
 		reg = <0x90000000 0x800000>;
 	};

Then in DTB, we will have the 2 memory nodes, which is incorrect and
cause misbehavior during DT parsing by U-boot:

	memory {
		device_type = "memory";
		reg = <0x00 0x00>;
	};

	memory@90000000 {
		device_type = "memory";
		reg = <0x90000000 0x800000>;
	};

Issue found when synchronizing MCU's STM32 DT from kernel v5.10-rc1.
When using fdtdec_setup_mem_size_base() or fdtdec_setup_memory_banksize()
API, first above memory node is found (with reg = <0x00 0x00>), so
gd->ram_size, gd->ram_base, gd->bd->bi_dram[bank].start and
gd->bd->bi_dram[bank].size are all set to 0 which avoid boards to boot.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-25 10:29:23 +01:00
Icenowy Zheng
6d5d6bb50d sunxi: dts: sync Allwinner V3s-related DTs from Linux 5.10-rc1
This commit imports device tree files that are related to Allwinner V3
series from Linux commit 3650b228f83a ("Linux 5.10-rc1").

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-11-17 00:42:21 +00:00
Samuel Holland
e210ec0181 sunxi: DT: A64: update device tree files
Import updated device trees from Linux tag v5.9. This picks up new
hardware (PinePhone, PineTab); and it drops the U-Boot specific DTSI
files for the Pinebook and the Teres-I, since the ANX6345 bridge is
now supported upstream.

A couple of headers needed updates for recently-added hardware support.

Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-11-17 00:42:20 +00:00
Tom Rini
9324c9a823 Merge tag 'ti-v2021.01-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti
- Fix Nokia RX-51 boot issues
- Fix CONFIG_LOGLEVEL on K3 devices
- Add phyBOARD REGOR support
2020-11-16 13:42:29 -05:00
Tom Rini
530dcdd07c - Clock fix MMC driver for SM1 based platforms
- sync SOC Ids from Linux 5.10-rc1
 - fix potential build warning on meson_dw_hdmi and meson-g12a-usb2 phy
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAl+yUlUACgkQd9zb2sjI
 SdE/qg/+LFGSw26m9u0G9Umfpogy0DW73aJv/MOA3xcEyk7k2Cc6lJ6agk2oll7v
 6Uus8zZXWnPOQ/M2utELGIXBqP9J9i+I6JdGb5t7e0NqpzJqJiVUWIeuuDg9zSqP
 ZZmw3JoNRsMsrUBxJREOM2ERFYhYUkNM0EK7mRzoKs7kKYiJ4TsjeXpuDyxvZQ1o
 La9BGyiAAB+n3hRs1mjQ/lwO5M1nZgSNt3Krw61L9YOV+ahP7+F5FRJksW7Sgv5X
 /3DGm8eqsqVP8mNqZW55yp45uUVE4ZL98yibBLRJONW5/cKjUyGlnxy6Vy6OXDP4
 eXZzYct2nlIMNAbCjB49WoUxxbjg4eLPxSIGGLRdVJliYNOFXIgqEnsFCq7Zlare
 rLQc+TSl0pM+mWKjGchLxMxrA6D5F6ERjIwTukDEjkNQcsXNQkUGC0IKcUM0x7Rf
 N6+eMXBgWYIjgFLXju+B+dZgrDA0BdXs9oaok1idIxBgWqIQ3o4EyIk1sWIHcb/1
 8HL9XEd8oC3G1G4T3Ze++9sUd4MgA3ELOiCQapx7zh/gPDYaYr9yfr2WyRcoMcqK
 Dwlo9os2q0nfOmg6qcmyN5R0flGEDEtBB6/hj2v2mvj9qMA66kSfsMfkqSVbYSZg
 6Kt+ScmKYNpCZiFHX1yUygBHgexvWxxPqhm5eV4gd4/7cNWkCwM=
 =oTd7
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-amlogic-20201116' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- Clock fix MMC driver for SM1 based platforms
- sync SOC Ids from Linux 5.10-rc1
- fix potential build warning on meson_dw_hdmi and meson-g12a-usb2 phy
2020-11-16 10:50:32 -05:00
Parthiban Nallathambi
a1337e3581 ARM: am335x: Add phyBOARD REGOR support
phyBOARD-REGOR is based on phyCORE AM335x R2 SoM (PCL060).

CPU  : AM335X-GP rev 2.1
Model: Phytec AM335x phyBOARD-REGOR
DRAM:  512 MiB
NAND:  512 MiB
MMC:   OMAP SD/MMC: 0
eth0: ethernet@4a100000

Working:
 - Eth0
 - i2C
 - MMC/SD
 - NAND
 - UART
 - USB (host)

Device trees were taken from Linux mainline:
commit c4d6fe731176 ("Linux 5.9.0")

Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-11-15 15:14:04 +05:30
Hugh Cole-Baker
c180e2939d rockchip: rockpro64: fix boot from SPI flash on spi1
Commit c4cea2bbf9 ("rockchip: Enable building a SPI ROM image on bob")
added an alias spi1 referring to spi@ff1d0000, however there was already
an alias spi0 referring to the same node in rockpro64's u-boot.dtsi, and
having both aliases present broke booting from SPI flash for this board.

Remove the spi0 alias, set the default bus for SPI flash to 1, and
enable support for numbered aliases in SPL so that it uses the same bus
numbering as U-Boot proper. This fixes booting from U-Boot in SPI flash
on the rockpro64 board.

Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Suggested-by: Simon Glass <sjg@chromium.org>
Fixes: c4cea2bbf9 ("rockchip: Enable building a SPI ROM image on bob")
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-11-13 18:16:39 +08:00
Neil Armstrong
c87eab8161 ARM: dts: meson-sm1: add u-boot specific MMC controller compatible
In order to enable the Amlogic SM1 MMC controller fix, we need to add a u-boot specific
MMC controller compatible.

This adds a new meson-sm1-u-boot.dtsi and reworks the other -u-boot.dtsi
to use this for SM1 based boards.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-11-12 14:31:29 +01:00
Tom Rini
d062c1344c Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- Add a new SMBIOS parser and enable it when booting from coreboot
- Fix up various driver names to avoid dtoc warnings
- Fully enable ACPI support on Google Chromebook Coral
- Add a way to set SMBIOS properties using the devicetree
- Update existing boards to use devicetree for SMBIOS using a new
  default sysinfo driver
2020-11-06 09:46:43 -05:00
Simon Glass
fa9e1bcfc4 arm64: mvebu: Use devicetree for SMBIOS settings on uDPU
Add settings and enable the default sysinfo driver so that these can come
from the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 10:18:20 +08:00
Simon Glass
a1d63bc135 odroid-c2: Use devicetree for SMBIOS settings
Add settings and enable the default sysinfo driver so that these can come
from the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 10:18:20 +08:00
Simon Glass
c0697c1f4b imx: Use devicetree for SMBIOS settings on MYiR MYS-6ULX
Add settings and enable the default sysinfo driver so that these can come
from the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 10:18:20 +08:00
Simon Glass
70190f82cb rockchip: Use devicetree for SMBIOS settings
Add settings and enable the default sysinfo driver so that these can come
from the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 10:18:20 +08:00
Tom Rini
7716c328c8 u-boot-imx for 2021.1
---------------------
 
 - new boards : GE (new B1x5v2), phytec phyCORE-i.MX8MM
 - converted doc to reST
 - fixes for verdin-imx8mm (Toradex)
 - fixes for i.MX thermal driver
 - mx7ulp: Align the PLL_USB frequency
 - mx53: primary/secondary bmode
 
 Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/741465284
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQS2TmnA27QKhpKSZe309WXkmmjvpgUCX6QsVQ8cc2JhYmljQGRl
 bnguZGUACgkQ9PVl5Jpo76Z29ACfRdzFocIVEOFNm8v5yA1C/FU9q9sAn1kEAot5
 vkm2yvDQ7+9vl5G7+ZRn
 =rCCX
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20201105' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx for 2021.1
---------------------

- new boards : GE (new B1x5v2), phytec phyCORE-i.MX8MM
- converted doc to reST
- fixes for verdin-imx8mm (Toradex)
- fixes for i.MX thermal driver
- mx7ulp: Align the PLL_USB frequency
- mx53: primary/secondary bmode

Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/741465284
2020-11-05 11:57:50 -05:00
Tom Rini
7a8ac9df5d First set of u-boot-atmel fixes for 2021.01 cycle
-----BEGIN PGP SIGNATURE-----
 
 iQFQBAABCgA6FiEEqxhEmNJ6d7ZdeFLIHrMeAg6sL8gFAl+frmwcHGV1Z2VuLmhy
 aXN0ZXZAbWljcm9jaGlwLmNvbQAKCRAesx4CDqwvyP/tCACuq3aixxpR1qzb/Tk6
 MnE/Io9ehtq8WfY2M8ks5RK+K5Ezaukh9Edg7YW8j0mvoBZUQ35at8UXanr8XkEx
 vk51AkwmTJeckjZ7I8D9m/AIyAU4lVCB/HJp3KRcTdu39bSy+beudg7uinlmvoHP
 GSqmGArU58pbHrHi1xVgf8PIbCd52mVPvDu+ghxjKOTPl87WlRCjxelPuMxjLEQ2
 8KUuxuXad82S7oRFQz/TDkokf+d8AZVAbOXWqxAnHWNml+qXLWn/oohSQ5+QsYRY
 3K2cJFvI3cmAcr9usOX268u0wGd9kDYnQtfym2M8ul70S3pesqUsoiSET9vXq3zL
 yu8a
 =QSvy
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-atmel-fixes-2021.01-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel

First set of u-boot-atmel fixes for 2021.01 cycle:

This specific feature set includes the patches for DT required to fix
the warnings for newer DTC version (1.6.0+), i2c and spi bus unit
address.
2020-11-02 09:01:28 -05:00
Eugen Hristev
ef8f34aea5 ARM: dts: at91: sama5d3xmb_cmp: fix SPI bus unit address
w+arch/arm/dts/.at91sam9260ek.dtb.pre.tmp:119.21-123.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:38 +02:00
Eugen Hristev
2733e6fe5d ARM: dts: at91: sam9260ek: fix SPI bus unit address
w+arch/arm/dts/.at91sam9260ek.dtb.pre.tmp:119.21-123.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:38 +02:00
Eugen Hristev
9f37458b30 ARM: dts: at91: sama5d3xmb: fix I2C bus unit address
w+arch/arm/dts/sama5d3xmb.dtsi:64.25-83.7: Warning (i2c_bus_reg): /ahb/apb/i2c@f0018000/camera@0x30: I2C bus unit address format error, expected "30"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:38 +02:00
Eugen Hristev
e0df9e846c ARM: dts: at91: gurnard: fix SPI bus unit address
w+arch/arm/dts/.at91sam9g45-gurnard.dtb.pre.tmp:118.21-122.7: Warning (spi_bus_reg): /ahb/apb/spi@fffa4000/mtd_dataflash@0: SPI bus unit address format error, expected "1"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:38 +02:00
Eugen Hristev
397a28604c ARM: dts: at91: at91sam9g25ek: fix I2C bus unit address
w+arch/arm/dts/.at91sam9g25ek.dtb.pre.tmp:28.25-47.7: Warning (i2c_bus_reg): /ahb/apb/i2c@f8010000/camera@0x30: I2C bus unit address format error, expected "30"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:38 +02:00
Eugen Hristev
6f668d2756 ARM: dts: at91: at91sam9g20ek_common: fix SPI bus unit address
w+arch/arm/dts/at91sam9g20ek_common.dtsi:100.21-104.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:37 +02:00
Eugen Hristev
f56a0ca685 ARM: dts: at91: at91sam9g20-taurus: fix SPI bus unit address
w+arch/arm/dts/.at91sam9g20-taurus.dtb.pre.tmp:79.18-83.4: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:37 +02:00
Eugen Hristev
a013df93e1 ARM: dts: at91: at91sam9261ek: fix SPI unit address warning
w+arch/arm/dts/.at91sam9261ek.dtb.pre.tmp:124.15-144.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/tsc2046@0: SPI bus unit address format error, expected "2"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:37 +02:00
Eugen Hristev
7d0cad03d5 ARM: dts: at91: vinco: fix I2C warning bus unit address
w+arch/arm/dts/.at91-vinco.dtb.pre.tmp:131.18-134.7: Warning (i2c_bus_reg): /ahb/apb/i2c@f8024000/rtc@64: I2C bus unit address format error, expected "32"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:37 +02:00
Sebastian Reichel
64272efdaf board: ge: b1x5v2: Add GE B1x5v2 and B1x5Pv2
GE B1x5v2 patient monitor series is similar to the CARESCAPE Monitor
series (GE Bx50). It consists of a carrier PCB used in combination
with a Congatec QMX6 SoM. This adds U-Boot support using device model
everywhere and SPL for memory initialization.

Proper configuration is provided as 'ge_b1x5v2_defconfig' and the
combined image u-boot-with-spi.imx can be flashed directly to 1024
byte offset to /dev/mtdblock0. Alternatively SPL and u-boot.imx can
be loaded separately via USB-OTG using e.g. imx_usb.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-11-01 16:01:40 +01:00
Teresa Remmet
0cc2a07879 board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support
Add support PHYTEC phyCORE-i.MX8MM SOM.

Supported features:
 - 2GB LPDDR4 RAM
 - 1x 1Gbit Ethernet
 - eMMC
 - external SD
 - debug UART3
 - watchdog
 - i2c eeprom

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-11-01 15:58:19 +01:00
Lukasz Majewski
8a8ec73ebd dts: Provide LED DTS description for HSC and DDC imx53 devices
Those two LEDs are used to indicate U-Boot's boot stage.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2020-11-01 15:53:51 +01:00
Tom Rini
2c31d7e746 Merge tag 'u-boot-rockchip-20201031' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- New PX30 board: Engicam PX30.Core;
- Fix USB HID support for rock960;
- Remove host endianness dependency for rockchip mkimage;
- dts update for rk3288-tinker;
- Enable console MUX for some ROCKPi boards;
- Add config-based ddr selection for px30;
2020-10-30 23:13:13 -04:00
Jagan Teki
51656ae1d1 rockchip: Add Engicam PX30.Core C.TOUCH 2.0
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.

C.TOUCH 2.0 is a general purpose carrier board with capacitive
touch interface support.

PX30.Core needs to mount on top of this Carrier board for creating
complete PX30.Core C.TOUCH 2.0 board.

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Jagan Teki
d432975cec arm64: dts: rockchip: px30: Add Engicam C.TOUCH 2.0
Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose
carrier board with capacitive touch interface.

Genaral features:
- TFT 10.1" industrial, 1280x800 LVDS display
- Ethernet 10/100
- Wifi/BT
- USB Type A/OTG
- Audio Out
- CAN
- LVDS panel connector

SOM's like PX30.Core needs to mount on top of this Carrier board
for creating complete PX30.Core C.TOUCH 2.0 board.

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Jagan Teki
39c8b2c72a rockchip: Add Engicam PX30.Core EDIMM2.2 Starter Kit
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.

EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board from Engicam.

PX30.Core needs to mount on top of this Evaluation board for
creating complete PX30.Core EDIMM2.2 Starter Kit.

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Michael Trimarchi
9946bfd4a0 arm64: dts: rockchip: Add Engicam PX30.Core SOM
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.

General features:
- Rockchip PX30
- Up to 2GB DDR4
- eMMC 4 GB expandible
- rest of PX30 features

PX30.Core needs to mount on top of Engicam baseboards for creating
complete platform boards.

Possible baseboards are,
- EDIMM2.2
- C.TOUCH 2.0

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Jagan Teki
282ad86aaa arm64: dts: rockchip: px30: Add Engicam EDIMM2.2 Starter Kit
Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board.

Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Mini PCIe
- MIPI CSI
- 2x CAN
- Audio Out

SOM's like PX30.Core needs to mount on top of this Evaluation board
for creating complete PX30.Core EDIMM2.2 Starter Kit.

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Jagan Teki
dfec5a4ec0 arm64: dts: rockchip: Add chosen node for ROCK-Pi N8
Add chosen node in -u-boot.dtsi for ROCK-Pi N8 board.

This will help to get serial out messages.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 23:09:01 +08:00
Stefan Agner
ee68c83d0a rockchip: dts: tinker: remove unnecessary node
The property reg-shift with the same value is present in the base
device tree already. Remove unnecessary node from rk3288-tinker.dts.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-10-30 18:06:13 +08:00
Stefan Agner
cfac752dad rockchip: dts: tinker: move i2c node to shared device tree
The I2C EEPROM is present on Tinker Board S as well. Move the i2c node
to the shared, U-Boot specific rk3288-tinker-u-boot.dtsi device tree.

Cc: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-10-30 18:06:13 +08:00
Tom Rini
8d7f3fcb4a Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Armada 8k: Add NAND support via PXA3xx NAND driver (Baruch)
- Armada 8k: Use ATF serdes init instead of the "old" U-Boot version
  (Baruch)
- Minor update to Octeon TX/TX2 defconfig (Stefan)
2020-10-29 11:30:29 -04:00
Tom Rini
47754334b1 Xilinx changes for v2021.01-v2
common:
 - Add support for 64bit loadables from SPL
 
 xilinx:
 - Update documentation and record ownership
 - Enable eeprom board detection based legacy and fru formats
 - Add support for FRU format
 
 microblaze:
 - Optimize low level ASM code
 - Enable SPI/I2C
 - Enable distro boot
 
 zynq:
 - Add support for Zturn V5
 
 zynqmp:
 - Improve silicon detection code
 - Enable several kconfig options
 - Align DT with the latest state
 - Enabling security commands
 - Enable and support FPGA loading from SPL
 - Optimize xilinx_pm_request() calling
 
 versal:
 - Some DTs/Kconfig/defconfig alignments
 - Add binding header for clock and power
 
 zynq-sdhci:
 - Add support for tap delay programming
 
 zynq-spi/zynq-qspi:
 - Use clock framework for getting clocks
 
 xilinx-spi:
 - Fix some code issues (unused variables)
 
 serial:
 - Check return value from clock functions in pl01x
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCX5rH/QAKCRDKSWXLKUoM
 IRPAAJ9SvHR3w1qTc5W+Q5CWBUH5wJbNYQCaA4PpqZCdvyu1+nF5luL6JHhbDgw=
 =hOd7
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2021.01-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2021.01-v2

common:
- Add support for 64bit loadables from SPL

xilinx:
- Update documentation and record ownership
- Enable eeprom board detection based legacy and fru formats
- Add support for FRU format

microblaze:
- Optimize low level ASM code
- Enable SPI/I2C
- Enable distro boot

zynq:
- Add support for Zturn V5

zynqmp:
- Improve silicon detection code
- Enable several kconfig options
- Align DT with the latest state
- Enabling security commands
- Enable and support FPGA loading from SPL
- Optimize xilinx_pm_request() calling

versal:
- Some DTs/Kconfig/defconfig alignments
- Add binding header for clock and power

zynq-sdhci:
- Add support for tap delay programming

zynq-spi/zynq-qspi:
- Use clock framework for getting clocks

xilinx-spi:
- Fix some code issues (unused variables)

serial:
- Check return value from clock functions in pl01x
2020-10-29 11:30:15 -04:00
Tom Rini
eca57cafa5 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Bug fixes and updates on vid, ls1088a lx2160a and other layerscape
  platforms.
- Add optee_rpmb support for LX2 & Kontron sl28 support
2020-10-29 09:10:24 -04:00
Baruch Siach
a941226e00 arm: dts: armada-cp110-master: update nand-controller
Align node properties to kernel dts node.

The change of compatible property does not affect any currently
supported board.

Keep U-Boot specific nand-enable-arbiter, and num-cs for compatibility
with the current driver.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2020-10-29 08:00:12 +01:00
Shmuel Hazan
e2eafaa18a arm: dts: armada-cp110-slave: add missing cps_nand
Align node properties to kernel dts node.

Keep U-Boot specific nand-enable-arbiter, and num-cs for compatibility
with the current driver.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Shmuel Hazan <shmuel.h@siklu.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2020-10-29 08:00:12 +01:00
T Karthik Reddy
d93fbac512 arm64: zynqmp: Fix zynqmp mini qspi max frequency
For zynqmp qspi, frequencies up to 40MHz will work irrespective
of feedback clock enabled or disabled. If we want higher than
40Mhz the feedback clock should be enabled.

With spi-max-frequency 108MHz it is not working when the feedback
clock is disabled. Change it to 40MHz so that it works irrespective
of feedback clock enabled or disabled.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:33 +01:00
Ashok Reddy Soma
90f06e9d20 arm64: versal: Update mini u-boot eMMC node parameters
Mini u-boot eMMC dt parameters are not in sync with full u-boot dt.

Frequency for eMMC is fixed to 25Mhz. Due to this, mmc multi-block write
commands are failing. Increase frequency to 200Mhz to fix this issue.

Add bus-width = <8>, non-removable and disable-wp properties to the node
as this is eMMC.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:31 +01:00
Alexandre GRIVEAUX
bd897a0789 ARM: zynq: Add Z-turn board V5
Adding Z-turn board V5 to resolve the change between:

"Z-TURNBOARD_schematic.pdf" schematics state version 1 to 4 has Atheros AR8035
"Z-Turn_Board_sch_V15_20160303.pdf" schematics state version 5 has Micrel KSZ9031

At this time the S25FL128SAGNFI003 doesn't work because of bug:

*** Warning - spi_flash_probe_bus_cs() failed, using default environment

zynq-zturn was checked on V5 board, same error.

Maybe Z-turn board have the same problem (board with W25Q128BVFIG).

Signed-off-by: Alexandre GRIVEAUX <agriveaux@deutnet.info>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:01:36 +01:00
Michael Walle
4ceb5c6db2 board: kontron: add sl28 support
Add basic support for the Kontron SMARC-sAL28 board. This includes just
the bare minimum to be able to bring up the board and boot linux.

For now, the Single and Dual PHY variant is supported. Other variants
will fall back to the basic variant.

In particular, there is no watchdog support for now. This means that you
have to disable the default watchdog, otherwise you'll end up in the
recovery bootloader. See the board README for details.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-23 16:52:09 +05:30
Tom Rini
18261b8552 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi
- sun8i emac changes (Andre)
- SCP firmware (Samuel)
2020-10-22 20:32:02 -04:00
Chia-Wei, Wang
611a28ce27 reset: ast2500: Use SCU for reset control
The System Control Unit (SCU) controller of Aspeed
SoCs provides the reset control for each peripheral.

This patch refactors the reset method to leverage
the SCU reset control. Thus the driver dependency
on watchdog including dedicated WDT API and reset
flag encoding can be eliminated.

The Kconfig description is also updated accordingly.

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-10-22 11:26:14 -04:00
Robert Marko
cfec8d36ce IPQ40xx: Add PRNG support
Since we now have the driver for Qualcomm PRNG HW, lets use it and add the necessary clocks and nodes.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-10-22 09:54:54 -04:00
Robert Marko
5297341ab1 IPQ40xx: Add support for MDIO
Lets add the necessary DTS node and pinctrl properties for newly added MDIO driver.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-10-22 09:54:54 -04:00
Robert Marko
96d6036671 IPQ40xx: Add SPI support
Since we have SPI driver for IPQ40xx QUP SPI controller, lets add the necessary nodes, pinctrl and clocks.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-10-22 09:54:54 -04:00
Holger Brunck
5d57dfad3f km: fix license string and compatible strings
As the ownership is now Hitachi Power Grids, change the license string
and adapt the compatible string in DTS files. For kmeter1.dts we
change it to "keymile,KMETER1" for now, as this is then compliant with
what is submitted to the linux kernel. All other boards don't have
a upstreamed version in linux mainline.

Signed-off-by: Holger Brunck <holger.brunck@hitachi-powergrids.com>
CC: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com>
CC: Heiko Schocher <hs@denx.de>
CC: Marek Vasut <marex@denx.de>
CC: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-10-22 09:54:54 -04:00
Samuel Holland
e72a6be4fc sunxi: binman: Add support for including SCP firmware
Allwinner sun50i SoCs contain an OpenRISC 1000 CPU that functions as a
System Control Processor, or SCP. ARM Trusted Firmware (ATF)
communicates with the SCP over SCPI to implement the PSCI system
suspend, shutdown and reset functionality. Currently, SCP firmware is
optional; the system will boot and run without it, but system suspend
will be unavailable.

Since all communication with the SCP is mediated by ATF, the only thing
U-Boot needs to do is load the firmware into SRAM. The SCP firmware
occupies the last 16KiB of SRAM A2, immediately following ATF.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22 11:43:43 +05:30
Samuel Holland
68158d59d2 sunxi: binman: Update FIT component descriptions
Since commit d879616e9e ("spl: fit: simplify logic for FDT loading for
non-OS boots"), the SPL looks at the "os" properties of FIT images to
determine where to append the FDT.

The "os" property of the "firmware" image also determines how to execute
the next stage of the boot process, as in 1d3790905d ("spl: atf:
introduce spl_invoke_atf and make bl31_entry private"). For this reason,
the next stage must be specified in "firmware", not in "loadables".

To support this additional functionality, and to properly model the boot
process, where ATF runs before U-Boot, add the "os" properties and swap
the firmware/loadable images in the FIT image.

Since this description was copied as an example in commit 70248d6a2916
("binman: Support generating FITs with multiple dtbs"), update those
examples as well for correctness and consistency.

Acked-by: Patrick Wildt <patrick@blueri.se>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22 11:43:43 +05:30
Samuel Holland
827c420c40 sunxi: binman: Use a macro for the BL31 load address
This consolidates the SoC-specific part at the top of the file to avoid
cluttering it up with preprocessor conditions.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22 11:43:43 +05:30
Samuel Holland
6b7c7ed80a sunxi: binman: Provide a default BL31 filename
Prior to commit 7f7f8aca8257 ("sunxi: Convert 64-bit boards to use
binman"), if the BL31 environment variable was not defined, the firmware
would be loaded from a file "bl31.bin" in the current directory. Restore
that behavior by providing that as the default filename in case no entry
arg is provided, which will be the case if the environment variable is
unset.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22 11:43:43 +05:30
Samuel Holland
eafbdbb8eb sunxi: binman: Fix spacing between nodes
Nodes should have a blank line separating them from sibling nodes and
properties. Add the necessary lines.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22 11:43:43 +05:30
Tom Rini
adc0c39633 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sh
- Assorted R-Car Gen3 updates
2020-10-20 08:02:53 -04:00
Lad Prabhakar
fc5e552209 arm: dts: r8a774c0: Import DTS from Linux 5.9
Import R8A774C0 (RZ/G2E) SoC DTSI and headers from Linux 5.9
commit bbf5c979011a ("Linux 5.9").

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20 12:56:51 +02:00
Chunfeng Yun
d6fa8db8b9 arm: dts: mt8512: add usb related nodes
Add usb, usb phy, and fixed regulators nodes

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20 00:49:05 +02:00
Claudiu Beznea
42f2dfa789 ARM: dts: sam9x60: use alphabetical order
Use alphabetical order for entries in sam9x60ek-u-boot.dtsi

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
c37d59a170 ARM: dts: sam9x60: use CCF compatibles for PMC
Use CCF compatible for PMC. With this, the board/SoC will be
able to boot.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
dbe10b6274 ARM: dts: sam9x60: use slow clock CCF compatible bindings
Use slow clock CCF compatible DT bindings. This will not break
the above functionality as the SoC is not booting with current
PMC bindings.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
5dff16db16 ARM: dts: sam9x60: use u-boot,dm-pre-reloc
Use u-boot,dm-pre-reloc for slow xtal and main xtal.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
ffd204f347 ARM: dts: sam9x60ek: add clock frequencies to board file
Slow Xtal and Main Xtal are board specific. Add their proper
frequency to board file.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Tom Rini
9dc6aef8c9 Merge tag 'mmc-2020-10-14' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
- fsl_esdhc_imx cleanup
- not send cm13 if send_status is 0.
- Add reinit API
- Add mmc HS400 for fsl_esdhc
- Several cleanup for fsl_esdhc
- Add ADMA2 for sdhci
2020-10-15 08:20:42 -04:00
Andre Heider
f1a43c84a9 arm64: dts: a3720: add support for espressobin with populated emmc
Import armada-3720-espressobin-emmc.dts from Linux, but use sdhc1 for
emmc, since our dtsi is still based on downstream and sdhc0 is used for
the sd card.

Signed-off-by: Andre Heider <a.heider@gmail.com>
2020-10-14 07:56:17 +02:00
Andre Heider
03bb6a9b1e arm64: dts: armada-3720-espressobin: split common parts to .dtsi
Move most of the dts to the new common armada-3720-espressobin.dtsi
file, just like Linux, but keep the current, downstream based, version.

The dts itself is imported from Linux.

Signed-off-by: Andre Heider <a.heider@gmail.com>
2020-10-14 07:56:17 +02:00
Andre Heider
559ae35c96 arm64: dts: armada-3720-espressobin: use Linux model/compatible strings
Fix the actual board vendor and ease synching dts files from Linux.

Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-14 07:55:56 +02:00
Luka Kovacic
2ae2b8a2f2 arm: mvebu: Initial iEi Puzzle-M801 support
Add initial U-Boot support for the iEi Puzzle-M801 board based on the
Marvell Armada 88F8040 SoC.

Currently supported hardware:
1x USB 3.0
4x Gigabit Ethernet
2x SFP+ (with NXP PCA9555 and NXP PCA9544)
1x SATA 3.0
1x M.2 type B
1x RJ45 UART
1x SPI flash
1x EPSON RX8010 RTC

Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-14 07:55:56 +02:00
Yangbo Lu
dedd632f56 arm: dts: lx2160ardb: support eMMC HS400 mode
Add properties related to eMMC HS400 mode.

mmc-hs400-1_8v;
bus-width = <8>;

They had been already in kernel dts file since the first
lx2160ardb dts patch.

b068890 arm64: dts: add LX2160ARDB board support

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12 15:47:07 +08:00
Ley Foon Tan
98c28a79b4 arm: dts: socfpga: arria10: Move to use generic handoff dtsi
Move to use generic handoff dtsi (socfpga_arria10-handoff.dtsi) and include
the specify generated _handoff.h header file from qts-filter-a10.sh script.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:14 +08:00
Dalon Westergreen
ed9c0823c5 arm: socfpga: arria10: Add handoff header for A10 SoCDK SDMMC
Add the qts-filter-a10.sh generated handoff header file for the Arria10
SoCDK SDMMC u-boot device tree.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:14 +08:00
Chee Hong Ang
2473e13bb8 arm: socfpga: Use DM watchdog timer
All SoCFPGA platforms (except Cyclone V) are now switching
to CONFIG_WDT (driver model for watchdog timer drivers)
from CONFIG_HW_WATCHDOG.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:12 +08:00
Tom Rini
987ab49366 - generate unique mac address from SoC serial on S400 board
- Add USB support for GXL and AXG SoCs
 - Update Gadget code to use the new GXL and AXG USB glue driver
 - Add a VIM3 board support to add dynamic PCIe enable in OS DT
 - Fix AXG pinmux with requesting GPIOs
 - Add missing GPIOA_18 for AXG pinctrl
 - Add Amlogic PWM driver
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAl97ReAACgkQd9zb2sjI
 SdHHVA/9HuEAzwuJyJoyQcXARIqMwoi6w4qntlmb+VTnxxlKCzLL1Ir68W2+5Y5S
 l+sVkxYDwTmYRs40FOnMdFM1r1Q7IqWwTemqQAcfmGLV+/+MwoDiludGat7JAp1i
 mo/FBcBMLrf3dIJnhCyl2Rezgu06GLCQMAJOlusTDaruUZUHBxPVpAhfRvtlYq1Q
 bCINZfgMcmv8EfReIOE6xGt0+9TKILqQamMByc2ZWdz5UBioqUdQ82arW1rdV/ze
 ATU7vrxNmNlUQnRsMBOry9chbeuNrAhD8sqVloGPUikhf93y0BG7eINmCYrLoXjN
 mopApyWzo3+50GI6It+P9vX6mWVJhd8gAJsvTkRn8ok3flGlRQPmFmAfkjngN/GH
 wdkZpKi/u/ndm2Id7ekZff/Fm/ZmL/kskrRWaWrnuxHNiSNiJvAl+PU7MzCGrgED
 E0MduY1hFpa7wc47xFtI0WKlcdNVQCTRwuZYVIZYlnhXeVupJyQ0dx1ggonlvvIZ
 3cgS2qzd8z2RxKzhnRDvjSfwy7gWFjqpljocyRP4osoWJybJu88MIUFK2GlPdc7x
 3UD/+R88FsIVsQuxzbwBuFZnP+Zo1JqCmspyX4sCeUBDNK4+MqOqIxBZry+q4qso
 usWrTofg2hfxS3FgUL0pQW5GF8JGm4uXcIjbe7fMi47GJ6Lp/ec=
 =rbAX
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-amlogic-20201005' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- generate unique mac address from SoC serial on S400 board
- Add USB support for GXL and AXG SoCs
- Update Gadget code to use the new GXL and AXG USB glue driver
- Add a VIM3 board support to add dynamic PCIe enable in OS DT
- Fix AXG pinmux with requesting GPIOs
- Add missing GPIOA_18 for AXG pinctrl
- Add Amlogic PWM driver
2020-10-06 08:36:10 -04:00
Tom Rini
b7e7831e5d Merge branch 'next'
Bring in the assorted changes that have been staged in the 'next' branch
prior to release.

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-05 14:10:59 -04:00
Neil Armstrong
1110e49e34 ARM: dts: sync amlogic G12A/SM1 DT from Linux 5.9-rc1
This imports the G12A & SM1 SoC and boards DT changes from the Linux
commit 9123e3a74ec7 ("Linux 5.9-rc1").

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05 17:59:45 +02:00
Neil Armstrong
85a034c275 ARM: dts: meson-axg: add USB nodes for S400
Add the correcly architectured USB Glue node for Meson AXG and the
S400 board in -u-boot.dtsi until support in upstream Linux then
backported.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05 17:59:45 +02:00
Neil Armstrong
4e7b0a3f2a ARM: dts: sync amlogic AXG/GXL/GXM DT from Linux 5.8-rc1
This imports the AXG, GXL & GXM SoC and boards DT changes from the Linux
commit b3a9e3b9622a ("Linux 5.8-rc1").

This change also removes GXL & GXM u-boot.dtsi hacks for USB gadget.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05 17:59:45 +02:00
Tom Rini
caebff09ef First set of u-boot-atmel features for 2021.01 cycle
-----BEGIN PGP SIGNATURE-----
 
 iQFQBAABCgA6FiEEqxhEmNJ6d7ZdeFLIHrMeAg6sL8gFAl960JkcHGV1Z2VuLmhy
 aXN0ZXZAbWljcm9jaGlwLmNvbQAKCRAesx4CDqwvyDaWCACYjvloDzXQaYaauWwR
 whFwgkUAQ8yjadj/12We/X2b7HGisNFNE80e/V4MU8RrJDFZmohZdLWMfRKez29X
 d+BG+OzVXxHWozny7ZQ2g1yYJbgCI7sVUeemQjUBZJ6aKPneQlVfwyfT2l88wOVK
 yQMqS+ZyVogihR9/NHCOlJHog+6OOoBmc16w1tymM6QcO8ZsYeA66ed8SLnjDb3N
 Rg2Ll2RR/lHuD/Fpxt1aUhybXFKSIOr4Qopo5X0hw5B3ibkp6JXGRE2wIwQYw6CA
 q+sKTg37CSzylipkQ5EOGdLcXD7r3KIGkSbUMb8wvt6dROarnIuQ+zJeF3sr+l2H
 hSoU
 =vHqZ
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-atmel-2021.01-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel into next

First set of u-boot-atmel features for 2021.01 cycle:

This feature set includes a new CPU driver for at91 family, new driver
for PIT64B hardware timer, support for new at91 family SoC named sama7g5
which adds: clock support, including conversion of the clock tree to
CCF; SoC support in mach-at91, pinctrl and mmc drivers update.  The
feature set also includes updates for mmc driver and some other minor
fixes and features regarding building without the old Atmel PIT and the
possibility to read a secondary MAC address from a second i2c EEPROM.
2020-10-05 10:54:27 -04:00
Patrick Delaunay
62f95af92a ARM: dts: stm32mp1: DT alignment with Linux kernel v5.9-rc4
DT alignment with Linux kernel v5.9-rc4 for the STM32MP15x soc
device tree files and the STMicroelectronics boards device tree files.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-02 14:56:56 +02:00
Marek Vasut
d9839417cb ARM: dts: stm32: Add missing dm-spl props for SPI NOR on AV96
The u-boot,dm-spl DT props are missing on AV96, hence the pinmux and
flash0 nodes are not included in the reduced SPL DT. This prevents
SPI NOR boot from working at all. Fix this by filling them in.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-10-02 14:18:00 +02:00
Biju Das
3afde5aab6 arm: dts: r8a774e1: Import DTS from Linux 5.9-rc4
Import R8A774E1 (RZ/G2H) SoC DTSI and headers from upstream Linux kernel
5.9-rc4 commit f4d51dffc6c0 ("Linux 5.9-rc4")

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-26 17:25:43 +02:00
Biju Das
1abdab94f1 arm: dts: r8a774b1: Import DTS from Linux 5.9-rc4
Import R8A774B1 (RZ/G2N) SoC DTSI and headers from upstream Linux kernel
5.9-rc4 commit f4d51dffc6c0 ("Linux 5.9-rc4")

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-26 17:25:43 +02:00
Biju Das
00407251c3 arm: dts: r8a774a1: Import DTS from Linux 5.9-rc4
Synchronize RZ/G2M SoC DTs with mainline Linux 5.9-rc4 commit
f4d51dffc6c0 ("Linux 5.9-rc4")

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-26 17:25:43 +02:00
Marek Vasut
16dcfbcd2b ARM: rmobile: Enable RPC on Salvator-X, ULCB, Ebisu
Enable the RPC Hyperflash driver on R8A7795,R8A7796,R8A77965
Salvator-X,ULCB and R8A77990 Ebisu. Note that to make the HF
accessible, mainline ATF is mandatory and must be built with
RCAR_RPC_HYPERFLASH_LOCKED=0 . Note that this is intended for
development and testing convenience only and must be disabled
in deployment for platform security reasons.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-09-26 17:25:42 +02:00
Eugen Hristev
558378a4cd ARM: mach-at91: add support for new SoC sama7g5
Add support for new SoC sama7g5

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-09-25 10:39:22 +03:00
Wasim Khan
450d491293 arm: dts: lx2160a: Add IO range
Add IO range property to fix below error on uboot
PCI: Failed autoconfig bar 18

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 20:57:32 +05:30
hui.song
4e0dc38da0 armv8: dts: fsl-lx2160a: add gpio0 gpio1 gpio3 DT nodes
add gpio0 gpio1 gpio3 DT nodes to fsl-lx21600.dtsi

Signed-off-by: hui.song <hui.song_1@nxp.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 20:57:32 +05:30
Hou Zhiqiang
af288cb291 arm64: Layerscape: Survive LPI one-way reset workaround
The workaround of LPI one-way reset issue is broken by the series:
https://patchwork.ozlabs.org/project/uboot/list/?series=192398

This patch is to add DT node for GIC RD tables and create corresponding
reserved-memory node in kernel DT to fix it.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 20:57:32 +05:30
Tom Rini
67ece26d8b Xilinx changes for v2021.01
arm64:
 - Support for bigger U-Boot images compiled with PIE
 
 microblaze:
 - Extend support for LE/BE systems
 
 zynqmp:
 - Refactor silicon ID detection code with using firmware interface
 - Add support for saving variables based on bootmode
 
 zynqmp-r5:
 - Fix MPU mapping and defconfig setting.
 
 xilinx:
 - Minor driver changes: names alignment
 - Enable UBIFS
 - Minor DT and macros fixes
 - Fix boot with appended DT
 - Fix distro boot
 
 cmd:
 - pxe: Add fixing for platforms with manual relocation support
 
 clk:
 - fixed_rate: Add DM flag to support early boot on r5
 
 fpga:
 - zynqmppl: Use only firmware interface and enable SPL build
 
 serial:
 - uartlite: Enable for ARM systems and support endians
 
 mmc:
 - zynq: Fix indentation
 
 net:
 - gem: Support for multiple phys
 - emac: Fix 64bit support and enable it for arm64
 
 kconfig:
 - Setup default values for Xilinx platforms
 - Fix dependecies for Xilinx drivers
 - Source board Kconfig only when platform is enabled
 - Fix FPGA Kconfig entry with SPL
 - Change some defconfig values
 
 bindings:
 - Add binding doc for vsc8531
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCX2x4MgAKCRDKSWXLKUoM
 IZQtAJ9HpNwG5q3nHt9WedzLCTkr3YoLAACeJJ0Wlpp5p5xPzuPmnoo/Vi4MtNQ=
 =yxRo
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2021.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2021.01

arm64:
- Support for bigger U-Boot images compiled with PIE

microblaze:
- Extend support for LE/BE systems

zynqmp:
- Refactor silicon ID detection code with using firmware interface
- Add support for saving variables based on bootmode

zynqmp-r5:
- Fix MPU mapping and defconfig setting.

xilinx:
- Minor driver changes: names alignment
- Enable UBIFS
- Minor DT and macros fixes
- Fix boot with appended DT
- Fix distro boot

cmd:
- pxe: Add fixing for platforms with manual relocation support

clk:
- fixed_rate: Add DM flag to support early boot on r5

fpga:
- zynqmppl: Use only firmware interface and enable SPL build

serial:
- uartlite: Enable for ARM systems and support endians

mmc:
- zynq: Fix indentation

net:
- gem: Support for multiple phys
- emac: Fix 64bit support and enable it for arm64

kconfig:
- Setup default values for Xilinx platforms
- Fix dependecies for Xilinx drivers
- Source board Kconfig only when platform is enabled
- Fix FPGA Kconfig entry with SPL
- Change some defconfig values

bindings:
- Add binding doc for vsc8531
2020-09-24 08:33:47 -04:00
Saeed Nowshadi
ed6d31c8a6 arm64: zynqmp: Correct value of shunt resistor for VCCINT and VCC_SOC
Value of shunt resistor for INA226s that monitor VCCINT and VCC_SOC power
rails are incorrect.  This patch corrects those values.

Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
2020-09-23 10:31:40 +02:00
Saeed Nowshadi
02abe1fbf3 arm64: zynqmp: Add device tree node for 2nd mux on I2C1 bus
There is 2nd pca9548 mux on I2C1 bus that controls SFP0, SFP1, and QSFP1
ports. Channel 0 and 1 are connected to J287 connector for SFP0 & SFP1, and
channel 2 is connected to J288 connector for QSFP1.

Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:40 +02:00
Simon Glass
68de0679c9 binman: sunxi: Add help message for missing sunxi ATF BL31
Add a special help message pointing to the relevant README.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:54:13 -06:00
Simon Glass
cfa3db602c sunxi: Convert 64-bit boards to use binman
At present 64-bit sunxi boards use the Makefile to create a FIT, using
USE_SPL_FIT_GENERATOR. This is deprecated.

Update sunxi to use binman instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-22 12:50:43 -06:00
Tom Rini
751b18b8a1 Merge branch 'master' into next
Merge in v2020.10-rc5
2020-09-21 14:25:37 -04:00
Robert Marko
430e1dcfa4 IPQ40xx: Add USB nodes
There are drivers to support built in USB controller and PHY-s now, so lets add the USB nodes to DTSI.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-18 16:20:47 -04:00
Robert Marko
496a3aa5ff IPQ40xx: Add reset controller support
Since we have a driver for the reset controller, lets add the necessary node.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-18 16:20:47 -04:00
Robert Marko
6ef099b29e IPQ40xx: Add SMEM support
There is already existing driver for SMEM so lets enable it for IPQ40xx as well.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-18 16:20:47 -04:00
Robert Marko
5ae15415c1 IPQ40xx: clk: Use dt-bindings instead of hardcoding
Its common to use dt-bindings instead of hard-coding clocks or resets.
So lets use the imported Linux GCC bindings on IPQ40xx target.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-18 16:20:47 -04:00
Philippe Schenker
bf46474e21 apalis-imx8qm: rename all occurences to apalis-imx8
The Toradex product is called apalis-imx8 consisting of SoM with
i.MX8QM and i.MX8QP SoCs.

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-09-17 14:41:33 +02:00
Philippe Schenker
08b6a60ee8 colibri-imx8qxp: rename all occurences to colibri-imx8x
The Toradex product is called colibri-imx8x consisting of SoM with
i.MX8QXP and i.MX8DX SoCs.

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-09-17 14:41:26 +02:00
Kever Yang
fe4931c09a rockchip: rv1108: Enable grf as pre-reloc node
The grf node will be used before relocate, enable it in dts.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-09-16 16:31:18 +08:00
Tom Rini
bd4e8944cf Merge tag 'ti-v2021.01-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti into next
- Hyperflash boot for J7200
- Update Main R5FSS lockstep mode
- R5F remoteproc support for J7200
- Minor env fixes
- Add SPI boot support for am335x-icev2
2020-09-15 15:22:00 -04:00
Faiz Abbas
38e6ddc4d7 arm: dts: am335x-icev2: Add spi node
Add spi and spi nor flash nodes for am335x-icev2.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-09-15 18:51:53 +05:30
Suman Anna
70377b7279 arm: dts: k3-j7200-r5: Add fs_loader node
Add a generic fs_loader node to the K3 J7200 R5 common board dts
file and use it as the chosen firmware-loader so that it can be
used for loading various firmwares from a boot media/filesystem
in R5 SPL on K3 J7200 EVM.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-09-15 18:51:53 +05:30
Suman Anna
3f7e032f70 arm: dts: k3-j7200-main: Add MAIN domain R5F cluster nodes
The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster is present within the MCU
domain (MCU_R5FSS0), and the other one is present within the MAIN
domain (MAIN_R5FSS0). Each of these can be configured at boot time
to be either run in a LockStep mode or in an Asymmetric Multi
Processing (AMP) fashion in Split-mode. These subsystems have 64 KB
each Tightly-Coupled Memory (TCM) internal memories for each core
split between two banks - ATCM and BTCM (further interleaved into
two banks). The TCMs of both Cores are combined in LockStep-mode
to provide a larger 128 KB of memory.

Add the DT node for the MAIN domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in Split-mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-09-15 18:51:53 +05:30
Suman Anna
10c4de02f0 arm: dts: k3-j7200-mcu: Add MCU domain R5F cluster node
The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster is present within the MCU
domain (MCU_R5FSS0), and the other one is present within the MAIN
domain (MAIN_R5FSS0). Each of these can be configured at boot time
to be either run in a LockStep mode or in an Asymmetric Multi
Processing (AMP) fashion in Split-mode. These subsystems have 64 KB
each Tightly-Coupled Memory (TCM) internal memories for each core
split between two banks - ATCM and BTCM (further interleaved into
two banks). The TCMs of both Cores are combined in LockStep-mode
to provide a larger 128 KB of memory.

Add the DT node for the MCU domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in LockStep mode by default, with
the ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-09-15 18:51:53 +05:30
Suman Anna
31defbd347 arm: dts: k3-j721e-main: Configure MAIN R5FSS1 for Split-mode
Switch the MAIN R5FSS1 cluster to be configured for Split-mode as the
default so that two different applications can be run on each of the
R5F cores in performance mode. LockStep-mode would be available only
on SoCs efused with the appropriate bit, and Split-mode is the mode
that is available on all J721E SoCs.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-09-15 18:51:53 +05:30
Vignesh Raghavendra
c07d06855e ARM: dts: k3-j7200-r5-common-proc-board: Enable HyperFlash
Enable HyperBus and HyperFlash to support HyperFlash boot.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-09-15 18:51:53 +05:30
Thirupathaiah Annapureddy
0b65e494e9 arm: dts: fix ast2500-evb inclusion for the correct soc family
Include ast2500-evb.dtb for CONFIG_ASPEED_AST2500 instead of
for all aspeed targets.

ast2400 is based on ARM926EJ-S processor (ARMv5-architecture).
ast2500 is based on ARM1176JZS processor (ARMv6-architecture).
ast2600 is based on Cortex A7 processor (ARMv7-A architecture).
Each of the above SOC is using a different ARM CPU(s) with different ARM
architecture revision. It is not possible to support all 3 of these
families in a single binary. So there is no need to build ast2500-evb.dtb
for other SOC families.

Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com>
2020-09-10 11:17:46 -04:00
Ryan Chen
654ae299ec cosmetic: aspeed: Modify for SPDX-License
Modify SPDX-License for furture patch warning

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-09-09 16:57:36 -04:00
Ryan Chen
c39c9a94cb clock:aspeed: Sync with Linux kernel clock header define
v2: modify title description aspeed:clock -> clock:aspeed

Use kernel include/dt-bindings/clock/aspeed-clock.h define
for clock driver.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-09-09 16:57:35 -04:00
Ryan Chen
15b87feb2b cosmetic: aspeed: ast2500: Rename clock header
Rename the ast2500-scu.h to aspeed-clock.h.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
2020-09-09 16:57:35 -04:00
Marek Vasut
b6055945d6 ARM: dts: stm32: Adjust PLL4 settings on AV96 again
PLL4Q is supplying both FDCAN and LTDC. In case HDMI is in use, the
50 MHz generated from PLL4Q cannot be divided well enough to produce
accurate clock for HDMI pixel clock. Adjust it to generate 74.25 MHz
instead. The PLL4P/PLL4R are generating 99 MHz instead of 100 MHz,
which is in tolerance for the SDMMC.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Gerald Baeza <gerald.baeza@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-09 15:02:23 +02:00
Marek Vasut
43e2d1dd47 ARM: dts: stm32: Pull UART4 RX high on AV96
There is no dedicated pull resistor on the AV96 UART4 (console UART)
pin. In case there is no UART adapter installed on the AV96, the line
is floating and can trigger reception of garbage characters, which in
turn can abort U-Boot autoboot. Add default pull up to mitigate this
problem.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-09 15:01:53 +02:00
Tom Rini
6ade057e37 Merge tag 'ti-v2020.10-rc4' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti
- Update to ABI 3.0
- Fix i2c write in eeprom driver
2020-08-31 13:06:26 -04:00
Wilson Ding
96fa3c4fda arm: dts: a37x0: enable sd card support on espressobin
Enabled SDIO slot 0 (south bridge) for SD card on
Espressobin board.

Change-Id: I51a2debf9fba276b9c4a2bc6da91328d47f443e3
Signed-off-by: Wilson Ding <dingwei@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/60945
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
[pali: Define cd-gpios and enable CONFIG_DM_REGULATOR_GPIO]
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31 14:45:53 +02:00
Pali Rohár
563b85bd88 arm64: a37xx: pci: Make PCIe Reset GPIO DT compatible with Linux kernel DT
Change active-high to active-low and change DT property name from
reset-gpio to reset-gpios. This format of gpio reset is used by
pci-aardvark driver in Linux kernel.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31 14:45:53 +02:00
Marek Behún
545591132a arm64: dts: armada-3720-espressobin: fix COMPHY nodes
This commit fixes initialization of COMPHY on EspressoBin.

Commit 22f418935b ("phy: marvell: a3700: Use comphy_mux on Armada
37xx.") introduced usage of comphy_mux on Armada 37xx comphy driver.
The lanes are defined in comphy_a3700.c as described in functional
specification, that is:
  lane 0 is SGMII1 or USB3
  lane 1 is PCIe or SGMII0
  lane 2 is SATA or USB3

But the DTS for EspressoBin configures PCIe on lane 0 and USB3 on
lane 1, which is wrong in the sense of the specification and doesn't
work with the comphy_mux code, which is 2 years now (the aardvark driver
causes synchronous abort in U-Boot).

It worked till the above mentioned commit, because the code for powering
up PCIe PHY doesn't work with lane number at all, and the code for
powering up USB3 PHY works differently only if USB3 is on lane 2, ie.
the check goes like:
  if (lane == 2)
    something
  else
    something else
so it does not differentiate between lanes 0 and 1.

In the future I shall post patches that remove the comphy_a3700 driver
and add comphy driver which uses calls to ATF, like Linux' driver does.
This will have the advantage of same DTS bindings as Linux', but till
this is done, we need this patch.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Pali Rohár <pali@kernel.org>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31 14:45:53 +02:00
Lokesh Vutla
e66ae8e16b arm: dts: k3-am65: Update the RM resource types
Update the ringacc and udma dt nodes to use the latest RM resource types
similar to the ones used in k3-j721e dt nodes.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-08-31 14:39:39 +05:30
Tom Rini
e49a9d4ddb Merge tag 'u-boot-rockchip-20200820' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Fix rk3399 evb sdcard support
- Fix for SPL_LED support
2020-08-25 08:19:14 -04:00
Frank Wunderlich
35051db978 arm: dts: mt7623: add USB nodes
This adds USB nodes for MT7623/BPI-R2

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2020-08-24 14:11:31 -04:00
Frank Wunderlich
a13666b205 arm: dts: mt7622: add USB nodes
Add DTS nodes for MT7622/BPI-R64

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2020-08-24 14:11:31 -04:00
Frank Wunderlich
28e1b1df3b arm: dts: rename mt7622-bpi-r64.dts
rename mt7622-bpi-r64.dts to mt7622-bananapi-bpi-r64.dts
to follow naming convensions

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-24 14:11:31 -04:00
Usama Arif
565add124d board: armltd: Add support for Total Compute platform
Total Compute is based on ARM architecture and has
the following features enabled in u-boot:
- PL011 UART
- PL180 MMC
- NOR Flash
- FIT image with Signature
- AVB

Signed-off-by: Usama Arif <usama.arif@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-08-24 14:11:31 -04:00
Kever Yang
d6092e3229 rockchip: dts: rk3399-evb: add sdmmc node
The sdmmc node is missing after the dts sync patch:
  167efc2c7a arm64: dts: rk3399: Sync v5.7-rc1 from Linux
But we still need it for boot from SD card, so add it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-08-21 19:56:19 +08:00
Tom Rini
2e6132d835 Xilinx changes for v2020.10-rc3
- Fix fdtfile variable setup
 - Fix bootm_*/fdt_high/initrd_high variables handling
 - Fix Kconfig dependencies for Xilinx drivers
 - Fix booting u-boot from lowest memory
 - Fix firmware payload argument count for Versal
 - Fix dfu configurations
 - Fix mio_bank property handling
 - Fix and align code around ID detection
 - Start to use ENV_VARS_UBOOT_RUNTIME_CONFIG
 - Simplify logic around reading MAC from eeprom
 - Decrease malloc length for zynqmp mini qspi
 - Enable preboot for ZynqMP and Versal
 
 i2c:
 - Fix i2c eeprom partitions handling
 
 mmc:
 - Fix logic around HS mode enabling and use proper functions
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCXz6IMgAKCRDKSWXLKUoM
 IfV4AKCbILpxWM+wyIornyU02CE9VO9j9wCggpoxmxJJfPlgGBn2ssiDh8pYKM8=
 =dIwc
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2020.10-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2020.10-rc3

- Fix fdtfile variable setup
- Fix bootm_*/fdt_high/initrd_high variables handling
- Fix Kconfig dependencies for Xilinx drivers
- Fix booting u-boot from lowest memory
- Fix firmware payload argument count for Versal
- Fix dfu configurations
- Fix mio_bank property handling
- Fix and align code around ID detection
- Start to use ENV_VARS_UBOOT_RUNTIME_CONFIG
- Simplify logic around reading MAC from eeprom
- Decrease malloc length for zynqmp mini qspi
- Enable preboot for ZynqMP and Versal

i2c:
- Fix i2c eeprom partitions handling

mmc:
- Fix logic around HS mode enabling and use proper functions
2020-08-20 14:46:43 -04:00
Michal Simek
01a6da1661 xilinx: Fix xlnx,mio_bank property
s/xlnx,mio_bank/xlnx,mio-bank/g

DT binding is describing mio-bank not mio_bank that's why fix all DTSes and
also driver itself.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2020-08-20 09:49:20 +02:00
Michal Simek
f692b479f0 i2c: eeprom: Use reg property instead of offset and size
Remove adhoc dt binding for fixed-partition definition for i2c eeprom.
fixed-partition are using reg property instead of offset/size pair.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-20 09:49:20 +02:00
Frank Wunderlich
7cf8537d5e dts: r64: add sata- and asm_sel nodes
asm_sel is for switching between sata and pcie mode
on r64 there is GPIO90 connected to ASM1480 which
switches RX/TX pairs to PCIe/SATA connector
output-low means sata-controller is active

with 2020-10 now reg is also needed for the phy itself

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-19 17:38:15 -04:00
Frank Wunderlich
f08c2c2d87 arm: dts: mt7622: add PCIe nodes for BananaPi-R64
this patch adds PCIe-Nodes for BananaPi R64

original nodes from Chuanjia Liu for mt7622-rfb

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-19 17:38:14 -04:00
Frank Wunderlich
8ad2fc413f dts: r64: add r64 dts
add a separate DTS for BananaPi R64 because it has 1GB RAM and SATA-Support

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-19 17:38:14 -04:00
Frank Wunderlich
35d0fdbf17 arm: dts: add watchdog-node for mt7622
adding a watchdog-node to mt7622 dtsi

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-19 17:37:37 -04:00
Chuanjia Liu
bb9d3ad521 arm: dts: mediatek: add PCIe node for MT7622
This patch adds PCIe node in dts for Mediatek MT7622 Soc.

Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com>
Signed-off-by: Henry Yen <henry.yen@mediatek.com>
2020-08-19 17:37:37 -04:00
Chuanjia Liu
0cc587dd86 arm: dts: mediatek: add pciesys support for MT7622 SoC
This patch adds pciesys support in dts for MediaTek MT7622 SoC.

Signed-off-by: Henry Yen <henry.yen@mediatek.com>
Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com>
2020-08-19 17:37:37 -04:00
Masahiro Yamada
65282edbdf ARM: dts: uniphier: resync DT with Linux 5.9-rc1
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-08-18 02:01:14 +09:00
Tom Rini
cdcf591d9b Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Fix dtc warnings for some MVEBU boards
2020-08-13 08:25:25 -04:00
Tom Rini
6808dc62d7 - Use IS_ENABLED to prevent ifdef in board_key_check for STM32MP
- Add STM32 FMC2 EBI controller driver
   - Fix dwc3-sti-glue which allows STiH410-B2260 to boot again
   - Add fitImage its entry for 587-200 DHCOR SoM
   - Add both PDK2 and DRC02 DT into DHCOM fitImage its
   - Fix DHCOM KS8851 ethernet MAC address
   - Remove stm32mp1 board.c file
   - Use const for struct node_info in board stm32mp1.c file
 -----BEGIN PGP SIGNATURE-----
 
 iQJLBAABCgA1FiEEXyrViUccKBz9c35Jysd4L3sz/6YFAl81JrkXHHBhdHJpY2Uu
 Y2hvdGFyZEBzdC5jb20ACgkQysd4L3sz/6ZZBw//TiEtosS/6NRuC3kzK9KrpVUY
 hIvrZldrh5lr+RZn7GqmNHD9CUZeXFBweG6ah5oHImsyaUdUnWZSftXykEzdIyoL
 +r2j27npjqviATH1dZNliZnb/QiMsPmmf7XmF2MO0U7NTkbc7GMvsPWHAllk7jue
 cPfa+uiRWsfM2oiHki6zC+QvfYQ5x+yxsWjoaOXgyAqjC8oIFBTqXFCHEYPhhZPr
 9yu7uIXkahpEZe0x2J/5B0rCfgwpaX/fkF9OU35ThhpSEJOLWneiNwMtODGS96CQ
 VjJhpdP3T/8TL8cQF+DJVP3tBQn60zepb12LvYY4Lhm08EolBRS8E/reukthkhWP
 9C8KBHNFZG/PTccuHhF2t75AsFOQm37xR5S6qf2vjTYddTojqKQ404/BB89+jkJP
 2bYfi5VZc9kz5gD4faGObHqqhhaMeC64ihrtJouFR8APS8IMEzsb282LX6mpa+IM
 Id9zKHEyLZ9vig/ybQ2G1lpucFYtDrEcl7HBLFGrPkzWXhhvh8Onm6BGda378lBM
 JTTstUlDPrmc8OSUR8RSE15LXnoYP4QfJwUUy2/DOYt3GoHWCIHAY2V5Eo+ATl7q
 2p2/5pi/mOblSk5LW3cnjAqlnFmH7IVp4rLNLPvunRSDC34lhjvOzTgEiBvwqA/Z
 2YbPPXFM7nwU/OXbG7w=
 =J4aq
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-stm32-20200813' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

  - Use IS_ENABLED to prevent ifdef in board_key_check for STM32MP
  - Add STM32 FMC2 EBI controller driver
  - Fix dwc3-sti-glue which allows STiH410-B2260 to boot again
  - Add fitImage its entry for 587-200 DHCOR SoM
  - Add both PDK2 and DRC02 DT into DHCOM fitImage its
  - Fix DHCOM KS8851 ethernet MAC address
  - Remove stm32mp1 board.c file
  - Use const for struct node_info in board stm32mp1.c file
2020-08-13 08:11:27 -04:00
Stefan Roese
ac5cd429e3 arm: mvebu: armada-3720-turris-mox.dts: Fix dtc warning
Fix this dtc warning:
Warning (avoid_default_addr_size)

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Behún <marek.behun@nic.cz>
2020-08-13 12:07:05 +02:00
Stefan Roese
fcede1e5f6 arm: mvebu: armada-388-gp.dts: Fix dtc warnings
Fix these dtc warnings:
Warning (reg_format)
Warning (avoid_default_addr_size)

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
2020-08-13 12:07:05 +02:00
Stefan Roese
cc2afbd47b arm: mvebu: armada-xp-maxbcm.dts: Fix dtc warning
Fix this dtc warning:
Warning (avoid_default_addr_size)

Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-13 12:07:05 +02:00
Stefan Roese
092cb733e9 arm: mvebu: armada-xp-theadorable.dts: Fix dtc warning
Fix this dtc warning:
Warning (avoid_default_addr_size)

Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-13 12:07:05 +02:00
Marek Vasut
9ff770b497 ARM: dts: stm32: Update eth1addr from EEPROM if eth1 present
The STM32MP1 DHCOM has two ethernet interfaces, the on-SoM DWMAC and KS8851.
Set eth1addr for the KS8851 to a MAC address of the DWMAC incremented by 1.
The MAC of the DWMAC is set from on-SoM EEPROM already, but the MAC address
of KS8851 was left uninitialized, so fix this.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:56:44 +02:00
Christophe Kerello
acdaae6390 ARM: dts: stm32: add FMC2 EBI support for stm32mp157c
This patch adds FMC2 External Bus Interface support on stm32mp157c.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:53:35 +02:00
Vignesh Raghavendra
db6451ec0e arm: dts: k3-j7200-common-proc-board: Enable CPSW2G port
Enable CPSW2G port to support networking in U-Boot

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-08-11 20:34:46 +05:30
Vignesh Raghavendra
4bb4b06983 ARM: dts: k3-j7200-mcu-wakeup: Add CPSW2G support
Add MCU NAVSS, UDMA and CPSW2G DT nodes.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-08-11 20:34:46 +05:30
Vignesh Raghavendra
28e29fbb4f ARM: dts: k3-j7200: Add HyperBus and HyperFlash nodes
J7200 SoM has Cypress HyperFlash connected to HyperBus interface, add DT
entries for the same.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-08-11 20:34:46 +05:30
Vignesh Raghavendra
9e8a9b6457 ARM: dts: k3-j7200: Add wkup gpio node
Add wkup_gpio0 node required for detecting whether board mux is set
HyperFlash.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-08-11 20:34:46 +05:30
Vignesh Raghavendra
86c9bd4eb7 arm: dts: k3-j7200: Add USB related DT entries
Add USB related DT entries to enable USB device mode.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-08-11 20:34:46 +05:30