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Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spi

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This commit is contained in:
Tom Rini 2020-12-18 13:06:02 -05:00
commit 549e7cb708
27 changed files with 1092 additions and 171 deletions
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2
MAINTAINERS
View file

@ -195,6 +195,7 @@ F: drivers/watchdog/cortina_wdt.c
F: drivers/serial/serial_cortina.c
F: drivers/led/led_cortina.c
F: drivers/mmc/ca_dw_mmc.c
F: drivers/spi/ca_sflash.c
F: drivers/i2c/i2c-cortina.c
F: drivers/i2c/i2c-cortina.h
@ -800,6 +801,7 @@ F: drivers/watchdog/cortina_wdt.c
F: drivers/serial/serial_cortina.c
F: drivers/led/led_cortina.c
F: drivers/mmc/ca_dw_mmc.c
F: drivers/spi/ca_sflash.c
F: drivers/i2c/i2c-cortina.c
F: drivers/i2c/i2c-cortina.h

5
arch/arc/dts/axs10x_mb.dtsi
View file

@ -90,14 +90,15 @@
};
spi0: spi@0 {
compatible = "snps,dw-apb-ssi";
compatible = "snps,axs10x-spi", "snps,dw-apb-ssi";
reg = <0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <4000000>;
clocks = <&apbclk>;
clock-names = "spi_clk";
cs-gpio = <&cs_gpio 0>;
num-cs = <1>;
cs-gpios = <&cs_gpio 0>;
spi_flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;

5
arch/arc/dts/hsdk-common.dtsi
View file

@ -128,14 +128,15 @@
};
spi0: spi@f0020000 {
compatible = "snps,dw-apb-ssi";
compatible = "snps,hsdk-spi", "snps,dw-apb-ssi";
reg = <0xf0020000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <4000000>;
clocks = <&cgu_clk CLK_SYS_SPI_REF>;
clock-names = "spi_clk";
cs-gpio = <&cs_gpio 0>;
num-cs = <1>;
cs-gpios = <&cs_gpio 0>;
spi_flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;

6
arch/arm/dts/socfpga.dtsi
View file

@ -804,7 +804,8 @@
};
spi0: spi@fff00000 {
compatible = "snps,dw-apb-ssi";
compatible = "altr,socfpga-spi", "snps,dw-apb-ssi-3.20",
"snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfff00000 0x1000>;
@ -816,7 +817,8 @@
};
spi1: spi@fff01000 {
compatible = "snps,dw-apb-ssi";
compatible = "altr,socfpga-spi", "snps,dw-apb-ssi-3.20",
"snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfff01000 0x1000>;

6
arch/arm/dts/socfpga_agilex.dtsi
View file

@ -366,7 +366,8 @@
};
spi0: spi@ffda4000 {
compatible = "snps,dw-apb-ssi";
compatible = "intel,agilex-spi",
"snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda4000 0x1000>;
@ -379,7 +380,8 @@
};
spi1: spi@ffda5000 {
compatible = "snps,dw-apb-ssi";
compatible = "intel,agilex-spi",
"snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda5000 0x1000>;

6
arch/arm/dts/socfpga_arria10.dtsi
View file

@ -604,7 +604,8 @@
};
spi0: spi@ffda4000 {
compatible = "snps,dw-apb-ssi";
compatible = "altr,socfpga-arria10-spi",
"snps,dw-apb-ssi-3.22a", "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda4000 0x100>;
@ -617,7 +618,8 @@
};
spi1: spi@ffda5000 {
compatible = "snps,dw-apb-ssi";
compatible = "altr,socfpga-arria10-spi",
"snps,dw-apb-ssi-3.22a", "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda5000 0x100>;

6
arch/arm/dts/socfpga_stratix10.dtsi
View file

@ -268,7 +268,8 @@
};
spi0: spi@ffda4000 {
compatible = "snps,dw-apb-ssi";
compatible = "intel,stratix10-spi",
"snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda4000 0x1000>;
@ -281,7 +282,8 @@
};
spi1: spi@ffda5000 {
compatible = "snps,dw-apb-ssi";
compatible = "intel,stratix10-spi",
"snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda5000 0x1000>;

2
arch/mips/dts/mscc,jr2.dtsi
View file

@ -94,7 +94,7 @@
spi0: spi-master@101000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dw-apb-ssi";
compatible = "mscc,jaguar2-spi", "snps,dw-apb-ssi";
reg = <0x101000 0x40>;
num-chipselect = <4>;
bus-num = <0>;

2
arch/mips/dts/mscc,ocelot.dtsi
View file

@ -100,7 +100,7 @@
spi0: spi-master@101000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dw-apb-ssi";
compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi";
reg = <0x101000 0x40>;
num-chipselect = <4>;
bus-num = <0>;

46
arch/riscv/dts/k210-maix-bit.dts
View file

@ -152,7 +152,7 @@
pinmux = <K210_FPIOA(26, K210_PCF_SPI1_D1)>,
<K210_FPIOA(27, K210_PCF_SPI1_SCLK)>,
<K210_FPIOA(28, K210_PCF_SPI1_D0)>,
<K210_FPIOA(29, K210_PCF_GPIOHS13)>;
<K210_FPIOA(29, K210_PCF_GPIOHS13)>; /* cs */
};
};
@ -160,3 +160,47 @@
pinctrl-0 = <&fpioa_dvp>;
pinctrl-names = "default";
};
&spi0 {
pinctrl-0 = <&fpioa_spi0>;
pinctrl-names = "default";
num-cs = <1>;
cs-gpios = <&gpio0 20 0>;
panel@0 {
compatible = "sitronix,st7789v";
reg = <0>;
reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
dc-gpios = <&gpio0 22 0>;
spi-max-frequency = <15000000>;
status = "disabled";
};
};
&spi1 {
pinctrl-0 = <&fpioa_spi1>;
pinctrl-names = "default";
num-cs = <1>;
cs-gpios = <&gpio0 13 0>;
status = "okay";
slot@0 {
compatible = "mmc-spi-slot";
reg = <0>;
spi-max-frequency = <25000000>;
voltage-ranges = <3300 3300>;
broken-cd;
};
};
&spi3 {
status = "okay";
spi-flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
m25p,fast-read;
broken-flash-reset;
};
};

15
arch/riscv/dts/k210.dtsi
View file

@ -284,7 +284,8 @@
};
spi2: spi@50240000 {
compatible = "kendryte,k120-spislave",
compatible = "canaan,kendryte-k210-spi",
"snps,dw-apb-ssi-4.01",
"snps,dw-apb-ssi";
spi-slave;
reg = <0x50240000 0x100>;
@ -495,6 +496,8 @@
interrupts = <24>;
clocks = <&sysclk K210_CLK_DVP>;
resets = <&sysrst K210_RST_DVP>;
kendryte,sysctl = <&sysctl>;
kendryte,misc-offset = <K210_SYSCTL_MISC>;
status = "disabled";
};
@ -557,7 +560,8 @@
spi0: spi@52000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "kendryte,k210-spi",
compatible = "canaan,kendryte-k210-spi",
"snps,dw-apb-ssi-4.01",
"snps,dw-apb-ssi";
reg = <0x52000000 0x100>;
interrupts = <1>;
@ -573,7 +577,8 @@
spi1: spi@53000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "kendryte,k210-spi",
compatible = "canaan,kendryte-k210-spi",
"snps,dw-apb-ssi-4.01",
"snps,dw-apb-ssi";
reg = <0x53000000 0x100>;
interrupts = <2>;
@ -589,8 +594,8 @@
spi3: spi@54000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "kendryte,k210-spi",
"snps,dw-apb-ssi";
compatible = "canaan,kendryte-k210-ssi",
"snps,dwc-ssi-1.01a";
reg = <0x54000000 0x200>;
interrupts = <4>;
clocks = <&sysclk K210_CLK_SPI3>;

7
configs/cl-som-imx7_defconfig
View file

@ -7,6 +7,7 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DM_GPIO=y
CONFIG_TARGET_CL_SOM_IMX7=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
@ -39,7 +40,6 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
@ -52,17 +52,19 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
# CONFIG_ENV_IS_IN_MMC is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_CMD_PCA953X=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_SPI_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_ATMEL=y
@ -79,6 +81,7 @@ CONFIG_MII=y
CONFIG_DM_REGULATOR=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y

3
configs/cm_fx6_defconfig
View file

@ -54,10 +54,12 @@ CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=spi0.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:768k(uboot),256k(uboot-environment),-(reserved)"
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SPL_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
# CONFIG_DWC_AHSATA_AHCI is not set
@ -85,6 +87,7 @@ CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y

3
configs/dh_imx6_defconfig
View file

@ -51,12 +51,14 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="imx6q-dhcom-pdk2 imx6dl-dhcom-pdk2"
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
CONFIG_BOOTCOUNT_LIMIT=y
@ -103,4 +105,5 @@ CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
CONFIG_IMX_WATCHDOG=y
# CONFIG_SPL_WDT is not set
CONFIG_BZIP2=y

56
doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt Normal file
View file

@ -0,0 +1,56 @@
Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface
and Synopsys DesignWare High Performance Synchronous Serial Interface
Required properties:
- compatible : One of
"altr,socfpga-spi",
"altr,socfpga-arria10-spi",
"canaan,kendryte-k210-spi",
"canaan,kendryte-k210-ssi",
"intel,stratix10-spi",
"intel,agilex-spi",
"mscc,ocelot-spi",
or "mscc,jaguar2-spi";
and one of
"snps,dw-apb-ssi-3.20a",
"snps,dw-apb-ssi-3.22a",
"snps,dw-apb-ssi-3.23",
"snps,dw-apb-ssi-4.00a",
"snps,dw-apb-ssi-4.01",
or "snps,dwc-ssi-1.01a".
"snps,dw-apb-ssi" may also be used, but is deprecated in favor of specific
version strings.
- reg : The register base for the controller. For "mscc,<soc>-spi", a second
register set is required (named ICPU_CFG:SPI_MST)
- #address-cells : <1>, as required by generic SPI binding.
- #size-cells : <0>, also as required by generic SPI binding.
- clocks : phandles for the clocks, see the description of clock-names below.
The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock
is optional. If a single clock is specified but no clock-name, it is the
"ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be first.
Optional properties:
- clock-names : Contains the names of the clocks:
"ssi_clk", for the core clock used to generate the external SPI clock.
"pclk", the interface clock, required for register access.
- cs-gpios : Specifies the gpio pins to be used for chipselects.
- num-cs : The number of chipselects. If omitted, this will default to 4.
- reg-io-width : The I/O register width (in bytes) implemented by this
device. Supported values are 2 or 4 (the default).
Child nodes as per the generic SPI binding.
Example:
spi@fff00000 {
compatible = "altr,socfpga-arria10-spi",
"snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
reg = <0xfff00000 0x1000>;
interrupts = <0 154 4>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&spi_m_clk>;
num-cs = <2>;
cs-gpios = <&gpio0 13 0>,
<&gpio0 14 0>;
};

2
doc/uImage.FIT/source_file_format.txt
View file

@ -172,7 +172,7 @@ the '/images' node should have the following layout:
- os : OS name, mandatory for types "kernel" and "ramdisk". Valid OS names
are: "openbsd", "netbsd", "freebsd", "4_4bsd", "linux", "svr4", "esix",
"solaris", "irix", "sco", "dell", "ncr", "lynxos", "vxworks", "psos", "qnx",
"u_boot", "rtems", "unity", "integrity".
"u-boot", "rtems", "unity", "integrity".
- arch : Architecture name, mandatory for types: "standalone", "kernel",
"firmware", "ramdisk" and "fdt". Valid architecture names are: "alpha",
"arm", "i386", "ia64", "mips", "mips64", "ppc", "s390", "sh", "sparc",

10
drivers/mtd/nand/core.c
View file

@ -130,10 +130,18 @@ EXPORT_SYMBOL_GPL(nanddev_isreserved);
*/
int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos)
{
unsigned int entry;
if (nanddev_isbad(nand, pos) || nanddev_isreserved(nand, pos)) {
pr_warn("attempt to erase a bad/reserved block @%llx\n",
nanddev_pos_to_offs(nand, pos));
return -EIO;
if (nanddev_isreserved(nand, pos))
return -EIO;
/* remove bad block from BBT */
entry = nanddev_bbt_pos_to_entry(nand, pos);
nanddev_bbt_set_block_status(nand, entry,
NAND_BBT_BLOCK_STATUS_UNKNOWN);
}
return nand->ops->erase(nand, pos);

24
drivers/mtd/nand/spi/core.c
View file

@ -655,16 +655,16 @@ static int spinand_mtd_write(struct mtd_info *mtd, loff_t to,
static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos)
{
struct spinand_device *spinand = nand_to_spinand(nand);
u8 marker[2] = { };
struct nand_page_io_req req = {
.pos = *pos,
.ooblen = 2,
.ooblen = sizeof(marker),
.ooboffs = 0,
.oobbuf.in = spinand->oobbuf,
.oobbuf.in = marker,
.mode = MTD_OPS_RAW,
};
int ret;
memset(spinand->oobbuf, 0, 2);
ret = spinand_select_target(spinand, pos->target);
if (ret)
return ret;
@ -673,7 +673,7 @@ static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos)
if (ret)
return ret;
if (spinand->oobbuf[0] != 0xff || spinand->oobbuf[1] != 0xff)
if (marker[0] != 0xff || marker[1] != 0xff)
return true;
return false;
@ -702,28 +702,20 @@ static int spinand_mtd_block_isbad(struct mtd_info *mtd, loff_t offs)
static int spinand_markbad(struct nand_device *nand, const struct nand_pos *pos)
{
struct spinand_device *spinand = nand_to_spinand(nand);
u8 marker[2] = { };
struct nand_page_io_req req = {
.pos = *pos,
.ooboffs = 0,
.ooblen = 2,
.oobbuf.out = spinand->oobbuf,
.ooblen = sizeof(marker),
.oobbuf.out = marker,
.mode = MTD_OPS_RAW,
};
int ret;
/* Erase block before marking it bad. */
ret = spinand_select_target(spinand, pos->target);
if (ret)
return ret;
ret = spinand_write_enable_op(spinand);
if (ret)
return ret;
ret = spinand_erase_op(spinand, pos);
if (ret)
return ret;
memset(spinand->oobbuf, 0, 2);
return spinand_write_page(spinand, &req);
}

5
drivers/mtd/spi/spi-nor-ids.c
View file

@ -150,7 +150,7 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("mx25u1635e", 0xc22535, 0, 64 * 1024, 32, SECT_4K) },
{ INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) },
{ INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, 0) },
{ INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, SECT_4K) },
{ INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K) },
{ INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
{ INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
@ -185,6 +185,7 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
{ INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ INFO("mt25ql01g", 0x21ba20, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
@ -320,6 +321,8 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
#endif
#ifdef CONFIG_SPI_FLASH_XMC
/* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */

8
drivers/spi/Kconfig
View file

@ -106,6 +106,14 @@ config BCMSTB_SPI
be used to access the SPI flash on platforms embedding this
Broadcom SPI core.
config CORTINA_SFLASH
bool "Cortina-Access Serial Flash controller driver"
depends on DM_SPI && SPI_MEM
help
Enable the Cortina-Access Serial Flash controller driver. This driver
can be used to access the SPI NOR/NAND flash on platforms embedding this
Cortina-Access IP core.
config CADENCE_QSPI
bool "Cadence QSPI driver"
help

1
drivers/spi/Makefile
View file

@ -24,6 +24,7 @@ obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o
obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o
obj-$(CONFIG_BCMSTB_SPI) += bcmstb_spi.o
obj-$(CONFIG_CF_SPI) += cf_spi.o
obj-$(CONFIG_CORTINA_SFLASH) += ca_sflash.o
obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o

576
drivers/spi/ca_sflash.c Normal file
View file

@ -0,0 +1,576 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for Cortina SPI-FLASH Controller
*
* Copyright (C) 2020 Cortina Access Inc. All Rights Reserved.
*
* Author: PengPeng Chen <pengpeng.chen@cortina-access.com>
*/
#include <common.h>
#include <malloc.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <linux/compat.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/ioport.h>
#include <linux/sizes.h>
#include <spi.h>
#include <spi-mem.h>
#include <reset.h>
DECLARE_GLOBAL_DATA_PTR;
struct ca_sflash_regs {
u32 idr; /* 0x00:Flash word ID Register */
u32 tc; /* 0x04:Flash Timeout Counter Register */
u32 sr; /* 0x08:Flash Status Register */
u32 tr; /* 0x0C:Flash Type Register */
u32 asr; /* 0x10:Flash ACCESS START/BUSY Register */
u32 isr; /* 0x14:Flash Interrupt Status Register */
u32 imr; /* 0x18:Flash Interrupt Mask Register */
u32 fcr; /* 0x1C:NAND Flash FIFO Control Register */
u32 ffsr; /* 0x20:Flash FIFO Status Register */
u32 ffar; /* 0x24:Flash FIFO ADDRESS Register */
u32 ffmar; /* 0x28:Flash FIFO MATCHING ADDRESS Register */
u32 ffdr; /* 0x2C:Flash FIFO Data Register */
u32 ar; /* 0x30:Serial Flash Access Register */
u32 ear; /* 0x34:Serial Flash Extend Access Register */
u32 adr; /* 0x38:Serial Flash ADdress Register */
u32 dr; /* 0x3C:Serial Flash Data Register */
u32 tmr; /* 0x40:Serial Flash Timing Register */
};
/*
* FLASH_TYPE
*/
#define CA_FLASH_TR_PIN BIT(15)
#define CA_FLASH_TR_TYPE_MSK GENMASK(14, 12)
#define CA_FLASH_TR_TYPE(tp) (((tp) << 12) & CA_FLASH_TR_TYPE_MSK)
#define CA_FLASH_TR_WIDTH BIT(11)
#define CA_FLASH_TR_SIZE_MSK GENMASK(10, 9)
#define CA_FLASH_TR_SIZE(sz) (((sz) << 9) & CA_FLASH_TR_SIZE_MSK)
/*
* FLASH_FLASH_ACCESS_START
*/
#define CA_FLASH_ASR_IND_START_EN BIT(1)
#define CA_FLASH_ASR_DMA_START_EN BIT(3)
#define CA_FLASH_ASR_WR_ACCESS_EN BIT(9)
/*
* FLASH_FLASH_INTERRUPT
*/
#define CA_FLASH_ISR_REG_IRQ BIT(1)
#define CA_FLASH_ISR_FIFO_IRQ BIT(2)
/*
* FLASH_SF_ACCESS
*/
#define CA_SF_AR_OP_MSK GENMASK(7, 0)
#define CA_SF_AR_OP(op) ((op) << 0 & CA_SF_AR_OP_MSK)
#define CA_SF_AR_ACCODE_MSK GENMASK(11, 8)
#define CA_SF_AR_ACCODE(ac) (((ac) << 8) & CA_SF_AR_ACCODE_MSK)
#define CA_SF_AR_FORCE_TERM BIT(12)
#define CA_SF_AR_FORCE_BURST BIT(13)
#define CA_SF_AR_AUTO_MODE_EN BIT(15)
#define CA_SF_AR_CHIP_EN_ALT BIT(16)
#define CA_SF_AR_HI_SPEED_RD BIT(17)
#define CA_SF_AR_MIO_INF_DC BIT(24)
#define CA_SF_AR_MIO_INF_AC BIT(25)
#define CA_SF_AR_MIO_INF_CC BIT(26)
#define CA_SF_AR_DDR_MSK GENMASK(29, 28)
#define CA_SF_AR_DDR(ddr) (((ddr) << 28) & CA_SF_AR_DDR_MSK)
#define CA_SF_AR_MIO_INF_MSK GENMASK(31, 30)
#define CA_SF_AR_MIO_INF(io) (((io) << 30) & CA_SF_AR_MIO_INF_MSK)
/*
* FLASH_SF_EXT_ACCESS
*/
#define CA_SF_EAR_OP_MSK GENMASK(7, 0)
#define CA_SF_EAR_OP(op) (((op) << 0) & CA_SF_EAR_OP_MSK)
#define CA_SF_EAR_DATA_CNT_MSK GENMASK(20, 8)
#define CA_SF_EAR_DATA_CNT(cnt) (((cnt) << 8) & CA_SF_EAR_DATA_CNT_MSK)
#define CA_SF_EAR_DATA_CNT_MAX (4096)
#define CA_SF_EAR_ADDR_CNT_MSK GENMASK(23, 21)
#define CA_SF_EAR_ADDR_CNT(cnt) (((cnt) << 21) & CA_SF_EAR_ADDR_CNT_MSK)
#define CA_SF_EAR_ADDR_CNT_MAX (5)
#define CA_SF_EAR_DUMY_CNT_MSK GENMASK(29, 24)
#define CA_SF_EAR_DUMY_CNT(cnt) (((cnt) << 24) & CA_SF_EAR_DUMY_CNT_MSK)
#define CA_SF_EAR_DUMY_CNT_MAX (32)
#define CA_SF_EAR_DRD_CMD_EN BIT(31)
/*
* FLASH_SF_ADDRESS
*/
#define CA_SF_ADR_REG_MSK GENMASK(31, 0)
#define CA_SF_ADR_REG(addr) (((addr) << 0) & CA_SF_ADR_REG_MSK)
/*
* FLASH_SF_DATA
*/
#define CA_SF_DR_REG_MSK GENMASK(31, 0)
#define CA_SF_DR_REG(addr) (((addr) << 0) & CA_SF_DR_REG_MSK)
/*
* FLASH_SF_TIMING
*/
#define CA_SF_TMR_IDLE_MSK GENMASK(7, 0)
#define CA_SF_TMR_IDLE(idle) (((idle) << 0) & CA_SF_TMR_IDLE_MSK)
#define CA_SF_TMR_HOLD_MSK GENMASK(15, 8)
#define CA_SF_TMR_HOLD(hold) (((hold) << 8) & CA_SF_TMR_HOLD_MSK)
#define CA_SF_TMR_SETUP_MSK GENMASK(23, 16)
#define CA_SF_TMR_SETUP(setup) (((setup) << 16) & CA_SF_TMR_SETUP_MSK)
#define CA_SF_TMR_CLK_MSK GENMASK(26, 24)
#define CA_SF_TMR_CLK(clk) (((clk) << 24) & CA_SF_TMR_CLK_MSK)
#define CA_SFLASH_IND_WRITE 0
#define CA_SFLASH_IND_READ 1
#define CA_SFLASH_MEM_MAP 3
#define CA_SFLASH_FIFO_TIMEOUT_US 30000
#define CA_SFLASH_BUSY_TIMEOUT_US 40000
#define CA_SF_AC_OP 0x00
#define CA_SF_AC_OP_1_DATA 0x01
#define CA_SF_AC_OP_2_DATA 0x02
#define CA_SF_AC_OP_3_DATA 0x03
#define CA_SF_AC_OP_4_DATA 0x04
#define CA_SF_AC_OP_3_ADDR 0x05
#define CA_SF_AC_OP_4_ADDR (CA_SF_AC_OP_3_ADDR)
#define CA_SF_AC_OP_3_ADDR_1_DATA 0x06
#define CA_SF_AC_OP_4_ADDR_1_DATA (CA_SF_AC_OP_3_ADDR_1_DATA << 2)
#define CA_SF_AC_OP_3_ADDR_2_DATA 0x07
#define CA_SF_AC_OP_4_ADDR_2_DATA (CA_SF_AC_OP_3_ADDR_2_DATA << 2)
#define CA_SF_AC_OP_3_ADDR_3_DATA 0x08
#define CA_SF_AC_OP_4_ADDR_3_DATA (CA_SF_AC_OP_3_ADDR_3_DATA << 2)
#define CA_SF_AC_OP_3_ADDR_4_DATA 0x09
#define CA_SF_AC_OP_4_ADDR_4_DATA (CA_SF_AC_OP_3_ADDR_4_DATA << 2)
#define CA_SF_AC_OP_3_ADDR_X_1_DATA 0x0A
#define CA_SF_AC_OP_4_ADDR_X_1_DATA (CA_SF_AC_OP_3_ADDR_X_1_DATA << 2)
#define CA_SF_AC_OP_3_ADDR_X_2_DATA 0x0B
#define CA_SF_AC_OP_4_ADDR_X_2_DATA (CA_SF_AC_OP_3_ADDR_X_2_DATA << 2)
#define CA_SF_AC_OP_3_ADDR_X_3_DATA 0x0C
#define CA_SF_AC_OP_4_ADDR_X_3_DATA (CA_SF_AC_OP_3_ADDR_X_3_DATA << 2)
#define CA_SF_AC_OP_3_ADDR_X_4_DATA 0x0D
#define CA_SF_AC_OP_4_ADDR_X_4_DATA (CA_SF_AC_OP_3_ADDR_X_4_DATA << 2)
#define CA_SF_AC_OP_3_ADDR_4X_1_DATA 0x0E
#define CA_SF_AC_OP_4_ADDR_4X_1_DATA (CA_SF_AC_OP_3_ADDR_4X_1_DATA << 2)
#define CA_SF_AC_OP_EXTEND 0x0F
#define CA_SF_ACCESS_MIO_SINGLE 0
#define CA_SF_ACCESS_MIO_DUAL 1
#define CA_SF_ACCESS_MIO_QUARD 2
enum access_type {
RD_ACCESS,
WR_ACCESS,
};
struct ca_sflash_priv {
struct ca_sflash_regs *regs;
u8 rx_width;
u8 tx_width;
};
/*
* This function doesn't do anything except help with debugging
*/
static int ca_sflash_claim_bus(struct udevice *dev)
{
debug("%s:\n", __func__);
return 0;
}
static int ca_sflash_release_bus(struct udevice *dev)
{
debug("%s:\n", __func__);
return 0;
}
static int ca_sflash_set_speed(struct udevice *dev, uint speed)
{
debug("%s:\n", __func__);
return 0;
}
static int ca_sflash_set_mode(struct udevice *dev, uint mode)
{
struct ca_sflash_priv *priv = dev_get_priv(dev);
if (mode & SPI_RX_QUAD)
priv->rx_width = 4;
else if (mode & SPI_RX_DUAL)
priv->rx_width = 2;
else
priv->rx_width = 1;
if (mode & SPI_TX_QUAD)
priv->tx_width = 4;
else if (mode & SPI_TX_DUAL)
priv->tx_width = 2;
else
priv->tx_width = 1;
debug("%s: mode=%d, rx_width=%d, tx_width=%d\n",
__func__, mode, priv->rx_width, priv->tx_width);
return 0;
}
static int _ca_sflash_wait_for_not_busy(struct ca_sflash_priv *priv)
{
u32 asr;
if (readl_poll_timeout(&priv->regs->asr, asr,
!(asr & CA_FLASH_ASR_IND_START_EN),
CA_SFLASH_BUSY_TIMEOUT_US)) {
pr_err("busy timeout (stat:%#x)\n", asr);
return -1;
}
return 0;
}
static int _ca_sflash_wait_cmd(struct ca_sflash_priv *priv,
enum access_type type)
{
if (type == WR_ACCESS) {
/* Enable write access and start the sflash indirect access */
clrsetbits_le32(&priv->regs->asr, GENMASK(31, 0),
CA_FLASH_ASR_WR_ACCESS_EN
| CA_FLASH_ASR_IND_START_EN);
} else if (type == RD_ACCESS) {
/* Start the sflash indirect access */
clrsetbits_le32(&priv->regs->asr, GENMASK(31, 0),
CA_FLASH_ASR_IND_START_EN);
} else {
printf("%s: !error access type.\n", __func__);
return -1;
}
/* Wait til the action(rd/wr) completed */
return _ca_sflash_wait_for_not_busy(priv);
}
static int _ca_sflash_read(struct ca_sflash_priv *priv,
u8 *buf, unsigned int data_len)
{
u32 reg_data;
int len;
len = data_len;
while (len >= 4) {
if (_ca_sflash_wait_cmd(priv, RD_ACCESS))
return -1;
reg_data = readl(&priv->regs->dr);
*buf++ = reg_data & 0xFF;
*buf++ = (reg_data >> 8) & 0xFF;
*buf++ = (reg_data >> 16) & 0xFF;
*buf++ = (reg_data >> 24) & 0xFF;
len -= 4;
debug("%s: reg_data=%#08x\n",
__func__, reg_data);
}
if (len > 0) {
if (_ca_sflash_wait_cmd(priv, RD_ACCESS))
return -1;
reg_data = readl(&priv->regs->dr);
debug("%s: reg_data=%#08x\n",
__func__, reg_data);
}
switch (len) {
case 3:
*buf++ = reg_data & 0xFF;
*buf++ = (reg_data >> 8) & 0xFF;
*buf++ = (reg_data >> 16) & 0xFF;
break;
case 2:
*buf++ = reg_data & 0xFF;
*buf++ = (reg_data >> 8) & 0xFF;
break;
case 1:
*buf++ = reg_data & 0xFF;
break;
case 0:
break;
default:
printf("%s: error data_length %d!\n", __func__, len);
}
return 0;
}
static int _ca_sflash_mio_set(struct ca_sflash_priv *priv,
u8 width)
{
if (width == 4) {
setbits_le32(&priv->regs->ar,
CA_SF_AR_MIO_INF_DC
| CA_SF_AR_MIO_INF(CA_SF_ACCESS_MIO_QUARD)
| CA_SF_AR_FORCE_BURST);
} else if (width == 2) {
setbits_le32(&priv->regs->ar,
CA_SF_AR_MIO_INF_DC
| CA_SF_AR_MIO_INF(CA_SF_ACCESS_MIO_DUAL)
| CA_SF_AR_FORCE_BURST);
} else if (width == 1) {
setbits_le32(&priv->regs->ar,
CA_SF_AR_MIO_INF(CA_SF_ACCESS_MIO_SINGLE)
| CA_SF_AR_FORCE_BURST);
} else {
printf("%s: error rx/tx width %d!\n", __func__, width);
return -1;
}
return 0;
}
static int _ca_sflash_write(struct ca_sflash_priv *priv,
u8 *buf, unsigned int data_len)
{
u32 reg_data;
int len;
len = data_len;
while (len > 0) {
reg_data = buf[0]
| (buf[1] << 8)
| (buf[2] << 16)
| (buf[3] << 24);
debug("%s: reg_data=%#08x\n",
__func__, reg_data);
/* Fill data */
clrsetbits_le32(&priv->regs->dr, GENMASK(31, 0), reg_data);
if (_ca_sflash_wait_cmd(priv, WR_ACCESS))
return -1;
len -= 4;
buf += 4;
}
return 0;
}
static int _ca_sflash_access_data(struct ca_sflash_priv *priv,
struct spi_mem_op *op)
{
int total_cnt;
unsigned int len;
unsigned int data_cnt = op->data.nbytes;
u64 addr_offset = op->addr.val;
u8 addr_cnt = op->addr.nbytes;
u8 *data_buf = NULL;
u8 *buf = NULL;
if (op->data.dir == SPI_MEM_DATA_IN)
data_buf = (u8 *)op->data.buf.in;
else
data_buf = (u8 *)op->data.buf.out;
if (data_cnt > CA_SF_EAR_DATA_CNT_MAX)
buf = malloc(CA_SF_EAR_DATA_CNT_MAX);
else
buf = malloc(data_cnt);
total_cnt = data_cnt;
while (total_cnt > 0) {
/* Fill address */
if (addr_cnt > 0)
clrsetbits_le32(&priv->regs->adr,
GENMASK(31, 0), (u32)addr_offset);
if (total_cnt > CA_SF_EAR_DATA_CNT_MAX) {
len = CA_SF_EAR_DATA_CNT_MAX;
addr_offset += CA_SF_EAR_DATA_CNT_MAX;
/* Clear start bit before next bulk read */
clrbits_le32(&priv->regs->asr, GENMASK(31, 0));
} else {
len = total_cnt;
}
memset(buf, 0, len);
if (op->data.dir == SPI_MEM_DATA_IN) {
if (_ca_sflash_read(priv, buf, len))
break;
memcpy(data_buf, buf, len);
} else {
memcpy(buf, data_buf, len);
if (_ca_sflash_write(priv, buf, len))
break;
}
total_cnt -= len;
data_buf += len;
}
if (buf)
free(buf);
return total_cnt > 0 ? -1 : 0;
}
static int _ca_sflash_issue_cmd(struct ca_sflash_priv *priv,
struct spi_mem_op *op, u8 opcode)
{
u8 dummy_cnt = op->dummy.nbytes;
u8 addr_cnt = op->addr.nbytes;
u8 mio_width;
unsigned int data_cnt = op->data.nbytes;
u64 addr_offset = op->addr.val;
/* Set the access register */
clrsetbits_le32(&priv->regs->ar,
GENMASK(31, 0), CA_SF_AR_ACCODE(opcode));
if (opcode == CA_SF_AC_OP_EXTEND) { /* read_data, write_data */
if (data_cnt > 6) {
if (op->data.dir == SPI_MEM_DATA_IN)
mio_width = priv->rx_width;
else
mio_width = priv->tx_width;
if (_ca_sflash_mio_set(priv, mio_width))
return -1;
}
debug("%s: FLASH ACCESS reg=%#08x\n",
__func__, readl(&priv->regs->ar));
/* Use command in extend_access register */
clrsetbits_le32(&priv->regs->ear,
GENMASK(31, 0), CA_SF_EAR_OP(op->cmd.opcode)
| CA_SF_EAR_DUMY_CNT(dummy_cnt * 8 - 1)
| CA_SF_EAR_ADDR_CNT(addr_cnt - 1)
| CA_SF_EAR_DATA_CNT(4 - 1)
| CA_SF_EAR_DRD_CMD_EN);
debug("%s: FLASH EXT ACCESS reg=%#08x\n",
__func__, readl(&priv->regs->ear));
if (_ca_sflash_access_data(priv, op))
return -1;
} else { /* reset_op, wr_enable, wr_disable */
setbits_le32(&priv->regs->ar,
CA_SF_AR_OP(op->cmd.opcode));
debug("%s: FLASH ACCESS reg=%#08x\n",
__func__, readl(&priv->regs->ar));
if (opcode == CA_SF_AC_OP_4_ADDR) { /* erase_op */
/* Configure address length */
if (addr_cnt > 3) /* 4 Bytes address */
setbits_le32(&priv->regs->tr,
CA_FLASH_TR_SIZE(2));
else /* 3 Bytes address */
clrbits_le32(&priv->regs->tr,
CA_FLASH_TR_SIZE_MSK);
/* Fill address */
if (addr_cnt > 0)
clrsetbits_le32(&priv->regs->adr,
GENMASK(31, 0),
(u32)addr_offset);
}
if (_ca_sflash_wait_cmd(priv, RD_ACCESS))
return -1;
}
/* elapse 10us before issuing any other command */
udelay(10);
return 0;
}
static int ca_sflash_exec_op(struct spi_slave *slave,
const struct spi_mem_op *op)
{
struct ca_sflash_priv *priv = dev_get_priv(slave->dev->parent);
u8 opcode;
debug("%s: cmd:%#02x addr.val:%#llx addr.len:%#x data.len:%#x data.dir:%#x\n",
__func__, op->cmd.opcode, op->addr.val,
op->addr.nbytes, op->data.nbytes, op->data.dir);
if (op->data.nbytes == 0 && op->addr.nbytes == 0) {
opcode = CA_SF_AC_OP;
} else if (op->data.nbytes == 0 && op->addr.nbytes > 0) {
opcode = CA_SF_AC_OP_4_ADDR;
} else if (op->data.nbytes > 0) {
opcode = CA_SF_AC_OP_EXTEND;
} else {
printf("%s: can't support cmd.opcode:(%#02x) type currently!\n",
__func__, op->cmd.opcode);
return -1;
}
return _ca_sflash_issue_cmd(priv, (struct spi_mem_op *)op, opcode);
}
static void ca_sflash_init(struct ca_sflash_priv *priv)
{
/* Set FLASH_TYPE as serial flash, value: 0x0400*/
clrsetbits_le32(&priv->regs->tr,
GENMASK(31, 0), CA_FLASH_TR_SIZE(2));
debug("%s: FLASH_TYPE reg=%#x\n",
__func__, readl(&priv->regs->tr));
/* Minimize flash timing, value: 0x07010101 */
clrsetbits_le32(&priv->regs->tmr,
GENMASK(31, 0),
CA_SF_TMR_CLK(0x07)
| CA_SF_TMR_SETUP(0x01)
| CA_SF_TMR_HOLD(0x01)
| CA_SF_TMR_IDLE(0x01));
debug("%s: FLASH_TIMING reg=%#x\n",
__func__, readl(&priv->regs->tmr));
}
static int ca_sflash_probe(struct udevice *dev)
{
struct ca_sflash_priv *priv = dev_get_priv(dev);
struct resource res;
int ret;
/* Map the registers */
ret = dev_read_resource_byname(dev, "sflash-regs", &res);
if (ret) {
dev_err(dev, "can't get regs base addresses(ret = %d)!\n", ret);
return ret;
}
priv->regs = devm_ioremap(dev, res.start, resource_size(&res));
if (IS_ERR(priv->regs))
return PTR_ERR(priv->regs);
ca_sflash_init(priv);
printf("SFLASH: Controller probed ready\n");
return 0;
}
static const struct spi_controller_mem_ops ca_sflash_mem_ops = {
.exec_op = ca_sflash_exec_op,
};
static const struct dm_spi_ops ca_sflash_ops = {
.claim_bus = ca_sflash_claim_bus,
.release_bus = ca_sflash_release_bus,
.set_speed = ca_sflash_set_speed,
.set_mode = ca_sflash_set_mode,
.mem_ops = &ca_sflash_mem_ops,
};
static const struct udevice_id ca_sflash_ids[] = {
{.compatible = "cortina,ca-sflash"},
{}
};
U_BOOT_DRIVER(ca_sflash) = {
.name = "ca_sflash",
.id = UCLASS_SPI,
.of_match = ca_sflash_ids,
.ops = &ca_sflash_ops,
.priv_auto_alloc_size = sizeof(struct ca_sflash_priv),
.probe = ca_sflash_probe,
};

401
drivers/spi/designware_spi.c
View file

@ -3,37 +3,42 @@
* Designware master SPI core controller driver
*
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
* Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
*
* Very loosely based on the Linux driver:
* drivers/spi/spi-dw.c, which is:
* Copyright (c) 2009, Intel Corporation.
*/
#define LOG_CATEGORY UCLASS_SPI
#include <common.h>
#include <log.h>
#include <asm-generic/gpio.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <spi.h>
#include <fdtdec.h>
#include <reset.h>
#include <dm/device_compat.h>
#include <errno.h>
#include <fdtdec.h>
#include <log.h>
#include <malloc.h>
#include <reset.h>
#include <spi.h>
#include <spi-mem.h>
#include <asm/io.h>
#include <asm-generic/gpio.h>
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/compat.h>
#include <linux/iopoll.h>
#include <asm/io.h>
#include <linux/sizes.h>
/* Register offsets */
#define DW_SPI_CTRL0 0x00
#define DW_SPI_CTRL1 0x04
#define DW_SPI_CTRLR0 0x00
#define DW_SPI_CTRLR1 0x04
#define DW_SPI_SSIENR 0x08
#define DW_SPI_MWCR 0x0c
#define DW_SPI_SER 0x10
#define DW_SPI_BAUDR 0x14
#define DW_SPI_TXFLTR 0x18
#define DW_SPI_RXFLTR 0x1c
#define DW_SPI_TXFTLR 0x18
#define DW_SPI_RXFTLR 0x1c
#define DW_SPI_TXFLR 0x20
#define DW_SPI_RXFLR 0x24
#define DW_SPI_SR 0x28
@ -53,28 +58,48 @@
#define DW_SPI_DR 0x60
/* Bit fields in CTRLR0 */
#define SPI_DFS_OFFSET 0
/*
* Only present when SSI_MAX_XFER_SIZE=16. This is the default, and the only
* option before version 3.23a.
*/
#define CTRLR0_DFS_MASK GENMASK(3, 0)
#define SPI_FRF_OFFSET 4
#define SPI_FRF_SPI 0x0
#define SPI_FRF_SSP 0x1
#define SPI_FRF_MICROWIRE 0x2
#define SPI_FRF_RESV 0x3
#define CTRLR0_FRF_MASK GENMASK(5, 4)
#define CTRLR0_FRF_SPI 0x0
#define CTRLR0_FRF_SSP 0x1
#define CTRLR0_FRF_MICROWIRE 0x2
#define CTRLR0_FRF_RESV 0x3
#define SPI_MODE_OFFSET 6
#define SPI_SCPH_OFFSET 6
#define SPI_SCOL_OFFSET 7
#define CTRLR0_MODE_MASK GENMASK(7, 6)
#define CTRLR0_MODE_SCPH 0x1
#define CTRLR0_MODE_SCPOL 0x2
#define SPI_TMOD_OFFSET 8
#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
#define SPI_TMOD_TR 0x0 /* xmit & recv */
#define SPI_TMOD_TO 0x1 /* xmit only */
#define SPI_TMOD_RO 0x2 /* recv only */
#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
#define CTRLR0_TMOD_MASK GENMASK(9, 8)
#define CTRLR0_TMOD_TR 0x0 /* xmit & recv */
#define CTRLR0_TMOD_TO 0x1 /* xmit only */
#define CTRLR0_TMOD_RO 0x2 /* recv only */
#define CTRLR0_TMOD_EPROMREAD 0x3 /* eeprom read mode */
#define SPI_SLVOE_OFFSET 10
#define SPI_SRL_OFFSET 11
#define SPI_CFS_OFFSET 12
#define CTRLR0_SLVOE_OFFSET 10
#define CTRLR0_SRL_OFFSET 11
#define CTRLR0_CFS_MASK GENMASK(15, 12)
/* Only present when SSI_MAX_XFER_SIZE=32 */
#define CTRLR0_DFS_32_MASK GENMASK(20, 16)
/* The next field is only present on versions after 4.00a */
#define CTRLR0_SPI_FRF_MASK GENMASK(22, 21)
#define CTRLR0_SPI_FRF_BYTE 0x0
#define CTRLR0_SPI_FRF_DUAL 0x1
#define CTRLR0_SPI_FRF_QUAD 0x2
/* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */
#define DWC_SSI_CTRLR0_DFS_MASK GENMASK(4, 0)
#define DWC_SSI_CTRLR0_FRF_MASK GENMASK(7, 6)
#define DWC_SSI_CTRLR0_MODE_MASK GENMASK(9, 8)
#define DWC_SSI_CTRLR0_TMOD_MASK GENMASK(11, 10)
#define DWC_SSI_CTRLR0_SRL_OFFSET 13
#define DWC_SSI_CTRLR0_SPI_FRF_MASK GENMASK(23, 22)
/* Bit fields in SR, 7 bits */
#define SR_MASK GENMASK(6, 0) /* cover 7 bits */
@ -94,27 +119,29 @@ struct dw_spi_platdata {
};
struct dw_spi_priv {
void __iomem *regs;
unsigned int freq; /* Default frequency */
unsigned int mode;
struct clk clk;
unsigned long bus_clk_rate;
struct reset_ctl_bulk resets;
struct gpio_desc cs_gpio; /* External chip-select gpio */
int bits_per_word;
u8 cs; /* chip select pin */
u8 tmode; /* TR/TO/RO/EEPROM */
u8 type; /* SPI/SSP/MicroWire */
int len;
u32 (*update_cr0)(struct dw_spi_priv *priv);
u32 fifo_len; /* depth of the FIFO buffer */
void *tx;
void *tx_end;
void __iomem *regs;
unsigned long bus_clk_rate;
unsigned int freq; /* Default frequency */
unsigned int mode;
const void *tx;
const void *tx_end;
void *rx;
void *rx_end;
u32 fifo_len; /* depth of the FIFO buffer */
u32 max_xfer; /* Maximum transfer size (in bits) */
struct reset_ctl_bulk resets;
int bits_per_word;
int len;
u8 cs; /* chip select pin */
u8 tmode; /* TR/TO/RO/EEPROM */
u8 type; /* SPI/SSP/MicroWire */
};
static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset)
@ -127,6 +154,53 @@ static inline void dw_write(struct dw_spi_priv *priv, u32 offset, u32 val)
__raw_writel(val, priv->regs + offset);
}
static u32 dw_spi_dw16_update_cr0(struct dw_spi_priv *priv)
{
return FIELD_PREP(CTRLR0_DFS_MASK, priv->bits_per_word - 1)
| FIELD_PREP(CTRLR0_FRF_MASK, priv->type)
| FIELD_PREP(CTRLR0_MODE_MASK, priv->mode)
| FIELD_PREP(CTRLR0_TMOD_MASK, priv->tmode);
}
static u32 dw_spi_dw32_update_cr0(struct dw_spi_priv *priv)
{
return FIELD_PREP(CTRLR0_DFS_32_MASK, priv->bits_per_word - 1)
| FIELD_PREP(CTRLR0_FRF_MASK, priv->type)
| FIELD_PREP(CTRLR0_MODE_MASK, priv->mode)
| FIELD_PREP(CTRLR0_TMOD_MASK, priv->tmode);
}
static u32 dw_spi_dwc_update_cr0(struct dw_spi_priv *priv)
{
return FIELD_PREP(DWC_SSI_CTRLR0_DFS_MASK, priv->bits_per_word - 1)
| FIELD_PREP(DWC_SSI_CTRLR0_FRF_MASK, priv->type)
| FIELD_PREP(DWC_SSI_CTRLR0_MODE_MASK, priv->mode)
| FIELD_PREP(DWC_SSI_CTRLR0_TMOD_MASK, priv->tmode);
}
static int dw_spi_apb_init(struct udevice *bus, struct dw_spi_priv *priv)
{
/* If we read zeros from DFS, then we need to use DFS_32 instead */
dw_write(priv, DW_SPI_SSIENR, 0);
dw_write(priv, DW_SPI_CTRLR0, 0xffffffff);
if (FIELD_GET(CTRLR0_DFS_MASK, dw_read(priv, DW_SPI_CTRLR0))) {
priv->max_xfer = 16;
priv->update_cr0 = dw_spi_dw16_update_cr0;
} else {
priv->max_xfer = 32;
priv->update_cr0 = dw_spi_dw32_update_cr0;
}
return 0;
}
static int dw_spi_dwc_init(struct udevice *bus, struct dw_spi_priv *priv)
{
priv->max_xfer = 32;
priv->update_cr0 = dw_spi_dwc_update_cr0;
return 0;
}
static int request_gpio_cs(struct udevice *bus)
{
#if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD)
@ -134,12 +208,13 @@ static int request_gpio_cs(struct udevice *bus)
int ret;
/* External chip select gpio line is optional */
ret = gpio_request_by_name(bus, "cs-gpio", 0, &priv->cs_gpio, 0);
ret = gpio_request_by_name(bus, "cs-gpios", 0, &priv->cs_gpio,
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
if (ret == -ENOENT)
return 0;
if (ret < 0) {
printf("Error: %d: Can't get %s gpio!\n", ret, bus->name);
dev_err(bus, "Couldn't request gpio! (error %d)\n", ret);
return ret;
}
@ -148,7 +223,7 @@ static int request_gpio_cs(struct udevice *bus)
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
}
debug("%s: used external gpio for CS management\n", __func__);
dev_dbg(bus, "Using external gpio for CS management\n");
#endif
return 0;
}
@ -158,27 +233,27 @@ static int dw_spi_ofdata_to_platdata(struct udevice *bus)
struct dw_spi_platdata *plat = bus->platdata;
plat->regs = dev_read_addr_ptr(bus);
if (!plat->regs)
return -EINVAL;
/* Use 500KHz as a suitable default */
plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
500000);
debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs,
plat->frequency);
if (dev_read_bool(bus, "spi-slave"))
return -EINVAL;
dev_info(bus, "max-frequency=%d\n", plat->frequency);
return request_gpio_cs(bus);
}
static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable)
{
dw_write(priv, DW_SPI_SSIENR, (enable ? 1 : 0));
}
/* Restart the controller, disable all interrupts, clean rx fifo */
static void spi_hw_init(struct dw_spi_priv *priv)
static void spi_hw_init(struct udevice *bus, struct dw_spi_priv *priv)
{
spi_enable_chip(priv, 0);
dw_write(priv, DW_SPI_SSIENR, 0);
dw_write(priv, DW_SPI_IMR, 0xff);
spi_enable_chip(priv, 1);
dw_write(priv, DW_SPI_SSIENR, 1);
/*
* Try to detect the FIFO depth if not set by interface driver,
@ -188,15 +263,15 @@ static void spi_hw_init(struct dw_spi_priv *priv)
u32 fifo;
for (fifo = 1; fifo < 256; fifo++) {
dw_write(priv, DW_SPI_TXFLTR, fifo);
if (fifo != dw_read(priv, DW_SPI_TXFLTR))
dw_write(priv, DW_SPI_TXFTLR, fifo);
if (fifo != dw_read(priv, DW_SPI_TXFTLR))
break;
}
priv->fifo_len = (fifo == 1) ? 0 : fifo;
dw_write(priv, DW_SPI_TXFLTR, 0);
dw_write(priv, DW_SPI_TXFTLR, 0);
}
debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
dev_dbg(bus, "fifo_len=%d\n", priv->fifo_len);
}
/*
@ -221,8 +296,7 @@ __weak int dw_spi_get_clk(struct udevice *bus, ulong *rate)
if (!*rate)
goto err_rate;
debug("%s: get spi controller clk via device tree: %lu Hz\n",
__func__, *rate);
dev_dbg(bus, "Got clock via device tree: %lu Hz\n", *rate);
return 0;
@ -247,25 +321,31 @@ static int dw_spi_reset(struct udevice *bus)
if (ret == -ENOENT || ret == -ENOTSUPP)
return 0;
dev_warn(bus, "Can't get reset: %d\n", ret);
dev_warn(bus, "Couldn't find/assert reset device (error %d)\n",
ret);
return ret;
}
ret = reset_deassert_bulk(&priv->resets);
if (ret) {
reset_release_bulk(&priv->resets);
dev_err(bus, "Failed to reset: %d\n", ret);
dev_err(bus, "Failed to de-assert reset for SPI (error %d)\n",
ret);
return ret;
}
return 0;
}
typedef int (*dw_spi_init_t)(struct udevice *bus, struct dw_spi_priv *priv);
static int dw_spi_probe(struct udevice *bus)
{
dw_spi_init_t init = (dw_spi_init_t)dev_get_driver_data(bus);
struct dw_spi_platdata *plat = dev_get_platdata(bus);
struct dw_spi_priv *priv = dev_get_priv(bus);
int ret;
u32 version;
priv->regs = plat->regs;
priv->freq = plat->frequency;
@ -278,13 +358,24 @@ static int dw_spi_probe(struct udevice *bus)
if (ret)
return ret;
if (!init)
return -EINVAL;
ret = init(bus, priv);
if (ret)
return ret;
version = dw_read(priv, DW_SPI_VERSION);
dev_dbg(bus, "ssi_version_id=%c.%c%c%c ssi_max_xfer_size=%u\n",
version >> 24, version >> 16, version >> 8, version,
priv->max_xfer);
/* Currently only bits_per_word == 8 supported */
priv->bits_per_word = 8;
priv->tmode = 0; /* Tx & Rx */
/* Basic HW init */
spi_hw_init(priv);
spi_hw_init(bus, priv);
return 0;
}
@ -322,7 +413,7 @@ static inline u32 rx_max(struct dw_spi_priv *priv)
static void dw_writer(struct dw_spi_priv *priv)
{
u32 max = tx_max(priv);
u16 txw = 0;
u32 txw = 0xFFFFFFFF;
while (max--) {
/* Set the tx word if the transfer's original "tx" is not null */
@ -333,7 +424,7 @@ static void dw_writer(struct dw_spi_priv *priv)
txw = *(u16 *)(priv->tx);
}
dw_write(priv, DW_SPI_DR, txw);
debug("%s: tx=0x%02x\n", __func__, txw);
log_content("tx=0x%02x\n", txw);
priv->tx += priv->bits_per_word >> 3;
}
}
@ -345,7 +436,7 @@ static void dw_reader(struct dw_spi_priv *priv)
while (max--) {
rxw = dw_read(priv, DW_SPI_DR);
debug("%s: rx=0x%02x\n", __func__, rxw);
log_content("rx=0x%02x\n", rxw);
/* Care about rx if the transfer's original "rx" is not null */
if (priv->rx_end - priv->len) {
@ -400,7 +491,7 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
/* spi core configured to do 8 bit transfers */
if (bitlen % 8) {
debug("Non byte aligned SPI transfer.\n");
dev_err(dev, "Non byte aligned SPI transfer.\n");
return -1;
}
@ -408,26 +499,20 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
if (flags & SPI_XFER_BEGIN)
external_cs_manage(dev, false);
cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) |
(priv->mode << SPI_MODE_OFFSET) |
(priv->tmode << SPI_TMOD_OFFSET);
if (rx && tx)
priv->tmode = SPI_TMOD_TR;
priv->tmode = CTRLR0_TMOD_TR;
else if (rx)
priv->tmode = SPI_TMOD_RO;
priv->tmode = CTRLR0_TMOD_RO;
else
/*
* In transmit only mode (SPI_TMOD_TO) input FIFO never gets
* In transmit only mode (CTRL0_TMOD_TO) input FIFO never gets
* any data which breaks our logic in poll_transfer() above.
*/
priv->tmode = SPI_TMOD_TR;
priv->tmode = CTRLR0_TMOD_TR;
cr0 &= ~SPI_TMOD_MASK;
cr0 |= (priv->tmode << SPI_TMOD_OFFSET);
cr0 = priv->update_cr0(priv);
priv->len = bitlen >> 3;
debug("%s: rx=%p tx=%p len=%d [bytes]\n", __func__, rx, tx, priv->len);
priv->tx = (void *)tx;
priv->tx_end = priv->tx + priv->len;
@ -435,12 +520,13 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
priv->rx_end = priv->rx + priv->len;
/* Disable controller before writing control registers */
spi_enable_chip(priv, 0);
dw_write(priv, DW_SPI_SSIENR, 0);
debug("%s: cr0=%08x\n", __func__, cr0);
dev_dbg(dev, "cr0=%08x rx=%p tx=%p len=%d [bytes]\n", cr0, rx, tx,
priv->len);
/* Reprogram cr0 only if changed */
if (dw_read(priv, DW_SPI_CTRL0) != cr0)
dw_write(priv, DW_SPI_CTRL0, cr0);
if (dw_read(priv, DW_SPI_CTRLR0) != cr0)
dw_write(priv, DW_SPI_CTRLR0, cr0);
/*
* Configure the desired SS (slave select 0...3) in the controller
@ -451,7 +537,7 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
dw_write(priv, DW_SPI_SER, 1 << cs);
/* Enable controller after writing control registers */
spi_enable_chip(priv, 1);
dw_write(priv, DW_SPI_SSIENR, 1);
/* Start transfer in a polling loop */
ret = poll_transfer(priv);
@ -476,9 +562,110 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
return ret;
}
/*
* This function is necessary for reading SPI flash with the native CS
* c.f. https://lkml.org/lkml/2015/12/23/132
*/
static int dw_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
{
bool read = op->data.dir == SPI_MEM_DATA_IN;
int pos, i, ret = 0;
struct udevice *bus = slave->dev->parent;
struct dw_spi_priv *priv = dev_get_priv(bus);
u8 op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
u8 op_buf[op_len];
u32 cr0;
if (read)
priv->tmode = CTRLR0_TMOD_EPROMREAD;
else
priv->tmode = CTRLR0_TMOD_TO;
cr0 = priv->update_cr0(priv);
dev_dbg(bus, "cr0=%08x buf=%p len=%u [bytes]\n", cr0, op->data.buf.in,
op->data.nbytes);
dw_write(priv, DW_SPI_SSIENR, 0);
dw_write(priv, DW_SPI_CTRLR0, cr0);
if (read)
dw_write(priv, DW_SPI_CTRLR1, op->data.nbytes - 1);
dw_write(priv, DW_SPI_SSIENR, 1);
/* From spi_mem_exec_op */
pos = 0;
op_buf[pos++] = op->cmd.opcode;
if (op->addr.nbytes) {
for (i = 0; i < op->addr.nbytes; i++)
op_buf[pos + i] = op->addr.val >>
(8 * (op->addr.nbytes - i - 1));
pos += op->addr.nbytes;
}
if (op->dummy.nbytes)
memset(op_buf + pos, 0xff, op->dummy.nbytes);
external_cs_manage(slave->dev, false);
priv->tx = &op_buf;
priv->tx_end = priv->tx + op_len;
priv->rx = NULL;
priv->rx_end = NULL;
while (priv->tx != priv->tx_end)
dw_writer(priv);
/*
* XXX: The following are tight loops! Enabling debug messages may cause
* them to fail because we are not reading/writing the fifo fast enough.
*/
if (read) {
priv->rx = op->data.buf.in;
priv->rx_end = priv->rx + op->data.nbytes;
dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev));
while (priv->rx != priv->rx_end)
dw_reader(priv);
} else {
u32 val;
priv->tx = op->data.buf.out;
priv->tx_end = priv->tx + op->data.nbytes;
/* Fill up the write fifo before starting the transfer */
dw_writer(priv);
dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev));
while (priv->tx != priv->tx_end)
dw_writer(priv);
if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
(val & SR_TF_EMPT) && !(val & SR_BUSY),
RX_TIMEOUT * 1000)) {
ret = -ETIMEDOUT;
}
}
dw_write(priv, DW_SPI_SER, 0);
external_cs_manage(slave->dev, true);
dev_dbg(bus, "%u bytes xfered\n", op->data.nbytes);
return ret;
}
/* The size of ctrl1 limits data transfers to 64K */
static int dw_spi_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op)
{
op->data.nbytes = min(op->data.nbytes, (unsigned int)SZ_64K);
return 0;
}
static const struct spi_controller_mem_ops dw_spi_mem_ops = {
.exec_op = dw_spi_exec_op,
.adjust_op_size = dw_spi_adjust_op_size,
};
static int dw_spi_set_speed(struct udevice *bus, uint speed)
{
struct dw_spi_platdata *plat = bus->platdata;
struct dw_spi_platdata *plat = dev_get_platdata(bus);
struct dw_spi_priv *priv = dev_get_priv(bus);
u16 clk_div;
@ -486,7 +673,7 @@ static int dw_spi_set_speed(struct udevice *bus, uint speed)
speed = plat->frequency;
/* Disable controller before writing control registers */
spi_enable_chip(priv, 0);
dw_write(priv, DW_SPI_SSIENR, 0);
/* clk_div doesn't support odd number */
clk_div = priv->bus_clk_rate / speed;
@ -494,11 +681,10 @@ static int dw_spi_set_speed(struct udevice *bus, uint speed)
dw_write(priv, DW_SPI_BAUDR, clk_div);
/* Enable controller after writing control registers */
spi_enable_chip(priv, 1);
dw_write(priv, DW_SPI_SSIENR, 1);
priv->freq = speed;
debug("%s: regs=%p speed=%d clk_div=%d\n", __func__, priv->regs,
priv->freq, clk_div);
dev_dbg(bus, "speed=%d clk_div=%d\n", priv->freq, clk_div);
return 0;
}
@ -513,7 +699,7 @@ static int dw_spi_set_mode(struct udevice *bus, uint mode)
* real transfer function.
*/
priv->mode = mode;
debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
dev_dbg(bus, "mode=%d\n", priv->mode);
return 0;
}
@ -541,6 +727,7 @@ static int dw_spi_remove(struct udevice *bus)
static const struct dm_spi_ops dw_spi_ops = {
.xfer = dw_spi_xfer,
.mem_ops = &dw_spi_mem_ops,
.set_speed = dw_spi_set_speed,
.set_mode = dw_spi_set_mode,
/*
@ -550,7 +737,35 @@ static const struct dm_spi_ops dw_spi_ops = {
};
static const struct udevice_id dw_spi_ids[] = {
{ .compatible = "snps,dw-apb-ssi" },
/* Generic compatible strings */
{ .compatible = "snps,dw-apb-ssi", .data = (ulong)dw_spi_apb_init },
{ .compatible = "snps,dw-apb-ssi-3.20a", .data = (ulong)dw_spi_apb_init },
{ .compatible = "snps,dw-apb-ssi-3.22a", .data = (ulong)dw_spi_apb_init },
/* First version with SSI_MAX_XFER_SIZE */
{ .compatible = "snps,dw-apb-ssi-3.23a", .data = (ulong)dw_spi_apb_init },
/* First version with Dual/Quad SPI; unused by this driver */
{ .compatible = "snps,dw-apb-ssi-4.00a", .data = (ulong)dw_spi_apb_init },
{ .compatible = "snps,dw-apb-ssi-4.01", .data = (ulong)dw_spi_apb_init },
{ .compatible = "snps,dwc-ssi-1.01a", .data = (ulong)dw_spi_dwc_init },
/* Compatible strings for specific SoCs */
/*
* Both the Cyclone V and Arria V share a device tree and have the same
* version of this device. This compatible string is used for those
* devices, and is not used for sofpgas in general.
*/
{ .compatible = "altr,socfpga-spi", .data = (ulong)dw_spi_apb_init },
{ .compatible = "altr,socfpga-arria10-spi", .data = (ulong)dw_spi_apb_init },
{ .compatible = "canaan,kendryte-k210-spi", .data = (ulong)dw_spi_apb_init },
{ .compatible = "canaan,kendryte-k210-ssi", .data = (ulong)dw_spi_dwc_init },
{ .compatible = "intel,stratix10-spi", .data = (ulong)dw_spi_apb_init },
{ .compatible = "intel,agilex-spi", .data = (ulong)dw_spi_apb_init },
{ .compatible = "mscc,ocelot-spi", .data = (ulong)dw_spi_apb_init },
{ .compatible = "mscc,jaguar2-spi", .data = (ulong)dw_spi_apb_init },
{ .compatible = "snps,axs10x-spi", .data = (ulong)dw_spi_apb_init },
{ .compatible = "snps,hsdk-spi", .data = (ulong)dw_spi_apb_init },
{ }
};

51
drivers/spi/spi-uclass.c
View file

@ -3,12 +3,15 @@
* Copyright (c) 2014 Google, Inc
*/
#define LOG_CATEGORY UCLASS_SPI
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
#include <malloc.h>
#include <spi.h>
#include <dm/device_compat.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
#include <dm/lists.h>
@ -29,7 +32,7 @@ static int spi_set_speed_mode(struct udevice *bus, int speed, int mode)
else
ret = -EINVAL;
if (ret) {
printf("Cannot set speed (err=%d)\n", ret);
dev_err(bus, "Cannot set speed (err=%d)\n", ret);
return ret;
}
@ -38,7 +41,7 @@ static int spi_set_speed_mode(struct udevice *bus, int speed, int mode)
else
ret = -EINVAL;
if (ret) {
printf("Cannot set mode (err=%d)\n", ret);
dev_err(bus, "Cannot set mode (err=%d)\n", ret);
return ret;
}
@ -138,13 +141,15 @@ int spi_write_then_read(struct spi_slave *slave, const u8 *opcode,
ret = spi_xfer(slave, n_opcode * 8, opcode, NULL, flags);
if (ret) {
debug("spi: failed to send command (%zu bytes): %d\n",
n_opcode, ret);
dev_dbg(slave->dev,
"spi: failed to send command (%zu bytes): %d\n",
n_opcode, ret);
} else if (n_buf != 0) {
ret = spi_xfer(slave, n_buf * 8, txbuf, rxbuf, SPI_XFER_END);
if (ret)
debug("spi: failed to transfer %zu bytes of data: %d\n",
n_buf, ret);
dev_dbg(slave->dev,
"spi: failed to transfer %zu bytes of data: %d\n",
n_buf, ret);
}
return ret;
@ -248,7 +253,7 @@ int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp)
}
if (ret) {
printf("Invalid cs %d (err=%d)\n", cs, ret);
dev_err(bus, "Invalid cs %d (err=%d)\n", cs, ret);
return ret;
}
@ -257,7 +262,7 @@ int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp)
struct dm_spi_slave_platdata *plat;
plat = dev_get_parent_platdata(dev);
debug("%s: plat=%p, cs=%d\n", __func__, plat, plat->cs);
dev_dbg(bus, "%s: plat=%p, cs=%d\n", __func__, plat, plat->cs);
if (plat->cs == cs) {
*devp = dev;
return 0;
@ -275,7 +280,7 @@ int spi_cs_is_valid(unsigned int busnum, unsigned int cs)
ret = uclass_find_device_by_seq(UCLASS_SPI, busnum, false, &bus);
if (ret) {
debug("%s: No bus %d\n", __func__, busnum);
log_debug("%s: No bus %d\n", __func__, busnum);
return ret;
}
@ -304,12 +309,12 @@ int spi_find_bus_and_cs(int busnum, int cs, struct udevice **busp,
ret = uclass_find_device_by_seq(UCLASS_SPI, busnum, false, &bus);
if (ret) {
debug("%s: No bus %d\n", __func__, busnum);
log_debug("%s: No bus %d\n", __func__, busnum);
return ret;
}
ret = spi_find_chip_select(bus, cs, &dev);
if (ret) {
debug("%s: No cs %d\n", __func__, cs);
dev_dbg(bus, "%s: No cs %d\n", __func__, cs);
return ret;
}
*busp = bus;
@ -334,7 +339,7 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode,
ret = uclass_get_device_by_seq(UCLASS_SPI, busnum, &bus);
#endif
if (ret) {
printf("Invalid bus %d (err=%d)\n", busnum, ret);
log_err("Invalid bus %d (err=%d)\n", busnum, ret);
return ret;
}
ret = spi_find_chip_select(bus, cs, &dev);
@ -345,12 +350,12 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode,
* SPI flash chip - we will bind to the correct driver.
*/
if (ret == -ENODEV && drv_name) {
debug("%s: Binding new device '%s', busnum=%d, cs=%d, driver=%s\n",
__func__, dev_name, busnum, cs, drv_name);
dev_dbg(bus, "%s: Binding new device '%s', busnum=%d, cs=%d, driver=%s\n",
__func__, dev_name, busnum, cs, drv_name);
ret = device_bind_driver(bus, drv_name, dev_name, &dev);
if (ret) {
debug("%s: Unable to bind driver (ret=%d)\n", __func__,
ret);
dev_dbg(bus, "%s: Unable to bind driver (ret=%d)\n",
__func__, ret);
return ret;
}
plat = dev_get_parent_platdata(dev);
@ -358,15 +363,15 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode,
if (speed) {
plat->max_hz = speed;
} else {
printf("Warning: SPI speed fallback to %u kHz\n",
SPI_DEFAULT_SPEED_HZ / 1000);
dev_warn(bus,
"Warning: SPI speed fallback to %u kHz\n",
SPI_DEFAULT_SPEED_HZ / 1000);
plat->max_hz = SPI_DEFAULT_SPEED_HZ;
}
plat->mode = mode;
created = true;
} else if (ret) {
printf("Invalid chip select %d:%d (err=%d)\n", busnum, cs,
ret);
dev_err(bus, "Invalid chip select %d:%d (err=%d)\n", busnum, cs, ret);
return ret;
}
@ -394,13 +399,13 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode,
*busp = bus;
*devp = slave;
debug("%s: bus=%p, slave=%p\n", __func__, bus, *devp);
log_debug("%s: bus=%p, slave=%p\n", __func__, bus, *devp);
return 0;
err:
debug("%s: Error path, created=%d, device '%s'\n", __func__,
created, dev->name);
log_debug("%s: Error path, created=%d, device '%s'\n", __func__,
created, dev->name);
if (created) {
device_remove(dev, DM_REMOVE_NORMAL);
device_unbind(dev);

7
include/configs/cm_fx6.h
View file

@ -150,13 +150,6 @@
/* APBH DMA is required for NAND support */
#endif
/* SPI Flash Configs */
#if defined(CONFIG_SPL_BUILD)
#undef CONFIG_DM_SPI
#undef CONFIG_DM_SPI_FLASH
#undef CONFIG_SPI_FLASH_MTD
#endif
/* Ethernet */
#define CONFIG_FEC_MXC
#define CONFIG_FEC_MXC_PHYADDR 0

6
include/configs/dh_imx6.h
View file

@ -52,12 +52,6 @@
/* SATA Configs */
#define CONFIG_LBA48
/* SPI Flash Configs */
#if defined(CONFIG_SPL_BUILD)
#undef CONFIG_DM_SPI
#undef CONFIG_DM_SPI_FLASH
#endif
/* UART */
#define CONFIG_MXC_UART_BASE UART1_BASE

2
include/spi.h
View file

@ -51,7 +51,7 @@ struct dm_spi_bus {
* struct from a spi_slave, use dev_get_parent_platdata(dev) or
* dev_get_parent_platdata(slave->dev).
*
* This data is immuatable. Each time the device is probed, @max_hz and @mode
* This data is immutable. Each time the device is probed, @max_hz and @mode
* will be copied to struct spi_slave.
*
* @cs: Chip select number (0..n-1)