Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-24 13:43:28 +00:00
Code Issues Projects Releases Packages Wiki Activity

Merge branch 'next'

Browse source 
Bring in the assorted changes that have been staged in the 'next' branch
prior to release.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2020-10-05 13:05:46 -04:00
commit b7e7831e5d
864 changed files with 47418 additions and 11313 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
Kconfig
View file

@ -659,12 +659,11 @@ config SPL_FIT_SOURCE
config USE_SPL_FIT_GENERATOR
bool "Use a script to generate the .its script"
default y if SPL_FIT
default y if SPL_FIT && !ARCH_SUNXI
config SPL_FIT_GENERATOR
string ".its file generator script for U-Boot FIT image"
depends on USE_SPL_FIT_GENERATOR
default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI
default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && ARCH_ROCKCHIP
default "arch/arm/mach-zynqmp/mkimage_fit_atf.sh" if SPL_LOAD_FIT && ARCH_ZYNQMP
default "arch/riscv/lib/mkimage_fit_opensbi.sh" if SPL_LOAD_FIT && RISCV

12
MAINTAINERS
View file

@ -237,6 +237,10 @@ M: Luka Kovacic <luka.kovacic@sartura.hr>
M: Luka Perkov <luka.perkov@sartura.hr>
S: Maintained
F: arch/arm/mach-ipq40xx/
F: include/dt-bindings/clock/qcom,ipq4019-gcc.h
F: include/dt-bindings/reset/qcom,ipq4019-reset.h
F: drivers/reset/reset-ipq4019.c
F: drivers/phy/phy-qcom-ipq4019-usb.c
ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
M: Stefan Roese <sr@denx.de>
@ -291,7 +295,9 @@ S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-atmel.git
F: arch/arm/mach-at91/
F: board/atmel/
F: drivers/cpu/at91_cpu.c
F: drivers/misc/microchip_flexcom.c
F: drivers/timer/mchp-pit64b-timer.c
ARM NEXELL S5P4418
M: Stefan Bosch <stefan_b@posteo.net>
@ -599,6 +605,8 @@ F: tools/binman/
BTRFS
M: Marek Behun <marek.behun@nic.cz>
R: Qu Wenruo <wqu@suse.com>
L: linux-btrfs@vger.kernel.org
S: Maintained
F: cmd/btrfs.c
F: fs/btrfs/
@ -1005,6 +1013,10 @@ F: arch/arm/dts/ns3-board.dts
F: arch/arm/dts/ns3.dtsi
F: arch/arm/cpu/armv8/bcmns3
F: arch/arm/include/asm/arch-bcmns3/
F: cmd/broadcom/Makefile
F: cmd/broadcom/chimp_boot.c
F: cmd/broadcom/nitro_image_load.c
F: cmd/broadcom/chimp_handshake.c
TDA19988 HDMI ENCODER
M: Liviu Dudau <liviu.dudau@foss.arm.com>

23
Makefile
View file

@ -923,11 +923,6 @@ INPUTS-$(CONFIG_REMAKE_ELF) += u-boot.elf
INPUTS-$(CONFIG_EFI_APP) += u-boot-app.efi
INPUTS-$(CONFIG_EFI_STUB) += u-boot-payload.efi
# Build a combined spl + u-boot image for sunxi
ifeq ($(CONFIG_ARCH_SUNXI)$(CONFIG_ARM64)$(CONFIG_SPL),yyy)
INPUTS-y += u-boot-sunxi-with-spl.bin
endif
# Generate this input file for binman
ifeq ($(CONFIG_SPL),)
INPUTS-$(CONFIG_ARCH_MEDIATEK) += u-boot-mtk.bin
@ -1024,13 +1019,9 @@ PHONY += inputs
inputs: $(INPUTS-y)
all: .binman_stamp inputs
# Hack for sunxi which doesn't have a proper binman definition for
# 64-bit boards
ifneq ($(CONFIG_ARCH_SUNXI)$(CONFIG_ARM64),yy)
ifeq ($(CONFIG_BINMAN),y)
$(call if_changed,binman)
endif
endif
# Timestamp file to make sure that binman always runs
.binman_stamp: FORCE
@ -1330,13 +1321,16 @@ u-boot.ldr: u-boot
# binman
# ---------------------------------------------------------------------------
# Use 'make BINMAN_DEBUG=1' to enable debugging
default_dt := $(if $(DEVICE_TREE),$(DEVICE_TREE),$(CONFIG_DEFAULT_DEVICE_TREE))
quiet_cmd_binman = BINMAN $@
cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
--toolpath $(objtree)/tools \
$(if $(BINMAN_VERBOSE),-v$(BINMAN_VERBOSE)) \
build -u -d u-boot.dtb -O . \
$(if $(BUILD_ROM),,-m --allow-missing) \
build -u -d u-boot.dtb -O . -m --allow-missing \
-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
-I arch/$(ARCH)/dts -a of-list=$(CONFIG_OF_LIST) \
-a atf-bl31-path=${BL31} \
-a default-dt=$(default_dt) \
$(BINMAN_$(@F))
OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex
@ -1626,13 +1620,6 @@ u-boot-x86-reset16.bin: u-boot FORCE
endif # CONFIG_X86
ifneq ($(CONFIG_ARCH_SUNXI),)
ifeq ($(CONFIG_ARM64),y)
u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.itb FORCE
$(call if_changed,cat)
endif
endif
OBJCOPYFLAGS_u-boot-app.efi := $(OBJCOPYFLAGS_EFI)
u-boot-app.efi: u-boot FORCE
$(call if_changed,zobjcopy)

4
README
View file

@ -3425,6 +3425,10 @@ List of environment variables (most likely not complete):
mempos - Index position of the last match found by the 'ms' command,
in units of the size (.b, .w, .l) of the search
zbootbase - (x86 only) Base address of the bzImage 'setup' block
zbootaddr - (x86 only) Address of the loaded bzImage, typically
BZIMAGE_LOAD_ADDR which is 0x100000
The following image location variables contain the location of images
used in booting. The "Image" column gives the role of the image and is

3
api/api_platform-mips.c
View file

@ -24,8 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
int platform_sys_info(struct sys_info *si)
{
platform_set_mr(si, gd->bd->bi_memstart,
gd->bd->bi_memsize, MR_ATTR_DRAM);
platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
return 1;
}

2
api/api_platform-powerpc.c
View file

@ -42,7 +42,7 @@ int platform_sys_info(struct sys_info *si)
si->bar = 0;
#endif
platform_set_mr(si, gd->bd->bi_memstart, gd->bd->bi_memsize, MR_ATTR_DRAM);
platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH);
platform_set_mr(si, gd->bd->bi_sramstart, gd->bd->bi_sramsize, MR_ATTR_SRAM);

16
arch/arm/Kconfig
View file

@ -16,8 +16,8 @@ config POSITION_INDEPENDENT
help
U-Boot expects to be linked to a specific hard-coded address, and to
be loaded to and run from that address. This option lifts that
restriction, thus allowing the code to be loaded to and executed
from almost any address. This logic relies on the relocation
restriction, thus allowing the code to be loaded to and executed from
almost any 4K aligned address. This logic relies on the relocation
information that is embedded in the binary to support U-Boot
relocating itself to the top-of-RAM later during execution.
@ -767,8 +767,11 @@ config ARCH_IPQ40XX
select DM
select DM_GPIO
select DM_SERIAL
select DM_RESET
select MSM_SMEM
select PINCTRL
select CLK
select SMEM
select OF_CONTROL
imply CMD_DM
@ -940,9 +943,9 @@ config ARCH_QEMU
config ARCH_RMOBILE
bool "Renesas ARM SoCs"
select BOARD_EARLY_INIT_F if !RZA1
select DM
select DM_SERIAL
imply BOARD_EARLY_INIT_F
imply CMD_DM
imply FAT_WRITE
imply SYS_THUMB_BUILD
@ -1152,7 +1155,8 @@ config ARCH_ZYNQMP
select OF_CONTROL
select SPL_BOARD_INIT if SPL
select SPL_CLK if SPL
select SPL_DM_SPI if SPI
select SPL_DM if SPL
select SPL_DM_SPI if SPI && SPL_DM
select SPL_DM_SPI_FLASH if SPL_DM_SPI
select SPL_DM_MAILBOX if SPL
select SPL_FIRMWARE if SPL
@ -1997,10 +2001,6 @@ source "board/tcl/sl50/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/variscite/dart_6ul/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/xilinx/Kconfig"
source "board/xilinx/zynq/Kconfig"
source "board/xilinx/zynqmp/Kconfig"
source "board/xilinx/versal/Kconfig"
source "board/phytium/durian/Kconfig"
source "board/xen/xenguest_arm64/Kconfig"

2
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View file

@ -56,7 +56,7 @@ int ls_gic_rd_tables_init(void *blob)
lpi_base.start = addr;
lpi_base.end = addr + size - 1;
ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL);
ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL, false);
if (ret) {
debug("%s: failed to add reserved memory\n", __func__);
return ret;

23
arch/arm/cpu/armv8/start.S
View file

@ -59,6 +59,23 @@ reset:
save_boot_params_ret:
#if CONFIG_POSITION_INDEPENDENT
/* Verify that we're 4K aligned. */
adr x0, _start
ands x0, x0, #0xfff
b.eq 1f
0:
/*
* FATAL, can't continue.
* U-Boot needs to be loaded at a 4K aligned address.
*
* We use ADRP and ADD to load some symbol addresses during startup.
* The ADD uses an absolute (non pc-relative) lo12 relocation
* thus requiring 4K alignment.
*/
wfi
b 0b
1:
/*
* Fix .rela.dyn relocations. This allows U-Boot to be loaded to and
* executed at a different address than it was linked at.
@ -67,8 +84,10 @@ pie_fixup:
adr x0, _start /* x0 <- Runtime value of _start */
ldr x1, _TEXT_BASE /* x1 <- Linked value of _start */
sub x9, x0, x1 /* x9 <- Run-vs-link offset */
adr x2, __rel_dyn_start /* x2 <- Runtime &__rel_dyn_start */
adr x3, __rel_dyn_end /* x3 <- Runtime &__rel_dyn_end */
adrp x2, __rel_dyn_start /* x2 <- Runtime &__rel_dyn_start */
add x2, x2, #:lo12:__rel_dyn_start
adrp x3, __rel_dyn_end /* x3 <- Runtime &__rel_dyn_end */
add x3, x3, #:lo12:__rel_dyn_end
pie_fix_loop:
ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */
ldr x4, [x2], #8 /* x4 <- addend */

2
arch/arm/dts/Makefile
View file

@ -938,7 +938,7 @@ dtb-$(CONFIG_ARCH_BCM6858) += \
dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb
dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb
dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb

50
arch/arm/dts/am335x-icev2.dts
View file

@ -436,3 +436,53 @@
reg = <3>;
};
};
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins_default>;
sn65hvs882@1 {
compatible = "pisosr-gpio";
gpio-controller;
#gpio-cells = <2>;
load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
reg = <1>;
spi-max-frequency = <1000000>;
spi-cpol;
};
spi_nor: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "winbond,w25q64", "jedec,spi-nor";
spi-max-frequency = <80000000>;
m25p,fast-read;
reg = <0>;
partition@0 {
label = "u-boot-spl";
reg = <0x0 0x80000>;
read-only;
};
partition@1 {
label = "u-boot";
reg = <0x80000 0x100000>;
read-only;
};
partition@2 {
label = "u-boot-env";
reg = <0x180000 0x20000>;
read-only;
};
partition@3 {
label = "misc";
reg = <0x1A0000 0x660000>;
};
};
};

23
arch/arm/dts/ast2500-u-boot.dtsi
View file

@ -1,4 +1,5 @@
#include <dt-bindings/clock/ast2500-scu.h>
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/aspeed-clock.h>
#include <dt-bindings/reset/ast2500-reset.h>
#include "ast2500.dtsi"
@ -25,7 +26,7 @@
reg = <0x1e6e0000 0x174
0x1e6e0200 0x1d4 >;
#reset-cells = <1>;
clocks = <&scu PLL_MPLL>;
clocks = <&scu ASPEED_CLK_MPLL>;
resets = <&rst AST_RESET_SDRAM>;
};
@ -39,7 +40,7 @@
compatible = "aspeed,ast2500-sdhci";
reg = <0x1e740100>;
#reset-cells = <1>;
clocks = <&scu BCLK_SDCLK>;
clocks = <&scu ASPEED_CLK_SDIO>;
resets = <&rst AST_RESET_SDIO>;
};
@ -47,7 +48,7 @@
compatible = "aspeed,ast2500-sdhci";
reg = <0x1e740200>;
#reset-cells = <1>;
clocks = <&scu BCLK_SDCLK>;
clocks = <&scu ASPEED_CLK_SDIO>;
resets = <&rst AST_RESET_SDIO>;
};
};
@ -56,23 +57,23 @@
};
&uart1 {
clocks = <&scu PCLK_UART1>;
clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
};
&uart2 {
clocks = <&scu PCLK_UART2>;
clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
};
&uart3 {
clocks = <&scu PCLK_UART3>;
clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
};
&uart4 {
clocks = <&scu PCLK_UART4>;
clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
};
&uart5 {
clocks = <&scu PCLK_UART5>;
clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
};
&timer {
@ -80,9 +81,9 @@
};
&mac0 {
clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>;
clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
};
&mac1 {
clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>;
clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
};

28
arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
View file

@ -131,3 +131,31 @@
dr_mode = "peripheral";
u-boot,dm-spl;
};
&wkup_gpio_pins_default {
u-boot,dm-spl;
};
&wkup_gpio0 {
u-boot,dm-spl;
};
&mcu_fss0_hpb0_pins_default {
u-boot,dm-spl;
};
&fss {
u-boot,dm-spl;
};
&hbmc {
u-boot,dm-spl;
flash@0,0 {
u-boot,dm-spl;
};
};
&hbmc_mux {
u-boot,dm-spl;
};

7
arch/arm/dts/k3-j7200-common-proc-board.dts
View file

@ -13,6 +13,13 @@
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
};
aliases {
remoteproc0 = &mcu_r5fss0_core0;
remoteproc1 = &mcu_r5fss0_core1;
remoteproc2 = &main_r5fss0_core0;
remoteproc3 = &main_r5fss0_core1;
};
};
&wkup_pmx0 {

40
arch/arm/dts/k3-j7200-main.dtsi
View file

@ -340,4 +340,44 @@
dr_mode = "otg";
};
};
main_r5fss0: r5fss@5c00000 {
compatible = "ti,j7200-r5fss";
lockstep-mode = <0>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
<0x5d00000 0x00 0x5d00000 0x20000>;
power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
main_r5fss0_core0: r5f@5c00000 {
compatible = "ti,j7200-r5f";
reg = <0x5c00000 0x00010000>,
<0x5c10000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <245>;
ti,sci-proc-ids = <0x06 0xFF>;
resets = <&k3_reset 245 1>;
firmware-name = "j7200-main-r5f0_0-fw";
atcm-enable = <1>;
btcm-enable = <1>;
loczrama = <1>;
};
main_r5fss0_core1: r5f@5d00000 {
compatible = "ti,j7200-r5f";
reg = <0x5d00000 0x00008000>,
<0x5d10000 0x00008000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <246>;
ti,sci-proc-ids = <0x07 0xFF>;
resets = <&k3_reset 246 1>;
firmware-name = "j7200-main-r5f0_1-fw";
atcm-enable = <1>;
btcm-enable = <1>;
loczrama = <1>;
};
};
};

40
arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
View file

@ -269,4 +269,44 @@
ti,cpts-periodic-outputs = <2>;
};
};
mcu_r5fss0: r5fss@41000000 {
compatible = "ti,j7200-r5fss";
lockstep-mode = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x41000000 0x00 0x41000000 0x20000>,
<0x41400000 0x00 0x41400000 0x20000>;
power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
mcu_r5fss0_core0: r5f@41000000 {
compatible = "ti,j7200-r5f";
reg = <0x41000000 0x00010000>,
<0x41010000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <250>;
ti,sci-proc-ids = <0x01 0xff>;
resets = <&k3_reset 250 1>;
firmware-name = "j7200-mcu-r5f0_0-fw";
atcm-enable = <1>;
btcm-enable = <1>;
loczrama = <1>;
};
mcu_r5fss0_core1: r5f@41400000 {
compatible = "ti,j7200-r5f";
reg = <0x41400000 0x00008000>,
<0x41410000 0x00008000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <251>;
ti,sci-proc-ids = <0x02 0xff>;
resets = <&k3_reset 251 1>;
firmware-name = "j7200-mcu-r5f0_1-fw";
atcm-enable = <1>;
btcm-enable = <1>;
loczrama = <1>;
};
};
};

46
arch/arm/dts/k3-j7200-r5-common-proc-board.dts
View file

@ -18,6 +18,12 @@
chosen {
stdout-path = &main_uart0;
tick-timer = &timer1;
firmware-loader = &fs_loader0;
};
fs_loader0: fs_loader@0 {
u-boot,dm-pre-reloc;
compatible = "u-boot,fs-loader";
};
a72_0: a72@0 {
@ -107,6 +113,31 @@
J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
>;
};
mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
>;
};
wkup_gpio_pins_default: wkup-gpio-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
>;
};
};
&main_pmx0 {
@ -214,4 +245,19 @@
maximum-speed = "high-speed";
};
&hbmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
reg = <0x0 0x47040000 0x0 0x100>,
<0x0 0x50000000 0x0 0x8000000>;
ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */
<0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */
flash@0,0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0x0 0x0 0x4000000>;
};
};
#include "k3-j7200-common-proc-board-u-boot.dtsi"

2
arch/arm/dts/k3-j721e-main.dtsi
View file

@ -302,7 +302,7 @@
main_r5fss1: r5fss@5e00000 {
compatible = "ti,j721e-r5fss";
lockstep-mode = <1>;
lockstep-mode = <0>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5e00000 0x00 0x5e00000 0x20000>,

93
arch/arm/dts/qcom-ipq4019.dtsi
View file

@ -10,6 +10,8 @@
#include "skeleton.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
#include <dt-bindings/clock/qcom,ipq4019-gcc.h>
#include <dt-bindings/reset/qcom,ipq4019-reset.h>
/ {
#address-cells = <1>;
@ -38,6 +40,11 @@
};
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
@ -52,6 +59,14 @@
u-boot,dm-pre-reloc;
};
reset: gcc-reset@1800000 {
compatible = "qcom,gcc-reset-ipq4019";
reg = <0x1800000 0x60000>;
#clock-cells = <1>;
#reset-cells = <1>;
u-boot,dm-pre-reloc;
};
pinctrl: qcom,tlmm@1000000 {
compatible = "qcom,tlmm-ipq4019";
reg = <0x1000000 0x300000>;
@ -61,7 +76,7 @@
blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
clock = <&gcc 26>;
clock = <&gcc GCC_BLSP1_UART1_APPS_CLK>;
bit-rate = <0xFF>;
status = "disabled";
u-boot,dm-pre-reloc;
@ -75,5 +90,81 @@
gpio-bank-name="soc";
#gpio-cells = <2>;
};
usb3_ss_phy: ssphy@9a000 {
compatible = "qcom,usb-ss-ipq4019-phy";
#phy-cells = <0>;
reg = <0x9a000 0x800>;
reg-names = "phy_base";
resets = <&reset USB3_UNIPHY_PHY_ARES>;
reset-names = "por_rst";
status = "disabled";
};
usb3_hs_phy: hsphy@a6000 {
compatible = "qcom,usb-hs-ipq4019-phy";
#phy-cells = <0>;
reg = <0xa6000 0x40>;
reg-names = "phy_base";
resets = <&reset USB3_HSPHY_POR_ARES>, <&reset USB3_HSPHY_S_ARES>;
reset-names = "por_rst", "srif_rst";
status = "disabled";
};
usb3: usb3@8af8800 {
compatible = "qcom,dwc3";
reg = <0x8af8800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&gcc GCC_USB3_MASTER_CLK>,
<&gcc GCC_USB3_SLEEP_CLK>,
<&gcc GCC_USB3_MOCK_UTMI_CLK>;
clock-names = "master", "sleep", "mock_utmi";
ranges;
status = "disabled";
dwc3@8a00000 {
compatible = "snps,dwc3";
reg = <0x8a00000 0xf8000>;
phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
phy-names = "usb2-phy", "usb3-phy";
dr_mode = "host";
maximum-speed = "super-speed";
snps,dis_u2_susphy_quirk;
};
};
usb2_hs_phy: hsphy@a8000 {
compatible = "qcom,usb-hs-ipq4019-phy";
#phy-cells = <0>;
reg = <0xa8000 0x40>;
reg-names = "phy_base";
resets = <&reset USB2_HSPHY_POR_ARES>, <&reset USB2_HSPHY_S_ARES>;
reset-names = "por_rst", "srif_rst";
status = "disabled";
};
usb2: usb2@60f8800 {
compatible = "qcom,dwc3";
reg = <0x60f8800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&gcc GCC_USB2_MASTER_CLK>,
<&gcc GCC_USB2_SLEEP_CLK>,
<&gcc GCC_USB2_MOCK_UTMI_CLK>;
clock-names = "master", "sleep", "mock_utmi";
ranges;
status = "disabled";
dwc3@6000000 {
compatible = "snps,dwc3";
reg = <0x6000000 0xf8000>;
phys = <&usb2_hs_phy>;
phy-names = "usb2-phy";
dr_mode = "host";
maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk;
};
};
};
};

10
arch/arm/dts/r8a774a1.dtsi
View file

@ -10,6 +10,8 @@
#include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
#include <dt-bindings/power/r8a774a1-sysc.h>
#define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4
/ {
compatible = "renesas,r8a774a1";
#address-cells = <2>;
@ -2250,7 +2252,7 @@
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
@ -2262,7 +2264,7 @@
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
@ -2274,7 +2276,7 @@
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
@ -2286,7 +2288,7 @@
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;

2630
arch/arm/dts/r8a774b1.dtsi Normal file
View file

File diff suppressed because it is too large Load diff

1664
arch/arm/dts/r8a774e1.dtsi Normal file
View file

File diff suppressed because it is too large Load diff

5
arch/arm/dts/r8a77950-salvator-x-u-boot.dts
View file

@ -8,6 +8,11 @@
#include "r8a77950-salvator-x.dts"
#include "r8a77950-u-boot.dtsi"
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "okay";
};
&sdhi0 {
sd-uhs-sdr12;
sd-uhs-sdr25;

5
arch/arm/dts/r8a77950-ulcb-u-boot.dts
View file

@ -19,6 +19,11 @@
};
};
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "okay";
};
&sdhi0 {
sd-uhs-sdr12;
sd-uhs-sdr25;

5
arch/arm/dts/r8a77960-salvator-x-u-boot.dts
View file

@ -8,6 +8,11 @@
#include "r8a77960-salvator-x.dts"
#include "r8a77960-u-boot.dtsi"
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "okay";
};
&sdhi0 {
sd-uhs-sdr12;
sd-uhs-sdr25;

5
arch/arm/dts/r8a77960-ulcb-u-boot.dts
View file

@ -19,6 +19,11 @@
};
};
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "okay";
};
&sdhi0 {
sd-uhs-sdr12;
sd-uhs-sdr25;

5
arch/arm/dts/r8a77965-salvator-x-u-boot.dts
View file

@ -8,6 +8,11 @@
#include "r8a77965-salvator-x.dts"
#include "r8a77965-u-boot.dtsi"
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "okay";
};
&sdhi0 {
sd-uhs-sdr12;
sd-uhs-sdr25;

5
arch/arm/dts/r8a77965-ulcb-u-boot.dts
View file

@ -19,6 +19,11 @@
};
};
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "okay";
};
&sdhi0 {
sd-uhs-sdr12;
sd-uhs-sdr25;

5
arch/arm/dts/r8a77990-ebisu-u-boot.dts
View file

@ -18,6 +18,11 @@
};
};
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "okay";
};
&sdhi0 {
sd-uhs-sdr12;
sd-uhs-sdr25;

5
arch/arm/dts/r8a77995-draak-u-boot.dts
View file

@ -7,3 +7,8 @@
#include "r8a77995-draak.dts"
#include "r8a77995-u-boot.dtsi"
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "okay";
};

924
arch/arm/dts/sama7g5-pinfunc.h Normal file
View file

@ -0,0 +1,924 @@
/* SPDX-License-Identifier: GPL-2.0 */
#define PINMUX_PIN(no, func, ioset) \
(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20))
#define PIN_PA0 0
#define PIN_PA0__GPIO PINMUX_PIN(PIN_PA0, 0, 0)
#define PIN_PA0__SDMMC0_CK PINMUX_PIN(PIN_PA0, 1, 1)
#define PIN_PA0__FLEXCOM0_IO0 PINMUX_PIN(PIN_PA0, 2, 1)
#define PIN_PA0__CANTX3 PINMUX_PIN(PIN_PA0, 3, 1)
#define PIN_PA0__PWML0 PINMUX_PIN(PIN_PA0, 5, 2)
#define PIN_PA1 1
#define PIN_PA1__GPIO PINMUX_PIN(PIN_PA1, 0, 0)
#define PIN_PA1__SDMMC0_CMD PINMUX_PIN(PIN_PA1, 1, 1)
#define PIN_PA1__FLEXCOM0_IO1 PINMUX_PIN(PIN_PA1, 2, 1)
#define PIN_PA1__CANRX3 PINMUX_PIN(PIN_PA1, 3, 1)
#define PIN_PA1__D14 PINMUX_PIN(PIN_PA1, 4, 1)
#define PIN_PA1__PWMH0 PINMUX_PIN(PIN_PA1, 5, 3)
#define PIN_PA2 2
#define PIN_PA2__GPIO PINMUX_PIN(PIN_PA2, 0, 0)
#define PIN_PA2__SDMMC0_RSTN PINMUX_PIN(PIN_PA2, 1, 1)
#define PIN_PA2__FLEXCOM0_IO2 PINMUX_PIN(PIN_PA2, 2, 1)
#define PIN_PA2__PDMC1_CLK PINMUX_PIN(PIN_PA2, 3, 1)
#define PIN_PA2__D15 PINMUX_PIN(PIN_PA2, 4, 1)
#define PIN_PA2__PWMH1 PINMUX_PIN(PIN_PA2, 5, 3)
#define PIN_PA2__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA2, 6, 3)
#define PIN_PA3 3
#define PIN_PA3__GPIO PINMUX_PIN(PIN_PA3, 0, 0)
#define PIN_PA3__SDMMC0_DAT0 PINMUX_PIN(PIN_PA3, 1, 1)
#define PIN_PA3__FLEXCOM0_IO3 PINMUX_PIN(PIN_PA3, 2, 1)
#define PIN_PA3__PDMC1_DS0 PINMUX_PIN(PIN_PA3, 3, 1)
#define PIN_PA3__NWR1_NBS1 PINMUX_PIN(PIN_PA3, 4, 1)
#define PIN_PA3__PWML3 PINMUX_PIN(PIN_PA3, 5, 3)
#define PIN_PA3__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA3, 6, 3)
#define PIN_PA4 4
#define PIN_PA4__GPIO PINMUX_PIN(PIN_PA4, 0, 0)
#define PIN_PA4__SDMMC0_DAT1 PINMUX_PIN(PIN_PA4, 1, 1)
#define PIN_PA4__FLEXCOM0_IO4 PINMUX_PIN(PIN_PA4, 2, 1)
#define PIN_PA4__PDMC1_DS1 PINMUX_PIN(PIN_PA4, 3, 1)
#define PIN_PA4__NCS2 PINMUX_PIN(PIN_PA4, 4, 1)
#define PIN_PA4__PWMH3 PINMUX_PIN(PIN_PA4, 5, 3)
#define PIN_PA4__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA4, 6, 3)
#define PIN_PA5 5
#define PIN_PA5__GPIO PINMUX_PIN(PIN_PA5, 0, 0)
#define PIN_PA5__SDMMC0_DAT2 PINMUX_PIN(PIN_PA5, 1, 1)
#define PIN_PA5__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA5, 2, 1)
#define PIN_PA5__CANTX2 PINMUX_PIN(PIN_PA5, 3, 1)
#define PIN_PA5__A23 PINMUX_PIN(PIN_PA5, 4, 1)
#define PIN_PA5__PWMEXTRG0 PINMUX_PIN(PIN_PA5, 5, 3)
#define PIN_PA5__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA5, 6, 3)
#define PIN_PA6 6
#define PIN_PA6__GPIO PINMUX_PIN(PIN_PA6, 0, 0)
#define PIN_PA6__SDMMC0_DAT3 PINMUX_PIN(PIN_PA6, 1, 1)
#define PIN_PA6__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA6, 2, 1)
#define PIN_PA6__CANRX2 PINMUX_PIN(PIN_PA6, 3, 1)
#define PIN_PA6__A24 PINMUX_PIN(PIN_PA6, 4, 1)
#define PIN_PA6__PWMEXTRG1 PINMUX_PIN(PIN_PA6, 5, 3)
#define PIN_PA6__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA6, 6, 3)
#define PIN_PA7 7
#define PIN_PA7__GPIO PINMUX_PIN(PIN_PA7, 0, 0)
#define PIN_PA7__SDMMC0_DAT4 PINMUX_PIN(PIN_PA7, 1, 1)
#define PIN_PA7__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA7, 2, 1)
#define PIN_PA7__CANTX1 PINMUX_PIN(PIN_PA7, 3, 1)
#define PIN_PA7__NWAIT PINMUX_PIN(PIN_PA7, 4, 1)
#define PIN_PA7__PWMFI0 PINMUX_PIN(PIN_PA7, 5, 3)
#define PIN_PA7__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA7, 6, 3)
#define PIN_PA8 8
#define PIN_PA8__GPIO PINMUX_PIN(PIN_PA8, 0, 0)
#define PIN_PA8__SDMMC0_DAT5 PINMUX_PIN(PIN_PA8, 1, 1)
#define PIN_PA8__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA8, 2, 1)
#define PIN_PA8__CANRX1 PINMUX_PIN(PIN_PA8, 3, 1)
#define PIN_PA8__NCS0 PINMUX_PIN(PIN_PA8, 4, 1)
#define PIN_PA8__PWMIF1 PINMUX_PIN(PIN_PA8, 5, 3)
#define PIN_PA8__FLEXCOM4_IO0 PINMUX_PIN(PIN_PA8, 6, 3)
#define PIN_PA9 9
#define PIN_PA9__GPIO PINMUX_PIN(PIN_PA9, 0, 0)
#define PIN_PA9__SDMMC0_DAT6 PINMUX_PIN(PIN_PA9, 1, 1)
#define PIN_PA9__FLEXCOM2_IO2 PINMUX_PIN(PIN_PA9, 2, 1)
#define PIN_PA9__CANTX0 PINMUX_PIN(PIN_PA9, 3, 1)
#define PIN_PA9__SMCK PINMUX_PIN(PIN_PA9, 4, 1)
#define PIN_PA9__SPDIF_RX PINMUX_PIN(PIN_PA9, 5, 1)
#define PIN_PA9__FLEXCOM4_IO1 PINMUX_PIN(PIN_PA9, 6, 3)
#define PIN_PA10 10
#define PIN_PA10__GPIO PINMUX_PIN(PIN_PA10, 0, 0)
#define PIN_PA10__SDMMC0_DAT7 PINMUX_PIN(PIN_PA10, 1, 1)
#define PIN_PA10__FLEXCOM2_IO3 PINMUX_PIN(PIN_PA10, 2, 1)
#define PIN_PA10__CANRX0 PINMUX_PIN(PIN_PA10, 3, 1)
#define PIN_PA10__NCS1 PINMUX_PIN(PIN_PA10, 4, 1)
#define PIN_PA10__SPDIF_TX PINMUX_PIN(PIN_PA10, 5, 1)
#define PIN_PA10__FLEXCOM5_IO0 PINMUX_PIN(PIN_PA10, 6, 3)
#define PIN_PA11 11
#define PIN_PA11__GPIO PINMUX_PIN(PIN_PA11, 0, 0)
#define PIN_PA11__SDMMC0_DS PINMUX_PIN(PIN_PA11, 1, 1)
#define PIN_PA11__FLEXCOM2_IO4 PINMUX_PIN(PIN_PA11, 2, 1)
#define PIN_PA11__A0_NBS0 PINMUX_PIN(PIN_PA11, 4, 1)
#define PIN_PA11__TIOA0 PINMUX_PIN(PIN_PA11, 5, 1)
#define PIN_PA11__FLEXCOM5_IO1 PINMUX_PIN(PIN_PA11, 6, 3)
#define PIN_PA12 12
#define PIN_PA12__GPIO PINMUX_PIN(PIN_PA12, 0, 0)
#define PIN_PA12__SDMMC0_WP PINMUX_PIN(PIN_PA12, 1, 1)
#define PIN_PA12__FLEXCOM1_IO3 PINMUX_PIN(PIN_PA12, 2, 1)
#define PIN_PA12__FLEXCOM3_IO5 PINMUX_PIN(PIN_PA12, 4, 1)
#define PIN_PA12__PWML2 PINMUX_PIN(PIN_PA12, 5, 3)
#define PIN_PA12__FLEXCOM6_IO0 PINMUX_PIN(PIN_PA12, 6, 3)
#define PIN_PA13 13
#define PIN_PA13__GPIO PINMUX_PIN(PIN_PA13, 0, 0)
#define PIN_PA13__SDMMC0_1V8SEL PINMUX_PIN(PIN_PA13, 1, 1)
#define PIN_PA13__FLEXCOM1_IO2 PINMUX_PIN(PIN_PA13, 2, 1)
#define PIN_PA13__FLEXCOM3_IO6 PINMUX_PIN(PIN_PA13, 4, 1)
#define PIN_PA13__PWMH2 PINMUX_PIN(PIN_PA13, 5, 3)
#define PIN_PA13__FLEXCOM6_IO1 PINMUX_PIN(PIN_PA13, 6, 3)
#define PIN_PA14 14
#define PIN_PA14__GPIO PINMUX_PIN(PIN_PA14, 0, 0)
#define PIN_PA14__SDMMC0_CD PINMUX_PIN(PIN_PA14, 1, 1)
#define PIN_PA14__FLEXCOM1_IO4 PINMUX_PIN(PIN_PA14, 2, 1)
#define PIN_PA14__A25 PINMUX_PIN(PIN_PA14, 4, 1)
#define PIN_PA14__PWML1 PINMUX_PIN(PIN_PA14, 5, 3)
#define PIN_PA15 15
#define PIN_PA15__GPIO PINMUX_PIN(PIN_PA15, 0, 0)
#define PIN_PA15__G0_TXEN PINMUX_PIN(PIN_PA15, 1, 1)
#define PIN_PA15__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA15, 2, 1)
#define PIN_PA15__ISC_MCK PINMUX_PIN(PIN_PA15, 3, 1)
#define PIN_PA15__A1 PINMUX_PIN(PIN_PA15, 4, 1)
#define PIN_PA15__TIOB0 PINMUX_PIN(PIN_PA15, 5, 1)
#define PIN_PA16 16
#define PIN_PA16__GPIO PINMUX_PIN(PIN_PA16, 0, 0)
#define PIN_PA16__G0_TX0 PINMUX_PIN(PIN_PA16, 1, 1)
#define PIN_PA16__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA16, 2, 1)
#define PIN_PA16__ISC_D0 PINMUX_PIN(PIN_PA16, 3, 1)
#define PIN_PA16__A2 PINMUX_PIN(PIN_PA16, 4, 1)
#define PIN_PA16__TCLK0 PINMUX_PIN(PIN_PA16, 5, 1)
#define PIN_PA17 17
#define PIN_PA17__GPIO PINMUX_PIN(PIN_PA17, 0, 0)
#define PIN_PA17__G0_TX1 PINMUX_PIN(PIN_PA17, 1, 1)
#define PIN_PA17__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA17, 2, 1)
#define PIN_PA17__ISC_D1 PINMUX_PIN(PIN_PA17, 3, 1)
#define PIN_PA17__A3 PINMUX_PIN(PIN_PA17, 4, 1)
#define PIN_PA17__TIOA1 PINMUX_PIN(PIN_PA17, 5, 1)
#define PIN_PA18 18
#define PIN_PA18__GPIO PINMUX_PIN(PIN_PA18, 0, 0)
#define PIN_PA18__G0_RXDV PINMUX_PIN(PIN_PA18, 1, 1)
#define PIN_PA18__FLEXCOM3_IO3 PINMUX_PIN(PIN_PA18, 2, 1)
#define PIN_PA18__ISC_D2 PINMUX_PIN(PIN_PA18, 3, 1)
#define PIN_PA18__A4 PINMUX_PIN(PIN_PA18, 4, 1)
#define PIN_PA18__TIOB1 PINMUX_PIN(PIN_PA18, 5, 1)
#define PIN_PA19 19
#define PIN_PA19__GPIO PINMUX_PIN(PIN_PA19, 0, 0)
#define PIN_PA19__G0_RX0 PINMUX_PIN(PIN_PA19, 1, 1)
#define PIN_PA19__FLEXCOM3_IO4 PINMUX_PIN(PIN_PA19, 2, 1)
#define PIN_PA19__ISC_D3 PINMUX_PIN(PIN_PA19, 3, 1)
#define PIN_PA19__A5 PINMUX_PIN(PIN_PA19, 4, 1)
#define PIN_PA19__TCLK1 PINMUX_PIN(PIN_PA19, 5, 1)
#define PIN_PA20 20
#define PIN_PA20__GPIO PINMUX_PIN(PIN_PA20, 0, 0)
#define PIN_PA20__G0_RX1 PINMUX_PIN(PIN_PA20, 1, 1)
#define PIN_PA20__FLEXCOM4_IO0 PINMUX_PIN(PIN_PA20, 2, 1)
#define PIN_PA20__ISC_D4 PINMUX_PIN(PIN_PA20, 3, 1)
#define PIN_PA20__A6 PINMUX_PIN(PIN_PA20, 4, 1)
#define PIN_PA20__TIOA2 PINMUX_PIN(PIN_PA20, 5, 1)
#define PIN_PA21 21
#define PIN_PA21__GPIO PINMUX_PIN(PIN_PA21, 0, 0)
#define PIN_PA21__G0_RXER PINMUX_PIN(PIN_PA21, 1, 1)
#define PIN_PA21__FLEXCOM4_IO1 PINMUX_PIN(PIN_PA21, 2, 1)
#define PIN_PA21__ISC_D5 PINMUX_PIN(PIN_PA21, 3, 1)
#define PIN_PA21__A7 PINMUX_PIN(PIN_PA21, 4, 1)
#define PIN_PA21__TIOB2 PINMUX_PIN(PIN_PA21, 5, 1)
#define PIN_PA22 22
#define PIN_PA22__GPIO PINMUX_PIN(PIN_PA22, 0, 0)
#define PIN_PA22__G0_MDC PINMUX_PIN(PIN_PA22, 1, 1)
#define PIN_PA22__FLEXCOM4_IO2 PINMUX_PIN(PIN_PA22, 2, 1)
#define PIN_PA22__ISC_D6 PINMUX_PIN(PIN_PA22, 3, 1)
#define PIN_PA22__A8 PINMUX_PIN(PIN_PA22, 4, 1)
#define PIN_PA22__TCLK2 PINMUX_PIN(PIN_PA22, 5, 1)
#define PIN_PA23 23
#define PIN_PA23__GPIO PINMUX_PIN(PIN_PA23, 0, 0)
#define PIN_PA23__G0_MDIO PINMUX_PIN(PIN_PA23, 1, 1)
#define PIN_PA23__FLEXCOM4_IO3 PINMUX_PIN(PIN_PA23, 2, 1)
#define PIN_PA23__ISC_D7 PINMUX_PIN(PIN_PA23, 3, 1)
#define PIN_PA23__A9 PINMUX_PIN(PIN_PA23, 4, 1)
#define PIN_PA24 24
#define PIN_PA24__GPIO PINMUX_PIN(PIN_PA24, 0, 0)
#define PIN_PA24__G0_TXCK PINMUX_PIN(PIN_PA24, 1, 1)
#define PIN_PA24__FLEXCOM4_IO4 PINMUX_PIN(PIN_PA24, 2, 1)
#define PIN_PA24__ISC_HSYNC PINMUX_PIN(PIN_PA24, 3, 1)
#define PIN_PA24__A10 PINMUX_PIN(PIN_PA24, 4, 1)
#define PIN_PA24__FLEXCOM0_IO5 PINMUX_PIN(PIN_PA24, 5, 1)
#define PIN_PA25 25
#define PIN_PA25__GPIO PINMUX_PIN(PIN_PA25, 0, 0)
#define PIN_PA25__G0_125CK PINMUX_PIN(PIN_PA25, 1, 1)
#define PIN_PA25__FLEXCOM5_IO4 PINMUX_PIN(PIN_PA25, 2, 1)
#define PIN_PA25__ISC_VSYNC PINMUX_PIN(PIN_PA25, 3, 1)
#define PIN_PA25__A11 PINMUX_PIN(PIN_PA25, 4, 1)
#define PIN_PA25__FLEXCOM0_IO6 PINMUX_PIN(PIN_PA25, 5, 1)
#define PIN_PA25__FLEXCOM7_IO0 PINMUX_PIN(PIN_PA25, 6, 3)
#define PIN_PA26 26
#define PIN_PA26__GPIO PINMUX_PIN(PIN_PA26, 0, 0)
#define PIN_PA26__G0_TX2 PINMUX_PIN(PIN_PA26, 1, 1)
#define PIN_PA26__FLEXCOM5_IO2 PINMUX_PIN(PIN_PA26, 2, 1)
#define PIN_PA26__ISC_FIELD PINMUX_PIN(PIN_PA26, 3, 1)
#define PIN_PA26__A12 PINMUX_PIN(PIN_PA26, 4, 1)
#define PIN_PA26__TF0 PINMUX_PIN(PIN_PA26, 5, 1)
#define PIN_PA26__FLEXCOM7_IO1 PINMUX_PIN(PIN_PA26, 6, 3)
#define PIN_PA27 27
#define PIN_PA27__GPIO PINMUX_PIN(PIN_PA27, 0, 0)
#define PIN_PA27__G0_TX3 PINMUX_PIN(PIN_PA27, 1, 1)
#define PIN_PA27__FLEXCOM5_IO3 PINMUX_PIN(PIN_PA27, 2, 1)
#define PIN_PA27__ISC_PCK PINMUX_PIN(PIN_PA27, 3, 1)
#define PIN_PA27__A13 PINMUX_PIN(PIN_PA27, 4, 1)
#define PIN_PA27__TK0 PINMUX_PIN(PIN_PA27, 5, 1)
#define PIN_PA27__FLEXCOM8_IO0 PINMUX_PIN(PIN_PA27, 6, 3)
#define PIN_PA28 28
#define PIN_PA28__GPIO PINMUX_PIN(PIN_PA28, 0, 0)
#define PIN_PA28__G0_RX2 PINMUX_PIN(PIN_PA28, 1, 1)
#define PIN_PA28__FLEXCOM5_IO0 PINMUX_PIN(PIN_PA28, 2, 1)
#define PIN_PA28__ISC_D8 PINMUX_PIN(PIN_PA28, 3, 1)
#define PIN_PA28__A14 PINMUX_PIN(PIN_PA28, 4, 1)
#define PIN_PA28__RD0 PINMUX_PIN(PIN_PA28, 5, 1)
#define PIN_PA28__FLEXCOM8_IO1 PINMUX_PIN(PIN_PA28, 6, 3)
#define PIN_PA29 29
#define PIN_PA29__GPIO PINMUX_PIN(PIN_PA29, 0, 0)
#define PIN_PA29__G0_RX3 PINMUX_PIN(PIN_PA29, 1, 1)
#define PIN_PA29__FLEXCOM5_IO1 PINMUX_PIN(PIN_PA29, 2, 1)
#define PIN_PA29__ISC_D9 PINMUX_PIN(PIN_PA29, 3, 1)
#define PIN_PA29__A15 PINMUX_PIN(PIN_PA29, 4, 1)
#define PIN_PA29__RF0 PINMUX_PIN(PIN_PA29, 5, 1)
#define PIN_PA29__FLEXCOM9_IO0 PINMUX_PIN(PIN_PA29, 6, 3)
#define PIN_PA30 30
#define PIN_PA30__GPIO PINMUX_PIN(PIN_PA30, 0, 0)
#define PIN_PA30__G0_RXCK PINMUX_PIN(PIN_PA30, 1, 1)
#define PIN_PA30__FLEXCOM6_IO4 PINMUX_PIN(PIN_PA30, 2, 1)
#define PIN_PA30__ISC_D10 PINMUX_PIN(PIN_PA30, 3, 1)
#define PIN_PA30__A16 PINMUX_PIN(PIN_PA30, 4, 1)
#define PIN_PA30__RK0 PINMUX_PIN(PIN_PA30, 5, 1)
#define PIN_PA30__FLEXCOM9_IO1 PINMUX_PIN(PIN_PA30, 6, 3)
#define PIN_PA31 31
#define PIN_PA31__GPIO PINMUX_PIN(PIN_PA31, 0, 0)
#define PIN_PA31__G0_TXER PINMUX_PIN(PIN_PA31, 1, 1)
#define PIN_PA31__FLEXCOM6_IO2 PINMUX_PIN(PIN_PA31, 2, 1)
#define PIN_PA31__ISC_D11 PINMUX_PIN(PIN_PA31, 3, 1)
#define PIN_PA31__A17 PINMUX_PIN(PIN_PA31, 4, 1)
#define PIN_PA31__TD0 PINMUX_PIN(PIN_PA31, 5, 1)
#define PIN_PA31__FLEXCOM10_IO0 PINMUX_PIN(PIN_PA31, 6, 3)
#define PIN_PB0 32
#define PIN_PB0__GPIO PINMUX_PIN(PIN_PB0, 0, 0)
#define PIN_PB0__G0_COL PINMUX_PIN(PIN_PB0, 1, 1)
#define PIN_PB0__FLEXCOM6_IO3 PINMUX_PIN(PIN_PB0, 2, 2)
#define PIN_PB0__EXT_IRQ0 PINMUX_PIN(PIN_PB0, 3, 1)
#define PIN_PB0__A18 PINMUX_PIN(PIN_PB0, 4, 1)
#define PIN_PB0__SPDIF_RX PINMUX_PIN(PIN_PB0, 5, 2)
#define PIN_PB0__FLEXCOM10_IO1 PINMUX_PIN(PIN_PB0, 6, 3)
#define PIN_PB1 33
#define PIN_PB1__GPIO PINMUX_PIN(PIN_PB1, 0, 0)
#define PIN_PB1__G0_CRS PINMUX_PIN(PIN_PB1, 1, 1)
#define PIN_PB1__FLEXCOM6_IO1 PINMUX_PIN(PIN_PB1, 2, 2)
#define PIN_PB1__EXT_IRQ1 PINMUX_PIN(PIN_PB1, 3, 1)
#define PIN_PB1__A19 PINMUX_PIN(PIN_PB1, 4, 1)
#define PIN_PB1__SPDIF_TX PINMUX_PIN(PIN_PB1, 5, 2)
#define PIN_PB1__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB1, 6, 3)
#define PIN_PB2 34
#define PIN_PB2__GPIO PINMUX_PIN(PIN_PB2, 0, 0)
#define PIN_PB2__G0_TSUCOMP PINMUX_PIN(PIN_PB2, 1, 1)
#define PIN_PB2__FLEXCOM6_IO0 PINMUX_PIN(PIN_PB2, 2, 1)
#define PIN_PB2__ADTRG PINMUX_PIN(PIN_PB2, 3, 1)
#define PIN_PB2__A20 PINMUX_PIN(PIN_PB2, 4, 1)
#define PIN_PB2__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB2, 6, 3)
#define PIN_PB3 35
#define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0)
#define PIN_PB3__RF1 PINMUX_PIN(PIN_PB3, 1, 1)
#define PIN_PB3__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB3, 2, 1)
#define PIN_PB3__PCK2 PINMUX_PIN(PIN_PB3, 3, 2)
#define PIN_PB3__D8 PINMUX_PIN(PIN_PB3, 4, 1)
#define PIN_PB4 36
#define PIN_PB4__GPIO PINMUX_PIN(PIN_PB4, 0, 0)
#define PIN_PB4__TF1 PINMUX_PIN(PIN_PB4, 1, 1)
#define PIN_PB4__FLEXCOM11_IO1 PINMUX_PIN(PIN_PB4, 2, 1)
#define PIN_PB4__PCK3 PINMUX_PIN(PIN_PB4, 3, 2)
#define PIN_PB4__D9 PINMUX_PIN(PIN_PB4, 4, 1)
#define PIN_PB5 37
#define PIN_PB5__GPIO PINMUX_PIN(PIN_PB5, 0, 0)
#define PIN_PB5__TK1 PINMUX_PIN(PIN_PB5, 1, 1)
#define PIN_PB5__FLEXCOM11_IO2 PINMUX_PIN(PIN_PB5, 2, 1)
#define PIN_PB5__PCK4 PINMUX_PIN(PIN_PB5, 3, 2)
#define PIN_PB5__D10 PINMUX_PIN(PIN_PB5, 4, 1)
#define PIN_PB6 38
#define PIN_PB6__GPIO PINMUX_PIN(PIN_PB6, 0, 0)
#define PIN_PB6__RK1 PINMUX_PIN(PIN_PB6, 1, 1)
#define PIN_PB6__FLEXCOM11_IO3 PINMUX_PIN(PIN_PB6, 2, 1)
#define PIN_PB6__PCK5 PINMUX_PIN(PIN_PB6, 3, 2)
#define PIN_PB6__D11 PINMUX_PIN(PIN_PB6, 4, 1)
#define PIN_PB7 39
#define PIN_PB7__GPIO PINMUX_PIN(PIN_PB7, 0, 0)
#define PIN_PB7__TD1 PINMUX_PIN(PIN_PB7, 1, 1)
#define PIN_PB7__FLEXCOM11_IO4 PINMUX_PIN(PIN_PB7, 2, 1)
#define PIN_PB7__FLEXCOM3_IO5 PINMUX_PIN(PIN_PB7, 3, 2)
#define PIN_PB7__D12 PINMUX_PIN(PIN_PB7, 4, 1)
#define PIN_PB8 40
#define PIN_PB8__GPIO PINMUX_PIN(PIN_PB8, 0, 0)
#define PIN_PB8__RD1 PINMUX_PIN(PIN_PB8, 1, 1)
#define PIN_PB8__FLEXCOM8_IO0 PINMUX_PIN(PIN_PB8, 2, 1)
#define PIN_PB8__FLEXCOM3_IO6 PINMUX_PIN(PIN_PB8, 3, 2)
#define PIN_PB8__D13 PINMUX_PIN(PIN_PB8, 4, 1)
#define PIN_PB9 41
#define PIN_PB9__GPIO PINMUX_PIN(PIN_PB9, 0, 0)
#define PIN_PB9__QSPI0_IO3 PINMUX_PIN(PIN_PB9, 1, 1)
#define PIN_PB9__FLEXCOM8_IO1 PINMUX_PIN(PIN_PB9, 2, 1)
#define PIN_PB9__PDMC0_CLK PINMUX_PIN(PIN_PB9, 3, 1)
#define PIN_PB9__NCS3_NANDCS PINMUX_PIN(PIN_PB9, 4, 1)
#define PIN_PB9__PWML0 PINMUX_PIN(PIN_PB9, 5, 2)
#define PIN_PB10 42
#define PIN_PB10__GPIO PINMUX_PIN(PIN_PB10, 0, 0)
#define PIN_PB10__QSPI0_IO2 PINMUX_PIN(PIN_PB10, 1, 1)
#define PIN_PB10__FLEXCOM8_IO2 PINMUX_PIN(PIN_PB10, 2, 1)
#define PIN_PB10__PDMC0_DS0 PINMUX_PIN(PIN_PB10, 3, 1)
#define PIN_PB10__NWE_NWR0_NANDWE PINMUX_PIN(PIN_PB10, 4, 1)
#define PIN_PB10__PWMH0 PINMUX_PIN(PIN_PB10, 5, 2)
#define PIN_PB11 43
#define PIN_PB11__GPIO PINMUX_PIN(PIN_PB11, 0, 0)
#define PIN_PB11__QSPI0_IO1 PINMUX_PIN(PIN_PB11, 1, 1)
#define PIN_PB11__FLEXCOM8_IO3 PINMUX_PIN(PIN_PB11, 2, 1)
#define PIN_PB11__PDMC0_DS1 PINMUX_PIN(PIN_PB11, 3, 1)
#define PIN_PB11__NRD_NANDOE PINMUX_PIN(PIN_PB11, 4, 1)
#define PIN_PB11__PWML1 PINMUX_PIN(PIN_PB11, 5, 2)
#define PIN_PB12 44
#define PIN_PB12__GPIO PINMUX_PIN(PIN_PB12, 0, 0)
#define PIN_PB12__QSPI0_IO0 PINMUX_PIN(PIN_PB12, 1, 1)
#define PIN_PB12__FLEXCOM8_IO4 PINMUX_PIN(PIN_PB12, 2, 1)
#define PIN_PB12__FLEXCOM6_IO5 PINMUX_PIN(PIN_PB12, 3, 1)
#define PIN_PB12__A21_NANDALE PINMUX_PIN(PIN_PB12, 4, 1)
#define PIN_PB12__PWMH1 PINMUX_PIN(PIN_PB12, 5, 2)
#define PIN_PB13 45
#define PIN_PB13__GPIO PINMUX_PIN(PIN_PB13, 0, 0)
#define PIN_PB13__QSPI0_CS PINMUX_PIN(PIN_PB13, 1, 1)
#define PIN_PB13__FLEXCOM9_IO0 PINMUX_PIN(PIN_PB13, 2, 1)
#define PIN_PB13__FLEXCOM6_IO6 PINMUX_PIN(PIN_PB13, 3, 1)
#define PIN_PB13__A22_NANDCLE PINMUX_PIN(PIN_PB13, 4, 1)
#define PIN_PB13__PWML2 PINMUX_PIN(PIN_PB13, 5, 2)
#define PIN_PB14 46
#define PIN_PB14__GPIO PINMUX_PIN(PIN_PB14, 0, 0)
#define PIN_PB14__QSPI0_SCK PINMUX_PIN(PIN_PB14, 1, 1)
#define PIN_PB14__FLEXCOM9_IO1 PINMUX_PIN(PIN_PB14, 2, 1)
#define PIN_PB14__D0 PINMUX_PIN(PIN_PB14, 4, 1)
#define PIN_PB14__PWMH2 PINMUX_PIN(PIN_PB14, 5, 2)
#define PIN_PB15 47
#define PIN_PB15__GPIO PINMUX_PIN(PIN_PB15, 0, 0)
#define PIN_PB15__QSPI0_SCKN PINMUX_PIN(PIN_PB15, 1, 1)
#define PIN_PB15__FLEXCOM9_IO2 PINMUX_PIN(PIN_PB15, 2, 1)
#define PIN_PB15__D1 PINMUX_PIN(PIN_PB15, 4, 1)
#define PIN_PB15__PWML3 PINMUX_PIN(PIN_PB15, 5, 2)
#define PIN_PB16 48
#define PIN_PB16__GPIO PINMUX_PIN(PIN_PB16, 0, 0)
#define PIN_PB16__QSPI0_IO4 PINMUX_PIN(PIN_PB16, 1, 1)
#define PIN_PB16__FLEXCOM9_IO3 PINMUX_PIN(PIN_PB16, 2, 1)
#define PIN_PB16__PCK0 PINMUX_PIN(PIN_PB16, 3, 1)
#define PIN_PB16__D2 PINMUX_PIN(PIN_PB16, 4, 1)
#define PIN_PB16__PWMH3 PINMUX_PIN(PIN_PB16, 5, 2)
#define PIN_PB16__EXT_IRQ0 PINMUX_PIN(PIN_PB16, 6, 2)
#define PIN_PB17 49
#define PIN_PB17__GPIO PINMUX_PIN(PIN_PB17, 0, 0)
#define PIN_PB17__QSPI0_IO5 PINMUX_PIN(PIN_PB17, 1, 1)
#define PIN_PB17__FLEXCOM9_IO4 PINMUX_PIN(PIN_PB17, 2, 1)
#define PIN_PB17__PCK1 PINMUX_PIN(PIN_PB17, 3, 1)
#define PIN_PB17__D3 PINMUX_PIN(PIN_PB17, 4, 1)
#define PIN_PB17__PWMEXTRG0 PINMUX_PIN(PIN_PB17, 5, 2)
#define PIN_PB17__EXT_IRQ1 PINMUX_PIN(PIN_PB17, 6, 2)
#define PIN_PB18 50
#define PIN_PB18__GPIO PINMUX_PIN(PIN_PB18, 0, 0)
#define PIN_PB18__QSPI0_IO6 PINMUX_PIN(PIN_PB18, 1, 1)
#define PIN_PB18__FLEXCOM10_IO0 PINMUX_PIN(PIN_PB18, 2, 1)
#define PIN_PB18__PCK2 PINMUX_PIN(PIN_PB18, 3, 1)
#define PIN_PB18__D4 PINMUX_PIN(PIN_PB18, 4, 1)
#define PIN_PB18__PWMEXTRG1 PINMUX_PIN(PIN_PB18, 5, 2)
#define PIN_PB19 51
#define PIN_PB19__GPIO PINMUX_PIN(PIN_PB19, 0, 0)
#define PIN_PB19__QSPI0_IO7 PINMUX_PIN(PIN_PB19, 1, 1)
#define PIN_PB19__FLEXCOM10_IO1 PINMUX_PIN(PIN_PB19, 2, 1)
#define PIN_PB19__PCK3 PINMUX_PIN(PIN_PB19, 3, 1)
#define PIN_PB19__D5 PINMUX_PIN(PIN_PB19, 4, 1)
#define PIN_PB19__PWMFI0 PINMUX_PIN(PIN_PB19, 5, 2)
#define PIN_PB20 52
#define PIN_PB20__GPIO PINMUX_PIN(PIN_PB20, 0, 0)
#define PIN_PB20__QSPI0_DQS PINMUX_PIN(PIN_PB20, 1, 1)
#define PIN_PB20__FLEXCOM10_IO2 PINMUX_PIN(PIN_PB20, 2, 1)
#define PIN_PB20__D6 PINMUX_PIN(PIN_PB20, 4, 1)
#define PIN_PB20__PWMFI1 PINMUX_PIN(PIN_PB20, 5, 2)
#define PIN_PB21 53
#define PIN_PB21__GPIO PINMUX_PIN(PIN_PB21, 0, 0)
#define PIN_PB21__QSPI0_INT PINMUX_PIN(PIN_PB21, 1, 1)
#define PIN_PB21__FLEXCOM10_IO3 PINMUX_PIN(PIN_PB21, 2, 1)
#define PIN_PB21__FLEXCOM9_IO5 PINMUX_PIN(PIN_PB21, 3, 1)
#define PIN_PB21__D7 PINMUX_PIN(PIN_PB21, 4, 1)
#define PIN_PB22 54
#define PIN_PB22__GPIO PINMUX_PIN(PIN_PB22, 0, 0)
#define PIN_PB22__QSPI1_IO3 PINMUX_PIN(PIN_PB22, 1, 1)
#define PIN_PB22__FLEXCOM10_IO4 PINMUX_PIN(PIN_PB22, 2, 1)
#define PIN_PB22__FLEXCOM9_IO6 PINMUX_PIN(PIN_PB22, 3, 1)
#define PIN_PB22__NANDRDY PINMUX_PIN(PIN_PB22, 4, 1)
#define PIN_PB23 55
#define PIN_PB23__GPIO PINMUX_PIN(PIN_PB23, 0, 0)
#define PIN_PB23__QSPI1_IO2 PINMUX_PIN(PIN_PB23, 1, 1)
#define PIN_PB23__FLEXCOM7_IO0 PINMUX_PIN(PIN_PB23, 2, 1)
#define PIN_PB23__I2SMCC0_CK PINMUX_PIN(PIN_PB23, 3, 1)
#define PIN_PB23__PCK4 PINMUX_PIN(PIN_PB23, 6, 1)
#define PIN_PB24 56
#define PIN_PB24__GPIO PINMUX_PIN(PIN_PB24, 0, 0)
#define PIN_PB24__QSPI1_IO1 PINMUX_PIN(PIN_PB24, 1, 1)
#define PIN_PB24__FLEXCOM7_IO1 PINMUX_PIN(PIN_PB24, 2, 1)
#define PIN_PB24__I2SMCC0_WS PINMUX_PIN(PIN_PB24, 3, 1)
#define PIN_PB24__PCK5 PINMUX_PIN(PIN_PB24, 6, 1)
#define PIN_PB25 57
#define PIN_PB25__GPIO PINMUX_PIN(PIN_PB25, 0, 0)
#define PIN_PB25__QSPI1_IO0 PINMUX_PIN(PIN_PB25, 1, 1)
#define PIN_PB25__FLEXCOM7_IO2 PINMUX_PIN(PIN_PB25, 2, 1)
#define PIN_PB25__I2SMCC0_DOUT1 PINMUX_PIN(PIN_PB25, 3, 1)
#define PIN_PB25__PCK6 PINMUX_PIN(PIN_PB25, 6, 1)
#define PIN_PB26 58
#define PIN_PB26__GPIO PINMUX_PIN(PIN_PB26, 0, 0)
#define PIN_PB26__QSPI1_CS PINMUX_PIN(PIN_PB26, 1, 1)
#define PIN_PB26__FLEXCOM7_IO3 PINMUX_PIN(PIN_PB26, 2, 1)
#define PIN_PB26__I2SMCC0_DOUT0 PINMUX_PIN(PIN_PB26, 3, 1)
#define PIN_PB26__PWMEXTRG0 PINMUX_PIN(PIN_PB26, 5, 1)
#define PIN_PB26__PCK7 PINMUX_PIN(PIN_PB26, 6, 1)
#define PIN_PB27 59
#define PIN_PB27__GPIO PINMUX_PIN(PIN_PB27, 0, 0)
#define PIN_PB27__QSPI1_SCK PINMUX_PIN(PIN_PB27, 1, 1)
#define PIN_PB27__FLEXCOM7_IO4 PINMUX_PIN(PIN_PB27, 2, 1)
#define PIN_PB27__I2SMCC0_MCK PINMUX_PIN(PIN_PB27, 3, 1)
#define PIN_PB27__PWMEXTRG1 PINMUX_PIN(PIN_PB27, 5, 1)
#define PIN_PB28 60
#define PIN_PB28__GPIO PINMUX_PIN(PIN_PB28, 0, 0)
#define PIN_PB28__SDMMC1_RSTN PINMUX_PIN(PIN_PB28, 1, 1)
#define PIN_PB28__ADTRG PINMUX_PIN(PIN_PB28, 2, 2)
#define PIN_PB28__PWMFI0 PINMUX_PIN(PIN_PB28, 5, 1)
#define PIN_PB28__FLEXCOM7_IO0 PINMUX_PIN(PIN_PB28, 6, 4)
#define PIN_PB29 61
#define PIN_PB29__GPIO PINMUX_PIN(PIN_PB29, 0, 0)
#define PIN_PB29__SDMMC1_CMD PINMUX_PIN(PIN_PB29, 1, 1)
#define PIN_PB29__FLEXCOM3_IO2 PINMUX_PIN(PIN_PB29, 2, 2)
#define PIN_PB29__FLEXCOM0_IO5 PINMUX_PIN(PIN_PB29, 3, 2)
#define PIN_PB29__TIOA3 PINMUX_PIN(PIN_PB29, 4, 2)
#define PIN_PB29__PWMFI1 PINMUX_PIN(PIN_PB29, 5, 1)
#define PIN_PB29__FLEXCOM7_IO1 PINMUX_PIN(PIN_PB29, 6, 4)
#define PIN_PB30 62
#define PIN_PB30__GPIO PINMUX_PIN(PIN_PB30, 0, 0)
#define PIN_PB30__SDMMC1_CK PINMUX_PIN(PIN_PB30, 1, 1)
#define PIN_PB30__FLEXCOM3_IO3 PINMUX_PIN(PIN_PB30, 2, 2)
#define PIN_PB30__FLEXCOM0_IO6 PINMUX_PIN(PIN_PB30, 3, 2)
#define PIN_PB30__TIOB3 PINMUX_PIN(PIN_PB30, 4, 1)
#define PIN_PB30__PWMH0 PINMUX_PIN(PIN_PB30, 5, 1)
#define PIN_PB30__FLEXCOM8_IO0 PINMUX_PIN(PIN_PB30, 6, 4)
#define PIN_PB31 63
#define PIN_PB31__GPIO PINMUX_PIN(PIN_PB31, 0, 0)
#define PIN_PB31__SDMMC1_DAT0 PINMUX_PIN(PIN_PB31, 1, 1)
#define PIN_PB31__FLEXCOM3_IO4 PINMUX_PIN(PIN_PB31, 2, 2)
#define PIN_PB31__FLEXCOM9_IO5 PINMUX_PIN(PIN_PB31, 3, 2)
#define PIN_PB31__TCLK3 PINMUX_PIN(PIN_PB31, 4, 1)
#define PIN_PB31__PWML0 PINMUX_PIN(PIN_PB31, 5, 1)
#define PIN_PB31__FLEXCOM8_IO1 PINMUX_PIN(PIN_PB31, 6, 4)
#define PIN_PC0 64
#define PIN_PC0__GPIO PINMUX_PIN(PIN_PC0, 0, 0)
#define PIN_PC0__SDMMC1_DAT1 PINMUX_PIN(PIN_PC0, 1, 1)
#define PIN_PC0__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC0, 2, 2)
#define PIN_PC0__TIOA4 PINMUX_PIN(PIN_PC0, 4, 1)
#define PIN_PC0__PWML1 PINMUX_PIN(PIN_PC0, 5, 1)
#define PIN_PC0__FLEXCOM9_IO0 PINMUX_PIN(PIN_PC0, 6, 4)
#define PIN_PC1 65
#define PIN_PC1__GPIO PINMUX_PIN(PIN_PC1, 0, 0)
#define PIN_PC1__SDMMC1_DAT2 PINMUX_PIN(PIN_PC1, 1, 1)
#define PIN_PC1__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC1, 2, 2)
#define PIN_PC1__TIOB4 PINMUX_PIN(PIN_PC1, 4, 1)
#define PIN_PC1__PWMH1 PINMUX_PIN(PIN_PC1, 5, 1)
#define PIN_PC1__FLEXCOM9_IO1 PINMUX_PIN(PIN_PC1, 6, 4)
#define PIN_PC2 66
#define PIN_PC2__GPIO PINMUX_PIN(PIN_PC2, 0, 0)
#define PIN_PC2__SDMMC1_DAT3 PINMUX_PIN(PIN_PC2, 1, 1)
#define PIN_PC2__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC2, 2, 2)
#define PIN_PC2__TCLK4 PINMUX_PIN(PIN_PC2, 4, 1)
#define PIN_PC2__PWML2 PINMUX_PIN(PIN_PC2, 5, 1)
#define PIN_PC2__FLEXCOM10_IO0 PINMUX_PIN(PIN_PC2, 6, 4)
#define PIN_PC3 67
#define PIN_PC3__GPIO PINMUX_PIN(PIN_PC3, 0, 0)
#define PIN_PC3__SDMMC1_WP PINMUX_PIN(PIN_PC3, 1, 1)
#define PIN_PC3__FLEXCOM4_IO1 PINMUX_PIN(PIN_PC3, 2, 2)
#define PIN_PC3__TIOA5 PINMUX_PIN(PIN_PC3, 4, 1)
#define PIN_PC3__PWMH2 PINMUX_PIN(PIN_PC3, 5, 1)
#define PIN_PC3__FLEXCOM10_IO1 PINMUX_PIN(PIN_PC3, 6, 4)
#define PIN_PC4 68
#define PIN_PC4__GPIO PINMUX_PIN(PIN_PC4, 0, 0)
#define PIN_PC4__SDMMC1_CD PINMUX_PIN(PIN_PC4, 1, 1)
#define PIN_PC4__FLEXCOM4_IO2 PINMUX_PIN(PIN_PC4, 2, 2)
#define PIN_PC4__FLEXCOM9_IO6 PINMUX_PIN(PIN_PC4, 3, 2)
#define PIN_PC4__TIOB5 PINMUX_PIN(PIN_PC4, 4, 1)
#define PIN_PC4__PWML3 PINMUX_PIN(PIN_PC4, 5, 1)
#define PIN_PC4__FLEXCOM11_IO0 PINMUX_PIN(PIN_PC4, 6, 4)
#define PIN_PC5 69
#define PIN_PC5__GPIO PINMUX_PIN(PIN_PC5, 0, 0)
#define PIN_PC5__SDMMC1_1V8SEL PINMUX_PIN(PIN_PC5, 1, 1)
#define PIN_PC5__FLEXCOM4_IO3 PINMUX_PIN(PIN_PC5, 2, 2)
#define PIN_PC5__FLEXCOM6_IO5 PINMUX_PIN(PIN_PC5, 3, 2)
#define PIN_PC5__TCLK5 PINMUX_PIN(PIN_PC5, 4, 1)
#define PIN_PC5__PWMH3 PINMUX_PIN(PIN_PC5, 5, 1)
#define PIN_PC5__FLEXCOM11_IO1 PINMUX_PIN(PIN_PC5, 6, 4)
#define PIN_PC6 70
#define PIN_PC6__GPIO PINMUX_PIN(PIN_PC6, 0, 0)
#define PIN_PC6__FLEXCOM4_IO4 PINMUX_PIN(PIN_PC6, 2, 2)
#define PIN_PC6__FLEXCOM6_IO6 PINMUX_PIN(PIN_PC6, 3, 2)
#define PIN_PC7 71
#define PIN_PC7__GPIO PINMUX_PIN(PIN_PC7, 0, 0)
#define PIN_PC7__I2SMCC0_DIN0 PINMUX_PIN(PIN_PC7, 1, 1)
#define PIN_PC7__FLEXCOM7_IO0 PINMUX_PIN(PIN_PC7, 2, 2)
#define PIN_PC8 72
#define PIN_PC8__GPIO PINMUX_PIN(PIN_PC8, 0, 0)
#define PIN_PC8__I2SMCC0_DIN1 PINMUX_PIN(PIN_PC8, 1, 1)
#define PIN_PC8__FLEXCOM7_IO1 PINMUX_PIN(PIN_PC8, 2, 2)
#define PIN_PC9 73
#define PIN_PC9__GPIO PINMUX_PIN(PIN_PC9, 0, 0)
#define PIN_PC9__I2SMCC0_DOUT3 PINMUX_PIN(PIN_PC9, 1, 1)
#define PIN_PC9__FLEXCOM7_IO2 PINMUX_PIN(PIN_PC9, 2, 2)
#define PIN_PC9__FLEXCOM1_IO0 PINMUX_PIN(PIN_PC9, 6, 4)
#define PIN_PC10 74
#define PIN_PC10__GPIO PINMUX_PIN(PIN_PC10, 0, 0)
#define PIN_PC10__I2SMCC0_DOUT2 PINMUX_PIN(PIN_PC10, 1, 1)
#define PIN_PC10__FLEXCOM7_IO3 PINMUX_PIN(PIN_PC10, 2, 2)
#define PIN_PC10__FLEXCOM1_IO1 PINMUX_PIN(PIN_PC10, 6, 4)
#define PIN_PC11 75
#define PIN_PC11__GPIO PINMUX_PIN(PIN_PC11, 0, 0)
#define PIN_PC11__I2SMCC1_CK PINMUX_PIN(PIN_PC11, 1, 1)
#define PIN_PC11__FLEXCOM7_IO4 PINMUX_PIN(PIN_PC11, 2, 2)
#define PIN_PC11__FLEXCOM2_IO0 PINMUX_PIN(PIN_PC11, 6, 4)
#define PIN_PC12 76
#define PIN_PC12__GPIO PINMUX_PIN(PIN_PC12, 0, 0)
#define PIN_PC12__I2SMCC1_WS PINMUX_PIN(PIN_PC12, 1, 1)
#define PIN_PC12__FLEXCOM8_IO2 PINMUX_PIN(PIN_PC12, 2, 2)
#define PIN_PC12__FLEXCOM2_IO1 PINMUX_PIN(PIN_PC12, 6, 4)
#define PIN_PC13 77
#define PIN_PC13__GPIO PINMUX_PIN(PIN_PC13, 0, 0)
#define PIN_PC13__I2SMCC1_MCK PINMUX_PIN(PIN_PC13, 1, 1)
#define PIN_PC13__FLEXCOM8_IO1 PINMUX_PIN(PIN_PC13, 2, 2)
#define PIN_PC13__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC13, 6, 4)
#define PIN_PC14 78
#define PIN_PC14__GPIO PINMUX_PIN(PIN_PC14, 0, 0)
#define PIN_PC14__I2SMCC1_DOUT0 PINMUX_PIN(PIN_PC14, 1, 1)
#define PIN_PC14__FLEXCOM8_IO0 PINMUX_PIN(PIN_PC14, 2, 2)
#define PIN_PC14__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC14, 6, 4)
#define PIN_PC15 79
#define PIN_PC15__GPIO PINMUX_PIN(PIN_PC15, 0, 0)
#define PIN_PC15__I2SMCC1_DOUT1 PINMUX_PIN(PIN_PC15, 1, 1)
#define PIN_PC15__FLEXCOM8_IO3 PINMUX_PIN(PIN_PC15, 2, 2)
#define PIN_PC15__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC15, 6, 4)
#define PIN_PC16 80
#define PIN_PC16__GPIO PINMUX_PIN(PIN_PC16, 0, 0)
#define PIN_PC16__I2SMCC_DOUT2 PINMUX_PIN(PIN_PC16, 1, 1)
#define PIN_PC16__FLEXCOM8_IO4 PINMUX_PIN(PIN_PC16, 2, 2)
#define PIN_PC16__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC16, 6, 4)
#define PIN_PC17 81
#define PIN_PC17__GPIO PINMUX_PIN(PIN_PC17, 0, 0)
#define PIN_PC17__I2SMCC1_DOUT3 PINMUX_PIN(PIN_PC17, 1, 1)
#define PIN_PC17__EXT_IRQ0 PINMUX_PIN(PIN_PC17, 2, 3)
#define PIN_PC17__FLEXCOM5_IO0 PINMUX_PIN(PIN_PC17, 6, 4)
#define PIN_PC18 82
#define PIN_PC18__GPIO PINMUX_PIN(PIN_PC18, 0, 0)
#define PIN_PC18__I2SMCC1_DIN0 PINMUX_PIN(PIN_PC18, 1, 1)
#define PIN_PC18__FLEXCOM9_IO0 PINMUX_PIN(PIN_PC18, 2, 2)
#define PIN_PC18__FLEXCOM5_IO1 PINMUX_PIN(PIN_PC18, 6, 4)
#define PIN_PC19 83
#define PIN_PC19__GPIO PINMUX_PIN(PIN_PC19, 0, 0)
#define PIN_PC19__I2SMCC1_DIN1 PINMUX_PIN(PIN_PC19, 1, 1)
#define PIN_PC19__FLEXCOM9_IO1 PINMUX_PIN(PIN_PC19, 2, 2)
#define PIN_PC19__FLEXCOM6_IO0 PINMUX_PIN(PIN_PC19, 6, 4)
#define PIN_PC20 84
#define PIN_PC20__GPIO PINMUX_PIN(PIN_PC20, 0, 0)
#define PIN_PC20__I2SMCC1_DIN2 PINMUX_PIN(PIN_PC20, 1, 1)
#define PIN_PC20__FLEXCOM9_IO4 PINMUX_PIN(PIN_PC20, 2, 2)
#define PIN_PC20__FLEXCOM6_IO1 PINMUX_PIN(PIN_PC20, 6, 4)
#define PIN_PC21 85
#define PIN_PC21__GPIO PINMUX_PIN(PIN_PC21, 0, 0)
#define PIN_PC21__I2SMCC1_DIN3 PINMUX_PIN(PIN_PC21, 1, 1)
#define PIN_PC21__FLEXCOM9_IO2 PINMUX_PIN(PIN_PC21, 2, 2)
#define PIN_PC21__D3 PINMUX_PIN(PIN_PC21, 4, 2)
#define PIN_PC21__FLEXCOM6_IO0 PINMUX_PIN(PIN_PC21, 6, 5)
#define PIN_PC22 86
#define PIN_PC22__GPIO PINMUX_PIN(PIN_PC22, 0, 0)
#define PIN_PC22__I2SMCC0_DIN2 PINMUX_PIN(PIN_PC22, 1, 1)
#define PIN_PC22__FLEXCOM9_IO3 PINMUX_PIN(PIN_PC22, 2, 2)
#define PIN_PC22__D4 PINMUX_PIN(PIN_PC22, 4, 2)
#define PIN_PC22__FLEXCOM6_IO1 PINMUX_PIN(PIN_PC22, 6, 5)
#define PIN_PC23 87
#define PIN_PC23__GPIO PINMUX_PIN(PIN_PC23, 0, 0)
#define PIN_PC23__I2SMCC0_DIN3 PINMUX_PIN(PIN_PC23, 1, 1)
#define PIN_PC23__FLEXCOM0_IO5 PINMUX_PIN(PIN_PC23, 2, 3)
#define PIN_PC23__D5 PINMUX_PIN(PIN_PC23, 4, 2)
#define PIN_PC23__FLEXCOM7_IO0 PINMUX_PIN(PIN_PC23, 6, 5)
#define PIN_PC24 88
#define PIN_PC24__GPIO PINMUX_PIN(PIN_PC24, 0, 0)
#define PIN_PC24__FLEXCOM0_IO6 PINMUX_PIN(PIN_PC24, 2, 3)
#define PIN_PC24__EXT_IRQ1 PINMUX_PIN(PIN_PC24, 3, 3)
#define PIN_PC24__D6 PINMUX_PIN(PIN_PC24, 4, 2)
#define PIN_PC24__FLEXCOM7_IO1 PINMUX_PIN(PIN_PC24, 6, 5)
#define PIN_PC25 89
#define PIN_PC25__GPIO PINMUX_PIN(PIN_PC25, 0, 0)
#define PIN_PC25__NTRST PINMUX_PIN(PIN_PC25, 1, 1)
#define PIN_PC26 90
#define PIN_PC26__GPIO PINMUX_PIN(PIN_PC26, 0, 0)
#define PIN_PC26__TCK_SWCLK PINMUX_PIN(PIN_PC26, 1, 1)
#define PIN_PC27 91
#define PIN_PC27__GPIO PINMUX_PIN(PIN_PC27, 0, 0)
#define PIN_PC27__TMS_SWDIO PINMUX_PIN(PIN_PC27, 1, 1)
#define PIN_PC28 92
#define PIN_PC28__GPIO PINMUX_PIN(PIN_PC28, 0, 0)
#define PIN_PC28__TDI PINMUX_PIN(PIN_PC28, 1, 1)
#define PIN_PC29 93
#define PIN_PC29__GPIO PINMUX_PIN(PIN_PC29, 0, 0)
#define PIN_PC29__TDO PINMUX_PIN(PIN_PC29, 1, 1)
#define PIN_PC30 94
#define PIN_PC30__GPIO PINMUX_PIN(PIN_PC30, 0, 0)
#define PIN_PC30__FLEXCOM10_IO0 PINMUX_PIN(PIN_PC30, 2, 2)
#define PIN_PC31 95
#define PIN_PC31__GPIO PINMUX_PIN(PIN_PC31, 0, 0)
#define PIN_PC31__FLEXCOM10_IO1 PINMUX_PIN(PIN_PC31, 2, 2)
#define PIN_PD0 96
#define PIN_PD0__GPIO PINMUX_PIN(PIN_PD0, 0, 0)
#define PIN_PD0__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD0, 2, 2)
#define PIN_PD1 97
#define PIN_PD1__GPIO PINMUX_PIN(PIN_PD1, 0, 0)
#define PIN_PD1__FLEXCOM11_IO1 PINMUX_PIN(PIN_PD1, 2, 2)
#define PIN_PD2 98
#define PIN_PD2__GPIO PINMUX_PIN(PIN_PD2, 0, 0)
#define PIN_PD2__SDMMC2_RSTN PINMUX_PIN(PIN_PD2, 1, 1)
#define PIN_PD2__PCK0 PINMUX_PIN(PIN_PD2, 2, 2)
#define PIN_PD2__CANTX4 PINMUX_PIN(PIN_PD2, 3, 1)
#define PIN_PD2__D7 PINMUX_PIN(PIN_PD2, 4, 2)
#define PIN_PD2__TIOA0 PINMUX_PIN(PIN_PD2, 5, 2)
#define PIN_PD2__FLEXCOM8_IO0 PINMUX_PIN(PIN_PD2, 6, 5)
#define PIN_PD3 99
#define PIN_PD3__GPIO PINMUX_PIN(PIN_PD3, 0, 0)
#define PIN_PD3__SDMMC2_CMD PINMUX_PIN(PIN_PD3, 1, 1)
#define PIN_PD3__FLEXCOM0_IO0 PINMUX_PIN(PIN_PD3, 2, 2)
#define PIN_PD3__CANRX4 PINMUX_PIN(PIN_PD3, 3, 1)
#define PIN_PD3__NANDRDY PINMUX_PIN(PIN_PD3, 4, 2)
#define PIN_PD3__TIOB0 PINMUX_PIN(PIN_PD3, 5, 2)
#define PIN_PD3__FLEXCOM8_IO1 PINMUX_PIN(PIN_PD3, 6, 5)
#define PIN_PD4 100
#define PIN_PD4__GPIO PINMUX_PIN(PIN_PD4, 0, 0)
#define PIN_PD4__SDMMC2_CK PINMUX_PIN(PIN_PD4, 1, 1)
#define PIN_PD4__FLEXCOM0_IO1 PINMUX_PIN(PIN_PD4, 2, 2)
#define PIN_PD4__CANTX5 PINMUX_PIN(PIN_PD4, 3, 1)
#define PIN_PD4__NCS3_NANDCS PINMUX_PIN(PIN_PD4, 4, 2)
#define PIN_PD4__TCLK0 PINMUX_PIN(PIN_PD4, 5, 2)
#define PIN_PD4__FLEXCOM9_IO0 PINMUX_PIN(PIN_PD4, 6, 5)
#define PIN_PD5 101
#define PIN_PD5__GPIO PINMUX_PIN(PIN_PD5, 0, 0)
#define PIN_PD5__SDMMC2_DAT0 PINMUX_PIN(PIN_PD5, 1, 1)
#define PIN_PD5__FLEXCOM0_IO2 PINMUX_PIN(PIN_PD5, 2, 2)
#define PIN_PD5__CANRX5 PINMUX_PIN(PIN_PD5, 3, 1)
#define PIN_PD5__NWE_NWR0_NANDWE PINMUX_PIN(PIN_PD5, 4, 2)
#define PIN_PD5__TIOA1 PINMUX_PIN(PIN_PD5, 5, 2)
#define PIN_PD5__FLEXCOM9_IO1 PINMUX_PIN(PIN_PD5, 6, 5)
#define PIN_PD6 102
#define PIN_PD6__GPIO PINMUX_PIN(PIN_PD6, 0, 0)
#define PIN_PD6__SDMMC2_DAT1 PINMUX_PIN(PIN_PD6, 1, 1)
#define PIN_PD6__FLEXCOM0_IO3 PINMUX_PIN(PIN_PD6, 2, 2)
#define PIN_PD6__SPDIF_RX PINMUX_PIN(PIN_PD6, 3, 3)
#define PIN_PD6__NRD_NANDOE PINMUX_PIN(PIN_PD6, 4, 2)
#define PIN_PD6__TIOB1 PINMUX_PIN(PIN_PD6, 5, 2)
#define PIN_PD6__FLEXCOM10_IO0 PINMUX_PIN(PIN_PD6, 6, 5)
#define PIN_PD7 103
#define PIN_PD7__GPIO PINMUX_PIN(PIN_PD7, 0, 0)
#define PIN_PD7__SDMMC2_DAT2 PINMUX_PIN(PIN_PD7, 1, 1)
#define PIN_PD7__FLEXCOM0_IO4 PINMUX_PIN(PIN_PD7, 2, 2)
#define PIN_PD7__SPDIF_TX PINMUX_PIN(PIN_PD7, 2, 2)
#define PIN_PD7__A21_NANDALE PINMUX_PIN(PIN_PD7, 4, 2)
#define PIN_PD7__TCLK1 PINMUX_PIN(PIN_PD7, 5, 2)
#define PIN_PD7__FLEXCOM10_IO1 PINMUX_PIN(PIN_PD7, 6, 5)
#define PIN_PD8 104
#define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0)
#define PIN_PD8__SDMMC2_DAT3 PINMUX_PIN(PIN_PD8, 1, 1)
#define PIN_PD8__I2SMCC0_DIN0 PINMUX_PIN(PIN_PD8, 3, 1)
#define PIN_PD8__A11_NANDCLE PINMUX_PIN(PIN_PD8, 4, 2)
#define PIN_PD8__TIOA2 PINMUX_PIN(PIN_PD8, 5, 2)
#define PIN_PD8__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD8, 6, 5)
#define PIN_PD9 105
#define PIN_PD9__GPIO PINMUX_PIN(PIN_PD9, 0, 0)
#define PIN_PD9__SDMMC2_WP PINMUX_PIN(PIN_PD9, 1, 1)
#define PIN_PD9__I2SMCC0_DIN1 PINMUX_PIN(PIN_PD9, 3, 2)
#define PIN_PD9__D0 PINMUX_PIN(PIN_PD9, 4, 2)
#define PIN_PD9__TIOB2 PINMUX_PIN(PIN_PD9, 5, 2)
#define PIN_PD9__FLEXCOM11_IO1 PINMUX_PIN(PIN_PD9, 6, 5)
#define PIN_PD10 106
#define PIN_PD10__GPIO PINMUX_PIN(PIN_PD10, 0, 0)
#define PIN_PD10__SDMMC2_CD PINMUX_PIN(PIN_PD10, 1, 1)
#define PIN_PD10__PCK6 PINMUX_PIN(PIN_PD10, 2, 2)
#define PIN_PD10__I2SMCC0_DIN2 PINMUX_PIN(PIN_PD10, 3, 2)
#define PIN_PD10__D1 PINMUX_PIN(PIN_PD10, 4, 2)
#define PIN_PD10__TCLK2 PINMUX_PIN(PIN_PD10, 5, 2)
#define PIN_PD10__FLEXCOM0_IO0 PINMUX_PIN(PIN_PD10, 6, 3)
#define PIN_PD11 107
#define PIN_PD11__GPIO PINMUX_PIN(PIN_PD11, 0, 0)
#define PIN_PD11__SDMMC2_1V8SEL PINMUX_PIN(PIN_PD11, 1, 1)
#define PIN_PD11__PCK7 PINMUX_PIN(PIN_PD11, 2, 2)
#define PIN_PD11__I2SMCC0_DIN3 PINMUX_PIN(PIN_PD11, 3, 2)
#define PIN_PD11__D2 PINMUX_PIN(PIN_PD11, 4, 2)
#define PIN_PD11__TIOA3 PINMUX_PIN(PIN_PD11, 5, 2)
#define PIN_PD11__FLEXCOM0_IO1 PINMUX_PIN(PIN_PD11, 6, 3)
#define PIN_PD12 108
#define PIN_PD12__GPIO PINMUX_PIN(PIN_PD12, 0, 0)
#define PIN_PD12__PCK1 PINMUX_PIN(PIN_PD12, 1, 2)
#define PIN_PD12__FLEXCOM1_IO0 PINMUX_PIN(PIN_PD12, 2, 2)
#define PIN_PD12__CANTX0 PINMUX_PIN(PIN_PD12, 4, 2)
#define PIN_PD12__TIOB3 PINMUX_PIN(PIN_PD12, 5, 2)
#define PIN_PD13 109
#define PIN_PD13__GPIO PINMUX_PIN(PIN_PD13, 0, 0)
#define PIN_PD13__I2SMCC0_CK PINMUX_PIN(PIN_PD13, 1, 2)
#define PIN_PD13__FLEXCOM1_IO1 PINMUX_PIN(PIN_PD13, 2, 2)
#define PIN_PD13__PWML0 PINMUX_PIN(PIN_PD13, 3, 4)
#define PIN_PD13__CANRX0 PINMUX_PIN(PIN_PD13, 4, 2)
#define PIN_PD13__TCLK3 PINMUX_PIN(PIN_PD13, 5, 2)
#define PIN_PD14 110
#define PIN_PD14__GPIO PINMUX_PIN(PIN_PD14, 0, 0)
#define PIN_PD14__I2SMCC0_MCK PINMUX_PIN(PIN_PD14, 1, 2)
#define PIN_PD14__FLEXCOM1_IO2 PINMUX_PIN(PIN_PD14, 2, 2)
#define PIN_PD14__PWMH0 PINMUX_PIN(PIN_PD14, 3, 4)
#define PIN_PD14__CANTX1 PINMUX_PIN(PIN_PD14, 4, 2)
#define PIN_PD14__TIOA4 PINMUX_PIN(PIN_PD14, 5, 2)
#define PIN_PD14__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD14, 6, 5)
#define PIN_PD15 111
#define PIN_PD15__GPIO PINMUX_PIN(PIN_PD15, 0, 0)
#define PIN_PD15__I2SMCC0_WS PINMUX_PIN(PIN_PD15, 1, 2)
#define PIN_PD15__FLEXCOM1_IO3 PINMUX_PIN(PIN_PD15, 2, 2)
#define PIN_PD15__PWML1 PINMUX_PIN(PIN_PD15, 3, 4)
#define PIN_PD15__CANRX1 PINMUX_PIN(PIN_PD15, 4, 2)
#define PIN_PD15__TIOB4 PINMUX_PIN(PIN_PD15, 5, 2)
#define PIN_PD15__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD15, 6, 5)
#define PIN_PD16 112
#define PIN_PD16__GPIO PINMUX_PIN(PIN_PD16, 0, 0)
#define PIN_PD16__I2SMCC0_DOUT0 PINMUX_PIN(PIN_PD16, 1, 2)
#define PIN_PD16__FLEXCOM1_IO4 PINMUX_PIN(PIN_PD16, 2, 2)
#define PIN_PD16__PWMH1 PINMUX_PIN(PIN_PD16, 3, 4)
#define PIN_PD16__CANTX2 PINMUX_PIN(PIN_PD16, 4, 2)
#define PIN_PD16__TCLK4 PINMUX_PIN(PIN_PD16, 5, 2)
#define PIN_PD16__FLEXCOM3_IO0 PINMUX_PIN(PIN_PD16, 6, 5)
#define PIN_PD17 113
#define PIN_PD17__GPIO PINMUX_PIN(PIN_PD17, 0, 0)
#define PIN_PD17__I2SMCC0_DOUT1 PINMUX_PIN(PIN_PD17, 1, 2)
#define PIN_PD17__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD17, 2, 2)
#define PIN_PD17__PWML2 PINMUX_PIN(PIN_PD17, 3, 4)
#define PIN_PD17__CANRX2 PINMUX_PIN(PIN_PD17, 4, 2)
#define PIN_PD17__TIOA5 PINMUX_PIN(PIN_PD17, 5, 2)
#define PIN_PD17__FLEXCOM3_IO1 PINMUX_PIN(PIN_PD17, 6, 5)
#define PIN_PD18 114
#define PIN_PD18__GPIO PINMUX_PIN(PIN_PD18, 0, 0)
#define PIN_PD18__I2SMCC0_DOUT2 PINMUX_PIN(PIN_PD18, 1, 2)
#define PIN_PD18__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD18, 2, 2)
#define PIN_PD18__PWMH2 PINMUX_PIN(PIN_PD18, 3, 4)
#define PIN_PD18__CANTX3 PINMUX_PIN(PIN_PD18, 4, 2)
#define PIN_PD18__TIOB5 PINMUX_PIN(PIN_PD18, 5, 2)
#define PIN_PD18__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD18, 6, 5)
#define PIN_PD19 115
#define PIN_PD19__GPIO PINMUX_PIN(PIN_PD19, 0, 0)
#define PIN_PD19__I2SMCC0_DOUT3 PINMUX_PIN(PIN_PD19, 1, 2)
#define PIN_PD19__FLEXCOM2_IO2 PINMUX_PIN(PIN_PD19, 2, 2)
#define PIN_PD19__PWML3 PINMUX_PIN(PIN_PD19, 3, 4)
#define PIN_PD19__CANRX3 PINMUX_PIN(PIN_PD19, 4, 2)
#define PIN_PD19__TCLK5 PINMUX_PIN(PIN_PD19, 5, 2)
#define PIN_PD19__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD19, 6, 5)
#define PIN_PD20 116
#define PIN_PD20__GPIO PINMUX_PIN(PIN_PD20, 0, 0)
#define PIN_PD20__PCK0 PINMUX_PIN(PIN_PD20, 1, 3)
#define PIN_PD20__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD20, 2, 2)
#define PIN_PD20__PWMH3 PINMUX_PIN(PIN_PD20, 3, 4)
#define PIN_PD20__CANTX4 PINMUX_PIN(PIN_PD20, 5, 2)
#define PIN_PD20__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD20, 6, 5)
#define PIN_PD21 117
#define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0)
#define PIN_PD21__PCK1 PINMUX_PIN(PIN_PD21, 1, 3)
#define PIN_PD21__FLEXCOM2_IO4 PINMUX_PIN(PIN_PD21, 2, 2)
#define PIN_PD21__CANRX4 PINMUX_PIN(PIN_PD21, 4, 2)
#define PIN_PD21__FLEXCOM5_IO1 PINMUX_PIN(PIN_PD21, 6, 5)
#define PIN_PD21__G1_TXEN PINMUX_PIN(PIN_PD21, 7, 1)
#define PIN_PD22 118
#define PIN_PD22__GPIO PINMUX_PIN(PIN_PD22, 0, 0)
#define PIN_PD22__PDMC0_CLK PINMUX_PIN(PIN_PD22, 1, 2)
#define PIN_PD22__PWMEXTRG0 PINMUX_PIN(PIN_PD22, 3, 4)
#define PIN_PD22__RD1 PINMUX_PIN(PIN_PD22, 4, 2)
#define PIN_PD22__CANTX5 PINMUX_PIN(PIN_PD22, 6, 2)
#define PIN_PD22__G1_TX0 PINMUX_PIN(PIN_PD22, 7, 1)
#define PIN_PD23 119
#define PIN_PD23__GPIO PINMUX_PIN(PIN_PD23, 0, 0)
#define PIN_PD23__PDMC0_DS0 PINMUX_PIN(PIN_PD23, 1, 2)
#define PIN_PD23__PWMEXTRG1 PINMUX_PIN(PIN_PD23, 3, 4)
#define PIN_PD23__RF1 PINMUX_PIN(PIN_PD23, 4, 2)
#define PIN_PD23__ISC_MCK PINMUX_PIN(PIN_PD23, 5, 2)
#define PIN_PD23__CANRX5 PINMUX_PIN(PIN_PD23, 6, 2)
#define PIN_PD23__G1_TX1 PINMUX_PIN(PIN_PD23, 7, 1)
#define PIN_PD24 120
#define PIN_PD24__GPIO PINMUX_PIN(PIN_PD24, 0, 0)
#define PIN_PD24__PDMC0_DS1 PINMUX_PIN(PIN_PD24, 1, 2)
#define PIN_PD24__PWMFI0 PINMUX_PIN(PIN_PD24, 3, 4)
#define PIN_PD24__RK1 PINMUX_PIN(PIN_PD24, 4, 2)
#define PIN_PD24__ISC_D0 PINMUX_PIN(PIN_PD24, 5, 2)
#define PIN_PD24__G1_RXDV PINMUX_PIN(PIN_PD24, 7, 1)
#define PIN_PD25 121
#define PIN_PD25__GPIO PINMUX_PIN(PIN_PD25, 0, 0)
#define PIN_PD25__PDMC1_CLK PINMUX_PIN(PIN_PD25, 1, 2)
#define PIN_PD25__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD25, 2, 2)
#define PIN_PD25__PWMFI1 PINMUX_PIN(PIN_PD25, 3, 4)
#define PIN_PD25__TD1 PINMUX_PIN(PIN_PD25, 4, 2)
#define PIN_PD25__ISC_D1 PINMUX_PIN(PIN_PD25, 5, 2)
#define PIN_PD25__G1_RX0 PINMUX_PIN(PIN_PD25, 7, 1)
#define PIN_PD26 122
#define PIN_PD26__GPIO PINMUX_PIN(PIN_PD26, 0, 0)
#define PIN_PD26__PDMC1_DS0 PINMUX_PIN(PIN_PD26, 1, 2)
#define PIN_PD26__FLEXCOM5_IO1 PINMUX_PIN(PIN_PD26, 2, 2)
#define PIN_PD26__ADTRG PINMUX_PIN(PIN_PD26, 3, 3)
#define PIN_PD26__TF1 PINMUX_PIN(PIN_PD26, 4, 2)
#define PIN_PD26__ISC_D2 PINMUX_PIN(PIN_PD26, 5, 2)
#define PIN_PD26__G1_RX1 PINMUX_PIN(PIN_PD26, 7, 1)
#define PIN_PD27 123
#define PIN_PD27__GPIO PINMUX_PIN(PIN_PD27, 0, 0)
#define PIN_PD27__PDMC1_DS1 PINMUX_PIN(PIN_PD27, 1, 2)
#define PIN_PD27__FLEXCOM5_IO2 PINMUX_PIN(PIN_PD27, 2, 2)
#define PIN_PD27__TIOA0 PINMUX_PIN(PIN_PD27, 3, 3)
#define PIN_PD27__TK1 PINMUX_PIN(PIN_PD27, 4, 2)
#define PIN_PD27__ISC_D3 PINMUX_PIN(PIN_PD27, 5, 2)
#define PIN_PD27__G1_RXER PINMUX_PIN(PIN_PD27, 7, 1)
#define PIN_PD28 124
#define PIN_PD28__GPIO PINMUX_PIN(PIN_PD28, 0, 0)
#define PIN_PD28__RD0 PINMUX_PIN(PIN_PD28, 1, 2)
#define PIN_PD28__FLEXCOM5_IO3 PINMUX_PIN(PIN_PD28, 2, 2)
#define PIN_PD28__TIOB0 PINMUX_PIN(PIN_PD28, 3, 3)
#define PIN_PD28__I2SMCC1_CK PINMUX_PIN(PIN_PD28, 4, 2)
#define PIN_PD28__ISC_D4 PINMUX_PIN(PIN_PD28, 5, 2)
#define PIN_PD28__PWML3 PINMUX_PIN(PIN_PD28, 6, 5)
#define PIN_PD28__G1_MDC PINMUX_PIN(PIN_PD28, 7, 1)
#define PIN_PD29 125
#define PIN_PD29__GPIO PINMUX_PIN(PIN_PD29, 0, 0)
#define PIN_PD29__RF0 PINMUX_PIN(PIN_PD29, 1, 2)
#define PIN_PD29__FLEXCOM5_IO4 PINMUX_PIN(PIN_PD29, 2, 2)
#define PIN_PD29__TCLK0 PINMUX_PIN(PIN_PD29, 3, 3)
#define PIN_PD29__I2SMCC1_WS PINMUX_PIN(PIN_PD29, 4, 2)
#define PIN_PD29__ISC_D5 PINMUX_PIN(PIN_PD29, 5, 2)
#define PIN_PD29__PWMH3 PINMUX_PIN(PIN_PD29, 6, 5)
#define PIN_PD29__G1_MDIO PINMUX_PIN(PIN_PD29, 7, 1)
#define PIN_PD30 126
#define PIN_PD30__GPIO PINMUX_PIN(PIN_PD30, 0, 0)
#define PIN_PD30__RK0 PINMUX_PIN(PIN_PD30, 1, 2)
#define PIN_PD30__FLEXCOM6_IO0 PINMUX_PIN(PIN_PD30, 2, 2)
#define PIN_PD30__TIOA1 PINMUX_PIN(PIN_PD30, 3, 3)
#define PIN_PD30__I2SMCC1_MCK PINMUX_PIN(PIN_PD30, 4, 2)
#define PIN_PD30__ISC_D6 PINMUX_PIN(PIN_PD30, 5, 2)
#define PIN_PD30__PWMEXTRG0 PINMUX_PIN(PIN_PD30, 6, 5)
#define PIN_PD30__G1_TXCK PINMUX_PIN(PIN_PD30, 7, 1)
#define PIN_PD31 127
#define PIN_PD31__GPIO PINMUX_PIN(PIN_PD31, 0, 0)
#define PIN_PD31__TD0 PINMUX_PIN(PIN_PD31, 1, 2)
#define PIN_PD31__FLEXCOM6_IO1 PINMUX_PIN(PIN_PD31, 2, 2)
#define PIN_PD31__TIOB1 PINMUX_PIN(PIN_PD31, 3, 3)
#define PIN_PD31__I2SMCC1_DOUT0 PINMUX_PIN(PIN_PD31, 4, 2)
#define PIN_PD31__ISC_D7 PINMUX_PIN(PIN_PD31, 5, 2)
#define PIN_PD31__PWM_EXTRG1 PINMUX_PIN(PIN_PD31, 6, 5)
#define PIN_PD31__G1_TX2 PINMUX_PIN(PIN_PD31, 7, 1)
#define PIN_PE0 128
#define PIN_PE0__GPIO PINMUX_PIN(PIN_PE0, 0, 0)
#define PIN_PE0__TF0 PINMUX_PIN(PIN_PE0, 1, 2)
#define PIN_PE0__FLEXCOM6_IO2 PINMUX_PIN(PIN_PE0, 2, 2)
#define PIN_PE0__TCLK1 PINMUX_PIN(PIN_PE0, 3, 3)
#define PIN_PE0__I2SMCC1_DOUT1 PINMUX_PIN(PIN_PE0, 4, 2)
#define PIN_PE0__ISC_HSYNC PINMUX_PIN(PIN_PE0, 5, 2)
#define PIN_PE0__PWMFI0 PINMUX_PIN(PIN_PE0, 6, 5)
#define PIN_PE0__G1_TX3 PINMUX_PIN(PIN_PE0, 7, 1)
#define PIN_PE1 129
#define PIN_PE1__GPIO PINMUX_PIN(PIN_PE1, 0, 0)
#define PIN_PE1__TK0 PINMUX_PIN(PIN_PE1, 1, 2)
#define PIN_PE1__FLEXCOM6_IO3 PINMUX_PIN(PIN_PE1, 2, 2)
#define PIN_PE1__TIOA2 PINMUX_PIN(PIN_PE1, 3, 3)
#define PIN_PE1__I2SMCC1_DOUT2 PINMUX_PIN(PIN_PE1, 4, 2)
#define PIN_PE1__ISC_VSYNC PINMUX_PIN(PIN_PE1, 5, 2)
#define PIN_PE1__PWMFI1 PINMUX_PIN(PIN_PE1, 6, 5)
#define PIN_PE1__G1_RX2 PINMUX_PIN(PIN_PE1, 7, 1)
#define PIN_PE2 130
#define PIN_PE2__GPIO PINMUX_PIN(PIN_PE2, 0, 0)
#define PIN_PE2__PWML0 PINMUX_PIN(PIN_PE2, 1, 5)
#define PIN_PE2__FLEXCOM6_IO4 PINMUX_PIN(PIN_PE2, 2, 2)
#define PIN_PE2__TIOB2 PINMUX_PIN(PIN_PE2, 3, 3)
#define PIN_PE2__I2SMCC1_DOUT3 PINMUX_PIN(PIN_PE2, 4, 2)
#define PIN_PE2__ISC_FIELD PINMUX_PIN(PIN_PE2, 5, 2)
#define PIN_PE2__G1_RX3 PINMUX_PIN(PIN_PE2, 7, 1)
#define PIN_PE3 131
#define PIN_PE3__GPIO PINMUX_PIN(PIN_PE3, 0, 0)
#define PIN_PE3__PWMH0 PINMUX_PIN(PIN_PE3, 1, 5)
#define PIN_PE3__FLEXCOM0_IO0 PINMUX_PIN(PIN_PE3, 2, 4)
#define PIN_PE3__TCLK2 PINMUX_PIN(PIN_PE3, 3, 3)
#define PIN_PE3__I2SMCC1_DIN0 PINMUX_PIN(PIN_PE3, 4, 2)
#define PIN_PE3__ISC_PCK PINMUX_PIN(PIN_PE3, 5, 2)
#define PIN_PE3__G1_RXCK PINMUX_PIN(PIN_PE3, 7, 1)
#define PIN_PE4 132
#define PIN_PE4__GPIO PINMUX_PIN(PIN_PE4, 0, 0)
#define PIN_PE4__PWML1 PINMUX_PIN(PIN_PE4, 1, 5)
#define PIN_PE4__FLEXCOM0_IO1 PINMUX_PIN(PIN_PE4, 2, 4)
#define PIN_PE4__TIOA3 PINMUX_PIN(PIN_PE4, 3, 3)
#define PIN_PE4__I2SMCC1_DIN1 PINMUX_PIN(PIN_PE4, 4, 2)
#define PIN_PE4__ISC_D8 PINMUX_PIN(PIN_PE4, 5, 2)
#define PIN_PE4__G1_TXER PINMUX_PIN(PIN_PE4, 7, 1)
#define PIN_PE5 133
#define PIN_PE5__GPIO PINMUX_PIN(PIN_PE5, 0, 0)
#define PIN_PE5__PWMH1 PINMUX_PIN(PIN_PE5, 1, 5)
#define PIN_PE5__FLEXCOM0_IO2 PINMUX_PIN(PIN_PE5, 2, 4)
#define PIN_PE5__TIOB3 PINMUX_PIN(PIN_PE5, 3, 3)
#define PIN_PE5__I2SMCC1_DIN2 PINMUX_PIN(PIN_PE5, 4, 2)
#define PIN_PE5__ISC_D9 PINMUX_PIN(PIN_PE5, 5, 2)
#define PIN_PE5__G1_COL PINMUX_PIN(PIN_PE5, 7, 1)
#define PIN_PE6 134
#define PIN_PE6__GPIO PINMUX_PIN(PIN_PE6, 0, 0)
#define PIN_PE6__PWML2 PINMUX_PIN(PIN_PE6, 1, 5)
#define PIN_PE6__FLEXCOM0_IO3 PINMUX_PIN(PIN_PE6, 2, 4)
#define PIN_PE6__TCLK3 PINMUX_PIN(PIN_PE6, 3, 3)
#define PIN_PE6__I2SMCC1_DIN3 PINMUX_PIN(PIN_PE6, 4, 2)
#define PIN_PE6__ISC_D10 PINMUX_PIN(PIN_PE6, 5, 2)
#define PIN_PE6__G1_CRS PINMUX_PIN(PIN_PE6, 7, 1)
#define PIN_PE7 135
#define PIN_PE7__GPIO PINMUX_PIN(PIN_PE7, 0, 0)
#define PIN_PE7__PWMH2 PINMUX_PIN(PIN_PE7, 1, 5)
#define PIN_PE7__FLEXCOM0_IO4 PINMUX_PIN(PIN_PE7, 2, 4)
#define PIN_PE7__TIOA4 PINMUX_PIN(PIN_PE7, 3, 3)
#define PIN_PE7__ISC_D11 PINMUX_PIN(PIN_PE7, 5, 2)
#define PIN_PE7__G1_TSUCOMP PINMUX_PIN(PIN_PE7, 7, 1)

263
arch/arm/dts/stm32mp15-pinctrl.dtsi
View file

@ -1573,6 +1573,20 @@
};
};
spi4_pins_a: spi4-0 {
pins {
pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
<STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
bias-disable;
};
};
stusb1600_pins_a: stusb1600-0 {
pins {
pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
@ -1580,6 +1594,133 @@
};
};
uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
bias-disable;
};
};
uart4_idle_pins_a: uart4-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
};
pins2 {
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
bias-disable;
};
};
uart4_sleep_pins_a: uart4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */
<STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
};
};
uart4_pins_b: uart4-1 {
pins1 {
pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
bias-disable;
};
};
uart4_pins_c: uart4-2 {
pins1 {
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
bias-disable;
};
};
uart7_pins_a: uart7-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART7_RX */
<STM32_PINMUX('E', 10, AF7)>, /* UART7_CTS */
<STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */
bias-disable;
};
};
uart7_pins_b: uart7-1 {
pins1 {
pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */
bias-disable;
};
};
uart7_pins_c: uart7-2 {
pins1 {
pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
bias-disable;
};
};
uart7_idle_pins_c: uart7-idle-2 {
pins1 {
pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* UART7_TX */
};
pins2 {
pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
bias-disable;
};
};
uart7_sleep_pins_c: uart7-sleep-2 {
pins {
pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* UART7_TX */
<STM32_PINMUX('E', 7, ANALOG)>; /* UART7_RX */
};
};
uart8_pins_a: uart8-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */
bias-disable;
};
};
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
@ -1628,6 +1769,42 @@
};
};
usart2_pins_c: usart2-2 {
pins1 {
pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */
<STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <3>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
<STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
bias-disable;
};
};
usart2_idle_pins_c: usart2-idle-2 {
pins1 {
pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
<STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
<STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
};
pins2 {
pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
bias-disable;
};
};
usart2_sleep_pins_c: usart2-sleep-2 {
pins {
pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
<STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
<STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */
<STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
};
};
usart3_pins_a: usart3-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
@ -1641,6 +1818,78 @@
};
};
usart3_pins_b: usart3-1 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
<STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
<STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
bias-disable;
};
};
usart3_idle_pins_b: usart3-idle-1 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
<STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
<STM32_PINMUX('I', 10, ANALOG)>; /* USART3_CTS_NSS */
};
pins2 {
pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
bias-disable;
};
};
usart3_sleep_pins_b: usart3-sleep-1 {
pins {
pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
<STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
<STM32_PINMUX('I', 10, ANALOG)>, /* USART3_CTS_NSS */
<STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
};
};
usart3_pins_c: usart3-2 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
<STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
<STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
bias-disable;
};
};
usart3_idle_pins_c: usart3-idle-2 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
<STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
<STM32_PINMUX('B', 13, ANALOG)>; /* USART3_CTS_NSS */
};
pins2 {
pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
bias-disable;
};
};
usart3_sleep_pins_c: usart3-sleep-2 {
pins {
pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
<STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
<STM32_PINMUX('B', 13, ANALOG)>, /* USART3_CTS_NSS */
<STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
};
};
uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
@ -1782,18 +2031,4 @@
bias-disable;
};
};
spi4_pins_a: spi4-0 {
pins {
pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
<STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
bias-disable;
};
};
};

4
arch/arm/dts/stm32mp151.dtsi
View file

@ -1153,7 +1153,7 @@
};
pwr_mcu: pwr_mcu@50001014 {
compatible = "syscon";
compatible = "st,stm32mp151-pwr-mcu", "syscon";
reg = <0x50001014 0x4>;
};
@ -1372,6 +1372,8 @@
dma-names = "tx", "rx";
clocks = <&rcc QSPI_K>;
resets = <&rcc QSPI_R>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};

2
arch/arm/dts/stm32mp157a-dk1.dts
View file

@ -18,6 +18,8 @@
aliases {
ethernet0 = &ethernet0;
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart7;
};
chosen {

11
arch/arm/dts/stm32mp157c-dk2.dts
View file

@ -19,6 +19,9 @@
aliases {
ethernet0 = &ethernet0;
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart7;
serial3 = &usart2;
};
chosen {
@ -84,3 +87,11 @@
};
};
};
&usart2 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&usart2_pins_c>;
pinctrl-1 = <&usart2_sleep_pins_c>;
pinctrl-2 = <&usart2_idle_pins_c>;
status = "disabled";
};

4
arch/arm/dts/stm32mp157c-ed1.dts
View file

@ -361,8 +361,10 @@
};
&uart4 {
pinctrl-names = "default";
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
status = "okay";
};

15
arch/arm/dts/stm32mp157c-ev1.dts
View file

@ -19,6 +19,7 @@
aliases {
serial0 = &uart4;
serial1 = &usart3;
ethernet0 = &ethernet0;
};
@ -343,6 +344,20 @@
};
};
&usart3 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&usart3_pins_b>;
pinctrl-1 = <&usart3_sleep_pins_b>;
pinctrl-2 = <&usart3_idle_pins_b>;
/*
* HW flow control USART3_RTS is optional, and isn't default wired to
* the connector. SB23 needs to be soldered in order to use it, and R77
* (ETH_CLK) should be removed.
*/
uart-has-rtscts;
status = "disabled";
};
&usbh_ehci {
phys = <&usbphyc_port0>;
status = "okay";

38
arch/arm/dts/stm32mp15xx-dkx.dtsi
View file

@ -62,7 +62,7 @@
led {
compatible = "gpio-leds";
blue {
led-blue {
label = "heartbeat";
gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
@ -391,6 +391,19 @@
};
};
&i2c5 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c5_pins_a>;
pinctrl-1 = <&i2c5_sleep_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
clock-frequency = <400000>;
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
};
&i2s2 {
clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
clock-names = "pclk", "i2sclk", "x8k", "x11k";
@ -610,20 +623,39 @@
};
&uart4 {
pinctrl-names = "default";
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
status = "okay";
};
&uart7 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&uart7_pins_c>;
pinctrl-1 = <&uart7_sleep_pins_c>;
pinctrl-2 = <&uart7_idle_pins_c>;
status = "disabled";
};
&usart3 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&usart3_pins_c>;
pinctrl-1 = <&usart3_sleep_pins_c>;
pinctrl-2 = <&usart3_idle_pins_c>;
uart-has-rtscts;
status = "disabled";
};
&usbh_ehci {
phys = <&usbphyc_port0>;
status = "okay";
};
&usbotg_hs {
dr_mode = "peripheral";
phys = <&usbphyc_port1 0>;
phy-names = "usb2-phy";
usb-role-switch;
status = "okay";
};

62
arch/arm/dts/sunxi-u-boot.dtsi
View file

@ -5,14 +5,74 @@
mmc1 = &mmc2;
};
binman {
binman: binman {
multiple-images;
};
};
&binman {
u-boot-sunxi-with-spl {
filename = "u-boot-sunxi-with-spl.bin";
pad-byte = <0xff>;
blob {
filename = "spl/sunxi-spl.bin";
};
#ifdef CONFIG_ARM64
fit {
description = "Configuration to load ATF before U-Boot";
#address-cells = <1>;
fit,fdt-list = "of-list";
images {
uboot {
description = "U-Boot (64-bit)";
type = "standalone";
arch = "arm64";
compression = "none";
load = <0x4a000000>;
u-boot-nodtb {
};
};
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
/* TODO: Do this with an overwrite in this board's dtb? */
#ifdef CONFIG_MACH_SUN50I_H6
load = <0x104000>;
entry = <0x104000>;
#else
load = <0x44000>;
entry = <0x44000>;
#endif
atf-bl31 {
missing-msg = "atf-bl31-sunxi";
};
};
@fdt-SEQ {
description = "NAME";
type = "flat_dt";
compression = "none";
};
};
configurations {
default = "config-1";
@config-SEQ {
description = "NAME";
firmware = "uboot";
loadables = "atf";
fdt = "fdt-SEQ";
};
};
};
#else
u-boot-img {
offset = <CONFIG_SPL_PAD_TO>;
};
#endif
};
};

33
arch/arm/dts/zynqmp-e-a2197-00-revA.dts
View file

@ -230,16 +230,16 @@
#io-channel-cells = <1>;
label = "ina226-vccint";
reg = <0x40>;
shunt-resistor = <5000>; /* R440 */
/* 0.78V @ 32A 1 of 6 Phases*/
shunt-resistor = <500>; /* R440 */
/* 0.80V @ 32A 1 of 6 Phases*/
};
vcc_soc: ina226@41 { /* u161 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-vcc-soc";
reg = <0x41>;
shunt-resistor = <2000>; /* R1186 */
/* 0.78V @ 18A */
shunt-resistor = <500>; /* R1702 */
/* 0.80V @ 18A */
};
vcc_pmc: ina226@42 { /* u163 */
compatible = "ti,ina226";
@ -554,6 +554,31 @@
reg = <7>;
};
};
i2c-mux@75 { /* u214 */
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x75>;
i2c@0 { /* SFP0_IIC */
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
/* SFP0 */
};
i2c@1 { /* SFP1_IIC */
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
/* SFP1 */
};
i2c@2 { /* QSFP1_I2C */
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
/* QSFP1 */
};
/* 3 - 7 unused */
};
};
&xilinx_ams {

8
arch/arm/lib/crt0_64.S
View file

@ -73,7 +73,12 @@ ENTRY(_main)
#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr x0, =(CONFIG_SPL_STACK)
#elif defined(CONFIG_INIT_SP_RELATIVE)
#if CONFIG_POSITION_INDEPENDENT
adrp x0, __bss_start /* x0 <- Runtime &__bss_start */
add x0, x0, #:lo12:__bss_start
#else
adr x0, __bss_start
#endif
add x0, x0, #CONFIG_SYS_INIT_SP_BSS_OFFSET
#else
ldr x0, =(CONFIG_SYS_INIT_SP_ADDR)
@ -102,7 +107,8 @@ ENTRY(_main)
adr lr, relocation_return
#if CONFIG_POSITION_INDEPENDENT
/* Add in link-vs-runtime offset */
adr x0, _start /* x0 <- Runtime value of _start */
adrp x0, _start /* x0 <- Runtime value of _start */
add x0, x0, #:lo12:_start
ldr x9, _TEXT_BASE /* x9 <- Linked value of _start */
sub x9, x9, x0 /* x9 <- Run-vs-link offset */
add lr, lr, x9

2
arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
View file

@ -19,7 +19,7 @@
#include <asm/arch/wdt.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <dt-bindings/clock/ast2500-scu.h>
#include <dt-bindings/clock/aspeed-clock.h>
/* These configuration parameters are taken from Aspeed SDK */
#define DDR4_MR46_MODE 0x08000000

4
arch/arm/mach-at91/Kconfig
View file

@ -47,6 +47,10 @@ config SAM9X60
bool
select CPU_ARM926EJS
config SAMA7G5
bool
select CPU_V7A
config SAMA5D2
bool
select CPU_V7A

1
arch/arm/mach-at91/armv7/Makefile
View file

@ -9,6 +9,7 @@
obj-$(CONFIG_SAMA5D2) += sama5d2_devices.o
obj-$(CONFIG_SAMA5D3) += sama5d3_devices.o
obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o
obj-$(CONFIG_SAMA7G5) += sama7g5_devices.o
obj-y += clock.o
obj-y += cpu.o
obj-y += reset.o

2
arch/arm/mach-at91/armv7/cpu.c
View file

@ -29,6 +29,7 @@ int arch_cpu_init(void)
void arch_preboot_os(void)
{
#if (IS_ENABLED(CONFIG_ATMEL_PIT_TIMER))
ulong cpiv;
at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
@ -40,6 +41,7 @@ void arch_preboot_os(void)
* without waiting for wrapping back to 0
*/
writel(cpiv + 0x1000, &pit->mr);
#endif
}
#if defined(CONFIG_DISPLAY_CPUINFO)

11
arch/arm/mach-at91/armv7/sama7g5_devices.c Normal file
View file

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2020 Microchip Technology, Inc.
* Eugen Hristev <eugen.hristev@microchip.com>
*/
char *get_cpu_name(void)
{
return "SAMA7G5";
}

1
arch/arm/mach-at91/include/mach/at91_common.h
View file

@ -40,6 +40,7 @@ void configure_ddrcfg_input_buffers(bool open);
#endif
int at91_set_ethaddr(int offset);
int at91_set_eth1addr(int offset);
void at91_spi_nor_set_ethaddr(void);
int at91_video_show_board_info(void);

2
arch/arm/mach-at91/include/mach/hardware.h
View file

@ -24,6 +24,8 @@
# include <asm/arch/at91sam9x5.h>
#elif defined(CONFIG_SAM9X60)
# include <asm/arch/sam9x60.h>
#elif defined(CONFIG_SAMA7G5)
# include <asm/arch/sama7g5.h>
#elif defined(CONFIG_SAMA5D2)
# include <asm/arch/sama5d2.h>
#elif defined(CONFIG_SAMA5D3)

74
arch/arm/mach-at91/include/mach/sama7g5.h Normal file
View file

@ -0,0 +1,74 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Chip-specific header file for the SAMA7G5 SoC
*
* Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries
* Eugen Hristev <eugen.hristev@microchip.com>
*/
#ifndef __SAMA7G5_H__
#define __SAMA7G5_H__
/*
* Peripheral identifiers/interrupts.
*/
#define ATMEL_ID_FLEXCOM0 38
#define ATMEL_ID_FLEXCOM1 39
#define ATMEL_ID_FLEXCOM2 40
#define ATMEL_ID_FLEXCOM3 41
#define ATMEL_ID_SDMMC0 80
#define ATMEL_ID_SDMMC1 81
#define ATMEL_ID_PIT64B0 70
#define ATMEL_ID_PIT64B ATMEL_ID_PIT64B0
#define ATMEL_CHIPID_CIDR 0xe0020000
#define ATMEL_CHIPID_EXID 0xe0020004
/*
* User Peripherals physical base addresses.
*/
#define ATMEL_BASE_PIOA 0xe0014000
#define ATMEL_BASE_PIOB (ATMEL_BASE_PIOA + 0x40)
#define ATMEL_BASE_PIOC (ATMEL_BASE_PIOB + 0x40)
#define ATMEL_BASE_PIOD (ATMEL_BASE_PIOC + 0x40)
#define ATMEL_BASE_PIOE (ATMEL_BASE_PIOD + 0x40)
#define ATMEL_PIO_PORTS 5
#define CPU_HAS_PCR
#define ATMEL_BASE_PMC 0xe0018000
#define ATMEL_BASE_WDT 0xe001c000
#define ATMEL_BASE_RSTC 0xe001d000
#define ATMEL_BASE_WDTS 0xe001d180
#define ATMEL_BASE_SCKCR 0xe001d050
#define ATMEL_BASE_SDMMC0 0xe1204000
#define ATMEL_BASE_SDMMC1 0xe1208000
#define ATMEL_BASE_PIT64B0 0xe1800000
#define ATMEL_BASE_FLEXCOM0 0xe1818000
#define ATMEL_BASE_FLEXCOM1 0xe181c000
#define ATMEL_BASE_FLEXCOM2 0xe1820000
#define ATMEL_BASE_FLEXCOM3 0xe1824000
#define ATMEL_BASE_FLEXCOM4 0xe2018000
#define ATMEL_BASE_TZC400 0xe3000000
#define ATMEL_BASE_UMCTL2 0xe3800000
#define ATMEL_BASE_UMCTL2_MP 0xe38003f8
#define ATMEL_BASE_PUBL 0xe3804000
#define ATMEL_NUM_FLEXCOM 12
#define ATMEL_PIO_PORTS 5
#define ATMEL_BASE_PIT64BC ATMEL_BASE_PIT64B0
#ifndef __ASSEMBLY__
char *get_cpu_name(void);
#endif
#endif /* #ifndef __SAMA7G5_H__ */

4
arch/arm/mach-ipq40xx/clock-ipq4019.c
View file

@ -13,6 +13,8 @@
#include <dm.h>
#include <errno.h>
#include <dt-bindings/clock/qcom,ipq4019-gcc.h>
struct msm_clk_priv {
phys_addr_t base;
};
@ -20,7 +22,7 @@ struct msm_clk_priv {
ulong msm_set_rate(struct clk *clk, ulong rate)
{
switch (clk->id) {
case 26: /*UART1*/
case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/
/* This clock is already initialized by SBL1 */
return 0;
break;

59
arch/arm/mach-k3/arm64-mmu.c
View file

@ -2,8 +2,9 @@
/*
* K3: ARM64 MMU setup
*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
* Suman Anna <s-anna@ti.com>
* (This file is derived from arch/arm/mach-zynqmp/cpu.c)
*
*/
@ -66,6 +67,8 @@ struct mm_region *mem_map = am654_mem_map;
#endif /* CONFIG_SOC_K3_AM6 */
#ifdef CONFIG_SOC_K3_J721E
#ifdef CONFIG_TARGET_J721E_A72_EVM
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6)
@ -122,4 +125,58 @@ struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
};
struct mm_region *mem_map = j721e_mem_map;
#endif /* CONFIG_TARGET_J721E_A72_EVM */
#ifdef CONFIG_TARGET_J7200_A72_EVM
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
/* ToDo: Add 64bit IO */
struct mm_region j7200_mem_map[NR_MMU_REGIONS] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xa0000000UL,
.phys = 0xa0000000UL,
.size = 0x04800000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_NON_SHARE
}, {
.virt = 0xa4800000UL,
.phys = 0xa4800000UL,
.size = 0x5b800000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x880000000UL,
.phys = 0x880000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x500000000UL,
.phys = 0x500000000UL,
.size = 0x400000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = j7200_mem_map;
#endif /* CONFIG_TARGET_J7200_A72_EVM */
#endif /* CONFIG_SOC_K3_J721E */

1
arch/arm/mach-k3/include/mach/j721e_spl.h
View file

@ -15,6 +15,7 @@
#define BOOT_DEVICE_ETHERNET 0x04
#define BOOT_DEVICE_I2C 0x06
#define BOOT_DEVICE_UART 0x07
#define BOOT_DEVICE_NOR BOOT_DEVICE_HYPERFLASH
/* With BootMode B = 1 */
#define BOOT_DEVICE_MMC2 0x10

8
arch/arm/mach-meson/board-gx.c
View file

@ -196,8 +196,8 @@ int board_usb_init(int index, enum usb_init_type init)
for (i = 0; i < 2; i++) {
ret = generic_phy_init(&usb_phys[i]);
if (ret) {
pr_err("Can't init USB PHY%d for %s\n",
i, ofnode_get_name(dwc2_node));
pr_debug("Can't init USB PHY%d for %s\n",
i, ofnode_get_name(dwc2_node));
return ret;
}
}
@ -205,8 +205,8 @@ int board_usb_init(int index, enum usb_init_type init)
for (i = 0; i < 2; i++) {
ret = generic_phy_power_on(&usb_phys[i]);
if (ret) {
pr_err("Can't power USB PHY%d for %s\n",
i, ofnode_get_name(dwc2_node));
pr_debug("Can't power USB PHY%d for %s\n",
i, ofnode_get_name(dwc2_node));
return ret;
}
}

18
arch/arm/mach-omap2/am33xx/board.c
View file

@ -14,6 +14,7 @@
#include <init.h>
#include <net.h>
#include <ns16550.h>
#include <omap3_spi.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
@ -49,6 +50,12 @@
#define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC
#define AM43XX_RDWRLVLFULL_START 0x80000000
/* SPI flash. */
#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
#define AM33XX_SPI0_BASE 0x48030000
#define AM33XX_SPI0_OFFSET (AM33XX_SPI0_BASE + OMAP4_MCSPI_REG_OFFSET)
#endif
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
@ -142,6 +149,17 @@ U_BOOT_DEVICES(am33xx_gpios) = {
#endif
};
#endif
#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
static const struct omap3_spi_plat omap3_spi_pdata = {
.regs = (struct mcspi *)AM33XX_SPI0_OFFSET,
.pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT,
};
U_BOOT_DEVICE(am33xx_spi) = {
.name = "omap3_spi",
.platdata = &omap3_spi_pdata,
};
#endif
#endif
#if !CONFIG_IS_ENABLED(DM_GPIO)

9
arch/arm/mach-rmobile/cpu_info-rcar.c
View file

@ -10,6 +10,7 @@
#define PRR_MASK 0x7fff
#define R8A7796_REV_1_0 0x5200
#define R8A7796_REV_1_1 0x5210
#define R8A7796_REV_1_3 0x5211
static u32 rmobile_get_prr(void)
{
@ -28,8 +29,9 @@ u32 rmobile_get_cpu_type(void)
u32 rmobile_get_cpu_rev_integer(void)
{
const u32 prr = rmobile_get_prr();
const u32 rev = prr & PRR_MASK;
if ((prr & PRR_MASK) == R8A7796_REV_1_1)
if (rev == R8A7796_REV_1_1 || rev == R8A7796_REV_1_3)
return 1;
else
return ((prr & 0x000000F0) >> 4) + 1;
@ -38,9 +40,12 @@ u32 rmobile_get_cpu_rev_integer(void)
u32 rmobile_get_cpu_rev_fraction(void)
{
const u32 prr = rmobile_get_prr();
const u32 rev = prr & PRR_MASK;
if ((prr & PRR_MASK) == R8A7796_REV_1_1)
if (rev == R8A7796_REV_1_1)
return 1;
else if (rev == R8A7796_REV_1_3)
return 3;
else
return prr & 0x0000000F;
}

6
arch/arm/mach-rmobile/lowlevel_init_gen3.S
View file

@ -31,6 +31,12 @@ ENTRY(save_boot_params)
b save_boot_params_ret
ENDPROC(save_boot_params)
.pushsection .text.s_init, "ax"
WEAK(s_init)
ret
ENDPROC(s_init)
.popsection
ENTRY(lowlevel_init)
mov x29, lr /* Save LR */

3
arch/arm/mach-versal/Kconfig
View file

@ -62,4 +62,7 @@ config VERSAL_NO_DDR
This option configures MMU with no DDR to avoid speculative
access to DDR memory where DDR is not present.
source "board/xilinx/Kconfig"
source "board/xilinx/versal/Kconfig"
endif

3
arch/arm/mach-zynq/Kconfig
View file

@ -70,4 +70,7 @@ config BOOT_INIT_FILE
config ZYNQ_SDHCI_MAX_FREQ
default 52000000
source "board/xilinx/Kconfig"
source "board/xilinx/zynq/Kconfig"
endif

6
arch/arm/mach-zynq/cpu.c
View file

@ -17,8 +17,7 @@
#define ZYNQ_SILICON_VER_MASK 0xF0000000
#define ZYNQ_SILICON_VER_SHIFT 28
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
#if CONFIG_IS_ENABLED(FPGA)
xilinx_desc fpga = {
.family = xilinx_zynq,
.iface = devcfg,
@ -111,8 +110,7 @@ static int __maybe_unused cpu_desc_id(void)
#if defined(CONFIG_ARCH_EARLY_INIT_R)
int arch_early_init_r(void)
{
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
#if CONFIG_IS_ENABLED(FPGA)
int cpu_id = cpu_desc_id();
if (cpu_id < 0)

2
arch/arm/mach-zynq/spl.c
View file

@ -34,7 +34,7 @@ void board_init_f(ulong dummy)
void spl_board_init(void)
{
preloader_console_init();
#if defined(CONFIG_ARCH_EARLY_INIT_R) && defined(CONFIG_SPL_FPGA_SUPPORT)
#if defined(CONFIG_ARCH_EARLY_INIT_R) && defined(CONFIG_SPL_FPGA)
arch_early_init_r();
#endif
board_init();

11
arch/arm/mach-zynqmp-r5/cpu.c
View file

@ -11,11 +11,9 @@
DECLARE_GLOBAL_DATA_PTR;
struct mpu_region_config region_config[] = {
{ 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
O_I_WB_RD_WR_ALLOC, REGION_1GB },
{ 0x20000000, REGION_1, XN_EN, PRIV_RO_USR_RO,
O_I_WB_RD_WR_ALLOC, REGION_512MB },
{ 0x40000000, REGION_2, XN_EN, PRIV_RO_USR_RO,
{ 0x00000000, REGION_0, XN_EN, PRIV_RW_USR_RW,
SHARED_WRITE_BUFFERED, REGION_4GB },
{ 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
O_I_WB_RD_WR_ALLOC, REGION_1GB },
};
@ -23,8 +21,7 @@ int arch_cpu_init(void)
{
gd->cpu_clk = CONFIG_CPU_FREQ_HZ;
setup_mpu_regions(region_config, sizeof(region_config) /
sizeof(struct mpu_region_config));
setup_mpu_regions(region_config, ARRAY_SIZE(region_config));
return 0;
}

3
arch/arm/mach-zynqmp/Kconfig
View file

@ -171,4 +171,7 @@ config SD1_LSHFT_MODE
endchoice
source "board/xilinx/Kconfig"
source "board/xilinx/zynqmp/Kconfig"
endif

2
arch/arm/mach-zynqmp/handoff.c
View file

@ -65,7 +65,7 @@ struct xfsbl_atf_handoff_params {
struct xfsbl_partition partition[FSBL_MAX_PARTITIONS];
};
#ifdef CONFIG_SPL_OS_BOOT
#ifdef CONFIG_SPL_ATF
struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry,
uintptr_t bl33_entry,
uintptr_t fdt_addr)

22
arch/microblaze/include/asm/io.h
View file

@ -50,14 +50,24 @@
#define outw(x, addr) ((void)writew(x, addr))
#define outl(x, addr) ((void)writel(x, addr))
/* Some #definitions to keep strange Xilinx code happy */
#define in_8(addr) readb(addr)
#define in_be16(addr) readw(addr)
#define in_be32(addr) readl(addr)
#define out_arch(type, endian, addr, x) \
__raw_write##type(cpu_to_##endian(x), addr)
#define in_arch(type, endian, addr) \
endian##_to_cpu(__raw_read##type(addr))
#define out_le16(addr, x) out_arch(w, le16, addr, x)
#define out_le32(addr, x) out_arch(l, le32, addr, x)
#define in_le16(addr) in_arch(w, le16, addr)
#define in_le32(addr) in_arch(l, le32, addr)
#define in_8(addr) readb(addr)
#define in_be16(addr) in_arch(w, be16, addr)
#define in_be32(addr) in_arch(l, be32, addr)
#define out_8(addr, x) outb(x, addr)
#define out_be16(addr, x) outw(x, addr)
#define out_be32(addr, x) outl(x, addr)
#define out_be16(addr, x) out_arch(w, be16, addr, x)
#define out_be32(addr, x) out_arch(l, be32, addr, x)
#define inb_p(port) inb((port))
#define outb_p(val, port) outb((val), (port))

2
arch/mips/lib/boot.c
View file

@ -17,7 +17,7 @@ unsigned long do_go_exec(ulong (*entry)(int, char * const []),
* whole SDRAM area, since we don't know the size of the image
* that was loaded.
*/
flush_cache(gd->bd->bi_memstart, gd->ram_top - gd->bd->bi_memstart);
flush_cache(gd->ram_base, gd->ram_top - gd->ram_base);
return entry(argc, argv);
}

2
arch/mips/lib/bootm.c
View file

@ -242,7 +242,7 @@ static int boot_reloc_fdt(bootm_headers_t *images)
#if CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && CONFIG_IS_ENABLED(OF_LIBFDT)
int arch_fixup_fdt(void *blob)
{
u64 mem_start = virt_to_phys((void *)gd->bd->bi_memstart);
u64 mem_start = virt_to_phys((void *)gd->ram_base);
u64 mem_size = gd->ram_size;
return fdt_fixup_memory_banks(blob, &mem_start, &mem_size, 1);

8
arch/powerpc/cpu/mpc83xx/Kconfig
View file

@ -101,34 +101,42 @@ config TARGET_IDS8313
config TARGET_KMETER1
bool "Support kmeter1"
select VENDOR_KM
select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_KMCOGE5NE
bool "Support kmcoge5ne"
select VENDOR_KM
select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_KMTEGR1
bool "Support kmtegr1"
select VENDOR_KM
select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_TUXX1
bool "Support tuxx1"
select VENDOR_KM
select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_KMSUPX5
bool "Support kmsupx5"
select VENDOR_KM
select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_TUGE1
bool "Support tuge1"
select VENDOR_KM
select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_KMOPTI2
bool "Support kmopti2"
select VENDOR_KM
select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_KMTEPR2
bool "Support kmtepr2"
select VENDOR_KM
select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_TQM834X
bool "Support TQM834x"

2
arch/powerpc/cpu/mpc83xx/Makefile
View file

@ -27,7 +27,9 @@ obj-y += cpu_init.o
obj-y += speed.o
obj-y += interrupts.o
obj-y += ecc.o
ifndef CONFIG_PINCTRL
obj-$(CONFIG_QE) += qe_io.o
endif
obj-$(CONFIG_FSL_SERDES) += serdes.o
ifndef CONFIG_ARCH_MPC8308
obj-$(CONFIG_PCI) += pci.o

11
arch/powerpc/cpu/mpc83xx/cpu_init.c
View file

@ -9,10 +9,14 @@
#include <ioports.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <fsl_qe.h>
#ifdef CONFIG_USB_EHCI_FSL
#include <usb/ehci-ci.h>
#endif
#include <linux/delay.h>
#ifdef CONFIG_QE
#include <fsl_qe.h>
#endif
#include "lblaw/lblaw.h"
#include "elbc/elbc.h"
@ -26,9 +30,8 @@ DECLARE_GLOBAL_DATA_PTR;
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
int open_drain, int assign);
extern void qe_init(uint qe_base);
extern void qe_reset(void);
#if !defined(CONFIG_PINCTRL)
static void config_qe_ioports(void)
{
u8 port, pin;
@ -45,6 +48,7 @@ static void config_qe_ioports(void)
}
}
#endif
#endif
/*
* Breathe some life into the CPU...
@ -191,10 +195,13 @@ void cpu_init_f (volatile immap_t * im)
__raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
#endif
#if !defined(CONFIG_PINCTRL)
#ifdef CONFIG_QE
/* Config QE ioports */
config_qe_ioports();
#endif
#endif
/* Set up preliminary BR/OR regs */
init_early_memctl_regs();

2
arch/powerpc/cpu/mpc83xx/fdt.c
View file

@ -121,7 +121,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
"clock-frequency", get_serial_clock(), 1);
#endif
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
(defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X))

98
arch/powerpc/cpu/mpc83xx/qe_io.c
View file

@ -12,57 +12,93 @@
#include <asm/immap_83xx.h>
#define NUM_OF_PINS 32
void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
/** qe_cfg_iopin configure one io pin setting
*
* @par_io: pointer to parallel I/O base
* @port: io pin port
* @pin: io pin number which get configured
* @dir: direction of io pin 2 bits valid
* 00 = pin disabled
* 01 = output
* 10 = input
* 11 = pin is I/O
* @open_drain: is pin open drain
* @assign: pin assignment registers select the function of the pin
*/
static void qe_cfg_iopin(qepio83xx_t *par_io, u8 port, u8 pin, int dir,
int open_drain, int assign)
{
u32 pin_2bit_mask;
u32 pin_2bit_dir;
u32 pin_2bit_assign;
u32 pin_1bit_mask;
u32 tmp_val;
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio;
u32 dbit_mask;
u32 dbit_dir;
u32 dbit_asgn;
u32 bit_mask;
u32 tmp_val;
int offset;
offset = (NUM_OF_PINS - (pin % (NUM_OF_PINS / 2) + 1) * 2);
/* Calculate pin location and 2bit mask and dir */
pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
dbit_mask = (u32)(0x3 << offset);
dbit_dir = (u32)(dir << offset);
/* Setup the direction */
tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \
tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
in_be32(&par_io->ioport[port].dir2) :
in_be32(&par_io->ioport[port].dir1);
if (pin > (NUM_OF_PINS/2) -1) {
out_be32(&par_io->ioport[port].dir2, ~pin_2bit_mask & tmp_val);
out_be32(&par_io->ioport[port].dir2, pin_2bit_dir | tmp_val);
if (pin > (NUM_OF_PINS / 2) - 1) {
out_be32(&par_io->ioport[port].dir2, ~dbit_mask & tmp_val);
out_be32(&par_io->ioport[port].dir2, dbit_dir | tmp_val);
} else {
out_be32(&par_io->ioport[port].dir1, ~pin_2bit_mask & tmp_val);
out_be32(&par_io->ioport[port].dir1, pin_2bit_dir | tmp_val);
out_be32(&par_io->ioport[port].dir1, ~dbit_mask & tmp_val);
out_be32(&par_io->ioport[port].dir1, dbit_dir | tmp_val);
}
/* Calculate pin location for 1bit mask */
pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1)));
bit_mask = (u32)(1 << (NUM_OF_PINS - (pin + 1)));
/* Setup the open drain */
tmp_val = in_be32(&par_io->ioport[port].podr);
if (open_drain) {
out_be32(&par_io->ioport[port].podr, pin_1bit_mask | tmp_val);
} else {
out_be32(&par_io->ioport[port].podr, ~pin_1bit_mask & tmp_val);
}
if (open_drain)
out_be32(&par_io->ioport[port].podr, bit_mask | tmp_val);
else
out_be32(&par_io->ioport[port].podr, ~bit_mask & tmp_val);
/* Setup the assignment */
tmp_val = (pin > (NUM_OF_PINS/2) - 1) ?
in_be32(&par_io->ioport[port].ppar2):
tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
in_be32(&par_io->ioport[port].ppar2) :
in_be32(&par_io->ioport[port].ppar1);
pin_2bit_assign = (u32)(assign
<< (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2));
dbit_asgn = (u32)(assign << offset);
/* Clear and set 2 bits mask */
if (pin > (NUM_OF_PINS/2) - 1) {
out_be32(&par_io->ioport[port].ppar2, ~pin_2bit_mask & tmp_val);
out_be32(&par_io->ioport[port].ppar2, pin_2bit_assign | tmp_val);
if (pin > (NUM_OF_PINS / 2) - 1) {
out_be32(&par_io->ioport[port].ppar2, ~dbit_mask & tmp_val);
out_be32(&par_io->ioport[port].ppar2, dbit_asgn | tmp_val);
} else {
out_be32(&par_io->ioport[port].ppar1, ~pin_2bit_mask & tmp_val);
out_be32(&par_io->ioport[port].ppar1, pin_2bit_assign | tmp_val);
out_be32(&par_io->ioport[port].ppar1, ~dbit_mask & tmp_val);
out_be32(&par_io->ioport[port].ppar1, dbit_asgn | tmp_val);
}
}
#if !defined(CONFIG_PINCTRL)
/** qe_config_iopin configure one io pin setting
*
* @port: io pin port
* @pin: io pin number which get configured
* @dir: direction of io pin 2 bits valid
* 00 = pin disabled
* 01 = output
* 10 = input
* 11 = pin is I/O
* @open_drain: is pin open drain
* @assign: pin assignment registers select the function of the pin
*/
void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
qepio83xx_t *par_io = (qepio83xx_t *)&im->qepio;
qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign);
}
#endif

2
arch/powerpc/cpu/mpc83xx/traps.c
View file

@ -23,7 +23,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* Returns 0 if exception not found and fixup otherwise. */
extern unsigned long search_exception_table(unsigned long);
#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
#define END_OF_MEM (gd->ram_base + gd->ram_size)
/*
* Trap & Exception support

61
arch/powerpc/cpu/mpc85xx/Kconfig
View file

@ -40,14 +40,6 @@ config TARGET_P4080DS
imply CMD_SATA
imply PANIC_HANG
config TARGET_P5020DS
bool "Support P5020DS"
select PHYS_64BIT
select ARCH_P5020
select BOARD_LATE_INIT if CHAIN_OF_TRUST
imply CMD_SATA
imply PANIC_HANG
config TARGET_P5040DS
bool "Support P5040DS"
select PHYS_64BIT
@ -109,22 +101,6 @@ config TARGET_P1010RDB_PB
imply CMD_SATA
imply PANIC_HANG
config TARGET_P1023RDB
bool "Support P1023RDB"
select ARCH_P1023
select FSL_DDR_INTERACTIVE
imply CMD_EEPROM
imply PANIC_HANG
config TARGET_P1020MBG
bool "Support P1020MBG-PC"
select SUPPORT_SPL
select SUPPORT_TPL
select ARCH_P1020
imply CMD_EEPROM
imply CMD_SATA
imply PANIC_HANG
config TARGET_P1020RDB_PC
bool "Support P1020RDB-PC"
select SUPPORT_SPL
@ -143,42 +119,6 @@ config TARGET_P1020RDB_PD
imply CMD_SATA
imply PANIC_HANG
config TARGET_P1020UTM
bool "Support P1020UTM"
select SUPPORT_SPL
select SUPPORT_TPL
select ARCH_P1020
imply CMD_EEPROM
imply CMD_SATA
imply PANIC_HANG
config TARGET_P1021RDB
bool "Support P1021RDB"
select SUPPORT_SPL
select SUPPORT_TPL
select ARCH_P1021
imply CMD_EEPROM
imply CMD_SATA
imply PANIC_HANG
config TARGET_P1024RDB
bool "Support P1024RDB"
select SUPPORT_SPL
select SUPPORT_TPL
select ARCH_P1024
imply CMD_EEPROM
imply CMD_SATA
imply PANIC_HANG
config TARGET_P1025RDB
bool "Support P1025RDB"
select SUPPORT_SPL
select SUPPORT_TPL
select ARCH_P1025
imply CMD_EEPROM
imply CMD_SATA
imply SATA_SIL
config TARGET_P2020RDB
bool "Support P2020RDB-PC"
select SUPPORT_SPL
@ -1506,7 +1446,6 @@ source "board/freescale/mpc8568mds/Kconfig"
source "board/freescale/mpc8569mds/Kconfig"
source "board/freescale/mpc8572ds/Kconfig"
source "board/freescale/p1010rdb/Kconfig"
source "board/freescale/p1023rdb/Kconfig"
source "board/freescale/p1_p2_rdb_pc/Kconfig"
source "board/freescale/p2041rdb/Kconfig"
source "board/freescale/qemu-ppce500/Kconfig"

4
arch/powerpc/cpu/mpc85xx/fdt.c
View file

@ -672,10 +672,10 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
"clock-frequency", get_bus_freq(0), 1);
#endif
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
#ifdef CONFIG_MP
ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
ft_fixup_cpu(blob, (u64)gd->ram_base + (u64)gd->ram_size);
ft_fixup_num_cores(blob);
#endif

2
arch/powerpc/cpu/mpc85xx/traps.c
View file

@ -37,7 +37,7 @@ extern unsigned long search_exception_table(unsigned long);
* amount of memory on the system if we're unable to keep all
* the memory mapped in.
*/
#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize())
#define END_OF_MEM (gd->ram_base + get_effective_memsize())
static __inline__ void set_tsr(unsigned long val)
{

4
arch/powerpc/cpu/mpc86xx/fdt.c
View file

@ -8,6 +8,8 @@
#include <fdt_support.h>
#include <asm/mp.h>
DECLARE_GLOBAL_DATA_PTR;
extern void ft_fixup_num_cores(void *blob);
extern void ft_srio_setup(void *blob);
@ -27,7 +29,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_busfreq, 1);
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
#ifdef CONFIG_SYS_NS16550
do_fixup_by_compat_u32(blob, "ns16550",

2
arch/powerpc/cpu/mpc86xx/traps.c
View file

@ -30,7 +30,7 @@ extern unsigned long search_exception_table(unsigned long);
* amount of memory on the system if we're unable to keep all
* the memory mapped in.
*/
#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize())
#define END_OF_MEM (gd->ram_base + get_effective_memsize())
/*
* Trap & Exception support

2
arch/powerpc/cpu/mpc8xx/fdt.c
View file

@ -25,5 +25,5 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency",
gd->arch.brg_clk, 1);
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
}

2
arch/powerpc/cpu/mpc8xxx/cpu.c
View file

@ -343,6 +343,7 @@ int fixup_cpu(void)
return 0;
}
#ifndef CONFIG_DM_ETH
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
@ -370,3 +371,4 @@ int cpu_eth_init(struct bd_info *bis)
#endif
return 0;
}
#endif

8
arch/powerpc/dts/Makefile
View file

@ -1,5 +1,11 @@
# SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_TARGET_KMCOGE5NE) += kmcoge5ne.dtb
dtb-$(CONFIG_TARGET_KMETER1) += kmeter1.dtb
dtb-$(CONFIG_TARGET_KMOPTI2) += kmopti2.dtb
dtb-$(CONFIG_TARGET_KMSUPX5) += kmsupc5.dtb kmsupm5.dtb
dtb-$(CONFIG_TARGET_KMTEGR1) += kmtegr1.dtb
dtb-$(CONFIG_TARGET_KMTEPR2) += kmtepr2.dtb
dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb
dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb
dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb
@ -16,6 +22,8 @@ dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb
dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
dtb-$(CONFIG_TARGET_T2080RDB) += t2080rdb.dtb
dtb-$(CONFIG_TARGET_T4240RDB) += t4240rdb.dtb
dtb-$(CONFIG_TARGET_TUGE1) += kmtuge1.dtb
dtb-$(CONFIG_TARGET_TUXX1) += kmtuxa1.dtb
dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb
dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb

33
arch/powerpc/dts/km8309-uboot.dtsi Normal file
View file

@ -0,0 +1,33 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA 8309 U-Boot specific Device Tree Source parts
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/ {
cpus {
u-boot,dm-pre-reloc;
PowerPC,8309@0 {
u-boot,dm-pre-reloc;
};
};
chosen {
stdout-path = &serial0;
};
};
&qe {
compatible = "fsl,qe", "simple-bus";
};
&soc {
u-boot,dm-pre-reloc;
};
&serial0 {
clock-frequency = <132000000>;
u-boot,dm-pre-reloc;
};

67
arch/powerpc/dts/km8321-uboot.dtsi Normal file
View file

@ -0,0 +1,67 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA 8321 U-Boot specific Device Tree Source parts
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/ {
cpus {
u-boot,dm-pre-reloc;
PowerPC,8321@0 {
u-boot,dm-pre-reloc;
};
};
chosen {
stdout-path = &serial0;
};
};
&enet_piggy2 {
status = "okay";
};
&qe {
compatible = "fsl,qe", "simple-bus";
};
&serial0 {
clock-frequency = <132000000>;
u-boot,dm-pre-reloc;
};
&soc {
u-boot,dm-pre-reloc;
par_io@1400 {
compatible = "fsl,mpc8360-par_io";
u-boot,dm-pre-reloc;
serial_pin@0 {
u-boot,dm-pre-reloc;
};
ucc_pin@0 {
u-boot,dm-pre-reloc;
};
ucc_pin@1 {
u-boot,dm-pre-reloc;
};
ucc_pin@3 {
u-boot,dm-pre-reloc;
};
ucc_pin@4 {
u-boot,dm-pre-reloc;
};
ucc_pin@5 {
u-boot,dm-pre-reloc;
};
ucc_pin@6 {
u-boot,dm-pre-reloc;
};
ucc_pin@7 {
u-boot,dm-pre-reloc;
};
};
};

220
arch/powerpc/dts/km8321.dtsi Normal file
View file

@ -0,0 +1,220 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA km8321 common ports Device Tree Source
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8321@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <16384>; // L1, 16K
i-cache-size = <16384>; // L1, 16K
timebase-frequency = <66000000>;
bus-frequency = <264000000>;
clock-frequency = <528000000>;
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>;
};
soc: soc8321@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
ranges = <0x0 0xe0000000 0x00100000>;
reg = <0xe0000000 0x00000200>;
bus-frequency = <264000000>;
i2c0: i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl,mpc8313-i2c","fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <14 0x8>;
interrupt-parent = <&ipic>;
clock-frequency = <100000>;
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <264000000>;
interrupts = <9 0x8>;
interrupt-parent = <&ipic>;
};
dma@82a8 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8321-dma", "fsl,elo-dma";
reg = <0x82a8 4>;
ranges = <0 0x8100 0x1a8>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8321-dma-channel",
"fsl,elo-dma-channel";
reg = <0 0x80>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@80 {
compatible = "fsl,mpc8321-dma-channel",
"fsl,elo-dma-channel";
reg = <0x80 0x80>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@100 {
compatible = "fsl,mpc8321-dma-channel",
"fsl,elo-dma-channel";
reg = <0x100 0x80>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@180 {
compatible = "fsl,mpc8321-dma-channel",
"fsl,elo-dma-channel";
reg = <0x180 0x28>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
};
ipic: pic@700 {
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "fsl,pq2pro-pic", "fsl,ipic";
interrupt-controller;
reg = <0x700 0x100>;
device_type = "ipic";
};
par_io: par_io@1400 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0x1400 0x100>;
ranges;
device_type = "par_io";
num-ports = <7>;
qe_pio_d: gpio-controller@48 {
#gpio-cells = <2>;
compatible = "fsl,mpc8360-qe-pario-bank",
"fsl,mpc8323-qe-pario-bank";
reg = <0x1448 0x18>;
gpio-controller;
};
};
};
qe: qe@e0100000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "qe";
compatible = "fsl,qe";
ranges = <0x0 0xe0100000 0x00100000>;
reg = <0xe0100000 0x480>;
brg-frequency = <0>;
bus-frequency = <396000000>;
muram@10000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,qe-muram", "fsl,cpm-muram";
ranges = <0x0 0x00010000 0x00004000>;
data-only@0 {
compatible = "fsl,qe-muram-data",
"fsl,cpm-muram-data";
reg = <0x0 0x4000>;
};
};
/* Piggy2 (UCC4, MDIO 0x00, RMII) */
enet_piggy2: ucc@3200 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <4>;
reg = <0x3200 0x200>;
interrupts = <35>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk17";
phy-handle = <&phy_piggy2>;
phy-connection-type = "rmii";
pio-handle = <&pio_ucc4>;
};
mdio: mdio@3320 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3320 0x18>;
compatible = "fsl,ucc-mdio";
/* Piggy2 (UCC4, MDIO 0x00, RMII) */
phy_piggy2: ethernet-phy@00 {
reg = <0x0>;
device_type = "ethernet-phy";
};
};
qeic: interrupt-controller@80 {
interrupt-controller;
compatible = "fsl,qe-ic";
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <0x80 0x80>;
big-endian;
interrupts = <32 8 33 8>;
interrupt-parent = <&ipic>;
};
bootcount@0x13ff8 {
device_type = "bootcount";
compatible = "u-boot,bootcount";
reg = <0x13ff8 0x08>;
};
spi0: spi@4c0 {
cell-index = <0>;
compatible = "fsl,spi";
reg = <0x4c0 0x40>;
interrupts = <2>;
interrupt-parent = <&qeic>;
mode = "qe";
#address-cells = <1>;
#size-cells = <0>;
pio-handle = <&pio_spi>;
};
};
localbus: localbus@e0005000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8321-localbus", "fsl,pq2pro-localbus",
"simple-bus";
reg = <0xe0005000 0xd8>;
};
};
#include "km8321-uboot.dtsi"

61
arch/powerpc/dts/km836x-uboot.dtsi Normal file
View file

@ -0,0 +1,61 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA km836x U-Boot specific Device Tree Source parts
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/ {
cpus {
u-boot,dm-pre-reloc;
PowerPC,8360@0 {
u-boot,dm-pre-reloc;
};
};
chosen {
stdout-path = &serial0;
};
};
&qe {
compatible = "fsl,qe", "simple-bus";
};
&soc {
u-boot,dm-pre-reloc;
par_io@1400 {
u-boot,dm-pre-reloc;
serial_pin@0 {
u-boot,dm-pre-reloc;
};
ucc_pin@0 {
u-boot,dm-pre-reloc;
};
ucc_pin@1 {
u-boot,dm-pre-reloc;
};
ucc_pin@3 {
u-boot,dm-pre-reloc;
};
ucc_pin@4 {
u-boot,dm-pre-reloc;
};
ucc_pin@5 {
u-boot,dm-pre-reloc;
};
ucc_pin@6 {
u-boot,dm-pre-reloc;
};
ucc_pin@7 {
u-boot,dm-pre-reloc;
};
};
};
&serial0 {
u-boot,dm-pre-reloc;
};

182
arch/powerpc/dts/km836x.dtsi Normal file
View file

@ -0,0 +1,182 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA km836x common ports Device Tree Source
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8360@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>; /* 32 bytes */
i-cache-line-size = <32>; /* 32 bytes */
d-cache-size = <32768>; /* L1, 32K */
i-cache-size = <32768>; /* L1, 32K */
timebase-frequency = <0>; /* Filled in by U-Boot */
bus-frequency = <0>; /* Filled in by U-Boot */
clock-frequency = <0>; /* Filled in by U-Boot */
};
};
memory {
device_type = "memory";
reg = <0 0>; /* Filled in by U-Boot */
};
soc: soc8360@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,mpc8360-immr", "simple-bus";
ranges = <0x0 0xe0000000 0x00200000>;
reg = <0xe0000000 0x00000200>;
bus-frequency = <0>;/* Filled in by U-Boot */
/* power management control module*/
pmc: power@b00 {
compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
reg = <0xb00 0x100 0xa00 0x100>;
interrupts = <80 0x8>;
interrupt-parent = <&ipic>;
};
i2c0: i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl,mpc8313-i2c","fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <14 0x8>;
interrupt-parent = <&ipic>;
clock-frequency = <100000>;
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <264000000>;
interrupts = <9 0x8>;
interrupt-parent = <&ipic>;
status = "disabled";
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <133333333>;
interrupts = <10 0x8>;
interrupt-parent = <&ipic>;
status = "disabled";
};
ipic: pic@700 {
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "fsl,pq2pro-pic", "fsl,ipic";
interrupt-controller;
reg = <0x700 0x100>;
};
par_io: par_io@1400 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0x1400 0x100>;
ranges;
compatible = "fsl,mpc8360-par_io";
device_type = "par_io";
num-ports = <7>;
qe_pio_c: gpio-controller@30 {
#gpio-cells = <2>;
compatible = "fsl,mpc8360-qe-pario-bank",
"fsl,mpc8323-qe-pario-bank";
reg = <0x1430 0x18>;
gpio-controller;
};
};
qe: qe@100000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,qe";
ranges = <0x0 0x100000 0x100000>;
reg = <0x100000 0x480>;
clock-frequency = <0>; /* Filled in by U-Boot */
brg-frequency = <0>; /* Filled in by U-Boot */
bus-frequency = <0>; /* Filled in by U-Boot */
muram@10000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,qe-muram", "fsl,cpm-muram";
ranges = <0x0 0x00010000 0x0000c000>;
data-only@0 {
compatible = "fsl,qe-muram-data",
"fsl,cpm-muram-data";
reg = <0x0 0xc000>;
};
};
qeic: interrupt-controller@80 {
interrupt-controller;
compatible = "fsl,qe-ic";
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <0x80 0x80>;
big-endian;
interrupts = <
32 0x8 /* ucc1 */
33 0x8 /* ucc2 */
34 0x8 /* ucc3 */
35 0x8 /* ucc4 */
40 0x8 /* ucc1 */
>;
interrupt-parent = <&ipic>;
};
spi0: spi@4c0 {
cell-index = <0>;
compatible = "fsl,spi";
reg = <0x4c0 0x40>;
interrupts = <2>;
interrupt-parent = <&qeic>;
mode = "qe";
#address-cells = <1>;
#size-cells = <0>;
pio-handle = <&pio_spi>;
};
bootcount@0x1bff8 {
device_type = "bootcount";
compatible = "u-boot,bootcount";
reg = <0x1bff8 0x08>;
};
};
};
localbus: localbus@e0005000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
"simple-bus";
reg = <0xe0005000 0xd8>;
};
};
#include "km836x-uboot.dtsi"

22
arch/powerpc/dts/kmcoge5ne-uboot.dtsi Normal file
View file

@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA kmcoge5ne U-Boot specific Device Tree Source parts
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/ {
aliases {
/delete-property/ ethernet1;
/delete-property/ ethernet2;
};
};
&enet_switch {
status = "disabled";
};
&enet_mate {
status = "disabled";
};

320
arch/powerpc/dts/kmcoge5ne.dts Normal file
View file

@ -0,0 +1,320 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA KMCOGE5ne Device Tree Source
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
#include "km836x.dtsi"
/ {
model = "kmcoge5ne";
compatible = "ABB,kmcoge5ne";
aliases {
ethernet0 = &enet_admin;
ethernet1 = &enet_mate;
ethernet2 = &enet_switch;
serial0 = &serial0;
};
};
&soc {
/* brg for hdlc clk */
brg@0 {
compatible = "fsl,mpc-brg";
brg-name = "brg16";
brg-frequency = <20000000>; /* 20 MHz */
pio-handle = <&pio_brg>;
};
};
&i2c0 {
mux@70 {
compatible = "nxp,pca9547";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
/* Inventory EEPROM of the unit itself */
ivm@50 {
label = "MAIN_CTRL";
compatible = "dummy";
reg = <0x50>;
};
};
i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
/* Inventory EEPROM of the fan unit */
fanu-ivm@50 {
label = "FANUV";
compatible = "dummy";
reg = <0x50>;
};
/* fan unit (GPIOs and so on) */
fanu@20 {
label = "FANUV_CTRL";
compatible = "dummy";
reg = <0x20>;
};
};
i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
backplane@50 {
label = "BP_CTRL";
compatible = "dummy";
reg = <0x50>;
};
};
};
};
&serial0 {
status = "okay";
};
&par_io {
pio_ucc1: ucc_pin@0 { /* RGMII mng-switch */
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */
0 2 1 0 1 0 /* MDC (PA2, in, f1) */
0 3 1 0 1 0 /* TxD0 (PA3, in, f1) */
0 4 1 0 1 0 /* TxD1 (PA4, in, f1) */
0 5 1 0 1 0 /* TxD2 (PA5, in, f1) */
0 6 1 0 1 0 /* TxD3 (PA6, in, f1) */
0 9 2 0 1 0 /* RxD0 (PA9, out, f1) */
0 10 2 0 1 0 /* RxD1 (PA10, out, f1) */
0 11 2 0 1 0 /* RxD2 (PA11, out, f1) */
0 12 2 0 1 0 /* RxD3 (PA12, out, f1) */
0 7 1 0 1 0 /* TX_EN (PA7, in, f1) */
0 15 2 0 1 0 /* RX_DV (PA15, out, f1) */
0 0 2 0 1 0 /* RX_CLK (PA0, out, f1) */
2 9 1 0 3 0 /* GTX_CLK (CLK10) */
2 8 2 0 1 0 /* GTX125 (CLK9) */
>;
};
pio_ucc4: ucc_pin@3 { /* RMII, admin front port */
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */
0 2 1 0 1 0 /* MDC (PA2, in, f1) */
1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */
1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */
1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */
1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */
1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */
1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */
1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */
2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */
>;
};
pio_ucc5: ucc_pin@4 { /* RMII, mate backplane port */
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */
0 2 1 0 1 0 /* MDC (PA2, in, f1) */
3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */
3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */
3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */
3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */
3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */
3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */
3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */
2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */
>;
};
pio_spi: spi_pin@01 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
4 28 3 0 3 0 /* SPI_MOSI (PE28, out, f3) */
4 29 3 0 3 0 /* SPI_MISO (PE29, out, f3) */
4 30 3 0 3 0 /* SPI_CLK (PE30, out, f3) */
>;
};
pio_brg: brg_pin@0 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
2 25 1 0 1 0 /* BRG (PC25, out, f1) */
>;
};
pio_tdm: tdm_pin@00 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
/* TDMa */
0 8 3 0 2 0 /* RxD0 (PA8, bi, f2) */
0 13 3 0 2 0 /* TxD0 (PA13, bi, f2) */
0 14 2 0 2 0 /* RSync0 (PA14, in, f2) */
2 7 2 0 1 0 /* RxClk8 (PC7, in, f1) */
/* TDMb */
0 27 3 0 2 0 /* RxD1 (PA27, bi, f2) */
0 22 3 0 2 0 /* TxD1 (PA22, bi, f2) */
0 28 2 0 2 0 /* RSync1 (PA28, in, f2) */
2 1 2 0 1 0 /* RxClk2 (PC1, in, f1) */
/* TDMc */
1 5 3 0 2 0 /* RxD2 (PB5, bi, f2) */
1 8 3 0 2 0 /* TxD2 (PB8, bi, f2) */
1 2 2 0 3 0 /* RSync2 (PB2, in, f3) */
2 6 2 0 1 0 /* RxClk7 (PC6, in, f1) */
/* TDMd */
1 22 3 0 2 0 /* RxD3 (PB22, bi, f2) */
1 19 3 0 1 0 /* TxD3 (PB19, bi, f1) */
1 16 2 0 2 0 /* RSync3 (PB16, in, f2) */
2 13 2 0 1 0 /* RxClk14 (PC13, in, f1) */
/* TDMe */
3 8 3 0 2 0 /* RxD4 (PD8, bi, f2) */
3 5 3 0 2 0 /* TxD4 (PD5, bi, f2) */
3 2 2 0 2 0 /* RSync4 (PD2 , in, f2) */
2 22 2 0 1 0 /* RxClk23 (PC22, in, f1) */
/* TDMf */
3 19 3 0 2 0 /* RxD5 (PD19, bi, f2) */
3 22 3 0 2 0 /* TxD5 (PD22, bi, f2) */
3 16 2 0 1 0 /* RSync5 (PD16, in, f1) */
2 17 2 0 1 0 /* RxClk18 (PC17, in, f1) */
/* TDMg */
4 8 3 0 2 0 /* RxD6 (PE8, bi, f2) */
4 5 3 0 2 0 /* TxD6 (PE5, bi, f2) */
4 2 2 0 1 0 /* RSync6 (PE2, in, f1) */
2 19 2 0 1 0 /* RxClk20 (PC19, in, f1) */
/* TDMh */
4 19 3 0 2 0 /* RxD7 (PE19, bi, f2) */
4 22 3 0 3 0 /* TxD7 (PE22, bi, f3) */
4 16 2 0 2 0 /* RSync7 (PE16, in, f2) */
2 21 2 0 1 0 /* RxClk22 (PC21, in, f1) */
/* RxTxClk0/1 */
2 0 2 0 1 0 /* Clk1 (PC0, in, f1) */
2 23 2 0 1 0 /* Clk24 (PC23, in, f1) */
/* RxTxSync0/1 */
2 10 2 0 1 0 /* Clk11 (PC10, in, f1) */
2 20 2 0 1 0>; /* Clk21 (PC20, in, f1) */
};
};
&qe {
/* mng-switch port (UCC1, MDIO 0x10, RGMII) */
enet_switch: ethernet@2000 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <1>;
reg = <0x2000 0x200>;
interrupts = <32>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk9";
/*id=0, full-dup, 1G, no-pause, no-asym_p*/
fixed-link = <0 1 1000 0 0>;
phy-connection-type = "rgmii-id";
pio-handle = <&pio_ucc1>;
};
/* admin and debug port (UCC4, MDIO 0x00, RMII) */
enet_admin: ucc@3200 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <4>;
reg = <0x3200 0x200>;
interrupts = <35>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk17";
phy-handle = <&phy_admin>;
phy-connection-type = "rmii";
pio-handle = <&pio_ucc4>;
};
/* mate backplane port (UCC5, MDIO 0x08, RMII) */
enet_mate: ucc@2400 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <5>;
reg = <0x2400 0x200>;
interrupts = <40>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk16";
phy-handle = <&phy_mate>;
phy-connection-type = "rmii";
pio-handle = <&pio_ucc5>;
};
mdio@3320 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3320 0x18>;
compatible = "fsl,ucc-mdio";
/* admin front port (UCC4, MDIO 0x00, RMII) */
phy_admin: ethernet-phy@00 {
reg = <0x0>;
};
/* mate bp port (UCC5, MDIO 0x08, RMII) */
phy_mate: ethernet-phy@08 {
reg = <0x08>;
};
};
};
&localbus {
ranges = <0 0 0xf0000000 0x04000000
1 0 0xe8000000 0x01000000
3 0 0xa0000000 0x10000000
4 0 0xb0000000 0x10000000>;
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x04000000>;
nornand = "nor";
#address-cells = <1>;
#size-cells = <1>;
bank-width = <2>;
partition@0 { /* 768KB */
label = "u-boot";
reg = <0 0xC0000>;
};
partition@c0000 { /* 128KB */
label = "env";
reg = <0xC0000 0x20000>;
};
partition@e0000 { /* 128KB */
label = "envred";
reg = <0xE0000 0x20000>;
};
partition@100000 { /* 64512KB */
label = "ubi0";
reg = <0x100000 0x3F00000>;
};
};
};
#include "kmcoge5ne-uboot.dtsi"

42
arch/powerpc/dts/kmeter1-uboot.dtsi Normal file
View file

@ -0,0 +1,42 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA kmeter1 U-Boot specific Device Tree Source parts
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/ {
aliases {
/delete-property/ ethernet1;
/delete-property/ ethernet2;
/delete-property/ ethernet3;
/delete-property/ ethernet4;
/delete-property/ ethernet5;
/delete-property/ ethernet6;
};
};
&enet_estar1 {
status = "disabled";
};
&enet_estar2 {
status = "disabled";
};
&enet_eth1 {
status = "disabled";
};
&enet_eth2 {
status = "disabled";
};
&enet_eth3 {
status = "disabled";
};
&enet_eth4 {
status = "disabled";
};

480
arch/powerpc/dts/kmeter1.dts Normal file
View file

@ -0,0 +1,480 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA KMETER1 Device Tree Source
*
* 2008-2011 DENX Software Engineering GmbH
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*/
/dts-v1/;
#include "km836x.dtsi"
/ {
model = "KMETER1";
compatible = "ABB,KMETER1";
aliases {
ethernet0 = &enet_piggy2;
ethernet1 = &enet_estar1;
ethernet2 = &enet_estar2;
ethernet3 = &enet_eth1;
ethernet4 = &enet_eth2;
ethernet5 = &enet_eth3;
ethernet6 = &enet_eth4;
serial0 = &serial0;
};
};
&i2c0 {
mux@70 {
compatible = "nxp,pca9547";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
/* Inventory EEPROM of the unit itself */
ivm@50 {
label = "MAIN_CTRL";
compatible = "dummy";
reg = <0x50>;
};
};
i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
/* Temperature sensors */
temp@48 {
label = "Top";
compatible = "national,lm75";
reg = <0x48>;
};
temp@49 {
label = "Control";
compatible = "national,lm75";
reg = <0x49>;
};
temp@4a {
label = "Power";
compatible = "national,lm75";
reg = <0x4a>;
};
temp@4b {
label = "Front";
compatible = "national,lm75";
reg = <0x4b>;
};
};
};
};
&serial0 {
status = "okay";
};
&par_io {
pio_ucc1: ucc_pin@0 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO */
0 2 1 0 1 0 /* MDC */
0 3 1 0 1 0 /* TxD0 */
0 4 1 0 1 0 /* TxD1 */
0 5 1 0 1 0 /* TxD2 */
0 6 1 0 1 0 /* TxD3 */
0 9 2 0 1 0 /* RxD0 */
0 10 2 0 1 0 /* RxD1 */
0 11 2 0 1 0 /* RxD2 */
0 12 2 0 1 0 /* RxD3 */
0 7 1 0 1 0 /* TX_EN */
0 8 1 0 1 0 /* TX_ER */
0 15 2 0 1 0 /* RX_DV */
0 16 2 0 1 0 /* RX_ER */
0 0 2 0 1 0 /* RX_CLK */
2 9 1 0 3 0 /* GTX_CLK - CLK10 */
2 8 2 0 1 0 /* GTX125 - CLK9 */
>;
};
pio_ucc2: ucc_pin@1 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO */
0 2 1 0 1 0 /* MDC */
0 17 1 0 1 0 /* TxD0 */
0 18 1 0 1 0 /* TxD1 */
0 19 1 0 1 0 /* TxD2 */
0 20 1 0 1 0 /* TxD3 */
0 23 2 0 1 0 /* RxD0 */
0 24 2 0 1 0 /* RxD1 */
0 25 2 0 1 0 /* RxD2 */
0 26 2 0 1 0 /* RxD3 */
0 21 1 0 1 0 /* TX_EN */
0 22 1 0 1 0 /* TX_ER */
0 29 2 0 1 0 /* RX_DV */
0 30 2 0 1 0 /* RX_ER */
0 31 2 0 1 0 /* RX_CLK */
2 2 1 0 2 0 /* GTX_CLK - CLK3 */
2 3 2 0 1 0 /* GTX125 - CLK4 */
>;
};
pio_ucc4: ucc_pin@3 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO */
0 2 1 0 1 0 /* MDC */
1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */
1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */
1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */
1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */
1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */
1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */
1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */
2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */
>;
};
pio_ucc5: ucc_pin@4 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO */
0 2 1 0 1 0 /* MDC */
3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */
3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */
3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */
3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */
3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */
3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */
3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */
>;
};
pio_ucc6: ucc_pin@5 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO */
0 2 1 0 1 0 /* MDC */
3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */
3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */
3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */
3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */
3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */
3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */
3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */
>;
};
pio_ucc7: ucc_pin@6 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO */
0 2 1 0 1 0 /* MDC */
4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */
4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */
4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */
4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */
4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */
4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */
4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */
>;
};
pio_ucc8: ucc_pin@7 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO */
0 2 1 0 1 0 /* MDC */
4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */
4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */
4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */
4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */
4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */
4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */
4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */
2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */
>;
};
pio_spi: spi_pin@01 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
4 28 3 0 3 0 /* SPI_MOSI (PE28, out, f3 */
4 30 3 0 3 0 /* SPI_CLK (PE30, out, f3 */
>;
};
/* UCC3 as HDLC controller for ICN */
pio5: ucc_pin@02 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
1 0 1 0 1 0 /* TxD0 */
1 6 2 0 1 0 /* RxD0 */
1 12 2 0 1 0 /* CTS */
2 11 2 0 1 0 /* TX-CLK12 */
>;
};
pio_tdm: tdm_pin@00 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
/* TDMa */
0 8 3 0 2 0 /* RxD0 (PA8, bi, f2) */
0 13 3 0 2 0 /* TxD0 (PA13, bi, f2) */
0 14 2 0 2 0 /* RSync0 (PA14, in, f2) */
2 7 2 0 1 0 /* RxClk8 (PC7, in, f1) */
/* TDMb */
0 27 3 0 2 0 /* RxD1 (PA27, bi, f2) */
0 22 3 0 2 0 /* TxD1 (PA22, bi, f2) */
0 28 2 0 2 0 /* RSync1 (PA28, in, f2) */
2 1 2 0 1 0 /* RxClk2 (PC1, in, f1) */
/* TDMc */
1 5 3 0 2 0 /* RxD2 (PB5, bi, f2) */
1 8 3 0 2 0 /* TxD2 (PB8, bi, f2) */
1 2 2 0 3 0 /* RSync2 (PB2, in, f3) */
2 6 2 0 1 0 /* RxClk7 (PC6, in, f1) */
/* TDMd */
1 22 3 0 2 0 /* RxD3 (PB22, bi, f2) */
1 19 3 0 1 0 /* TxD3 (PB19, bi, f1) */
1 16 2 0 2 0 /* RSync3 (PB16, in, f2) */
2 13 2 0 1 0 /* RxClk14 (PC13, in, f1) */
/* TDMe */
3 8 3 0 2 0 /* RxD4 (PD8, bi, f2) */
3 5 3 0 2 0 /* TxD4 (PD5, bi, f2) */
3 2 2 0 2 0 /* RSync4 (PD2 , in, f2) */
2 22 2 0 1 0 /* RxClk23 (PC22, in, f1) */
/* TDMf */
3 19 3 0 2 0 /* RxD5 (PD19, bi, f2) */
3 22 3 0 2 0 /* TxD5 (PD22, bi, f2) */
3 16 2 0 1 0 /* RSync5 (PD16, in, f1) */
2 17 2 0 1 0 /* RxClk18 (PC17, in, f1) */
/* TDMg */
4 8 3 0 2 0 /* RxD6 (PE8, bi, f2) */
4 5 3 0 2 0 /* TxD6 (PE5, bi, f2) */
4 2 2 0 1 0 /* RSync6 (PE2, in, f1) */
2 19 2 0 1 0 /* RxClk20 (PC19, in, f1) */
/* TDMh */
4 19 3 0 2 0 /* RxD7 (PE19, bi, f2) */
4 22 3 0 3 0 /* TxD7 (PE22, bi, f3) */
4 16 2 0 2 0 /* RSync7 (PE16, in, f2) */
2 21 2 0 1 0 /* RxClk22 (PC21, in, f1) */
/* RxTxClk0/1 */
2 0 2 0 1 0 /* Clk1 (PC0, in, f1) */
2 23 2 0 1 0 /* Clk24 (PC23, in, f1) */
/* RxTxSync0/1 */
2 10 2 0 1 0 /* Clk11 (PC10, in, f1) */
2 20 2 0 1 0>; /* Clk21 (PC20, in, f1) */
};
};
&qe {
/* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
enet_estar1: ucc@2000 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <1>;
reg = <0x2000 0x200>;
interrupts = <32>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk9";
phy-handle = <&phy_estar1>;
phy-connection-type = "rgmii-id";
pio-handle = <&pio_ucc1>;
};
/* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
enet_estar2: ucc@3000 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <2>;
reg = <0x3000 0x200>;
interrupts = <33>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk4";
phy-handle = <&phy_estar2>;
phy-connection-type = "rgmii-id";
pio-handle = <&pio_ucc2>;
};
/* Piggy2 (UCC4, MDIO 0x00, RMII) */
enet_piggy2: ucc@3200 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <4>;
reg = <0x3200 0x200>;
interrupts = <35>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk17";
phy-handle = <&phy_piggy2>;
phy-connection-type = "rmii";
pio-handle = <&pio_ucc4>;
};
/* Eth-1 (UCC5, MDIO 0x08, RMII) */
enet_eth1: ucc@2400 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <5>;
reg = <0x2400 0x200>;
interrupts = <40>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk16";
phy-handle = <&phy_eth1>;
phy-connection-type = "rmii";
pio-handle = <&pio_ucc5>;
};
/* Eth-2 (UCC6, MDIO 0x09, RMII) */
enet_eth2: ucc@3400 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <6>;
reg = <0x3400 0x200>;
interrupts = <41>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk16";
phy-handle = <&phy_eth2>;
phy-connection-type = "rmii";
pio-handle = <&pio_ucc6>;
};
/* Eth-3 (UCC7, MDIO 0x0a, RMII) */
enet_eth3: ucc@2600 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <7>;
reg = <0x2600 0x200>;
interrupts = <42>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk16";
phy-handle = <&phy_eth3>;
phy-connection-type = "rmii";
pio-handle = <&pio_ucc7>;
};
/* Eth-4 (UCC8, MDIO 0x0b, RMII) */
enet_eth4: ucc@3600 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <8>;
reg = <0x3600 0x200>;
interrupts = <43>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk16";
phy-handle = <&phy_eth4>;
phy-connection-type = "rmii";
pio-handle = <&pio_ucc8>;
};
mdio@3320 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3320 0x18>;
compatible = "fsl,ucc-mdio";
/* Piggy2 (UCC4, MDIO 0x00, RMII) */
phy_piggy2: ethernet-phy@0 {
reg = <0x0>;
};
/* Eth-1 (UCC5, MDIO 0x08, RMII) */
phy_eth1: ethernet-phy@8 {
reg = <0x08>;
};
/* Eth-2 (UCC6, MDIO 0x09, RMII) */
phy_eth2: ethernet-phy@9 {
reg = <0x09>;
};
/* Eth-3 (UCC7, MDIO 0x0a, RMII) */
phy_eth3: ethernet-phy@a {
reg = <0x0a>;
};
/* Eth-4 (UCC8, MDIO 0x0b, RMII) */
phy_eth4: ethernet-phy@b {
reg = <0x0b>;
};
/* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
phy_estar1: ethernet-phy@10 {
interrupt-parent = <&ipic>;
interrupts = <17 0x8>;
reg = <0x10>;
};
/* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
phy_estar2: ethernet-phy@11 {
interrupt-parent = <&ipic>;
interrupts = <18 0x8>;
reg = <0x11>;
};
};
};
&localbus {
ranges = <0 0 0xf0000000 0x04000000 /* LB 0 */
1 0 0xe8000000 0x01000000 /* LB 1 */
3 0 0xa0000000 0x10000000>; /* LB 3 */
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x04000000>;
#address-cells = <1>;
#size-cells = <1>;
bank-width = <2>;
partition@0 { /* 768KB */
label = "u-boot";
reg = <0 0xC0000>;
};
partition@c0000 { /* 128KB */
label = "env";
reg = <0xC0000 0x20000>;
};
partition@e0000 { /* 128KB */
label = "envred";
reg = <0xE0000 0x20000>;
};
partition@100000 { /* 64512KB */
label = "ubi0";
reg = <0x100000 0x3F00000>;
};
};
};
#include "kmeter1-uboot.dtsi"

161
arch/powerpc/dts/kmopti2.dts Normal file
View file

@ -0,0 +1,161 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA OPTI2 Device Tree Source
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
#include "km8321.dtsi"
/ {
model = "KMOPTI2";
compatible = "ABB,kmpbec8321";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet_piggy2;
serial0 = &serial0;
};
};
&i2c0 {
mux@70 {
compatible = "nxp,pca9547";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
/* Inventory EEPROM of the unit itself */
ivm@50 {
label = "MAIN_CTRL";
compatible = "dummy";
reg = <0x50>;
};
};
i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
/* Temperature sensors */
temp@49 {
label = "board";
compatible = "national,lm75";
reg = <0x49>;
};
temp@4a {
label = "power";
compatible = "national,lm75";
reg = <0x4a>;
};
};
i2c@6 {
reg = <6>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@5 {
reg = <5>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@4 {
reg = <4>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
&par_io {
/* UCC5 as HDLC controller for ICN */
pio_ucc5: ucc_pin@04 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
2 0 1 0 2 0 /* TxD0 */
2 8 2 0 2 0 /* RxD0 */
2 29 2 0 2 0 /* CTS */
3 30 2 0 1 0 /* ICN CLK */
>;
};
/* UCC4 Piggy Ethernet */
pio_ucc4: ucc_pin@03 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
3 4 3 0 2 0 /* MDIO */
3 5 1 0 2 0 /* MDC */
1 18 1 0 1 0 /* TxD0 */
1 19 1 0 1 0 /* TxD1 */
1 22 2 0 1 0 /* RxD0 */
1 23 2 0 1 0 /* RxD1 */
1 26 2 0 1 0 /* RX_ER */
1 28 2 0 1 0 /* RX_DV */
1 30 1 0 1 0 /* TX_EN */
1 31 2 0 1 0 /* CRS */
3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */
>;
};
pio_spi: spi_pin@01 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
3 0 3 0 1 0 /* SPI_MOSI (PD0, bi, f3) */
3 1 3 0 1 0 /* SPI_MISO (PD1, bi, f3) */
3 2 3 0 1 0 /* SPI_CLK (PD2, bi, f3) */
>;
};
};
&localbus {
ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
2 0 0xa0000000 0x10000000 /* LB 2 PAXE */
3 0 0xb0000000 0x10000000>; /* LB 3 OPI2 */
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0x00000000 0x04000000>;
bank-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
use-advanced-sector-protection;
partition@0 { /* 768KB */
label = "u-boot";
reg = <0 0xC0000>;
};
partition@c0000 { /* 128KB */
label = "env";
reg = <0xc0000 0x20000>;
};
partition@e0000 { /* 128KB */
label = "envred";
reg = <0xe0000 0x20000>;
};
partition@100000 { /* 64512KB */
label = "ubi0";
reg = <0x100000 0x3F00000>;
};
};
};

139
arch/powerpc/dts/kmsupc5.dts Normal file
View file

@ -0,0 +1,139 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA SUPC5 Device Tree Source
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
#include "km8321.dtsi"
/ {
model = "SUPC5";
compatible = "ABB,kmpbec8321";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet_piggy2;
serial0 = &serial0;
};
};
&i2c0 {
mux@70 {
compatible = "nxp,pca9547";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
/* Inventory EEPROM of the unit itself */
ivm@50 {
label = "MAIN_CTRL";
compatible = "dummy";
reg = <0x50>;
};
};
i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
/* Temperature sensors */
temp@49 {
label = "board";
compatible = "national,lm75";
reg = <0x49>;
};
};
};
};
&par_io {
/* UCC5 as HDLC controller for ICN */
pio_ucc5: ucc_pin@04 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
2 0 1 0 2 0 /* TxD0 */
2 8 2 0 2 0 /* RxD0 */
2 29 2 0 2 0 /* CTS */
3 30 2 0 1 0 /* ICN CLK */
>;
};
/* UCC4 Piggy Ethernet */
pio_ucc4: ucc_pin@03 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
3 4 3 0 2 0 /* MDIO */
3 5 1 0 2 0 /* MDC */
1 18 1 0 1 0 /* TxD0 */
1 19 1 0 1 0 /* TxD1 */
1 22 2 0 1 0 /* RxD0 */
1 23 2 0 1 0 /* RxD1 */
1 26 2 0 1 0 /* RX_ER */
1 28 2 0 1 0 /* RX_DV */
1 30 1 0 1 0 /* TX_EN */
1 31 2 0 1 0 /* CRS */
/* UCC4_RMII_CLK (CLK17) */
3 10 2 0 3 0
>;
};
pio_spi: spi_pin@01 {
pio-map = <
/*
* port pin dir open_drain assignment has_irq
* SPI_MOSI (PD0, bi, f3)
*/
3 0 3 0 1 0
/* SPI_MISO (PD1, bi, f3) */
3 1 3 0 1 0
/* SPI_CLK (PD2, bi, f3) */
3 2 3 0 1 0
>;
};
};
&spi0 {
pio-handle = <&pio_spi>;
};
&localbus {
ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
2 0 0xa0000000 0x10000000>; /* LB 2 LPXF */
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0x00000000 0x04000000>;
bank-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 { /* 768KB */
label = "u-boot";
reg = <0 0xC0000>;
};
partition@c0000 { /* 128KB */
label = "env";
reg = <0xc0000 0x20000>;
};
partition@e0000 { /* 128KB */
label = "envred";
reg = <0xe0000 0x20000>;
};
partition@100000 { /* 64512KB */
label = "ubi0";
reg = <0x100000 0x3F00000>;
};
};
};

129
arch/powerpc/dts/kmsupm5.dts Normal file
View file

@ -0,0 +1,129 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA SUPM5 Device Tree Source
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
#include "km8321.dtsi"
/ {
model = "SUPM5";
compatible = "ABB,kmpbec8321";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet_piggy2;
serial0 = &serial0;
};
};
&i2c0 {
mux@70 {
compatible = "nxp,pca9547";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
/* Inventory EEPROM of the unit itself */
ivm@50 {
label = "MAIN_CTRL";
compatible = "dummy";
reg = <0x50>;
};
};
i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
/* Temperature sensors */
temp@49 {
label = "board";
compatible = "national,lm75";
reg = <0x49>;
};
};
};
};
&par_io {
/* UCC5 as HDLC controller for ICN */
pio_ucc5: ucc_pin@04 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
2 0 1 0 2 0 /* TxD0 */
2 8 2 0 2 0 /* RxD0 */
2 29 2 0 2 0 /* CTS */
3 30 2 0 1 0 /* ICN CLK */
>;
};
/* UCC4 Piggy Ethernet */
pio_ucc4: ucc_pin@03 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
3 4 3 0 2 0 /* MDIO */
3 5 1 0 2 0 /* MDC */
1 18 1 0 1 0 /* TxD0 */
1 19 1 0 1 0 /* TxD1 */
1 22 2 0 1 0 /* RxD0 */
1 23 2 0 1 0 /* RxD1 */
1 26 2 0 1 0 /* RX_ER */
1 28 2 0 1 0 /* RX_DV */
1 30 1 0 1 0 /* TX_EN */
1 31 2 0 1 0 /* CRS */
3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */
>;
};
pio_spi: spi_pin@01 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
3 0 3 0 1 0 /* SPI_MOSI (PD0, bi, f3) */
3 1 3 0 1 0 /* SPI_MISO (PD1, bi, f3) */
3 2 3 0 1 0 /* SPI_CLK (PD2, bi, f3) */
>;
};
};
&localbus {
ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
2 0 0xa0000000 0x10000000>; /* LB 2 LPXF */
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0x00000000 0x04000000>;
bank-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 { /* 768KB */
label = "u-boot";
reg = <0 0xC0000>;
};
partition@c0000 { /* 128KB */
label = "env";
reg = <0xc0000 0x20000>;
};
partition@e0000 { /* 128KB */
label = "envred";
reg = <0xe0000 0x20000>;
};
partition@100000 { /* 64512KB */
label = "ubi0";
reg = <0x100000 0x3F00000>;
};
};
};

392
arch/powerpc/dts/kmtegr1.dts Normal file
View file

@ -0,0 +1,392 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA TEGR1 Device Tree Source
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
/ {
model = "KMTEGR1";
compatible = "ABB,kmpbec8309";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet_zynq;
ethernet1 = &enet_piggy2;
serial0 = &serial0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8309@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <16384>; // L1, 16K
i-cache-size = <16384>; // L1, 16K
timebase-frequency = <66000000>;
bus-frequency = <264000000>;
clock-frequency = <264000000>;
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>;
};
soc: soc8309@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
ranges = <0x0 0xe0000000 0x00100000>;
reg = <0xe0000000 0x00000200>;
bus-frequency = <264000000>;
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl,mpc8313-i2c","fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <14 0x8>;
interrupt-parent = <&ipic>;
clock-frequency = <400000>;
mux@70 {
compatible = "nxp,pca9547";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
/*
* Inventory EEPROM of the
* unit itself
*/
ivm@50 {
label = "MAIN_CTRL";
compatible = "dummy";
reg = <0x50>;
};
};
i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
/* Temperature sensors */
temp@48 {
label = "front";
compatible = "national,lm75";
reg = <0x48>;
};
temp@49 {
label = "board";
compatible = "national,lm75";
reg = <0x49>;
};
temp@4a {
label = "power";
compatible = "national,lm75";
reg = <0x4a>;
};
temp@4b {
label = "bottom";
compatible = "national,lm75";
reg = <0x4b>;
};
};
i2c@6 {
reg = <6>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@5 {
reg = <5>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@7 {
reg = <7>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <264000000>;
interrupts = <9 0x8>;
interrupt-parent = <&ipic>;
};
dma@82a8 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8309-dma", "fsl,elo-dma";
reg = <0x82a8 4>;
ranges = <0 0x8100 0x1a8>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8309-dma-channel",
"fsl,elo-dma-channel";
reg = <0 0x80>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@80 {
compatible = "fsl,mpc8309-dma-channel",
"fsl,elo-dma-channel";
reg = <0x80 0x80>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@100 {
compatible = "fsl,mpc8309-dma-channel",
"fsl,elo-dma-channel";
reg = <0x100 0x80>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@180 {
compatible = "fsl,mpc8309-dma-channel",
"fsl,elo-dma-channel";
reg = <0x180 0x28>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
};
ipic: pic@700 {
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "fsl,pq2pro-pic", "fsl,ipic";
interrupt-controller;
reg = <0x700 0x100>;
device_type = "ipic";
};
gpio1: gpio-controller@c00 {
#gpio-cells = <2>;
compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio";
reg = <0xc00 0x100>;
interrupts = <75 0x8>;
interrupt-parent = <&ipic>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio-controller@d00 {
#gpio-cells = <2>;
compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio";
reg = <0xd00 0x100>;
interrupts = <75 0x8>;
interrupt-parent = <&ipic>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
};
spi@7000 {
cell-index = <0>;
compatible = "fsl,spi";
reg = <0x7000 0x1000>;
interrupts = <16 0x8>;
interrupt-parent = <&ipic>;
mode = "cpu";
#address-cells = <1>;
#size-cells = <0>;
/* GPIO_15 chipselect for ZYNQ flash */
gpios = <&gpio1 15 0>;
zynq_flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,m25p80";
reg = <0>;
spi-max-frequency = <4000000>;
m25p,fast-read;
partition@0 {
label = "bootloader";
reg = <0x0 0x01000000>;
};
};
};
};
qe: qe@e0100000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "qe";
compatible = "fsl,qe";
ranges = <0x0 0xe0100000 0x00100000>;
reg = <0xe0100000 0x480>;
brg-frequency = <0>;
bus-frequency = <396000000>;
fsl,qe-num-snums = <32>;
muram@10000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,qe-muram", "fsl,cpm-muram";
ranges = <0x0 0x00010000 0x00004000>;
data-only@0 {
compatible = "fsl,qe-muram-data",
"fsl,cpm-muram-data";
reg = <0x0 0x4000>;
};
};
/* ZYNQ (UCC1, MDIO 0x10, MII) */
enet_zynq: ethernet@2000 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <1>;
reg = <0x2000 0x200>;
interrupts = <32>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
/*id=0, full-dup, 100M, no-pause, no-asym_p*/
fixed-link = <0 1 100 0 0>;
rx-clock-name = "clk9";
tx-clock-name = "clk10";
phy-connection-type = "mii";
};
/* Piggy2 (UCC3, MDIO 0x00, RMII) */
enet_piggy2: ucc@2200 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <3>;
reg = <0x2200 0x200>;
interrupts = <34>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk12";
phy-handle = <&phy_piggy2>;
phy-connection-type = "rmii";
};
mdio@2320 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2320 0x38>;
compatible = "fsl,ucc-mdio";
/* Piggy2 (UCC3, MDIO 0x00, RMII) */
phy_piggy2: ethernet-phy@0 {
reg = <0x0>;
device_type = "ethernet-phy";
};
/* Explicitly set the tbi-phy to a non-zero address
* so that it does not conflict with phy_piggy2 that
* is unfortunately at address 0
*/
tbi1: tbi-phy@1 {
reg = <0x1>;
device_type = "tbi-phy";
};
};
qeic: interrupt-controller@80 {
interrupt-controller;
compatible = "fsl,qe-ic";
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <0x80 0x80>;
big-endian;
interrupts = <32 8 33 8>;
interrupt-parent = <&ipic>;
};
bootcount@0x13ff8 {
device_type = "bootcount";
compatible = "u-boot,bootcount";
reg = <0x13ff8 0x08>;
};
};
localbus@e0005000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8309-localbus", "fsl,pq2pro-localbus",
"simple-bus";
reg = <0xe0005000 0xd8>;
ranges = <0 0 0xf0000000 0x04000000
1 0 0xe8000000 0x01000000
2 0 0xe0000000 0x10000000
3 0 0xb0000000 0x10000000>;
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0x00000000 0x04000000>;
bank-width = <2>;
nornand = "nor";
#address-cells = <1>;
#size-cells = <1>;
use-advanced-sector-protection;
partition@0 { /* 768KB */
label = "u-boot";
reg = <0 0xc0000>;
};
partition@c0000 { /* 256KB */
label = "qe-fw";
reg = <0xc0000 0x40000>;
};
partition@100000 { /* 128KB */
label = "env";
reg = <0x100000 0x20000>;
};
partition@120000 { /* 128KB */
label = "envred";
reg = <0x120000 0x20000>;
};
partition@140000 { /* 64256KB */
label = "ubi0";
reg = <0x140000 0x3EC0000>;
};
};
};
};
#include "km8309-uboot.dtsi"

142
arch/powerpc/dts/kmtepr2.dts Normal file
View file

@ -0,0 +1,142 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA TEPR2 Device Tree Source
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
#include "km8321.dtsi"
/ {
model = "KMTEPR2";
compatible = "ABB,kmpbec8321";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet_piggy2;
serial0 = &serial0;
};
};
&i2c0 {
mux@70 {
compatible = "nxp,pca9547";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
/* Inventory EEPROM of the unit itself */
ivm@50 {
label = "MAIN_CTRL";
compatible = "dummy";
reg = <0x50>;
};
};
i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
/* Temperature sensors */
temp@49 {
label = "board";
compatible = "national,lm75";
reg = <0x49>;
};
temp@4a {
label = "power";
compatible = "national,lm75";
reg = <0x4a>;
};
};
};
};
&par_io {
/* UCC5 as HDLC controller for ICN */
pio_ucc5: ucc_pin@04 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
2 0 1 0 2 0 /* TxD0 */
2 8 2 0 2 0 /* RxD0 */
2 29 2 0 2 0 /* CTS */
3 30 2 0 1 0 /* ICN CLK */
>;
};
/* UCC4 Piggy Ethernet */
pio_ucc4: ucc_pin@03 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
3 4 3 0 2 0 /* MDIO */
3 5 1 0 2 0 /* MDC */
1 18 1 0 1 0 /* TxD0 */
1 19 1 0 1 0 /* TxD1 */
1 22 2 0 1 0 /* RxD0 */
1 23 2 0 1 0 /* RxD1 */
1 26 2 0 1 0 /* RX_ER */
1 28 2 0 1 0 /* RX_DV */
1 30 1 0 1 0 /* TX_EN */
1 31 2 0 1 0 /* CRS */
3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */
>;
};
pio_spi: spi_pin@01 {
pio-map = <
/*
*port pin dir open_drain assignment has_irq
* SPI_MOSI (PD0, bi, f3)
*/
3 0 3 0 1 0
/* SPI_MISO (PD1, bi, f3) */
3 1 3 0 1 0
/* SPI_CLK (PD2, bi, f3) */
3 2 3 0 1 0
>;
};
};
&localbus {
ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
2 0 0xa0000000 0x10000000 /* LB 2 NVSRAM */
3 0 0xb0000000 0x10000000>; /* LB 3 TEP2 */
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0x00000000 0x04000000>;
bank-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
use-advanced-sector-protection;
partition@0 { /* 768KB */
label = "u-boot";
reg = <0 0xC0000>;
};
partition@c0000 { /* 128KB */
label = "env";
reg = <0xc0000 0x20000>;
};
partition@e0000 { /* 128KB */
label = "envred";
reg = <0xe0000 0x20000>;
};
partition@100000 { /* 64512KB */
label = "ubi0";
reg = <0x100000 0x3F00000>;
};
};
};

100
arch/powerpc/dts/kmtuge1.dts Normal file
View file

@ -0,0 +1,100 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA TUGE1 Device Tree Source
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
#include "km8321.dtsi"
/ {
model = "TUGE1";
compatible = "ABB,kmpbec8321";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet_piggy2;
serial0 = &serial0;
};
};
&par_io {
/* UCC5 as HDLC controller for ICN */
pio_ucc5: ucc_pin@04 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
2 0 1 0 2 0 /* TxD0 */
2 8 2 0 2 0 /* RxD0 */
2 29 2 0 2 0 /* CTS */
3 30 2 0 1 0 /* ICN CLK */
>;
};
/* UCC4 Piggy Ethernet */
pio_ucc4: ucc_pin@03 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
3 4 3 0 2 0 /* MDIO */
3 5 1 0 2 0 /* MDC */
1 18 1 0 1 0 /* TxD0 */
1 19 1 0 1 0 /* TxD1 */
1 22 2 0 1 0 /* RxD0 */
1 23 2 0 1 0 /* RxD1 */
1 26 2 0 1 0 /* RX_ER */
1 28 2 0 1 0 /* RX_DV */
1 30 1 0 1 0 /* TX_EN */
1 31 2 0 1 0 /* CRS */
3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */
>;
};
pio_spi: spi_pin@01 {
pio-map = <
/*
*port pin dir open_drain assignment has_irq
* SPI_MOSI (PD0, bi, f3)
*/
3 0 3 0 1 0
/* SPI_MISO (PD1, bi, f3) */
3 1 3 0 1 0
/* SPI_CLK (PD2, bi, f3) */
3 2 3 0 1 0
>;
};
};
&localbus {
ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
2 0 0xa0000000 0x10000000>; /* LB 2 PAXI */
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0x00000000 0x04000000>;
bank-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 { /* 768KB */
label = "u-boot";
reg = <0 0xC0000>;
};
partition@c0000 { /* 128KB */
label = "env";
reg = <0xc0000 0x20000>;
};
partition@e0000 { /* 128KB */
label = "envred";
reg = <0xe0000 0x20000>;
};
partition@100000 { /* 64512KB */
label = "ubi0";
reg = <0x100000 0x3F00000>;
};
};
};

100
arch/powerpc/dts/kmtuxa1.dts Normal file
View file

@ -0,0 +1,100 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA TUXA1 Device Tree Source
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
#include "km8321.dtsi"
/ {
model = "TUXA1";
compatible = "ABB,kmpbec8321";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet_piggy2;
serial0 = &serial0;
};
};
&par_io {
/* UCC5 as HDLC controller for ICN */
pio_ucc5: ucc_pin@04 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
2 0 1 0 2 0 /* TxD0 */
2 8 2 0 2 0 /* RxD0 */
2 29 2 0 2 0 /* CTS */
3 30 2 0 1 0 /* ICN CLK */
>;
};
/* UCC4 Piggy Ethernet */
pio_ucc4: ucc_pin@03 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
3 4 3 0 2 0 /* MDIO */
3 5 1 0 2 0 /* MDC */
1 18 1 0 1 0 /* TxD0 */
1 19 1 0 1 0 /* TxD1 */
1 22 2 0 1 0 /* RxD0 */
1 23 2 0 1 0 /* RxD1 */
1 26 2 0 1 0 /* RX_ER */
1 28 2 0 1 0 /* RX_DV */
1 30 1 0 1 0 /* TX_EN */
1 31 2 0 1 0 /* CRS */
3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */
>;
};
pio_spi: spi_pin@01 {
pio-map = <
/*
*port pin dir open_drain assignment has_irq
* SPI_MOSI (PD0, bi, f3)
*/
3 0 3 0 1 0
/* SPI_MISO (PD1, bi, f3) */
3 1 3 0 1 0
/* SPI_CLK (PD2, bi, f3) */
3 2 3 0 1 0
>;
};
};
&localbus {
ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
2 0 0xa0000000 0x10000000 /* LB 2 LPXF */
3 0 0xb0000000 0x10000000>; /* LB 3 PINC2 */
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0x00000000 0x04000000>;
bank-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 { /* 768KB */
label = "u-boot";
reg = <0 0xC0000>;
};
partition@c0000 { /* 128KB */
label = "env";
reg = <0xc0000 0x20000>;
};
partition@e0000 { /* 128KB */
label = "envred";
reg = <0xe0000 0x20000>;
};
partition@100000 { /* 64512KB */
label = "ubi0";
reg = <0x100000 0x3F00000>;
};
};
};

1
arch/powerpc/dts/p1010rdb-pa.dts
View file

@ -15,3 +15,4 @@
};
/include/ "p1010si-post.dtsi"
/include/ "p1010rdb.dtsi"

1
arch/powerpc/dts/p1010rdb-pa_36b.dts
View file

@ -15,3 +15,4 @@
};
/include/ "p1010si-post.dtsi"
/include/ "p1010rdb.dtsi"

67
arch/powerpc/dts/p1010rdb.dtsi
View file

@ -4,11 +4,78 @@
*
* Copyright 2020 NXP
*/
/ {
aliases {
spi0 = &espi0;
};
};
&soc {
mdio@24000 {
phy0: ethernet-phy@0 {
reg = <0x1>;
};
phy1: ethernet-phy@1 {
reg = <0x0>;
};
phy2: ethernet-phy@2 {
reg = <0x2>;
};
tbi-phy@3 {
device_type = "tbi-phy";
reg = <0x3>;
};
};
mdio@25000 {
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
mdio@26000 {
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet0: ethernet@b0000 {
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
};
enet1: ethernet@b1000 {
phy-handle = <&phy1>;
tbi-handle = <&tbi0>;
phy-connection-type = "sgmii";
};
enet2: ethernet@b2000 {
phy-handle = <&phy2>;
tbi-handle = <&tbi1>;
phy-connection-type = "sgmii";
};
i2c@3000 {
rtc@68 {
compatible = "pericom,pt7c4338";
reg = <0x68>;
};
};
spi@7000 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <10000000>; /* input clock */
};
};
};

35
arch/powerpc/dts/p1010si-post.dtsi
View file

@ -23,8 +23,43 @@
single-cpu-affinity;
last-interrupt-source = <255>;
};
espi0: spi@7000 {
compatible = "fsl,mpc8536-espi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x7000 0x1000>;
fsl,espi-num-chipselects = <1>;
status = "disabled";
};
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
/include/ "pq3-etsec2-0.dtsi"
enet0: ethernet@b0000 {
queue-group@b0000 {
fsl,rx-bit-map = <0xff>;
fsl,tx-bit-map = <0xff>;
};
};
/include/ "pq3-etsec2-1.dtsi"
enet1: ethernet@b1000 {
queue-group@b1000 {
fsl,rx-bit-map = <0xff>;
fsl,tx-bit-map = <0xff>;
};
};
/include/ "pq3-etsec2-2.dtsi"
enet2: ethernet@b2000 {
queue-group@b2000 {
fsl,rx-bit-map = <0xff>;
fsl,tx-bit-map = <0xff>;
};
};
};
/* controller at 0x9000 */

Some files were not shown because too many files have changed in this diff Show more