Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-29 16:10:58 +00:00
Code Issues Projects Releases Packages Wiki Activity

ARM: dts: stm32: Adjust PLL4 settings on AV96 again

Browse source 
PLL4Q is supplying both FDCAN and LTDC. In case HDMI is in use, the
50 MHz generated from PLL4Q cannot be divided well enough to produce
accurate clock for HDMI pixel clock. Adjust it to generate 74.25 MHz
instead. The PLL4P/PLL4R are generating 99 MHz instead of 100 MHz,
which is in tolerance for the SDMMC.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Gerald Baeza <gerald.baeza@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
This commit is contained in:
Marek Vasut 2020-08-22 22:45:25 +02:00 committed by Patrick Delaunay
parent 43e2d1dd47
commit b6055945d6
1 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
View file

@ -132,11 +132,11 @@
u-boot,dm-pre-reloc;
};
/* VCO = 600.0 MHz => P = 100, Q = 50, R = 100 */
/* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
cfg = < 1 49 5 11 5 PQR(1,1,1) >;
cfg = < 3 98 5 7 5 PQR(1,1,1) >;
u-boot,dm-pre-reloc;
};
};