mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-24 21:54:01 +00:00
Merge tag 'u-boot-rockchip-20201031' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- New PX30 board: Engicam PX30.Core; - Fix USB HID support for rock960; - Remove host endianness dependency for rockchip mkimage; - dts update for rk3288-tinker; - Enable console MUX for some ROCKPi boards; - Add config-based ddr selection for px30;
This commit is contained in:
commit
2c31d7e746
32 changed files with 773 additions and 35 deletions
|
@ -72,6 +72,8 @@ dtb-$(CONFIG_MACH_S700) += \
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|||
dtb-$(CONFIG_ROCKCHIP_PX30) += \
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px30-evb.dtb \
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px30-firefly.dtb \
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px30-px30-core-ctouch2.dtb \
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px30-px30-core-edimm2.2.dtb \
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rk3326-odroid-go2.dtb
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dtb-$(CONFIG_ROCKCHIP_RK3036) += \
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|
|
39
arch/arm/dts/px30-engicam-common.dtsi
Normal file
39
arch/arm/dts/px30-engicam-common.dtsi
Normal file
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@ -0,0 +1,39 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Engicam srl
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* Copyright (c) 2020 Amarula Solutions
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* Copyright (c) 2020 Amarula Solutions(India)
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*/
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/ {
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vcc5v0_sys: vcc5v0-sys {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_sys"; /* +5V */
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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};
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&gmac {
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clock_in_out = "output";
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phy-supply = <&vcc_3v3>; /* +3V3_SOM */
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snps,reset-active-low;
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snps,reset-delays-us = <0 50000 50000>;
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snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&sdmmc {
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cap-sd-highspeed;
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card-detect-delay = <800>;
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vmmc-supply = <&vcc_3v3>; /* +3V3_SOM */
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vqmmc-supply = <&vcc_3v3>;
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status = "okay";
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};
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&uart2 {
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pinctrl-0 = <&uart2m1_xfer>;
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status = "okay";
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};
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8
arch/arm/dts/px30-engicam-ctouch2.dtsi
Normal file
8
arch/arm/dts/px30-engicam-ctouch2.dtsi
Normal file
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@ -0,0 +1,8 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Engicam srl
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* Copyright (c) 2020 Amarula Solutions
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* Copyright (c) 2020 Amarula Solutions(India)
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*/
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#include "px30-engicam-common.dtsi"
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7
arch/arm/dts/px30-engicam-edimm2.2.dtsi
Normal file
7
arch/arm/dts/px30-engicam-edimm2.2.dtsi
Normal file
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@ -0,0 +1,7 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Engicam srl
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* Copyright (c) 2020 Amarula Solutions(India)
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*/
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#include "px30-engicam-common.dtsi"
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22
arch/arm/dts/px30-px30-core-ctouch2.dts
Normal file
22
arch/arm/dts/px30-px30-core-ctouch2.dts
Normal file
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@ -0,0 +1,22 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
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* Copyright (c) 2020 Engicam srl
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* Copyright (c) 2020 Amarula Solutions
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* Copyright (c) 2020 Amarula Solutions(India)
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*/
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/dts-v1/;
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#include "px30.dtsi"
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#include "px30-engicam-ctouch2.dtsi"
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#include "px30-px30-core.dtsi"
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/ {
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model = "Engicam PX30.Core C.TOUCH 2.0";
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compatible = "engicam,px30-core-ctouch2", "engicam,px30-px30-core",
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"rockchip,px30";
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chosen {
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stdout-path = "serial2:115200n8";
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};
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};
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21
arch/arm/dts/px30-px30-core-edimm2.2.dts
Normal file
21
arch/arm/dts/px30-px30-core-edimm2.2.dts
Normal file
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@ -0,0 +1,21 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
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* Copyright (c) 2020 Engicam srl
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* Copyright (c) 2020 Amarula Solutions(India)
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*/
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/dts-v1/;
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#include "px30.dtsi"
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#include "px30-engicam-edimm2.2.dtsi"
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#include "px30-px30-core.dtsi"
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/ {
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model = "Engicam PX30.Core EDIMM2.2 Starter Kit";
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compatible = "engicam,px30-core-edimm2.2", "engicam,px30-px30-core",
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"rockchip,px30";
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chosen {
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stdout-path = "serial2:115200n8";
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};
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};
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232
arch/arm/dts/px30-px30-core.dtsi
Normal file
232
arch/arm/dts/px30-px30-core.dtsi
Normal file
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@ -0,0 +1,232 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
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* Copyright (c) 2020 Engicam srl
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* Copyright (c) 2020 Amarula Solutons
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* Copyright (c) 2020 Amarula Solutons(India)
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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/ {
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compatible = "engicam,px30-px30-core", "rockchip,px30";
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};
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&cpu0 {
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cpu-supply = <&vdd_arm>;
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};
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&cpu1 {
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cpu-supply = <&vdd_arm>;
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};
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&cpu2 {
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cpu-supply = <&vdd_arm>;
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};
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&cpu3 {
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cpu-supply = <&vdd_arm>;
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};
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&emmc {
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cap-mmc-highspeed;
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mmc-hs200-1_8v;
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non-removable;
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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rk809: pmic@20 {
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compatible = "rockchip,rk809";
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reg = <0x20>;
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interrupt-parent = <&gpio0>;
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interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pmic_int>;
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rockchip,system-power-controller;
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wakeup-source;
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#clock-cells = <1>;
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clock-output-names = "rk808-clkout1", "rk808-clkout2";
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vcc1-supply = <&vcc5v0_sys>;
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vcc2-supply = <&vcc5v0_sys>;
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vcc3-supply = <&vcc5v0_sys>;
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vcc4-supply = <&vcc5v0_sys>;
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vcc5-supply = <&vcc3v3_sys>;
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vcc6-supply = <&vcc3v3_sys>;
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vcc7-supply = <&vcc3v3_sys>;
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vcc8-supply = <&vcc3v3_sys>;
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vcc9-supply = <&vcc5v0_sys>;
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regulators {
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vdd_log: DCDC_REG1 {
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regulator-name = "vdd_log";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <950000>;
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regulator-max-microvolt = <1350000>;
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regulator-ramp-delay = <6001>;
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <950000>;
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};
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};
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vdd_arm: DCDC_REG2 {
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regulator-name = "vdd_arm";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <950000>;
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regulator-max-microvolt = <1350000>;
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regulator-ramp-delay = <6001>;
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regulator-state-mem {
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regulator-off-in-suspend;
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regulator-suspend-microvolt = <950000>;
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};
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};
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vcc_ddr: DCDC_REG3 {
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regulator-name = "vcc_ddr";
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regulator-always-on;
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regulator-boot-on;
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regulator-state-mem {
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regulator-on-in-suspend;
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};
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};
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vcc_3v3: DCDC_REG4 {
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regulator-name = "vcc_3v3";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <3300000>;
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};
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};
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vcc3v3_sys: DCDC_REG5 {
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regulator-name = "vcc3v3_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <3300000>;
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};
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};
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vcc_1v0: LDO_REG1 {
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regulator-name = "vcc_1v0";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <1000000>;
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};
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};
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vcc_1v8: LDO_REG2 {
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regulator-name = "vcc_1v8";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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|
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <1800000>;
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};
|
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};
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|
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vdd_1v0: LDO_REG3 {
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regulator-name = "vdd_1v0";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
|
||||
|
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regulator-state-mem {
|
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regulator-on-in-suspend;
|
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regulator-suspend-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v0_pmu: LDO_REG4 {
|
||||
regulator-name = "vcc3v0_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc5v0_host: SWITCH_REG2 {
|
||||
regulator-name = "vcc5v0_host";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&io_domains {
|
||||
vccio1-supply = <&vcc_3v3>;
|
||||
vccio2-supply = <&vcc_3v3>;
|
||||
vccio3-supply = <&vcc_3v3>;
|
||||
vccio4-supply = <&vcc_3v3>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc_3v3>;
|
||||
pmuio2-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <1>;
|
||||
status = "okay";
|
||||
};
|
|
@ -5,6 +5,12 @@
|
|||
|
||||
#include "rk3288-u-boot.dtsi"
|
||||
|
||||
/{
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
};
|
||||
};
|
||||
|
||||
&dmc {
|
||||
rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
|
||||
0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
|
||||
|
|
|
@ -17,6 +17,13 @@
|
|||
rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
m24c08@50 {
|
||||
compatible = "at,24c08", "i2c-eeprom";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
|
|
@ -27,18 +27,7 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
reg-shift = <2>;
|
||||
};
|
||||
|
||||
&usb_host1 {
|
||||
vbus-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
m24c08@50 {
|
||||
compatible = "at,24c08", "i2c-eeprom";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -2,10 +2,31 @@ if ROCKCHIP_PX30
|
|||
|
||||
config TARGET_EVB_PX30
|
||||
bool "EVB_PX30"
|
||||
help
|
||||
This target config option used for below listed px30 boards.
|
||||
|
||||
EVB_PX30:
|
||||
* EVB_PX30 is an evaluation board for Rockchip PX30.
|
||||
|
||||
config TARGET_ODROID_GO2
|
||||
bool "ODROID_GO2"
|
||||
|
||||
config TARGET_PX30_CORE
|
||||
bool "Engicam PX30.Core"
|
||||
help
|
||||
PX30.Core EDIMM2.2:
|
||||
* PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
|
||||
* EDIMM2.2 is a Form Factor Capacitive Evaluation Board from Engicam.
|
||||
* PX30.Core needs to mount on top of EDIMM2.2 for creating complete
|
||||
PX30.Core EDIMM2.2 Starter Kit.
|
||||
|
||||
PX30.Core CTOUCH2:
|
||||
* PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
|
||||
* CTOUCH2.0 is a general purpose Carrier board with capacitive
|
||||
touch interface support.
|
||||
* PX30.Core needs to mount on top of CTOUCH2.0 for creating complete
|
||||
PX30.Core C.TOUCH Carrier board.
|
||||
|
||||
config ROCKCHIP_BOOT_MODE_REG
|
||||
default 0xff010200
|
||||
|
||||
|
@ -39,6 +60,7 @@ config DEBUG_UART_CHANNEL
|
|||
For using the UART for early debugging the route to use needs
|
||||
to be declared (0 or 1).
|
||||
|
||||
source "board/engicam/px30_core/Kconfig"
|
||||
source "board/hardkernel/odroid_go2/Kconfig"
|
||||
source "board/rockchip/evb_px30/Kconfig"
|
||||
|
||||
|
|
8
board/engicam/common/Kconfig
Normal file
8
board/engicam/common/Kconfig
Normal file
|
@ -0,0 +1,8 @@
|
|||
config IMX6_ENGICAM_COMMON
|
||||
bool "Engicam i.MX6 Common code"
|
||||
depends on SPL && MX6
|
||||
default y if TARGET_MX6Q_ENGICAM || TARGET_MX6UL_ENGICAM
|
||||
help
|
||||
Common SPL and U-Boot proper code for Engicam i.MX6 targets.
|
||||
|
||||
Enable it in board Kconfig if it uses i.MX6 variant Engicam boards.
|
|
@ -1,5 +1,8 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
# Copyright (C) 2016 Amarula Solutions B.V.
|
||||
|
||||
obj-y := board.o
|
||||
obj-$(CONFIG_SPL_BUILD) += spl.o
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-$(CONFIG_IMX6_ENGICAM_COMMON) += spl.o
|
||||
else
|
||||
obj-$(CONFIG_IMX6_ENGICAM_COMMON) += board.o
|
||||
endif
|
||||
|
|
|
@ -9,4 +9,6 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "imx6-engicam"
|
||||
|
||||
source "board/engicam/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
@ -9,4 +9,6 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "imx6-engicam"
|
||||
|
||||
source "board/engicam/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
16
board/engicam/px30_core/Kconfig
Normal file
16
board/engicam/px30_core/Kconfig
Normal file
|
@ -0,0 +1,16 @@
|
|||
if TARGET_PX30_CORE
|
||||
|
||||
config SYS_BOARD
|
||||
default "px30_core"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "engicam"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "px30_core"
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select RAM_PX30_DDR4
|
||||
|
||||
endif
|
13
board/engicam/px30_core/MAINTAINERS
Normal file
13
board/engicam/px30_core/MAINTAINERS
Normal file
|
@ -0,0 +1,13 @@
|
|||
PX30-Core-CTOUCH2.0
|
||||
M: Jagan Teki <jagan@amarulasolutions.com>
|
||||
M: Suniel Mahesh <sunil@amarulasolutions.com>
|
||||
S: Maintained
|
||||
F: configs/px30-core-ctouch2-px30_defconfig
|
||||
|
||||
PX30-Core-EDIMM2.2
|
||||
M: Jagan Teki <jagan@amarulasolutions.com>
|
||||
M: Suniel Mahesh <sunil@amarulasolutions.com>
|
||||
S: Maintained
|
||||
F: board/engicam/px30_core
|
||||
F: include/configs/px30_core.h
|
||||
F: configs/px30-core-edimm2.2-px30_defconfig
|
7
board/engicam/px30_core/Makefile
Normal file
7
board/engicam/px30_core/Makefile
Normal file
|
@ -0,0 +1,7 @@
|
|||
#
|
||||
# Copyright (c) 2020 Amarula Solutions(India)
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += px30_core.o
|
4
board/engicam/px30_core/px30_core.c
Normal file
4
board/engicam/px30_core/px30_core.c
Normal file
|
@ -0,0 +1,4 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) 2020 Amarula Solutions(India)
|
||||
*/
|
108
configs/px30-core-ctouch2-px30_defconfig
Normal file
108
configs/px30-core-ctouch2-px30_defconfig
Normal file
|
@ -0,0 +1,108 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x00200000
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_SPL_TEXT_BASE=0x00000000
|
||||
CONFIG_ROCKCHIP_PX30=y
|
||||
CONFIG_TARGET_PX30_CORE=y
|
||||
CONFIG_DEBUG_UART_CHANNEL=1
|
||||
CONFIG_TPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
CONFIG_DEBUG_UART_BASE=0xFF160000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-ctouch2"
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
|
||||
# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-ctouch2.dtb"
|
||||
CONFIG_MISC_INIT_R=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_BOOTROM_SUPPORT=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
CONFIG_SPL_STACK_R=y
|
||||
# CONFIG_TPL_BANNER_PRINT is not set
|
||||
CONFIG_SPL_CRC32_SUPPORT=y
|
||||
CONFIG_SPL_ATF=y
|
||||
# CONFIG_TPL_FRAMEWORK is not set
|
||||
# CONFIG_CMD_BOOTD is not set
|
||||
# CONFIG_CMD_ELF is not set
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_LZMADEC is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
CONFIG_CMD_GPT=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
# CONFIG_CMD_MISC is not set
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_FASTBOOT_BUF_ADDR=0x800800
|
||||
CONFIG_FASTBOOT_BUF_SIZE=0x04000000
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_ROCKCHIP_OTP=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_TPL_RAM=y
|
||||
CONFIG_ROCKCHIP_SDRAM_COMMON=y
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_DM_RNG=y
|
||||
CONFIG_RNG_ROCKCHIP=y
|
||||
# CONFIG_SPECIFY_CONSOLE_INDEX is not set
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_DEBUG_UART_SKIP_INIT=y
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_DWC2_OTG=y
|
||||
CONFIG_DM_VIDEO=y
|
||||
CONFIG_DISPLAY=y
|
||||
CONFIG_LCD=y
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
CONFIG_TPL_TINY_MEMSET=y
|
||||
CONFIG_LZO=y
|
||||
CONFIG_ERRNO_STR=y
|
108
configs/px30-core-edimm2.2-px30_defconfig
Normal file
108
configs/px30-core-edimm2.2-px30_defconfig
Normal file
|
@ -0,0 +1,108 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x00200000
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_SPL_TEXT_BASE=0x00000000
|
||||
CONFIG_ROCKCHIP_PX30=y
|
||||
CONFIG_TARGET_PX30_CORE=y
|
||||
CONFIG_DEBUG_UART_CHANNEL=1
|
||||
CONFIG_TPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
CONFIG_DEBUG_UART_BASE=0xFF160000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-edimm2.2"
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
|
||||
# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-edimm2.2.dtb"
|
||||
CONFIG_MISC_INIT_R=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_BOOTROM_SUPPORT=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
CONFIG_SPL_STACK_R=y
|
||||
# CONFIG_TPL_BANNER_PRINT is not set
|
||||
CONFIG_SPL_CRC32_SUPPORT=y
|
||||
CONFIG_SPL_ATF=y
|
||||
# CONFIG_TPL_FRAMEWORK is not set
|
||||
# CONFIG_CMD_BOOTD is not set
|
||||
# CONFIG_CMD_ELF is not set
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_LZMADEC is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
CONFIG_CMD_GPT=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
# CONFIG_CMD_MISC is not set
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_FASTBOOT_BUF_ADDR=0x800800
|
||||
CONFIG_FASTBOOT_BUF_SIZE=0x04000000
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_ROCKCHIP_OTP=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_TPL_RAM=y
|
||||
CONFIG_ROCKCHIP_SDRAM_COMMON=y
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_DM_RNG=y
|
||||
CONFIG_RNG_ROCKCHIP=y
|
||||
# CONFIG_SPECIFY_CONSOLE_INDEX is not set
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_DEBUG_UART_SKIP_INIT=y
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_DWC2_OTG=y
|
||||
CONFIG_DM_VIDEO=y
|
||||
CONFIG_DISPLAY=y
|
||||
CONFIG_LCD=y
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
CONFIG_TPL_TINY_MEMSET=y
|
||||
CONFIG_LZO=y
|
||||
CONFIG_ERRNO_STR=y
|
|
@ -14,9 +14,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3288-rock-pi-n8"
|
|||
CONFIG_DEBUG_UART=y
|
||||
# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rk3288-rock-pi-n8.dtb"
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
|
||||
|
|
|
@ -3,12 +3,12 @@ CONFIG_ARCH_ROCKCHIP=y
|
|||
CONFIG_SYS_TEXT_BASE=0x00200000
|
||||
CONFIG_ENV_OFFSET=0x3F8000
|
||||
CONFIG_ROCKCHIP_RK3399=y
|
||||
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
|
||||
CONFIG_TARGET_ROCK960_RK3399=y
|
||||
CONFIG_DEBUG_UART_BASE=0xFF1A0000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960"
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb"
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_MISC_INIT_R=y
|
||||
|
@ -41,6 +41,8 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y
|
|||
CONFIG_DM_ETH=y
|
||||
CONFIG_NVME=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_TYPEC=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
|
@ -54,10 +56,11 @@ CONFIG_USB_XHCI_HCD=y
|
|||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_GENERIC=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_ROCKCHIP_USB2_PHY=y
|
||||
CONFIG_DM_KEYBOARD=y
|
||||
CONFIG_USB_KEYBOARD=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_USB_ETHER_ASIX88179=y
|
||||
|
|
|
@ -123,6 +123,9 @@ To build rk3399 boards::
|
|||
Flashing
|
||||
--------
|
||||
|
||||
1. Package the image with U-Boot TPL/SPL
|
||||
-----------------------------------------
|
||||
|
||||
SD Card
|
||||
^^^^^^^
|
||||
|
||||
|
@ -187,6 +190,39 @@ Copy SPI boot images into SD card and boot from SD::
|
|||
sf erase 0x60000 +$filesize
|
||||
sf write $kernel_addr_r 0x60000 ${filesize}
|
||||
|
||||
2. Package the image with Rockchip miniloader
|
||||
---------------------------------------------
|
||||
|
||||
Image package with Rockchip miniloader requires robin [1].
|
||||
|
||||
Create idbloader.img
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
cd u-boot
|
||||
./tools/mkimage -n px30 -T rksd -d rkbin/bin/rk33/px30_ddr_333MHz_v1.15.bin idbloader.img
|
||||
cat rkbin/bin/rk33/px30_miniloader_v1.22.bin >> idbloader.img
|
||||
sudo dd if=idbloader.img of=/dev/sda seek=64
|
||||
|
||||
Create trust.img
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
cd rkbin
|
||||
./tools/trust_merger RKTRUST/PX30TRUST.ini
|
||||
sudo dd if=trust.img of=/dev/sda seek=24576
|
||||
|
||||
Create uboot.img
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
rbink/tools/loaderimage --pack --uboot u-boot-dtb.bin uboot.img 0x200000
|
||||
sudo dd if=uboot.img of=/dev/sda seek=16384
|
||||
|
||||
Note:
|
||||
1. 0x200000 is load address and it's an optional in some platforms.
|
||||
2. rkbin binaries are kept on updating, so would recommend to use the latest versions.
|
||||
|
||||
TODO
|
||||
----
|
||||
|
||||
|
@ -195,5 +231,7 @@ TODO
|
|||
- Document SPI flash boot
|
||||
- Add missing SoC's with it boards list
|
||||
|
||||
[1] https://github.com/rockchip-linux/rkbin
|
||||
|
||||
.. Jagan Teki <jagan@amarulasolutions.com>
|
||||
.. Tuesday 02 June 2020 12:18:57 AM IST
|
||||
.. Wednesday 28 October 2020 06:47:26 PM IST
|
||||
|
|
|
@ -233,6 +233,10 @@ enum {
|
|||
DCLK_VOP_DIV_CON_MASK = 0xff,
|
||||
DCLK_VOP_DIV_CON_SHIFT = 0,
|
||||
|
||||
/* CLKSEL_CON57 */
|
||||
PCLK_ALIVE_DIV_CON_SHIFT = 0,
|
||||
PCLK_ALIVE_DIV_CON_MASK = 0x1f << PCLK_ALIVE_DIV_CON_SHIFT,
|
||||
|
||||
/* CLKSEL_CON58 */
|
||||
CLK_SPI_PLL_SEL_WIDTH = 1,
|
||||
CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
|
||||
|
@ -867,6 +871,17 @@ static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru,
|
|||
return set_rate;
|
||||
}
|
||||
|
||||
static ulong rk3399_alive_get_clk(struct rockchip_cru *cru)
|
||||
{
|
||||
u32 div, val;
|
||||
|
||||
val = readl(&cru->clksel_con[57]);
|
||||
div = (val & PCLK_ALIVE_DIV_CON_MASK) >>
|
||||
PCLK_ALIVE_DIV_CON_SHIFT;
|
||||
|
||||
return DIV_TO_RATE(GPLL_HZ, div);
|
||||
}
|
||||
|
||||
static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru)
|
||||
{
|
||||
u32 div, val;
|
||||
|
@ -936,6 +951,10 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
|
|||
case ACLK_GIC_PRE:
|
||||
case PCLK_DDR:
|
||||
break;
|
||||
case PCLK_ALIVE:
|
||||
case PCLK_WDT:
|
||||
rate = rk3399_alive_get_clk(priv->cru);
|
||||
break;
|
||||
default:
|
||||
log_debug("Unknown clock %lu\n", clk->id);
|
||||
return -ENOENT;
|
||||
|
@ -1502,6 +1521,7 @@ static ulong rk3399_pmuclk_get_rate(struct clk *clk)
|
|||
case PLL_PPLL:
|
||||
return PPLL_HZ;
|
||||
case PCLK_RKPWM_PMU:
|
||||
case PCLK_WDT_M0_PMU:
|
||||
rate = rk3399_pwm_get_clk(priv->pmucru);
|
||||
break;
|
||||
case SCLK_I2C0_PMU:
|
||||
|
|
|
@ -22,6 +22,27 @@ config RAM_ROCKCHIP_DEBUG
|
|||
This is an option for developers to understand the ram drivers
|
||||
initialization, configurations and etc.
|
||||
|
||||
config RAM_PX30_DDR4
|
||||
bool "DDR3 support for Rockchip PX30"
|
||||
depends on RAM_ROCKCHIP && ROCKCHIP_PX30
|
||||
help
|
||||
This enables DDR4 sdram support instead of the default DDR3 support
|
||||
on Rockchip PC30 SoCs.
|
||||
|
||||
config RAM_PX30_LPDDR2
|
||||
bool "LPDDR2 support for Rockchip PX30"
|
||||
depends on RAM_ROCKCHIP && ROCKCHIP_PX30
|
||||
help
|
||||
This enables LPDDR2 sdram support instead of the default DDR3 support
|
||||
on Rockchip PC30 SoCs.
|
||||
|
||||
config RAM_PX30_LPDDR3
|
||||
bool "LPDDR3 support for Rockchip PX30"
|
||||
depends on RAM_ROCKCHIP && ROCKCHIP_PX30
|
||||
help
|
||||
This enables LPDDR3 sdram support instead of the default DDR3 support
|
||||
on Rockchip PC30 SoCs.
|
||||
|
||||
config RAM_RK3399_LPDDR4
|
||||
bool "LPDDR4 support for Rockchip RK3399"
|
||||
depends on RAM_ROCKCHIP && ROCKCHIP_RK3399
|
||||
|
|
|
@ -125,7 +125,15 @@ u32 addrmap[][8] = {
|
|||
struct dram_info dram_info;
|
||||
|
||||
struct px30_sdram_params sdram_configs[] = {
|
||||
#if defined(CONFIG_RAM_PX30_DDR4)
|
||||
#include "sdram-px30-ddr4-detect-333.inc"
|
||||
#elif defined(CONFIG_RAM_PX30_LPDDR2)
|
||||
#include "sdram-px30-lpddr2-detect-333.inc"
|
||||
#elif defined(CONFIG_RAM_PX30_LPDDR3)
|
||||
#include "sdram-px30-lpddr3-detect-333.inc"
|
||||
#else
|
||||
#include "sdram-px30-ddr3-detect-333.inc"
|
||||
#endif
|
||||
};
|
||||
|
||||
struct ddr_phy_skew skew = {
|
||||
|
|
|
@ -22,7 +22,7 @@ menuconfig VIDEO_ROCKCHIP
|
|||
config VIDEO_ROCKCHIP_MAX_XRES
|
||||
int "Maximum horizontal resolution (for memory allocation purposes)"
|
||||
depends on VIDEO_ROCKCHIP
|
||||
default 3840 if ROCKCHIP_RK3399 && DISPLAY_ROCKCHIP_HDMI
|
||||
default 3840 if DISPLAY_ROCKCHIP_HDMI
|
||||
default 1920
|
||||
help
|
||||
The maximum horizontal resolution to support for the framebuffer.
|
||||
|
@ -32,7 +32,7 @@ config VIDEO_ROCKCHIP_MAX_XRES
|
|||
config VIDEO_ROCKCHIP_MAX_YRES
|
||||
int "Maximum vertical resolution (for memory allocation purposes)"
|
||||
depends on VIDEO_ROCKCHIP
|
||||
default 2160 if ROCKCHIP_RK3399 && DISPLAY_ROCKCHIP_HDMI
|
||||
default 2160 if DISPLAY_ROCKCHIP_HDMI
|
||||
default 1080
|
||||
help
|
||||
The maximum vertical resolution to support for the framebuffer.
|
||||
|
|
|
@ -559,6 +559,12 @@ static int rk_edp_link_train_ce(struct rk_edp_priv *edp)
|
|||
channel_eq = 0;
|
||||
for (tries = 0; tries < 5; tries++) {
|
||||
rk_edp_set_link_training(edp, edp->train_set);
|
||||
ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET,
|
||||
edp->train_set,
|
||||
edp->link_train.lane_count);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
udelay(400);
|
||||
|
||||
if (rk_edp_dpcd_read_link_status(edp, status) < 0) {
|
||||
|
|
15
include/configs/px30_core.h
Normal file
15
include/configs/px30_core.h
Normal file
|
@ -0,0 +1,15 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2020 Amarula Solutions(India)
|
||||
*/
|
||||
|
||||
#ifndef __PX30_CORE_H
|
||||
#define __PX30_CORE_H
|
||||
|
||||
#include <configs/px30_common.h>
|
||||
|
||||
#define ROCKCHIP_DEVICE_SETTINGS \
|
||||
"stdout=serial,vidconsole\0" \
|
||||
"stderr=serial,vidconsole\0"
|
||||
|
||||
#endif /* __PX30_CORE_H */
|
|
@ -15,4 +15,6 @@
|
|||
|
||||
#define SDRAM_BANK_SIZE (2UL << 30)
|
||||
|
||||
#define CONFIG_USB_OHCI_NEW
|
||||
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
|
||||
#endif
|
||||
|
|
|
@ -221,12 +221,13 @@ bool rkcommon_need_rc4_spl(struct image_tool_params *params)
|
|||
static void rkcommon_set_header0(void *buf, struct image_tool_params *params)
|
||||
{
|
||||
struct header0_info *hdr = buf;
|
||||
uint32_t init_boot_size;
|
||||
|
||||
memset(buf, '\0', RK_INIT_OFFSET * RK_BLK_SIZE);
|
||||
hdr->signature = RK_SIGNATURE;
|
||||
hdr->disable_rc4 = !rkcommon_need_rc4_spl(params);
|
||||
hdr->init_offset = RK_INIT_OFFSET;
|
||||
hdr->init_size = spl_params.init_size / RK_BLK_SIZE;
|
||||
hdr->signature = cpu_to_le32(RK_SIGNATURE);
|
||||
hdr->disable_rc4 = cpu_to_le32(!rkcommon_need_rc4_spl(params));
|
||||
hdr->init_offset = cpu_to_le16(RK_INIT_OFFSET);
|
||||
hdr->init_size = cpu_to_le16(spl_params.init_size / RK_BLK_SIZE);
|
||||
|
||||
/*
|
||||
* init_boot_size needs to be set, as it is read by the BootROM
|
||||
|
@ -237,11 +238,10 @@ static void rkcommon_set_header0(void *buf, struct image_tool_params *params)
|
|||
* for a more detailed explanation by Andy Yan
|
||||
*/
|
||||
if (spl_params.boot_file)
|
||||
hdr->init_boot_size =
|
||||
hdr->init_size + spl_params.boot_size / RK_BLK_SIZE;
|
||||
init_boot_size = spl_params.init_size + spl_params.boot_size;
|
||||
else
|
||||
hdr->init_boot_size =
|
||||
hdr->init_size + RK_MAX_BOOT_SIZE / RK_BLK_SIZE;
|
||||
init_boot_size = spl_params.init_size + RK_MAX_BOOT_SIZE;
|
||||
hdr->init_boot_size = cpu_to_le16(init_boot_size / RK_BLK_SIZE);
|
||||
|
||||
rc4_encode(buf, RK_BLK_SIZE, rc4_key);
|
||||
}
|
||||
|
@ -294,14 +294,14 @@ static int rkcommon_parse_header(const void *buf, struct header0_info *header0,
|
|||
memcpy((void *)header0, buf, sizeof(struct header0_info));
|
||||
rc4_encode((void *)header0, sizeof(struct header0_info), rc4_key);
|
||||
|
||||
if (header0->signature != RK_SIGNATURE)
|
||||
if (le32_to_cpu(header0->signature) != RK_SIGNATURE)
|
||||
return -EPROTO;
|
||||
|
||||
/* We don't support RC4 encoded image payloads here, yet... */
|
||||
if (header0->disable_rc4 == 0)
|
||||
if (le32_to_cpu(header0->disable_rc4) == 0)
|
||||
return -ENOSYS;
|
||||
|
||||
hdr1_offset = header0->init_offset * RK_BLK_SIZE;
|
||||
hdr1_offset = le16_to_cpu(header0->init_offset) * RK_BLK_SIZE;
|
||||
hdr1_sdmmc = (struct header1_info *)(buf + hdr1_offset);
|
||||
hdr1_spi = (struct header1_info *)(buf +
|
||||
rkcommon_offset_to_spi(hdr1_offset));
|
||||
|
@ -359,7 +359,7 @@ void rkcommon_print_header(const void *buf)
|
|||
struct header0_info header0;
|
||||
struct spl_info *spl_info;
|
||||
uint8_t image_type;
|
||||
int ret, boot_size;
|
||||
int ret, boot_size, init_size;
|
||||
|
||||
ret = rkcommon_parse_header(buf, &header0, &spl_info);
|
||||
|
||||
|
@ -377,9 +377,10 @@ void rkcommon_print_header(const void *buf)
|
|||
printf("Image Type: Rockchip %s (%s) boot image\n",
|
||||
spl_info->spl_hdr,
|
||||
(image_type == IH_TYPE_RKSD) ? "SD/MMC" : "SPI");
|
||||
printf("Init Data Size: %d bytes\n", header0.init_size * RK_BLK_SIZE);
|
||||
init_size = le16_to_cpu(header0.init_size) * RK_BLK_SIZE;
|
||||
printf("Init Data Size: %d bytes\n", init_size);
|
||||
|
||||
boot_size = (header0.init_boot_size - header0.init_size) * RK_BLK_SIZE;
|
||||
boot_size = le16_to_cpu(header0.init_boot_size) * RK_BLK_SIZE - init_size;
|
||||
if (boot_size != RK_MAX_BOOT_SIZE)
|
||||
printf("Boot Data Size: %d bytes\n", boot_size);
|
||||
}
|
||||
|
|
Loading…
Reference in a new issue