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https://github.com/AsahiLinux/u-boot
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arm: dts: r8a774a1: Import DTS from Linux 5.9-rc4
Synchronize RZ/G2M SoC DTs with mainline Linux 5.9-rc4 commit
f4d51dffc6c0 ("Linux 5.9-rc4")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
This commit is contained in:
Biju Das
Marek Vasut
parent
953a3be768
commit
00407251c3
3 changed files with 51 additions and 57 deletions
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@ -10,6 +10,8 @@
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#include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
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#include <dt-bindings/power/r8a774a1-sysc.h>
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#define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4
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/ {
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compatible = "renesas,r8a774a1";
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#address-cells = <2>;
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@ -2250,7 +2252,7 @@
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status = "disabled";
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};
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sdhi0: sd@ee100000 {
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sdhi0: mmc@ee100000 {
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compatible = "renesas,sdhi-r8a774a1",
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"renesas,rcar-gen3-sdhi";
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reg = <0 0xee100000 0 0x2000>;
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@ -2262,7 +2264,7 @@
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status = "disabled";
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};
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sdhi1: sd@ee120000 {
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sdhi1: mmc@ee120000 {
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compatible = "renesas,sdhi-r8a774a1",
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"renesas,rcar-gen3-sdhi";
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reg = <0 0xee120000 0 0x2000>;
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@ -2274,7 +2276,7 @@
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status = "disabled";
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};
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sdhi2: sd@ee140000 {
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sdhi2: mmc@ee140000 {
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compatible = "renesas,sdhi-r8a774a1",
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"renesas,rcar-gen3-sdhi";
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reg = <0 0xee140000 0 0x2000>;
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@ -2286,7 +2288,7 @@
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status = "disabled";
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};
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sdhi3: sd@ee160000 {
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sdhi3: mmc@ee160000 {
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compatible = "renesas,sdhi-r8a774a1",
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"renesas,rcar-gen3-sdhi";
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reg = <0 0xee160000 0 0x2000>;
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@ -10,56 +10,50 @@
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/* r8a774a1 CPG Core Clocks */
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#define R8A774A1_CLK_Z 0
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#define R8A774A1_CLK_Z2 1
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#define R8A774A1_CLK_ZR 2
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#define R8A774A1_CLK_ZG 3
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#define R8A774A1_CLK_ZTR 4
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#define R8A774A1_CLK_ZTRD2 5
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#define R8A774A1_CLK_ZT 6
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#define R8A774A1_CLK_ZX 7
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#define R8A774A1_CLK_S0D1 8
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#define R8A774A1_CLK_S0D2 9
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#define R8A774A1_CLK_S0D3 10
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#define R8A774A1_CLK_S0D4 11
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#define R8A774A1_CLK_S0D6 12
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#define R8A774A1_CLK_S0D8 13
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#define R8A774A1_CLK_S0D12 14
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#define R8A774A1_CLK_S1D1 15
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#define R8A774A1_CLK_S1D2 16
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#define R8A774A1_CLK_S1D4 17
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#define R8A774A1_CLK_S2D1 18
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#define R8A774A1_CLK_S2D2 19
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#define R8A774A1_CLK_S2D4 20
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#define R8A774A1_CLK_S3D1 21
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#define R8A774A1_CLK_S3D2 22
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#define R8A774A1_CLK_S3D4 23
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#define R8A774A1_CLK_LB 24
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#define R8A774A1_CLK_CL 25
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#define R8A774A1_CLK_ZB3 26
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#define R8A774A1_CLK_ZB3D2 27
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#define R8A774A1_CLK_ZB3D4 28
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#define R8A774A1_CLK_CR 29
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#define R8A774A1_CLK_CRD2 30
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#define R8A774A1_CLK_SD0H 31
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#define R8A774A1_CLK_SD0 32
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#define R8A774A1_CLK_SD1H 33
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#define R8A774A1_CLK_SD1 34
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#define R8A774A1_CLK_SD2H 35
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#define R8A774A1_CLK_SD2 36
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#define R8A774A1_CLK_SD3H 37
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#define R8A774A1_CLK_SD3 38
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#define R8A774A1_CLK_SSP2 39
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#define R8A774A1_CLK_SSP1 40
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#define R8A774A1_CLK_SSPRS 41
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#define R8A774A1_CLK_RPC 42
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#define R8A774A1_CLK_RPCD2 43
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#define R8A774A1_CLK_MSO 44
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#define R8A774A1_CLK_CANFD 45
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#define R8A774A1_CLK_HDMI 46
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#define R8A774A1_CLK_CSI0 47
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#define R8A774A1_CLK_CSIREF 48
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#define R8A774A1_CLK_CP 49
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#define R8A774A1_CLK_CPEX 50
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#define R8A774A1_CLK_R 51
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#define R8A774A1_CLK_OSC 52
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#define R8A774A1_CLK_ZG 2
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#define R8A774A1_CLK_ZTR 3
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#define R8A774A1_CLK_ZTRD2 4
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#define R8A774A1_CLK_ZT 5
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#define R8A774A1_CLK_ZX 6
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#define R8A774A1_CLK_S0D1 7
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#define R8A774A1_CLK_S0D2 8
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#define R8A774A1_CLK_S0D3 9
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#define R8A774A1_CLK_S0D4 10
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#define R8A774A1_CLK_S0D6 11
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#define R8A774A1_CLK_S0D8 12
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#define R8A774A1_CLK_S0D12 13
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#define R8A774A1_CLK_S1D2 14
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#define R8A774A1_CLK_S1D4 15
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#define R8A774A1_CLK_S2D1 16
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#define R8A774A1_CLK_S2D2 17
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#define R8A774A1_CLK_S2D4 18
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#define R8A774A1_CLK_S3D1 19
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#define R8A774A1_CLK_S3D2 20
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#define R8A774A1_CLK_S3D4 21
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#define R8A774A1_CLK_LB 22
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#define R8A774A1_CLK_CL 23
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#define R8A774A1_CLK_ZB3 24
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#define R8A774A1_CLK_ZB3D2 25
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#define R8A774A1_CLK_ZB3D4 26
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#define R8A774A1_CLK_CR 27
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#define R8A774A1_CLK_CRD2 28
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#define R8A774A1_CLK_SD0H 29
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#define R8A774A1_CLK_SD0 30
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#define R8A774A1_CLK_SD1H 31
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#define R8A774A1_CLK_SD1 32
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#define R8A774A1_CLK_SD2H 33
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#define R8A774A1_CLK_SD2 34
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#define R8A774A1_CLK_SD3H 35
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#define R8A774A1_CLK_SD3 36
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#define R8A774A1_CLK_RPC 37
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#define R8A774A1_CLK_RPCD2 38
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#define R8A774A1_CLK_MSO 39
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#define R8A774A1_CLK_HDMI 40
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#define R8A774A1_CLK_CSI0 41
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#define R8A774A1_CLK_CP 42
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#define R8A774A1_CLK_CPEX 43
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#define R8A774A1_CLK_R 44
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#define R8A774A1_CLK_OSC 45
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#define R8A774A1_CLK_CANFD 46
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#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */
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@ -18,12 +18,10 @@
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#define R8A774A1_PD_CA53_CPU2 7
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#define R8A774A1_PD_CA53_CPU3 8
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#define R8A774A1_PD_CA57_SCU 12
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#define R8A774A1_PD_CR7 13
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#define R8A774A1_PD_A3VC 14
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#define R8A774A1_PD_3DG_A 17
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#define R8A774A1_PD_3DG_B 18
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#define R8A774A1_PD_CA53_SCU 21
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#define R8A774A1_PD_A3IR 24
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#define R8A774A1_PD_A2VC0 25
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#define R8A774A1_PD_A2VC1 26
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