Some CPUs of some architectures have SOC directories.
At present, the build system directly descends into SOC directories
from the top Makefile, but it should generally descend into each
directory from its parent directory.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
bcm911360_entphn
bcm911360_entphn-ns
bcm911360k
bcm958300k-ns
bcm958305k
- updates to support Cygnus and NSP board families better
- add functions so CONFIG_ARMV7_NONSEC can be enabled on Cygnus boards
Signed-off-by: Steve Rae <srae@broadcom.com>
U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does. This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.
Many of references of those macros must be fixed to suppress warnings.
We have two options:
- Use min, max, min3, max3 only when the arguments have the same type
(or add casts to the arguments)
- Use min_t/max_t instead with the appropriate type for the first
argument
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: Tom Rini <trini@ti.com>
When an invalid USDHC port is passed we should return -EINVAL instead of 0.
Also, return the error immediately on fsl_esdhc_initialize() failure.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
When an invalid USDHC port is passed we should return -EINVAL instead of 0.
Also, return the error immediately on fsl_esdhc_initialize() failure.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
When an invalid USDHC port is passed we should return -EINVAL instead of 0.
Also, return the error immediately on fsl_esdhc_initialize() failure.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
When an invalid USDHC port is passed we should return -EINVAL instead of 0.
Also, return the error immediately on fsl_esdhc_initialize() failure.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
When an invalid USDHC port is passed we should return -EINVAL instead of 0.
Also, return the error immediately on fsl_esdhc_initialize() failure.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
When an invalid USDHC port is passed we should return -EINVAL instead of 0.
Also, return the error immediately on fsl_esdhc_initialize() failure.
Based on similar patches by Fabio Estevam for mx6sabresd, mx53loco, wandboard
Signed-off-by: Soeren Moch <smoch@web.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Add platform data for the GPIO driver. It doesn't need to contain anything
since the GPIO driver will actually use information from the CONFIGs for
now. This merely serves to ensure that the GPIO driver is bound.
Signed-off-by: Simon Glass <sjg@chromium.org>
Convert this at91sam9260-based board to use driver model. This should serve
as an example for other similar boards. Serial and GPIO are supported so
far.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
Rename this vendor since it is intended to be used on any platform where
coreboot runs at reset and then loads U-Boot.
So far it is only tested on link. When other boards are supported it is
likely that we will need to move to multiple board names, all under the
'coreboot' vendor. So while it would be possible to remove the vendor for
now, that would be short-sighted.
Suggested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Add support for CAR so that we have memory to use prior to DRAM init.
On link there is a total of 128KB of CAR available, although some is
used for the memory reference code.
Signed-off-by: Simon Glass <sjg@chromium.org>
On x86 it is common to use 'post codes' which are 8-bit hex values emitted
from the code and visible to the user. Traditionally two 7-segment displays
were made available on the motherboard to show the last post code that was
emitted. This allows diagnosis of a boot problem since it is possible to
see where the code got to before it died.
On modern hardware these codes are not normally visible. On Chromebooks
they are displayed by the Embedded Controller (EC), so it is useful to emit
them. We must enable this feature for the EC to see the codes, so add an
option for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.
This initial commit has place holders for a wide range of features. These
will be added in follow-on patches and series. So far it cannot be booted
as there is no ROM image produced, but it does build without errors.
Signed-off-by: Simon Glass <sjg@chromium.org>
Use these new functions where possible. They default to a value of 2 so we
cannot use them in some places where we need a default value of 1.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@ti.com>
This function can fail if the device tree runs out of space. Rather than
silently booting with an incomplete device tree, allow the failure to be
detected.
Unfortunately this involves changing a lot of places in the code. I have
not changed behvaiour to return an error where one is not currently
returned, to avoid unexpected breakage.
Eventually it would be nice to allow boards to register functions to be
called to update the device tree. This would avoid all the many functions
to do this. However it's not clear yet if this should be done using driver
model or with a linker list. This work is left for later.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Modify the pfuze init for mx6sxsabresd to use the shared
"pfuze_common_init" function. And move this initialization to
power_init_board.
Signed-off-by: Ye.Li <B37916@freescale.com>
Modify the pfuze init for mx6sabresd to use the shared
"pfuze_common_init" function. And move this initialization to
power_init_board.
Signed-off-by: Ye.Li <B37916@freescale.com>
Since the Pfuze initializations are similar on various mx6 SABRE
boards. Factorize the initialization to a common function in file
board/freescale/common/pfuze.c. So that all SABRE boards BSP can
share the function.
Signed-off-by: Ye.Li <B37916@freescale.com>
Add full support for USDHC2, USDHC3, USDHC4 on mx6sx sabresd board.
The default boot socket is USDHC4, so the MMC environment device and
mmcdev variable are set to this device.
Signed-off-by: Ye.Li <B37916@freescale.com>
In U-boot it is preferred to access the register via structure pointer, so
convert it such style.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Let's add mx6sabresd_spl_defconfig entry into MAINTAINERS, so that we avoid
getting a warning that the mx6sabresd_spl is not maintained.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
We can simply the return the value from enable_fec_anatop_clock() to make the
code smaller and simpler.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
We can simply the return the value from enable_fec_anatop_clock() to make the
code smaller and simpler.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
When an invalid USDHC port is passed we should return -EINVAL instead of 0.
Also, return the error immediately on fsl_esdhc_initialize() failure.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
When an invalid USDHC port is passed we should return -EINVAL instead of 0.
Also, return the error immediately on fsl_esdhc_initialize() failure.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
mx6sabreauto boards come with 32 MiB of parallel NOR flash.
Add support for it:
U-Boot 2015.01-rc1-18107-g1543636-dirty (Nov 14 2014 - 11:11:04)
CPU: Freescale i.MX6Q rev1.2 at 792 MHz
Reset cause: POR
Board: MX6Q-Sabreauto revA
I2C: ready
DRAM: 2 GiB
Flash: 32 MiB
NAND: 0 MiB
Due to pin conflict with I2C3, only define configure I2C3 IOMUX when flash is
not used.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Many boards use a minimal .cfg file in the SPL case.
Introduce spl_sd.cfg so that we can reuse it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR.
Move the configuration to the spl code.
CCM_CCOSR setting is no longer required to get audio functionality in the
kernel, so remove such setting.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Marek Vasut <marex@denx.de>
mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR.
Move the configuration to the spl code.
CCM_CCOSR setting is no longer required to get audio functionality in the
kernel, so remove such setting.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR.
Move the configuration to the spl code.
CCM_CCOSR setting is no longer required to get audio functionality in the
kernel, so remove such setting.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The PFUZ probe failed with the following msg:
" wait_for_sr_state: failed sr=81 cr=a0 state=2020
i2c_init_transfer: failed for chip 0x8 retry=0
wait_for_sr_state: failed sr=81 cr=a0 state=2020
i2c_init_transfer: failed for chip 0x8 retry=1
wait_for_sr_state: failed sr=81 cr=a0 state=2020
i2c_init_transfer: failed for chip 0x8 retry=2
i2c_init_transfer: give up i2c_regs=021a0000
Can't find PMIC:PFUZE100 "
board_early_init_f is too early to call i2c related setting, because
init_func_i2c is called after board_early_init_f being invoked. Thus
move setup_i2c into board_init.
Also PFUZ is connected to I2C bus 0, so change "1" -> "0".
Using this patch PFUZ can be correctly probed:
"PMIC: PFUZE100 ID=0x11"
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
1000BASE-KX(1G-KX) uses SGMII protocol but the serdes lane runs in 1G-KX
mode. By default, the lane runs in SGMII mode, when a MAC uses a lane
in 1G-KX mode, corresponding bit in PCCR1 for the lane needs to be set,
and needs to fixup dtb accordingly for kernel to do proper initialization.
Hwconfig "fsl_1gkx" is used to indicate a MAC runs in 1G-KX mode, FM1 MAC
1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a
MAC runs in 1G-KX mode, set its' corresponding env in "fsl_1gkx",
'fm1_1g1' stands for FM1-MAC1, 'fm1_1g2' stands for FM1-MAC2, etc.
If all MAC 1/2/5/6/9/10 run in 1G-KX mode, the hwconfig should has below
setting:
fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
[York Sun: Fix compiling warning]
Reviewed-by: York Sun <yorksun@freescale.com>
XFI ports on t2080qds can work with fiber cable and direct attach
cable(copper). We use hwconfig to define cable type for XFI, and fixup
dtb based on the cable type.
For copper cable, set below env in hwconfig:
fsl_10gkr_copper:<10g_mac_name>
the <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4.
fm1_10g1 stands for FM1-MAC9, fm1_10g2 stands for FM1-MAC10, fm1_10g3
stands for FM1-MAC1, fm1_10g4 stands for FM1-MAC2. The four
<10g_mac_name>s do not have to be coexist in hwconfig. For XFI ports, if
a given 10G port will use the copper cable for 10GBASE-KR, set the
<10g_mac_name> of the port in hwconfig, otherwise, fiber cable will be
assumed to be used for the port.
For ex. if four XFI ports will both use copper cable, the hwconfig
should contain:
fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The gdsys hrcon board is based on a Freescale MPC8308 SOC.
It boots from NOR-Flash, kernel and rootfs are stored on
SD-Card.
On board peripherals include:
- 1x GbE (optional)
- Lattice ECP3 FPGA connected via eLBC and PCIe
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
Wolfgang Denk found this issue using cppcheck:
(error) Uninitialized variable: fpga_features
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
The code for this board supports following features:
- Boot media support: NAND flash/SD card/SPI flash
- Support LCD display (optional, disabled by default)
- Support ethernet
- Support USB mass storage
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The code for this board supports following features:
- Boot media support: NAND flash/SD card/SPI flash
- Support LCD display
- Support ethernet
- Support USB mass storage
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
replaces the at91bootstrap code with SPL code.
make the spl image with:
./tools/mkimage -T atmelimage -d spl/u-boot-spl.bin spl/boot.bin
this writes the length of the spl image into the 6th
execption vector. This is needed from the ROM bootloader.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
replaces the at91bootstrap code with SPL code.
make the spl image with:
./tools/mkimage -T atmelimage -d spl/u-boot-spl.bin spl/boot.bin
this writes the length of the spl image into the 6th
execption vector. This is needed from the ROM bootloader.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This change adds support for enabling the USB host features of the board.
This includes the USB3503A hub and the SMC LAN9730 ethernet controller
as well.
Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This adds following things :
- New config and defconfig for Peach-Pi board.
- Alterations in Kconfig and MAINTAINERS.
- Addition of CONFIG_EXYNOS5800.
- ADdition of exynos5800-peach-pi in dts list.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Gose board is defined CONFIG_SYS_SDRAM_BASE, and this can use a basic function of
dram_init_banksize instead.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Lager board is defined CONFIG_SYS_SDRAM_BASE, and this can use a basic function of
dram_init_banksize instead.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Koesch board is defined CONFIG_SYS_SDRAM_BASE, and this can use a basic function of
dram_init_banksize instead.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Alt board is defined CONFIG_SYS_SDRAM_BASE, and this can use a basic function of
dram_init_banksize instead.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode
There are two usb port on mx6sxsabresd board:
1. otg port
2. host port
The following are the connection between usb controller and board usb
interface, host port has not ID pin set:
otg1 core <---> board otg port
otg2 core <---> board host port
In order to make host port work, board_usb_phy_mode return USB_INIT_HOST
to make host port work in HOST mode.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye Li <B37916@freescale.com>
Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode
There are two usb port on mx6slevk board:
1. otg port
2. host port
The following are the connection between usb controller and board usb
interface, host port has not ID pin set:
otg1 core <---> board otg port
otg2 core <---> board host port
In order to make host port work, board_usb_phy_mode return USB_INIT_HOST
to let host port work in host mode.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye Li <B37916@freescale.com>
* fdt_fixup_mtdparts is called from ft_board_setup
* Run "mtdparts default" to create NAND partition on uboot
* Use mtdparts to create partitions dynamically rather
than using static partitions in device tree
Signed-off-by: Ashish Kumar <Ashish.Kumar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
* fdt_fixup_mtdparts is called from ft_board_setup
* run "mtdparts default" to create NAND, NOR partition on uboot
* Use mtdparts to create partitions dynamically rather
than using static partitions in device tree
Signed-off-by: Ashish Kumar <Ashish.Kumar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
-A_007662 states that for x1 link width, PCIe2 controller trains in
Gen1 speed while configured for Gen2 speed.
Workaround:Set the width to x1 and speed to Gen2 by writing to
CCSR registers in PBI phase
-A_008007 states that PVR register may show random value.
Workaround: Reset PVR register using DCSR space in PBI phase
Add PBI based software workaround for A_007662 and A_008007
in t104x_pbi.cfg. This is required for SPL-based bootloaders
like NAND-boot, SD-boot, SPI-boot
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This support of CPLD includes
- Files and register definitions
- Command to switch alternate bank
- Command to switch default bank
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Add initial support for TBS2910 Matrix ARM miniPC.
Support includes MMC, Ethernet, UARTs, HDMI, USB, SATA, PCI, I2C, RTC.
Signed-off-by: Soeren Moch <smoch@web.de>
When an invalid USDHC port is passed we should return -EINVAL instead of 0.
Also, return the error immediately on fsl_esdhc_initialize() failure.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
This patch will enable the support for SPL on iMX6 SabreSD.
It tested on SD2 and SD3 mmc port (Switch 1 or 2 of SW6)
Signed-off-by: John Tobias <john.tobias.ph@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
The i.MX6Q/DL sabreauto board has one NAND socket, set the
CONFIG_NAND_MXS and relevant NAND configurations to enable the
MXS NAND flash driver.
Add board level codes to set IOMUX and clock for GPMI-NAND and
BCH module.
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Today I got the final board and found out that a different
connector is used as the one on my development board. The
new connector has swaped pins for cd and wp.
This change is tested on a production ready board.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Since kernel 3.15 there are two dtb's for the imx53-qsb board:
imx53-qsb.dtb - For the boards with DA9053 PMIC
imx53-qsrb.dtb - For the boards with MC34708 PMIC
Change the 'fdt_file' dynamically, so that the correct dtb can be used depending
on the board variant.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
The magic bit toucher needs to be updated to reflect the new board Kconfig structure
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add support for the 2 ehci controllers found on the sun6i (A31) soc.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Marek Vasut <marex@denx.de>
Add proper Kconfig options to select the usb Vbus gpio-s, besides moving to
Kconfig being the right thing to do, an added advantage of this is that it
allows for boards without Vbus gpio-s.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Enable the SPL now that we've all the necessary bits in place.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The A31 uses the AXP221 pmic for various voltages.
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
--
Changes in v2:
-Rebase
Changes in v3:
-Add support for all dldo and aldo-s
-Add Kconfig option to select building AXP221 and to select voltage of
dldo and aldo-s
Changes in v4:
-Add axp221_setbits helper function
-Use symbolic names for enabled bits in CTRL1 - CTRL3 registers
This commit adds "select CPU_V7" for some new boards that were not
covered by commit 2e07c249a6
(kconfig: arm: introduce symbol for ARM CPUs).
Redundant "SYS_CPU" defines and "string" directives should be removed.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Georges Savoundararadj <savoundg@gmail.com>
Now each board selects one of CONFIG_CPU_SH2, CONFIG_CPU_SH3,
CONFIG_CPU_SH4, so let's move CONFIG_SYS_CPU definition to
arch/sh/Kconfig.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
mcc200 and prs200 are old and have no maintainer. Remove the boards.
This also removes the mcc200 specific 1bpp BMP support from
common/lcd.c
Cc: Wolfgang Denk <wd@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
The latest Xilinx tools generate ps7_init files that are explicitly
available under GPL. Change the makefile to allow drop in of those files
for building the SPL.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Reviewed-and-tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
cppcheck reports:
[board/esd/common/auto_update.c:458]: (error) Uninitialized variable: cnt
The variable is not really used anywhere, so remove it.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
The i2c_init function is no longer necessary.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Alt board was connected Power IC to channel 1 of sh-i2c. Source code that
controls this is already included, but channel 1 of sh-i2c is not enabled.
This enables channel 1 of sh-i2c, and can use.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Alt board does not use board_late_init function.
This removes this function and define of BOARD_LATE_INIT from config.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Lager board does not use board_late_init function.
This removes this function and define of BOARD_LATE_INIT from config.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Koelsch board does not use board_late_init function.
This removes this function and define of BOARD_LATE_INIT from config.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Gose board has one ether port, this works using sh-ether driver.
This adds GPIO settings and driver settings in order to use the sh-ether.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Fix error detected by cppcheck:
[board/renesas/ecovec/ecovec.c:66]: (error) Buffer is accessed out of
bounds.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Fix error detected by cppcheck:
[board/matrix_vision/mvblx/sys_eeprom.c:353]: (error) Buffer is
accessed out of bounds.
Signed-off-by: Wolfgang Denk <wd@denx.de>
cc: Michael Jones <michael.jones@matrix-vision.de>
Acked-by: Michael Jones <michael.jones@matrix-vision.de>
Fix error detected by cppcheck:
[board/cogent/lcd.c:237]: (error) Invalid number of character (()
when these macros are defined:
'CONFIG_SHOW_ACTIVITY;CONFIG_STATUS_LED'.
Signed-off-by: Wolfgang Denk <wd@denx.de>
There are a number of places where U-Boot intentionally and legally
accesses physical address 0x0000, for example when installing
exception vectors on systems where these are located in low memory.
Add "cppcheck-suppress nullPointer" comments to silence cppcheck
where this is intentional and legal.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Add example of an USB UDC configuration with DFU and UMS.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Add both host and mUSB support.
Currently, the selection between host USB and mUSB is done through the
config file.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Reviewed-by: Tom Rini <trini@ti.com>
CompuLab cm-t3517 is Computer on Module (CoM) based on AM3517 SoC.
Features: up to 256MB DDR2, up to 512MB NAND, USB hub, mUSB, WiFi, BT,
Analog audio codec, touch screen controller, LED.
Add basic support including:
LED, Serial console, NAND, MMC, GPIO, I2C, 256MB DRAM.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Switch the default CD GPIO polarity to active low.
The current hsmmc driver assumption that the CD GPIO is active high, but
in the real hardware, usually the opposite holds.
The usual SD card socket has a mechanical switch which is grounded as
soon as a card is inserted.
Of course there might be some board logic which inverts the signal, but
as far as current users are concerned, there is no such logic.
Current U-Boot users either not using the CD functionality, or have a
different way (e.g. external to SoC GPIO controller) for checking the
card presence.
This patch also brings the polarity assumption in line with the Linux
kernel and adds appropriate comments.
This patch also might spare issues once the TWL GPIO driver will be
converted to the DM.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Dmitry Lifshitz <lifshitz@compulab.co.il>
Reviewed-by: Tom Rini <trini@ti.com>
The fallback is used for cases when CONFIG_SERIAL_TAG defined, but the
eeprom is not used.
The fallback is useful for more than one CompuLab board, so move it to a
common location.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Reviewed-by: Tom Rini <trini@ti.com>
Extract the SMC911x initialization code to a common location where it
can be reused by other compulab omap3 based boards.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Reviewed-by: Tom Rini <trini@ti.com>
The splash screen loading code can be reused by other compulab boards.
For now extract it to a common location for further reuse.
This also switches the splash code dependency from CONFIG_LCD to
CONFIG_SPLASH_SCREEN as it should normally be.
In addition this patch fixes the accidental dependency of the
get_board_mem_timings() function on CONFIG_LCD, by just moving the
splash code and leaving the above function intact.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Reviewed-by: Tom Rini <trini@ti.com>
Extract the USB hub reset code to a common location where it can be
reused by other compulab boards.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Reviewed-by: Tom Rini <trini@ti.com>
Move board revision handling code to a common location
for further reuse.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Reviewed-by: Tom Rini <trini@ti.com>
disable internal delay through gmii_sel register, as this
is done in the ar8031 phy.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
Currently Keystone2 Lamar evm (K2L) board is added, so update
Keystone2 readme file to have such one.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
The 1GB DRAM configuration on mx6 solo uses 2 chip selects, but
the code tests 1GB DRAM configuration as if it is all present on one
chip select, and thus cannot see the full range of available memory.
Refactor the check to detect 1GB DRAM correctly.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Change the order in which GPIOs are toggled in SATA init sequence to
accomodate both SanDisk and Phison SSDs.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
The scsi_init() function uses a GPIO so should request it. There is no
way to return an error here, and the request may be made multiple times,
so just ignore errors for now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
For now we won't want to mess with the existing configurations. Create a
new one which will enable device tree and driver model. Note that this
brings the device tree binary into u-boot-sunxi-with-spl.bin.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This was done automatically with the following bits of scripting.
The Kconfig choice content was generated with this script snippet:
for i in $(git grep -l CONFIG_ARCH_SUNXI configs/*) ; do
TARGET=$(sed -n -e 's/CONFIG_SYS_EXTRA_OPTIONS="\([^,"]\+\).*/\1/p' $i);
MACH=$(sed -n -e 's/.*CONFIG_\(MACH_SUN.I\)=./\1/p' $i)
echo "config TARGET_$TARGET"
echo " bool \"$TARGET\""
echo " depends on $MACH"
echo
done
defconfigs were updated with a sed script (t):
# Extract board from first entry of CONFIG_SYS_EXTRA_OPTIONS,
/^CONFIG_SYS_EXTRA_OPTIONS/ {
s/^\(CONFIG_SYS_EXTRA_OPTIONS="\)\([^,"]\+\),\?\(.*\)/\1\3\nCONFIG_TARGET_\2=y/;
# Print and delete first line (CONFIG_SYS_EXTRA_OPTIONS), leaving
# CONFIG_TARGET_<BOARD> in pattern space
P;D;
};
# Move CONFIG_TARGET_<BOARD> to hold space
/^CONFIG_TARGET/{h;n}
# Print CONFIG_TARGET_<BOARD> after CONFIG_MACH_<SOC> in either SPL or
# normal mode.
/^CONFIG_MACH/{p;g;p;n};
/^\+S:CONFIG_MACH/{p;g;s/^CONFIG_TARGET/+S:&/;p;n};
# Print any remaining lines normally
p;
Run as:
sed -i -n -f t $(git grep -l CONFIG_ARCH_SUNXI configs/*)
and then manually removing the one instance of CONFIG_SYS_EXTRA_OPTIONS="" from
Colombus_defconfig
board/sunxi/Makefile was updated with:
sed -e 's/^\(obj-\$(CONFIG_\)\(.*\)\().*+= dram_.*\)/\1TARGET_\2\3/g' board/sunxi/Makefile
and manually retabbing a few lines to line up again.
The board descriptions could certainly be improved.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
It's unfortunate that this needs to be present in both .config and spl/.config
since it makes it slightly hard to enable FEL mode for a regular defconfig. It
can be done with:
echo CONFIG_SPL_FEL=y >> .config
echo CONFIG_SPL_FEL=y >> spl/.config
Ideally only one of those would be needed.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Now we have CONFIG_ARCH_SUNXI as the toplevel, CONFIG_MACH_SUN[45678]I as the
per-SoC option and leave CONFIG_TARGET_BLAH free for individual boards in the
future.
Done automatically with:
sed -i -e 's/TARGET_\(SUN[45678]I\)/MACH_\1/g' $(git grep -l TARGET_SUN[45678]I)
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
And make TARGET_SUN[45678]I a choice variable under this.
configs updated with:
sed -i -e 's/^\(\+S:\)\?CONFIG_TARGET_SUN.I=y/\1CONFIG_ARCH_SUNXI=y\n&/g' configs/*
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The defconfig for Ippo-q8h-v5 was incorrectly committed as
"Ippo_q8h". This patch renames it correctly, as well as
correct a typo in my name in the maintainers listing.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Defining CONFIG_SYS_TEXT_BASE in config.mk is very old style.
Create CONFIG_SYS_TEXT_BASE option in Kconfig, but let it
depend on CONFIG_SPARC because we do not want to disturb
the other architectures that still define CONFIG_SYS_TEXT_BASE
in their header files.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Daniel Hellstrom <daniel@gaisler.com>
For now, all the SPARC boards in U-Boot are provided by Gaisler.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Daniel Hellstrom <daniel@gaisler.com>
Alt board use SCIF2, not SCIF0.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Since board info structure is not still set up, the setting of RAM
address causes illegal access.
Therefore the setting of RAM address is removed.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Since board info structure is not still set up, the setting of RAM
address causes illegal access.
Therefore the setting of RAM address is removed.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Since board info structure is not still set up, the setting of RAM
address causes illegal access.
Therefore the setting of RAM address is removed.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
If CONFIG_RMOBILE_EXTRAM_BOOT is enabled, U-Boot is booted from External RAM.
The default boot address is 0x70000000.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
If CONFIG_RMOBILE_EXTRAM_BOOT is enabled, U-Boot is booted from External RAM.
The default boot address is 0x70000000.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
If CONFIG_RMOBILE_EXTRAM_BOOT is enabled, U-Boot is booted from External RAM.
The default boot address is 0xB0000000.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The change of the CPU frequency is waited for until PLL0ST of the PLLECR is
set to 1.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Commit f91c09acf5 ("ARM: mx6: Add support for Kosagi Novena") missed to
add a MAINTAINERS file, so add Marek as the maintainer.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
155fa9af95 "spi: mxc: fix sf probe when using mxc_spi" break
spi flash detection on the aristainetos board. Fix this.
Signed-off-by: Heiko Schocher <hs@denx.de>
On mx6 sabreauto board, there are two USB ports:
0: OTG
1: HOST
The EHCI driver is enabled for this board, but the IOMUX and VBUS power
control is not implemented, which cause both USB port failed to work.
This patch fix the problem by adding the board support codes.
Since the power control uses the GPIO pin from port expander MAX7310,
the PCA953X driver is enabled for accessing the MAX7310.
The ID pin of OTG Port needs to configure the GPR1 bit 13 for selecting
its daisy chain. Add a new function "imx_iomux_set_gpr_register" to
handle GPR register setting.
Signed-off-by: Ye.Li <B37916@freescale.com>
There are three SD/MMC sockets on mx6slevk boards. Implements the
full support for them.
The default boot socket is USDHC2, so the MMC environment is set
to that device.
Signed-off-by: Ye.Li <B37916@freescale.com>
The vct board can be built with various variants which are
configured via CONFIG_SYS_EXTRA_OPTIONS. This is deprecated. Thus
add new Kconfig options for those board variants.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
The dbau1x00 board can be built with various variants which are
configured via CONFIG_SYS_EXTRA_OPTIONS. This is deprecated. Thus
add new Kconfig options for those board variants.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Now the user can separately select the CPU type. Thus the
targets qemu_mips and qemu_mips64 can be merged to a single
target.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Now the user can select the CPU type for each target. Thus
CONFIG_SYS_CPU could be set globally.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Commit f91c09acf5 ("ARM: mx6: Add support for Kosagi Novena") missed to
add a MAINTAINERS file, so add Marek as the maintainer.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
[1] arch/arm/include/asm/arch-at91/at91_shdwn.h
The top9000 was the last board to use this header file.
It was removed by commit d58a9451e7 (ppc/arm: zap EMK boards).
[2] board/matrix_vision/common/*
Some Matrix Vision boards were dropped by commit e7a565638a
(powerpc: mpc83xx: remove board support for MERGERBOX and MVBLM7)
and commit af55e35d33
(powerpc: mpc5xxx: remove board support for MVBC_P and MVSMR).
Since then these files have been unused.
[3] include/usb/omap1510_udc.h
The omap5912osk was the last board to use this header file.
It was removed by commit 62d636aa2a
(omap: remove omap5912osk board support).
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-By: Wolfgang Denk <wd@denx.de>
Setting gpio value before dm gpio init has no effect,
so now, odroid gpio settings are moved after the gpio uclass init.
Using non-requested gpio pin cases printing error messages.
To avoid this, gpio_request() is added for those gpios.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch fixes conflict between PHY pins becoming outputs after reset and
imx6 still driving the pins. It also fixes the reset timing as recommended by
the PHY datasheet.
Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
The older 'mr' variant and the generic variant of the
OT1200 differ in some places. As the name suggests the
generic variant supports more boot devices.
In order to be compatible with the 'mr' variant we define
some 'feature' GPIOs. On the 'mr' variant this pads are
not connected so we define their state with the help
of the internal pullups.
On the generic variant this GPIOs are connected and
represent the state of the hardware.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Commit 155fa9af95 changed the way
to define a GPIO line, which can be used to force CS high
across multiple transactions. In order to fix sf detection
change board code to make use of board_spi_cs_gpio(..).
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
Add support for the 4.3'' Seiko WVGA parallel display.
In order to direct the splash screen to the Seiko display:
=> setenv panel SEIKO-WVGA
=> save
=> reset
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Add support for the Kosagi Novena board. Currently supported are:
- I2C busses
- FEC Ethernet
- MMC0, MMC1, Booting from MMC
- SATA
- USB ports
- USB Ethernet
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Nikolay Dimitrov <picmaster@mail.bg>
Reviewed-by: Nikolay Dimitrov <picmaster@mail.bg>
This commit introduces a Kconfig symbol for each ARM CPU:
CPU_ARM720T, CPU_ARM920T, CPU_ARM926EJS, CPU_ARM946ES, CPU_ARM1136,
CPU_ARM1176, CPU_V7, CPU_PXA, CPU_SA1100.
Also, it adds the CPU feature Kconfig symbol HAS_VBAR which is selected
for CPU_ARM1176 and CPU_V7.
For each target, the corresponding CPU is selected and the definition of
SYS_CPU in the corresponding Kconfig file is removed.
Also, it removes redundant "string" type in some Kconfig files.
Signed-off-by: Georges Savoundararadj <savoundg@gmail.com>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
The following bard configurations have been without active maintenance
for a long time, and the board maintainer agrees to have them removed:
MPC5200: TOP5200, MINI5200, EVAL5200
MPC860: TOP860
at91sam9xeXXX: top9000eval_xe, top9000su_xe
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
[trini: Add missing Kconfig removals]
Signed-off-by: Tom Rini <trini@ti.com>
This file should contain the bin_hdr generated by the original Marvell
U-Boot implementation. As this is currently not included in this
U-Boot version, we have added this placeholder, so that the U-Boot
image can be generated without errors.
If you have a known to be working bin_hdr for your board, then you
just need to replace this text file here with the binary header
and recompile U-Boot.
In a few weeks, mainline U-Boot will get support to generate the
bin_hdr with the DDR training code itself. By implementing this code
as SPL U-Boot. Then this file will not be needed any more and will
get removed.
Signed-off-by: Stefan Roese <sr@denx.de>
LaCie Wireless Space has no defined maintainer.
Set myself as maintainer, since I own one of these.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
This board is old and is using CONFIG_I2C_X, which is wrong.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
This board is old and is using CONFIG_I2C_X, which is wrong.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
This board is old and is using CONFIG_I2C_X, which is wrong.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
This is the only used of CONFIG_SPI_X macro, just zap this.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Remove this board as this is the only one last user of eeprom_probe(),
which is pretty non-standard stuff.
This patch also removes all the PHP, SQL and CSS stuff from U-Boot,
which probably makes U-Boot a bit less IoT ;-)
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
This board uses eeprom accessors in an incorrect way. The board
is old and unsupported, just zap it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
This board is the only user of CONFIG_SYS_EEPROM_X40430 , remove
it so the EEPROM command code can be cleansed of the related code
as well.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
The file board/Marvell/include/mv_gen_reg.h is incompatible with
the GPL (see for example the "MARVELL RESERVES THE RIGHT AT ITS SOLE
DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO
MARVELL" clause). As this cannot be fixed, we remove the file and all
code that depends on it. Fortunately this only affects some very old
boards that have long reached EOL:
CPCI750
DB64360
DB64460
p3m750
p3m7448
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Roger Meier <r.meier@siemens.com>
The config targets described in README are not present
any more, update the info to currently used targets.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Add a Kconfig option which users can select when they want to boot older
kernels, e.g. the linux-sunxi 3.4 kernels. For now this just forces the pll5
"p" value to 1 (divide by 2) as that is what those kernels are hardcoded too,
in the future this may enable further workarounds.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Tom Rini <trini@ti.com>
--
Changes in v2:
-s/CONFIG_OLD_KERNEL_COMPAT/CONFIG_OLD_SUNXI_KERNEL_COMPAT.
-Move the code block setting P(1) for old kernels to where P gets cleared
Ippo q8h is a series of A23 tablet boards. This defconfig
is for v5 of these boards, though for u-boot purposes they
are mostly the same.
See: http://linux-sunxi.org/Ippo_q8h
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The basic blocks of the A23 are similar to the A31 (sun6i). Re-use
sun6i code for initial clock, gpio, and uart setup.
There is no SPL support for A23, as we do not have any documentation
or sample code for DRAM initialization.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Unify the sunxi Kconfig code, instead of having separate code blocks for
each of sun4i - sun7i.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
None of the known sunxi devices actually use mmc1 routed through PH, where
as some devices do actually use mmc1 routed through PG, so change the routing
of mmc1 to PG. If in the future we encounter devices with mmc1 routed through
PH, we will need to change things to be a bit more flexible.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
sunxi SOCs can boot from both mmc0 and mmc2, detect from which one we're
booting, and make that one "mmc dev 0" so that a single u-boot binary can
be used for both the onboard eMMC and for external sdcards.
When we're booting from mmc2, we make it dev 0 because that is where the SPL
will load the tertiary payload (the actual u-boot binary in our case) from,
see: common/spl/spl_mmc.c, which has dev 0 hardcoded everywhere.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Note we also drop the SPL check for initializing the 2nd mmc slot, the SPL
check is not necessary with Kconfig, because only options explicitly marked
as also being for the SPL get set during SPL builds.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The Colombus board is an A31 evaluation board from WITS Technology.
Maxime has kindly agreed to maintain this board.
[1] http://lists.denx.de/pipermail/u-boot/2014-September/190043.html
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add a new sun6i machine that supports UART and MMC.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: use SPDX labels, adapt to Kconfig system, drop ifdef
around mmc and smp code, drop MACH_TYPE]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The Mele M3 is yet another Allwinnner based Android top set box from Mele.
It uses a housing similar to the A2000, but without the USM sata storage slot
at the top.
It features an A20 SoC, 1G RAM, 4G eMMC (unique for Allwinner devices),
100Mbit ethernet, HDMI out, 3 USB A receptacles, VGA, and A/V OUT connections.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This adds support for the Olimex A20-OLinuXino-Lime2
https://www.olimex.com/Products/OLinuXino/A20/A20-OLinuXIno-LIME2
Differences to previous Lime boards are 1GB RAM and gigabit ethernet
Signed-off-by: Iain Paton <ipaton0@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The platform_data definitions are generally referenced from both
drivers and board files. That is why header files defining
platform_data sturectures are placed in "include" directory,
but our top level "include" directory is already too cluttered.
Let's collect platform_data definitions under the directory
"include/dm/platform_data" like Linux gathers ones around under
"include/linux/platform_data".
This commit moves two header files:
include/serial_mxc.h -> include/dm/platform_data/serial_mxc.h
include/serial_pl01x.h -> include/dm/platform_data/serial_pl01x.h
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Adjust the configuration for the am33xx boards, including beagleboard,
to use driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Tom Rini <trini@ti.com>
The gpmc_init() function already calls enable_gpmc_cs_config() for chip
select 0. Although the bus width is configured for 16 bit, it gets
reconfigured correctly in the omap_gpmc driver later.
Remove the enable_gpmc_cs_config() function call and the associated
gpmc_nand_config[] array.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
In the case of Beaglebone Black we only want to set the NAND or NOR cape
pinmux when the config has been specifically modified by the user for
this non-default case. Make the default be to set the MMC1 (eMMC)
pinmux. We don't need similar changes for Beaglebone White as there is
nothing on MMC1 by default there.
Signed-off-by: Tom Rini <trini@ti.com>
Separate overo module and expansion board MUX configuration. This allows
an foreign expansion board to use the boot loader without any adaption.
It only needs to save the expansion name in the EEPROM to load a
specific device tree.
Signed-off-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Move ethernet setup to the board_eth_init function and select
the available network devices via expansion id.
Signed-off-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
This patch adds the DDR3 ECC support to enable ECC in the DDR3
EMIF controller for Keystone II devices.
By default, ECC will only be enabled if RMW is supported in the
DDR EMIF controller. The entire DDR memory will be scrubbed to
zero using an EDMA channel after ECC is enabled and before
u-boot is re-located to DDR memory.
An ecc_test environment variable is added for ECC testing.
If ecc_test is set to 0, a detection of 2-bit error will reset
the device, if ecc_test is set to 1, 2-bit error detection
will not reset the device, user can still boot the kernel to
check the ECC error handling in kernel.
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
For K2E and K2L SoCs clock output from PASS PLL has to be enabled
after NETCP domain and PA module are enabled. So create new function
for that and call it after PA module is enabled.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Remove unused tx_send_loop variable.
Removes duplicated get_link_status() call from the
keystone2_eth_send_packet().
The emac_gigabit_enable() is called at opening Ethernet and there is no
need to enable it on sending each packet. So remove that call
from keystone2_eth_send_packet() as well.
The calling of power/clock up functions are mostly the responsibility
of SoC/board code, so move these functions to appropriate place.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
The header file for the driver should be in correct place.
So move it to "arch/arm/include/asm/ti-common/keystone_net.h"
and correct driver's external dependencies. At the same time
align and correct some definitions.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
The initialization of PLLs is a part of board specific code, so
move it appropriate places.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
The maxBCM board is equipped with the Marvell Armada-XP MV78460 SoC. It
integrates an SPI NOR flash and an Marvell 88E6185 switch.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds basic support for the Marvell DB-MV784MP-GP evaulation
board. This is the first board that uses the recently created
Armada XP 78460 SoC support.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Additionally the SDRAM address decoding register address is not hard coded
in the C code any more. A define is introduced for this base address.
This makes is possible to use those gpio functions from other MVEBU SoC's
as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
This makes is possible to use those gpio functions from other MVEBU SoC's as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
This move makes is possible to use this header not only from kirkwood
platforms but from all Marvell mvebu platforms.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Commit 155fa9af95 changed the way
to define a GPIO line, which can be used to force CS high
across multiple transactions. In order to fix sf detection
change board code to make use of board_spi_cs_gpio(..).
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
The built-in SMSC 95xx chip doesn't know its own MAC address. Instead,
we must query it from the VC firmware; it's probably encoded in fuses
on the BCM2835.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Convert the BCM2835 GPIO driver to use driver model, and switch over
Raspberry Pi to use this, since it is the only board.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Now that serial and GPIO are available for iMX.6, move cm_fx6 over as an
example.
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
Use gpio_request for all the gpios that are utilized by various
subsystems in cm-fx6, and refactor the relevant init functions
so that all gpios are requested during board_init(), not during
subsystem init, thus avoiding the need to manage gpio ownership
each time a subsystem is initialized.
The new division of labor is:
During board_init() muxes are setup and gpios are requested.
During subsystem init gpios are toggled.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
This converts the Tegra SPI drivers to use driver model. This is tested
on:
- Tegra20 - trimslice
- Tegra30 - beaver
- Tegra124 - dalmore
(not tested on Tegra124)
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Since spi_flash.h is supposed to be the public API for SPI flash, move
private things to sf_internal.h. Also tidy up a few comment nits.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Adjust this board to use the driver model soft_spi implementation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Move the exynos SPI driver over to driver model. This removes quite a bit
of boilerplate from the driver, although it adds some for driver model.
A few device tree additions are needed to make the SPI flash available.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
With driver model GPIOs must be requested before use. Make sure this is
done correctly.
(Note that the soft SPI part of universal is omitted, since this driver
is about to be replaced with a driver-model-aware version)
Signed-off-by: Simon Glass <sjg@chromium.org>
The wrong header is being included, thus requiring the code to re-declare
the generic GPIO interface in each GPIO header.
Fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add proper initialization of GPIO pins used by software i2c.
Signed-off-by: Robert Baldyga <r.baldyga@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Update Apalis T30 as per the following commits
c369139234
tegra: dts: Add serial port details
461be2f96e
kconfig: remove redundant "string" type in arch and board Kconfigs
f1ef2b6233
kconfig: move CONFIG_DEFAULT_DEVICE_TREE to kconfig
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Fix ASIX USB to Ethernet reset which due to the new driver model Tegra
GPIO driver changes now requires a label string to be provided
otherwise the reservation and subsequent direction/value calls will
fail.
This fixes a regression introduced by commit:
2fccd2d96b
tegra: Convert tegra GPIO driver to use driver model
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This patch adds board support for the Toradex Apalis T30 a computer on
module which can be used on different carrier boards.
For the sake of ease of use we do not distinguish between different
carrier boards for now as the base module features are deemed
sufficient enough for regular booting.
The following functionality is working so far:
- eMMC boot and environment storage
- Gigabit Ethernet (once Thierry's PCIe as well as my E1000 resp. i210
fixes hit mainline)
- MMC/SD cards (both 8-bit as well as 4-bit slot)
- USB client/host (dual role port as client e.g. for DFU/UMS, other two
ports as host)
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This pinmux tables currently omit any configuration for PCIe clk_req,
wake, and rst pins, which in turn causes intermittent failures in
U-Boot's PCIe support. Import an updated version of the pinmux tables
which rectifies this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Provide a public declaration of the board_spi_cs_gpio()
callback for i.MX SPI chip selects to prevent the warning
"Should it be static?" when compiling with "make C=1".
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Hardware accelerated support for SHA-1 and SHA-256 has been added.
Hash command enabled along with hardware accelerated support for
SHA-1 and SHA-256 for platforms which have CAAM block.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Update readme file for Keystone II EVM boards to actual sources.
Also correct some typos. For now the Edison evaluation board is
added, README for K2E is mostly the same, so update README to
contain information also for K2E evm. Rename file to README as
it contains information for all keystone evm boards.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
The lines COL (collision detect) and CRS (carrier sense) needs to be connected
and muxed to the CPSW MAC for a proper function in half-duplex Mode of the
interface.
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
Cc: Tom Rini <trini@ti.com>
fix broken SPI access by adding/activating BOARD_EARLY_INIT_F
functionality and calling spi_init_f() from there.
Signed-off-by: David Müller <d.mueller@elsoft.ch>
Fix typo of commit d4e53f063d.
i2c2 pullup resisters are controlled by bit 0 of CONTROL_PROG_IO1.
It's value after reset is 0x00100001.
In order to clear bit 0, original code write 0xfffffffe to
CONTROL_PROG_IO1 and toggle almost all default values.
Original code affect following:
* disable i2c1 pullup resisters
* increase far end load setting for many modules
* setup invalid SC/LB combination
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
CC: Tom Rini <trini@ti.com>
CC: Steve Kipisz <s-kipisz2@ti.com>
This board has been orphaned for more than 6 months.
It is the last board defining CONFIG_APM821XX.
The code inside #ifdef CONFIG_APM821XX should be removed too.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
On OMAP platforms, SATA controller provides the SCSI subsystem
so implement scsi_init().
Get rid of the unnecessary sata_init() call from dra7xx-evm
and omap5-uevm board files.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Add default eeprom bus setting.
This addresses the trimslice compile error that was introduced
with the addition of this setting.
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
In order for the gmac nic to work reliable on the Bananapi, we need to set
bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain" of the GMAC clk register
(0x01c20164) to 3.
Without this about 9 out of 10 ethernet packets get lost, with this setting
there is no packet loss.
So far setting these bits is only necessary on the Bananapi, so this commit
solves this with a bit of #ifdef CONFIG_BANANAPI code. If in the future we
need to do something similar for other boards, we can create a specific
CONFIG_FOO option for this then.
Reported-by: Karsten Merker <merker@debian.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Tested-by: Karsten Merker <merker@debian.org>
Tested-by: Zoltan HERPAI <wigyori@openwrt.org>
Tested-by: Tony Zhang <tony.zhang@lemaker.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This change fixes suspend/resume issue in the kernel caused
by the wrong 'aclk_cores' clock value expected by the kernel.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The email address of Rajeshwari Shinde <rajeshwari.s@samsung.com>
is not working.
This commit gives Akshay the maintainership of Snow and
SMDK5420 boards.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Removed settings in unsupported register fields. They didn’t
do anything, and in most cases, were not documented in the
reference manual.
Changed register settings to comply with JEDEC required values.
Changed timing parameters because they included full clock
periods that were doing nothing.
Signed-off-by: Anthony Felice <tony.felice@timesys.com>
[rebased on v2014.10-rc2]
Signed-off-by: Stefan Agner <stefan@agner.ch>
The HPD pin and RX_SENSE registers have proven to be less reliable
than using I2C on the EDID pins for detection of an HDMI monitor.
In particular, when the HDMI output is reset through a "reboot"
cycle, the detect_hdmi() routine often bounces, resulting in
a failure to detect a connected monitor.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Add support for WVGA (800x480) panels using VESA GTF timings over
LVDS.
No auto-detection is supported, so you must configure this panel
manually through the 'panel' environment variable:
U-Boot > setenv panel svga
U-Boot > saveenv && reset
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Add support for an Ampire 1024x600 LVDS panel with integrated Ilitek
capacitive touch screen.
Auto-detection is enabled, so no explicit configuration is needed.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Add support for 800x600 18-bit RGB displays using VESA GTF timings.
No auto-detection is supported, so you must configure this panel
manually through the 'panel' environment variable:
U-Boot > setenv panel svga
U-Boot > saveenv && reset
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Add support for the Touch Revolution Fusion7 display: 800x480 RGB
with a custom F0710A resistive touch controller.
Auto-detection of this panel is supported so no configuration is
required.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
This patch adds support for LVDS WXGA displays that use the SPWG encoding
standard instead of JEIDA.
No auto-detection is enabled and you must explicitly set the 'panel'
environment variable:
U-Boot > setenv panel LDB-WXGA-S
U-Boot > saveenv && reset
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Add support for LG 9.7" LVDS panel (1024x768) with integrated eGalax
touch screen.
Note that this panel differs only slightly from the Hannstar XGA panel
(margins).
No auto-detection is available because it shares the same touch controller
as the Hannstar-XGA display, so you'll need to configure it through the
'panel' environment variable:
U-Boot > setenv panel LG-9.7
U-Boot > saveenv && reset
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Add support for a 1/4 VGA panel with a 24-bit RGB interface.
No auto-detection is enabled, so you must configure the 'panel'
environment variable to use this display:
U-Boot > setenv panel qvga
U-Boot > saveenv && reset
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Add support for Boundary Devices 7" and 10.1" 1280x800 displays with
integrated FocalTech ft5x06 10-point touch controller.
Because they share the touch controller with the 1024x600 displays,
auto-detection is disabled and you must explicitly set the 'panel'
environment variable:
U-Boot > setenv panel LDB-WXGA
U-Boot > saveenv && reset
Signed-off-by: Robert Winkler <robert.winkler@boundarydevices.com>
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Include declarations of board_ehci callbacks to prevent compiler warnings
and enforce function prototypes.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Testing shows that the Micrel PHY may not be completely out
of reset if accessed immediately.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Declare locally-used data structures and functions as
static and pull in header files to prevent compiler warnings
of "Should it be static?" when building with "make C=1".
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Configure CLKO outputs for SGTL5000, CSI camera.
The sys_mclk output for the SGTL500 in particular prevents
Windows CE from properly driving audio.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Ensure that cameras and USB OTG power are in a stable (reset)
state at reset by configuring their pads and toggling GPIOs.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Pads SD2_CLK/CMD/DAT0-3 are connected to an SDIO WiFi device on
Nitrogen and unconnected on BD-SL-i.MX6 (sabre lite).
Configure them as SDIO pins to prevent them from being in a state
that confuses the WiFi part.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
The same logic applies to both SD card slots, only with different
GPIOs and the code should make that easier to see.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Several customers have asked to leave the display quiet during
boot, so allow the user to express this request by the presence
of environment variable "novideo".
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Move icache_enable() and dcache_enable() function calls from
board code into the CPU code and into the enable_caches()
function. This is how the cache enabling code was designed
to work.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
The code is now fixed to the point where we can safely enable
the L1 data cache. Enable the D-Cache and set it as write-alloc.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Cosmetic change to the checkboard() function output. Align the
output with the rest of initial output produced by U-Boot.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
The bi_boot_params must point to offset 0x100 in DRAM. Make it so.
Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Add some stub defines, which are used by the clock code, but are
missing from the auto-generated header file for the SoCFPGA family.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
This patch adds support for the OT1200 series of devices.
Following components are used in u-boot:
+ ethernet
+ i2c
+ emmc
+ gpio
For more details see README.
Changes v1 > v2
- make use of enable_cspi_clock(..)
- fix usage of OUTPUT_40OHM define
- added README
Changes v2 > v3
- improve spelling in README
- added own copy of mx6q_4x_mt41j128.cfg
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Update DDR calibration settings based on a larger test set.
The initial values were gathered on a small number of boards,
and have been found to fail on some boards under load.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Zeroing GD in board_init_f() is not needed any more. As its now done in
crt0.S. The patch that clears the GD in crt0.S is this one:
aae2aef9 [arm: Set up global data before board_init_f()] from Simon.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Update the ddr scripts for LPDDR2 and add two build configs for LPDDR2
arm2 board. Since the LPDDR2 arm2 board has different DDR size, use
CONFIG_DDR_MB in defconfig to replace the PHYS_SDRAM_SIZE.
Signed-off-by: Ye.Li <B37916@freescale.com>
This patch adds the i.MX6DL arm2 board support. The i.MX6DL ARM2
shared the same board with i.MX6Q ARM2 board since the i.MX6DL is
pin-pin compatible with i.MX6Q.
The patch also support the DDR 32-BIT mode option. Please define
CONFIG_DDR_32BIT in the board configure file to enable DDR 32-BIT
mode.But due to the board design, it's 64bit DDR buswidth physically,
so, if you CONFIG_DDR_32BIT, the DDR memory size will be half of it.
Signed-off-by: Ye.Li <B37916@freescale.com>
Add fine-tuning for the DRAM configuration according to the DRAM chip
datasheet. THis configuration applies to both Hynix HY5DU12622DTP and
Samsung K5H511538J-D43 .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Enable the power to the USB port only when the USB port is really needed.
Do not enable the power unconditionally.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig
for this variant to enable DDR4 support. RAW timing parameters are not
added for DDR4. The board timing parameters are only tuned for single-
rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM
availability.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alison Wang <alison.wang@freescale.com>
Spin table is at the very beginning of boot code. Each core has an individual
release address within the spin table, the ft_cpu_setup fn updates the
"cpu-release-addr" property of each cpu node with the corresponding release
address.
Also fix CPU_RELEASE_ADDR to point to secondary_boot_func.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
DP-DDR is used for DPAA, separated from main memory pool for general
use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit).
Signed-off-by: York Sun <yorksun@freescale.com>
Since commit ddaf5c8f30
(patman: RunPipe() should not pipe stdout/stderr unless asked),
Patman spits lots of "Invalid MAINTAINERS address: '-'"
error messages for patches with global changes.
It takes too long for Patman to process them.
Anyway, "M: -" does not carry any important information.
Rather, it is just like a place holder in case of assigning
a new board maintainer. Let's comment out.
This commit can be reproduced by the following command:
find . -name MAINTAINERS | xargs sed -i -e '/^M:[[:blank:]]*-$/s/^/#/'
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The "S: Orphan" in MAINTAINERS means that the maintainer in the
"M:" field is unreachable (i.e. the email address is not working).
(Refer to the definition of "Orphan" adopted in U-Boot
in the log of commit 31f1b654b2,
"boards.cfg: move boards with invalid emails to Orphan")
For patch files adding global changes, scripts/get_maintainer.pl
adds bunch of such invalid email addresses, which results in
tons of annoying bounce emails.
This commit can be reproduced by the following command:
find . -name MAINTAINERS | xargs sed -i -e '
/^M:[[:blank:]]/ {
N
/S:[[:blank:]]Orphan/s/^/#/
}
'
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Each CPU of PowerPC has its default linker script under the CPU
directory, except mpc8xx.
Every mpc8xx board has its own linker script under the board
directory, resulting in lots of duplication of linker scripts.
I notice eight mpc8xx boards have the same linker script.
We can decrease the number of linker scripts by putting a single
default linker script, arch/powerpc/cpu/mpc8xx/u-boot.lds.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
T1042QDS (T1042 is T1040 Personality without L2 switch) supports following
sgmii interfaces with serdes protocol 0xA7
-SGMII-MAC3 on Lane B - slot 7
-SGMII-MAC5 on Lane H - slot 7
-SGMII2.5G-MAC1 on Lane C - slot 6
-SGMII2.5G-MAC2 on Lane D - slot 5
Add support of above sgmii interfaces
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
DDR-ODT require cfg_dram_type switch set properly as per DDR type.
T1040RDB, T1042RDB boards have DDR3L type DDR, so cfg_dram_type
should be set to OFF for DDR3L
Update t104xrdb/README for switch setting
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
T1042RDB is a Freescale reference board that hosts the T1042 SoC
(and variants). The board is similar to T1040RDB, T1042 is a reduced
personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).
T1042RDB is configured with serdes protocol 0x86 which can support
following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 1 SGMII on DTSEC3
DTSEC1, DTSEC2 are not connected on board.
This Patch
- add T1042RDB support
- updates README file for T1042RDB details and update commands for switching
to alternate banks from vBank0 to vBank4 and vice versa
This patch also does minor clean ups for fdt defines for T1042RDB and
T1042RDB_PI board
Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds support of rcw for T1042RDB, it makes following changes :
- Adds t1042_rcw.cfg file for serdes protocol 0x86 for T1042RDB
- Renames t1042_pi_rcw.cfg file from t1042_rcw.cfg and also updates
comments for valid serdes protocol which is 0x06
- Also updates CONFIG_SYS_FSL_PBL_RCW for T1042RDB
Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
LS2085a has 2 regions in system memory map. Region1 is default map from
where system boots. Once u-boot is moved to DDR, IFC is re-mapped to
Region2.
So, update gd->env_addr to reflect correct address.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
MXC SPI driver has a feature whereas a GPIO line can be used to force CS high
across multiple transactions. This is set up by embedding the GPIO information
in the CS value:
cs = (cs | gpio << 8)
This merge of cs and gpio data into one value breaks the sf probe command:
if the use of gpio is required, invoking "sf probe <cs>" will not work, because
the CS argument doesn't have the GPIO information in it. Instead, the user must
use "sf probe <cs | gpio << 8>". For example, if bank 2 gpio 30 is used to force
cs high on cs 0, bus 0, then instead of typing "sf probe 0" the user now must
type "sf probe 15872".
This is inconsistent with the description of the sf probe command, and forces
the user to be aware of implementaiton details.
Fix this by introducing a new board function: board_spi_cs_gpio(), which will
accept a naked CS value, and provide the driver with the relevant GPIO, if one
is necessary.
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Eric Benard <eric@eukrea.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Provide cgtqmx6eval board its own variant of ddr
setup config file. Move board/freescale/imx/ddr/
mx6q_4x_mt41j128.cfg to board/freescale/mx6sabresd/
as this is was designed for the mx6sabresd board.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
- Use _defconfig instead of _config, but still _config is working.
- Corrected README.sandbox path in ./README
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add NOR flash hardware init function, including SMC and PIO
configuration.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This patch implements a workaround to fix DDR3 memory issue.
The code for workaround detects PGSR0 errors and then preps for
and executes a software-controlled hard reset.In board_early_init,
where logic has been added to identify whether or not the previous
reset was a PORz. PLL initialization is skipped in the case of a
software-controlled hard reset.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Keegan Garcia <kgarcia@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
commit d6d07a9b... arm: vf610: add NAND support for vf610twr
generates the following warnings:
WARNING: no status info for 'vf610twr_nand'
WARNING: no maintainers for 'vf610twr_nand'WARNING: no status info for
'vf610twr_nand'
This is due to the fact that vf610twr_nand_defconfig has no Maintainer.
This patch proposed Alison as Maintainer and fix it.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Acked-by: Alison Wang <b18965@freescale.com>
CC: Stefan Agner <stefan@agner.ch>
We do not have to distinguish CONFIG_TARGET_VEXPRESS_AEMV8A_SEMI
from CONFIG_TARGET_VEXPRESS_AEMV8A. Rename the former to the latter.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Steve Rae <srae@broadcom.com>
Cc: David Feng <fenghua@phytium.com.cn>
i2c_pad_info1 is only used locally, so it can be made static.
Fix the following sparse warning:
board/freescale/mx6sxsabresd/mx6sxsabresd.c:160:22: warning: symbol 'i2c_pad_info1' was not declared. Should it be static?
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
This adds NAND support for the Vybrid tower system (TWR-VF65GS10)
provided by the vf610_nfc driver. Full 16-Bit bus width is
supported. Also an aditional config vf610twr_nand is introduced
which gets the environment from NAND. However, booting U-Boot from
NAND is not yet possible due to missing boot configuration block
(BCB).
Signed-off-by: Stefan Agner <stefan@agner.ch>
Now the types of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME}
are specified in arch/Kconfig.
We can delete the ones in arch and board Kconfig files.
This commit can be easily reproduced by the following command:
find . -name Kconfig -a ! -path ./arch/Kconfig | xargs sed -i -e '
/config[[:space:]]SYS_\(ARCH\|CPU\|SOC\|\VENDOR\|BOARD\|CONFIG_NAME\)/ {
N
s/\n[[:space:]]*string//
}
'
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This is an implementation of GPIOs for Tegra that uses driver model. It has
been tested on trimslice and also using the new iotrace feature.
The implementation uses a top-level GPIO device (which has no actual GPIOS).
Under this all the banks are created as separate GPIO devices.
The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7,
..., Z0..Z7, AA0..AA7, etc.
Since driver model is not yet available before relocation, or in SPL, a
special function is provided for seaboard's SPL code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Currently mx6dlsabresd shares the same DCD settings with the nitrogen board.
Provide a DCD configuration file specific to mx6dlsabresd with the settings
recommended by the Freescale hardware team.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The leds array within struct ventana has space for 3 elements, but the
setup_board_gpio() function tries to set up 4 GPIOs for LEDs. Recent
versions of GCC complain about that:
board/gateworks/gw_ventana/gw_ventana.c: In function 'setup_board_gpio':
board/gateworks/gw_ventana/gw_ventana.c:987:27: warning: iteration 3u invokes undefined behavior [-Waggressive-loop-optimizations]
if (gpio_cfg[board].leds[i])
^
board/gateworks/gw_ventana/gw_ventana.c:986:2: note: containing loop
for (i = 0; i < 4; i++) {
^
Fix this by making the upper bound of the loop match the array size.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Most Gateworks Ventana boards use a PLX PEX860x PCIe switch for PCIe expansion.
These boards use GPIO on the PLX device as PERST# for the downstream ports
thus we assert this when the PLX is enumerated.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Add support for SATA.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Use Compulab eeprom module to obtain revision number, serial number, and
mac address from the EEPROM.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Add support for all 3 I2C busses on Compulab CM-FX6 CoM.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Add USB and USB OTG host support for Compulab CM-FX6 CoM.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
