Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-12-03 01:50:25 +00:00
Code Issues Projects Releases Packages Wiki Activity

Merge branch 'uboot'

Browse source
This commit is contained in:
Minkyu Kang 2014-10-07 19:14:03 +09:00
commit 3cc83f9d08
637 changed files with 11748 additions and 2040 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

14
Kconfig
View file

@ -91,7 +91,7 @@ config SYS_EXTRA_OPTIONS
depends on !SPL_BUILD
help
The old configuration infrastructure (= mkconfig + boards.cfg)
provided the extra options field. It you have something like
provided the extra options field. If you have something like
"HAS_BAR,BAZ=64", the optional options
#define CONFIG_HAS
#define CONFIG_BAZ 64
@ -103,3 +103,15 @@ config SYS_EXTRA_OPTIONS
endmenu # Boot images
source "arch/Kconfig"
source "common/Kconfig"
source "dts/Kconfig"
source "net/Kconfig"
source "drivers/Kconfig"
source "fs/Kconfig"
source "lib/Kconfig"

9
MAINTAINERS
View file

@ -149,6 +149,15 @@ F: arch/arm/include/asm/arch-davinci/
F: arch/arm/include/asm/arch-omap*/
F: arch/arm/include/asm/ti-common/
ARM UNIPHIER
M: Masahiro Yamada <yamada.m@jp.panasonic.com>
S: Maintained
T: git git://git.denx.de/u-boot-uniphier.git
F: arch/arm/cpu/armv7/uniphier/
F: arch/arm/include/asm/arch-uniphier/
F: configs/ph1_*_defconfig
F: drivers/serial/serial_uniphier.c
ARM ZYNQ
M: Michal Simek <monstr@monstr.eu>
S: Maintained

3
Makefile
View file

@ -613,11 +613,9 @@ libs-y += fs/
libs-y += net/
libs-y += disk/
libs-y += drivers/
libs-$(CONFIG_DM) += drivers/core/
libs-y += drivers/dma/
libs-y += drivers/gpio/
libs-y += drivers/i2c/
libs-y += drivers/input/
libs-y += drivers/mmc/
libs-y += drivers/mtd/
libs-$(CONFIG_CMD_NAND) += drivers/mtd/nand/
@ -649,7 +647,6 @@ libs-$(CONFIG_API) += api/
libs-$(CONFIG_HAS_POST) += post/
libs-y += test/
libs-y += test/dm/
libs-$(CONFIG_DM_DEMO) += drivers/demo/
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
libs-y += arch/$(ARCH)/imx-common/

23
README
View file

@ -272,7 +272,7 @@ board. This allows feature development which is not board- or architecture-
specific to be undertaken on a native platform. The sandbox is also used to
run some of U-Boot's tests.
See board/sandbox/sandbox/README.sandbox for more details.
See board/sandbox/README.sandbox for more details.
Configuration Options:
@ -538,6 +538,12 @@ The following options need to be configured:
interleaving mode, handled by Dickens for Freescale layerscape
SoCs with ARM core.
CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
Number of controllers used as main memory.
CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
Number of controllers used for other than main memory.
- Intel Monahans options:
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
@ -1629,6 +1635,16 @@ The following options need to be configured:
downloads. This buffer should be as large as possible for a
platform. Define this to the size available RAM for fastboot.
CONFIG_FASTBOOT_FLASH
The fastboot protocol includes a "flash" command for writing
the downloaded image to a non-volatile storage device. Define
this to enable the "fastboot flash" command.
CONFIG_FASTBOOT_FLASH_MMC_DEV
The fastboot "flash" command requires additional information
regarding the non-volatile storage device. Define this to
the eMMC device that fastboot should use to store the image.
- Journaling Flash filesystem support:
CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
CONFIG_JFFS2_NAND_DEV
@ -3849,12 +3865,9 @@ Configuration Settings:
The memory will be freed (or in fact just forgotton) when
U-Boot relocates itself.
Pre-relocation malloc() is only supported on sandbox
Pre-relocation malloc() is only supported on ARM and sandbox
at present but is fairly easy to enable for other archs.
Pre-relocation malloc() is only supported on ARM at present
but is fairly easy to enable for other archs.
- CONFIG_SYS_BOOTM_LEN:
Normally compressed uImages are limited to an
uncompressed size of 8 MBytes. If this is not enough,

4
arch/Kconfig
View file

@ -7,6 +7,7 @@ config ARC
config ARM
bool "ARM architecture"
select SUPPORT_OF_CONTROL
config AVR32
bool "AVR32 architecture"
@ -19,6 +20,7 @@ config M68K
config MICROBLAZE
bool "MicroBlaze architecture"
select SUPPORT_OF_CONTROL
config MIPS
bool "MIPS architecture"
@ -37,6 +39,7 @@ config PPC
config SANDBOX
bool "Sandbox"
select SUPPORT_OF_CONTROL
config SH
bool "SuperH architecture"
@ -46,6 +49,7 @@ config SPARC
config X86
bool "x86 architecture"
select SUPPORT_OF_CONTROL
endchoice

21
arch/arm/Kconfig
View file

@ -4,6 +4,9 @@ menu "ARM architecture"
config SYS_ARCH
default "arm"
config ARM64
bool
choice
prompt "Target select"
@ -423,6 +426,9 @@ config OMAP54XX
config RMOBILE
bool "Renesas ARM SoCs"
config TARGET_CM_FX6
bool "Support cm_fx6"
config TARGET_S5P_GONI
bool "Support s5p_goni"
@ -456,18 +462,19 @@ config ZYNQ
config TEGRA
bool "NVIDIA Tegra"
select SPL
select OF_CONTROL if !SPL_BUILD
config TARGET_VEXPRESS_AEMV8A
bool "Support vexpress_aemv8a"
config TARGET_VEXPRESS_AEMV8A_SEMI
bool "Support vexpress_aemv8a_semi"
select ARM64
config TARGET_LS2085A_EMU
bool "Support ls2085a_emu"
select ARM64
config TARGET_LS2085A_SIMU
bool "Support ls2085a_simu"
select ARM64
config TARGET_LS1021AQDS
bool "Support ls1021aqds_nor"
@ -514,8 +521,13 @@ config TARGET_COLIBRI_PXA270
config TARGET_JORNADA
bool "Support jornada"
config ARCH_UNIPHIER
bool "Panasonic UniPhier platform"
endchoice
source "arch/arm/cpu/armv8/Kconfig"
source "arch/arm/cpu/arm926ejs/davinci/Kconfig"
source "arch/arm/cpu/armv7/exynos/Kconfig"
@ -540,6 +552,8 @@ source "arch/arm/cpu/armv7/rmobile/Kconfig"
source "arch/arm/cpu/armv7/tegra-common/Kconfig"
source "arch/arm/cpu/armv7/uniphier/Kconfig"
source "arch/arm/cpu/arm926ejs/versatile/Kconfig"
source "arch/arm/cpu/armv7/zynq/Kconfig"
@ -584,6 +598,7 @@ source "board/cirrus/edb93xx/Kconfig"
source "board/cm4008/Kconfig"
source "board/cm41xx/Kconfig"
source "board/compulab/cm_t335/Kconfig"
source "board/compulab/cm_fx6/Kconfig"
source "board/congatec/cgtqmx6eval/Kconfig"
source "board/creative/xfi3/Kconfig"
source "board/davedenx/qong/Kconfig"

2
arch/arm/cpu/arm1176/tnetv107x/clock.c
View file

@ -362,7 +362,7 @@ static void init_pll(const struct pll_init_data *data)
pllctl_reg_write(data->pll, ctl, tmp);
mult = data->pll_freq / fpll;
for (mult = MAX(mult, 1); mult <= MAX_MULT; mult++) {
for (mult = max(mult, 1); mult <= MAX_MULT; mult++) {
div = (fpll * mult) / data->pll_freq;
if (div < 1 || div > MAX_DIV)
continue;

24
arch/arm/cpu/armv7/at91/clock.c
View file

@ -114,9 +114,25 @@ int at91_clock_init(unsigned long main_clock)
void at91_periph_clk_enable(int id)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
u32 regval;
if (id > 31)
writel(1 << (id - 32), &pmc->pcer1);
else
writel(1 << id, &pmc->pcer);
if (id > AT91_PMC_PCR_PID_MASK)
return;
regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id;
writel(regval, &pmc->pcr);
}
void at91_periph_clk_disable(int id)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
u32 regval;
if (id > AT91_PMC_PCR_PID_MASK)
return;
regval = AT91_PMC_PCR_CMD_WRITE | id;
writel(regval, &pmc->pcr);
}

5
arch/arm/cpu/armv7/exynos/Kconfig
View file

@ -23,18 +23,23 @@ config TARGET_ODROID
config TARGET_ARNDALE
bool "Exynos5250 Arndale board"
select OF_CONTROL if !SPL_BUILD
config TARGET_SMDK5250
bool "SMDK5250 board"
select OF_CONTROL if !SPL_BUILD
config TARGET_SNOW
bool "Snow board"
select OF_CONTROL if !SPL_BUILD
config TARGET_SMDK5420
bool "SMDK5420 board"
select OF_CONTROL if !SPL_BUILD
config TARGET_PEACH_PIT
bool "Peach Pi board"
select OF_CONTROL if !SPL_BUILD
endchoice

75
arch/arm/cpu/armv7/keystone/ddr3.c
View file

@ -10,6 +10,7 @@
#include <asm/io.h>
#include <common.h>
#include <asm/arch/ddr3.h>
#include <asm/arch/psc_defs.h>
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
{
@ -86,3 +87,77 @@ void ddr3_reset_ddrphy(void)
tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
__raw_writel(tmp, KS2_DDR3APLLCTL1);
}
#ifdef CONFIG_SOC_K2HK
/**
* ddr3_reset_workaround - reset workaround in case if leveling error
* detected for PG 1.0 and 1.1 k2hk SoCs
*/
void ddr3_err_reset_workaround(void)
{
unsigned int tmp;
unsigned int tmp_a;
unsigned int tmp_b;
/*
* Check for PGSR0 error bits of DDR3 PHY.
* Check for WLERR, QSGERR, WLAERR,
* RDERR, WDERR, REERR, WEERR error to see if they are set or not
*/
tmp_a = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
tmp_b = __raw_readl(KS2_DDR3B_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
if (((tmp_a & 0x0FE00000) != 0) || ((tmp_b & 0x0FE00000) != 0)) {
printf("DDR Leveling Error Detected!\n");
printf("DDR3A PGSR0 = 0x%x\n", tmp_a);
printf("DDR3B PGSR0 = 0x%x\n", tmp_b);
/*
* Write Keys to KICK registers to enable writes to registers
* in boot config space
*/
__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
/*
* Move DDR3A Module out of reset isolation by setting
* MDCTL23[12] = 0
*/
tmp_a = __raw_readl(KS2_PSC_BASE +
PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
tmp_a = PSC_REG_MDCTL_SET_RESET_ISO(tmp_a, 0);
__raw_writel(tmp_a, KS2_PSC_BASE +
PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
/*
* Move DDR3B Module out of reset isolation by setting
* MDCTL24[12] = 0
*/
tmp_b = __raw_readl(KS2_PSC_BASE +
PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
tmp_b = PSC_REG_MDCTL_SET_RESET_ISO(tmp_b, 0);
__raw_writel(tmp_b, KS2_PSC_BASE +
PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
/*
* Write 0x5A69 Key to RSTCTRL[15:0] to unlock writes
* to RSTCTRL and RSTCFG
*/
tmp = __raw_readl(KS2_RSTCTRL);
tmp &= KS2_RSTCTRL_MASK;
tmp |= KS2_RSTCTRL_KEY;
__raw_writel(tmp, KS2_RSTCTRL);
/*
* Set PLL Controller to drive hard reset on SW trigger by
* setting RSTCFG[13] = 0
*/
tmp = __raw_readl(KS2_RSTCTRL_RSCFG);
tmp &= ~KS2_RSTYPE_PLL_SOFT;
__raw_writel(tmp, KS2_RSTCTRL_RSCFG);
reset_cpu(0);
}
}
#endif

107
arch/arm/cpu/armv7/mx6/clock.c
View file

@ -36,6 +36,35 @@ void enable_ocotp_clk(unsigned char enable)
}
#endif
#ifdef CONFIG_NAND_MXS
void setup_gpmi_io_clk(u32 cfg)
{
/* Disable clocks per ERR007177 from MX6 errata */
clrbits_le32(&imx_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
clrsetbits_le32(&imx_ccm->cs2cdr,
MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
cfg);
setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
setbits_le32(&imx_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
}
#endif
void enable_usboh3_clk(unsigned char enable)
{
u32 reg;
@ -49,6 +78,67 @@ void enable_usboh3_clk(unsigned char enable)
}
#if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
void enable_enet_clk(unsigned char enable)
{
u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
if (enable)
setbits_le32(&imx_ccm->CCGR1, mask);
else
clrbits_le32(&imx_ccm->CCGR1, mask);
}
#endif
#ifdef CONFIG_MXC_UART
void enable_uart_clk(unsigned char enable)
{
u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
if (enable)
setbits_le32(&imx_ccm->CCGR5, mask);
else
clrbits_le32(&imx_ccm->CCGR5, mask);
}
#endif
#ifdef CONFIG_SPI
/* spi_num can be from 0 - 4 */
int enable_cspi_clock(unsigned char enable, unsigned spi_num)
{
u32 mask;
if (spi_num > 4)
return -EINVAL;
mask = MXC_CCM_CCGR_CG_MASK << (spi_num * 2);
if (enable)
setbits_le32(&imx_ccm->CCGR1, mask);
else
clrbits_le32(&imx_ccm->CCGR1, mask);
return 0;
}
#endif
#ifdef CONFIG_MMC
int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
{
u32 mask;
if (bus_num > 3)
return -EINVAL;
mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
if (enable)
setbits_le32(&imx_ccm->CCGR6, mask);
else
clrbits_le32(&imx_ccm->CCGR6, mask);
return 0;
}
#endif
#ifdef CONFIG_SYS_I2C_MXC
/* i2c_num can be from 0 - 2 */
int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
@ -509,6 +599,7 @@ int enable_pcie_clock(void)
struct anatop_regs *anatop_regs =
(struct anatop_regs *)ANATOP_BASE_ADDR;
struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
u32 lvds1_clk_sel;
/*
* Here be dragons!
@ -518,17 +609,25 @@ int enable_pcie_clock(void)
* marked as ANATOP_MISC1 is actually documented in the PMU section
* of the datasheet as PMU_MISC1.
*
* Switch LVDS clock source to SATA (0xb), disable clock INPUT and
* enable clock OUTPUT. This is important for PCI express link that
* is clocked from the i.MX6.
* Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
* mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
* for PCI express link that is clocked from the i.MX6.
*/
#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
if (is_cpu_type(MXC_CPU_MX6SX))
lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
else
lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
clrsetbits_le32(&anatop_regs->ana_misc1,
ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb);
ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
/* PCIe reference clock sourced from AXI. */
clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);

277
arch/arm/cpu/armv7/mx6/ddr.c
View file

@ -184,18 +184,18 @@ void mx6sdl_dram_iocfg(unsigned width,
*/
#define MR(val, ba, cmd, cs1) \
((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
const struct mx6_mmdc_calibration *c,
const struct mx6_ddr3_cfg *m)
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
const struct mx6_mmdc_calibration *calib,
const struct mx6_ddr3_cfg *ddr3_cfg)
{
volatile struct mmdc_p_regs *mmdc0;
volatile struct mmdc_p_regs *mmdc1;
u32 reg;
u32 val;
u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
u16 CS0_END;
u16 cs0_end;
u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
u8 coladdr;
int clkper; /* clock period in picoseconds */
@ -215,13 +215,12 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
clock = 400;
tcwl = 3;
}
clkper = (1000*1000)/clock; /* ps */
clkper = (1000 * 1000) / clock; /* pico seconds */
todtlon = tcwl;
taxpd = tcwl;
tanpd = tcwl;
tcwl = tcwl;
switch (m->density) {
switch (ddr3_cfg->density) {
case 1: /* 1Gb per chip */
trfc = DIV_ROUND_UP(110000, clkper) - 1;
txs = DIV_ROUND_UP(120000, clkper) - 1;
@ -240,80 +239,82 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
break;
default:
/* invalid density */
printf("invalid chip density\n");
puts("invalid chip density\n");
hang();
break;
}
txpr = txs;
switch (m->mem_speed) {
switch (ddr3_cfg->mem_speed) {
case 800:
txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
tcke = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
if (m->pagesz == 1) {
txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
if (ddr3_cfg->pagesz == 1) {
tfaw = DIV_ROUND_UP(40000, clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
} else {
tfaw = DIV_ROUND_UP(50000, clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
}
break;
case 1066:
txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
if (m->pagesz == 1) {
txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
if (ddr3_cfg->pagesz == 1) {
tfaw = DIV_ROUND_UP(37500, clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
} else {
tfaw = DIV_ROUND_UP(50000, clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
}
break;
case 1333:
txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
if (m->pagesz == 1) {
txp = DIV_ROUND_UP(max(3 * clkper, 6000), clkper) - 1;
tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
if (ddr3_cfg->pagesz == 1) {
tfaw = DIV_ROUND_UP(30000, clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
trrd = DIV_ROUND_UP(max(4 * clkper, 6000), clkper) - 1;
} else {
tfaw = DIV_ROUND_UP(45000, clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
}
break;
case 1600:
txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
tcke = DIV_ROUND_UP(MAX(3*clkper, 5000), clkper) - 1;
if (m->pagesz == 1) {
txp = DIV_ROUND_UP(max(3 * clkper, 6000), clkper) - 1;
tcke = DIV_ROUND_UP(max(3 * clkper, 5000), clkper) - 1;
if (ddr3_cfg->pagesz == 1) {
tfaw = DIV_ROUND_UP(30000, clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
trrd = DIV_ROUND_UP(max(4 * clkper, 6000), clkper) - 1;
} else {
tfaw = DIV_ROUND_UP(40000, clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
}
break;
default:
printf("invalid memory speed\n");
puts("invalid memory speed\n");
hang();
break;
}
txpdll = DIV_ROUND_UP(MAX(10*clkper, 24000), clkper) - 1;
tcl = DIV_ROUND_UP(m->trcd, clkper/10) - 3;
tcksre = DIV_ROUND_UP(MAX(5*clkper, 10000), clkper);
tcksrx = tcksre;
txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1;
tcksre = DIV_ROUND_UP(max(5 * clkper, 10000), clkper);
taonpd = DIV_ROUND_UP(2000, clkper) - 1;
tcksrx = tcksre;
taofpd = taonpd;
trp = DIV_ROUND_UP(m->trcd, clkper/10) - 1;
twr = DIV_ROUND_UP(15000, clkper) - 1;
tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1;
trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
trcd = trp;
trc = DIV_ROUND_UP(m->trcmin, clkper/10) - 1;
tras = DIV_ROUND_UP(m->trasmin, clkper/10) - 1;
twr = DIV_ROUND_UP(15000, clkper) - 1;
tmrd = DIV_ROUND_UP(MAX(12*clkper, 15000), clkper) - 1;
twtr = ROUND(MAX(4*clkper, 7500)/clkper, 1) - 1;
trtp = twtr;
CS0_END = ((4*i->cs_density) <= 120) ? (4*i->cs_density)+7 : 127;
debug("density:%d Gb (%d Gb per chip)\n", i->cs_density, m->density);
cs0_end = 4 * sysinfo->cs_density - 1;
debug("density:%d Gb (%d Gb per chip)\n",
sysinfo->cs_density, ddr3_cfg->density);
debug("clock: %dMHz (%d ps)\n", clock, clkper);
debug("memspd:%d\n", m->mem_speed);
debug("memspd:%d\n", ddr3_cfg->mem_speed);
debug("tcke=%d\n", tcke);
debug("tcksrx=%d\n", tcksrx);
debug("tcksre=%d\n", tcksre);
@ -340,11 +341,11 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
debug("twtr=%d\n", twtr);
debug("trrd=%d\n", trrd);
debug("txpr=%d\n", txpr);
debug("CS0_END=%d\n", CS0_END);
debug("ncs=%d\n", i->ncs);
debug("Rtt_wr=%d\n", i->rtt_wr);
debug("Rtt_nom=%d\n", i->rtt_nom);
debug("SRT=%d\n", m->SRT);
debug("cs0_end=%d\n", cs0_end);
debug("ncs=%d\n", sysinfo->ncs);
debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
debug("SRT=%d\n", ddr3_cfg->SRT);
debug("tcl=%d\n", tcl);
debug("twr=%d\n", twr);
@ -354,142 +355,136 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
* see:
* appnote, ddr3 spreadsheet
*/
mmdc0->mpwldectrl0 = c->p0_mpwldectrl0;
mmdc0->mpwldectrl1 = c->p0_mpwldectrl1;
mmdc0->mpdgctrl0 = c->p0_mpdgctrl0;
mmdc0->mpdgctrl1 = c->p0_mpdgctrl1;
mmdc0->mprddlctl = c->p0_mprddlctl;
mmdc0->mpwrdlctl = c->p0_mpwrdlctl;
if (i->dsize > 1) {
mmdc1->mpwldectrl0 = c->p1_mpwldectrl0;
mmdc1->mpwldectrl1 = c->p1_mpwldectrl1;
mmdc1->mpdgctrl0 = c->p1_mpdgctrl0;
mmdc1->mpdgctrl1 = c->p1_mpdgctrl1;
mmdc1->mprddlctl = c->p1_mprddlctl;
mmdc1->mpwrdlctl = c->p1_mpwrdlctl;
mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
mmdc0->mprddlctl = calib->p0_mprddlctl;
mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
if (sysinfo->dsize > 1) {
mmdc1->mpwldectrl0 = calib->p1_mpwldectrl0;
mmdc1->mpwldectrl1 = calib->p1_mpwldectrl1;
mmdc1->mpdgctrl0 = calib->p1_mpdgctrl0;
mmdc1->mpdgctrl1 = calib->p1_mpdgctrl1;
mmdc1->mprddlctl = calib->p1_mprddlctl;
mmdc1->mpwrdlctl = calib->p1_mpwrdlctl;
}
/* Read data DQ Byte0-3 delay */
mmdc0->mprddqby0dl = (u32)0x33333333;
mmdc0->mprddqby1dl = (u32)0x33333333;
if (i->dsize > 0) {
mmdc0->mprddqby2dl = (u32)0x33333333;
mmdc0->mprddqby3dl = (u32)0x33333333;
mmdc0->mprddqby0dl = 0x33333333;
mmdc0->mprddqby1dl = 0x33333333;
if (sysinfo->dsize > 0) {
mmdc0->mprddqby2dl = 0x33333333;
mmdc0->mprddqby3dl = 0x33333333;
}
if (i->dsize > 1) {
mmdc1->mprddqby0dl = (u32)0x33333333;
mmdc1->mprddqby1dl = (u32)0x33333333;
mmdc1->mprddqby2dl = (u32)0x33333333;
mmdc1->mprddqby3dl = (u32)0x33333333;
if (sysinfo->dsize > 1) {
mmdc1->mprddqby0dl = 0x33333333;
mmdc1->mprddqby1dl = 0x33333333;
mmdc1->mprddqby2dl = 0x33333333;
mmdc1->mprddqby3dl = 0x33333333;
}
/* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
reg = (i->rtt_nom == 2) ? 0x00011117 : 0x00022227;
mmdc0->mpodtctrl = reg;
if (i->dsize > 1)
mmdc1->mpodtctrl = reg;
val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
mmdc0->mpodtctrl = val;
if (sysinfo->dsize > 1)
mmdc1->mpodtctrl = val;
/* complete calibration */
reg = (1 << 11); /* Force measurement on delay-lines */
mmdc0->mpmur0 = reg;
if (i->dsize > 1)
mmdc1->mpmur0 = reg;
val = (1 << 11); /* Force measurement on delay-lines */
mmdc0->mpmur0 = val;
if (sysinfo->dsize > 1)
mmdc1->mpmur0 = val;
/* Step 1: configuration request */
mmdc0->mdscr = (u32)(1 << 15); /* config request */
/* Step 2: Timing configuration */
reg = (trfc << 24) | (txs << 16) | (txp << 13) | (txpdll << 9) |
(tfaw << 4) | tcl;
mmdc0->mdcfg0 = reg;
reg = (trcd << 29) | (trp << 26) | (trc << 21) | (tras << 16) |
(1 << 15) | /* trpa */
(twr << 9) | (tmrd << 5) | tcwl;
mmdc0->mdcfg1 = reg;
reg = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
mmdc0->mdcfg2 = reg;
reg = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) | (taxpd << 16) |
(todtlon << 12) | (todt_idle_off << 4);
mmdc0->mdotc = reg;
mmdc0->mdasp = CS0_END; /* CS addressing */
mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
(txpdll << 9) | (tfaw << 4) | tcl;
mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
(tras << 16) | (1 << 15) /* trpa */ |
(twr << 9) | (tmrd << 5) | tcwl;
mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
(taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
mmdc0->mdasp = cs0_end; /* CS addressing */
/* Step 3: Configure DDR type */
reg = (i->cs1_mirror << 19) | (i->walat << 16) | (i->bi_on << 12) |
(i->mif3_mode << 9) | (i->ralat << 6);
mmdc0->mdmisc = reg;
mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
(sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
(sysinfo->ralat << 6);
/* Step 4: Configure delay while leaving reset */
reg = (txpr << 16) | (i->sde_to_rst << 8) | (i->rst_to_cke << 0);
mmdc0->mdor = reg;
mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
(sysinfo->rst_to_cke << 0);
/* Step 5: Configure DDR physical parameters (density and burst len) */
coladdr = m->coladdr;
if (m->coladdr == 8) /* 8-bit COL is 0x3 */
coladdr = ddr3_cfg->coladdr;
if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
coladdr += 4;
else if (m->coladdr == 12) /* 12-bit COL is 0x4 */
else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
coladdr += 1;
reg = (m->rowaddr - 11) << 24 | /* ROW */
(coladdr - 9) << 20 | /* COL */
(1 << 19) | /* Burst Length = 8 for DDR3 */
(i->dsize << 16); /* DDR data bus size */
mmdc0->mdctl = reg;
mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */
(coladdr - 9) << 20 | /* COL */
(1 << 19) | /* Burst Length = 8 for DDR3 */
(sysinfo->dsize << 16); /* DDR data bus size */
/* Step 6: Perform ZQ calibration */
reg = (u32)0xa1390001; /* one-time HW ZQ calib */
mmdc0->mpzqhwctrl = reg;
if (i->dsize > 1)
mmdc1->mpzqhwctrl = reg;
val = 0xa1390001; /* one-time HW ZQ calib */
mmdc0->mpzqhwctrl = val;
if (sysinfo->dsize > 1)
mmdc1->mpzqhwctrl = val;
/* Step 7: Enable MMDC with desired chip select */
reg = mmdc0->mdctl |
(1 << 31) | /* SDE_0 for CS0 */
((i->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
mmdc0->mdctl = reg;
mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
/* Step 8: Write Mode Registers to Init DDR3 devices */
for (cs = 0; cs < i->ncs; cs++) {
for (cs = 0; cs < sysinfo->ncs; cs++) {
/* MR2 */
reg = (i->rtt_wr & 3) << 9 | (m->SRT & 1) << 7 |
val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
((tcwl - 3) & 3) << 3;
mmdc0->mdscr = (u32)MR(reg, 2, 3, cs);
mmdc0->mdscr = MR(val, 2, 3, cs);
/* MR3 */
mmdc0->mdscr = (u32)MR(0, 3, 3, cs);
mmdc0->mdscr = MR(0, 3, 3, cs);
/* MR1 */
reg = ((i->rtt_nom & 1) ? 1 : 0) << 2 |
((i->rtt_nom & 2) ? 1 : 0) << 6;
mmdc0->mdscr = (u32)MR(reg, 1, 3, cs);
reg = ((tcl - 1) << 4) | /* CAS */
val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
mmdc0->mdscr = MR(val, 1, 3, cs);
/* MR0 */
val = ((tcl - 1) << 4) | /* CAS */
(1 << 8) | /* DLL Reset */
((twr - 3) << 9); /* Write Recovery */
/* MR0 */
mmdc0->mdscr = (u32)MR(reg, 0, 3, cs);
mmdc0->mdscr = MR(val, 0, 3, cs);
/* ZQ calibration */
reg = (1 << 10);
mmdc0->mdscr = (u32)MR(reg, 0, 4, cs);
val = (1 << 10);
mmdc0->mdscr = MR(val, 0, 4, cs);
}
/* Step 10: Power down control and self-refresh */
reg = (tcke & 0x7) << 16 |
5 << 12 | /* PWDT_1: 256 cycles */
5 << 8 | /* PWDT_0: 256 cycles */
1 << 6 | /* BOTH_CS_PD */
(tcksrx & 0x7) << 3 |
(tcksre & 0x7);
mmdc0->mdpdc = reg;
mmdc0->mapsr = (u32)0x00011006; /* ADOPT power down enabled */
mmdc0->mdpdc = (tcke & 0x7) << 16 |
5 << 12 | /* PWDT_1: 256 cycles */
5 << 8 | /* PWDT_0: 256 cycles */
1 << 7 | /* SLOW_PD */
1 << 6 | /* BOTH_CS_PD */
(tcksrx & 0x7) << 3 |
(tcksre & 0x7);
mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
/* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
mmdc0->mpzqhwctrl = (u32)0xa1390003;
if (i->dsize > 1)
mmdc1->mpzqhwctrl = (u32)0xa1390003;
val = 0xa1390003;
mmdc0->mpzqhwctrl = val;
if (sysinfo->dsize > 1)
mmdc1->mpzqhwctrl = val;
/* Step 12: Configure and activate periodic refresh */
reg = (1 << 14) | /* REF_SEL: Periodic refresh cycles of 32kHz */
(7 << 11); /* REFR: Refresh Rate - 8 refreshes */
mmdc0->mdref = reg;
mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
(7 << 11); /* REFR: Refresh Rate - 8 refreshes */
/* Step 13: Deassert config request - init complete */
mmdc0->mdscr = (u32)0x00000000;
mmdc0->mdscr = 0x00000000;
/* wait for auto-ZQ calibration to complete */
mdelay(1);

11
arch/arm/cpu/armv7/mx6/soc.c
View file

@ -324,10 +324,10 @@ const struct boot_mode soc_boot_modes[] = {
/* reserved value should start rom usb */
{"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
{"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
{"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
{"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
{"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
{"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
{"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
{"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
{"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
{"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
/* 4 bit bus width */
{"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
{"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
@ -430,6 +430,9 @@ void v7_outer_cache_enable(void)
}
#endif
/* Must disable the L2 before changing the latency parameters */
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
writel(0x132, &pl310->pl310_tag_latency_ctrl);
writel(0x132, &pl310->pl310_data_latency_ctrl);

32
arch/arm/cpu/armv7/uniphier/Kconfig Normal file
View file

@ -0,0 +1,32 @@
menu "Panasonic UniPhier platform"
depends on ARCH_UNIPHIER
config SYS_CPU
string
default "armv7"
config SYS_SOC
string
default "uniphier"
config SYS_CONFIG_NAME
string
default "ph1_pro4" if MACH_PH1_PRO4
default "ph1_ld4" if MACH_PH1_LD4
default "ph1_sld8" if MACH_PH1_SLD8
choice
prompt "UniPhier SoC select"
config MACH_PH1_PRO4
bool "PH1-Pro4"
config MACH_PH1_LD4
bool "PH1-LD4"
config MACH_PH1_SLD8
bool "PH1-sLD8"
endchoice
endmenu

23
arch/arm/cpu/armv7/uniphier/Makefile Normal file
View file

@ -0,0 +1,23 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_SPL_BUILD) += lowlevel_init.o init_page_table.o
obj-$(CONFIG_SPL_BUILD) += spl.o
obj-y += timer.o
obj-y += reset.o
obj-y += cache_uniphier.o
obj-y += dram_init.o
obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
obj-$(CONFIG_UNIPHIER_SMP) += smp.o
obj-$(if $(CONFIG_SPL_BUILD),,y) += cmd_pinmon.o
obj-y += board_common.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o
obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += support_card.o
obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/
obj-$(CONFIG_MACH_PH1_PRO4) += ph1-pro4/
obj-$(CONFIG_MACH_PH1_SLD8) += ph1-sld8/

32
arch/arm/cpu/armv7/uniphier/board_common.c Normal file
View file

@ -0,0 +1,32 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/led.h>
/*
* Routine: board_init
* Description: Early hardware init.
*/
int board_init(void)
{
led_write(U, B, O, O);
return 0;
}
#if CONFIG_NR_DRAM_BANKS >= 2
void dram_init_banksize(void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = CONFIG_SDRAM0_BASE;
gd->bd->bi_dram[0].size = CONFIG_SDRAM0_SIZE;
gd->bd->bi_dram[1].start = CONFIG_SDRAM1_BASE;
gd->bd->bi_dram[1].size = CONFIG_SDRAM1_SIZE;
}
#endif

91
arch/arm/cpu/armv7/uniphier/board_late_init.c Normal file
View file

@ -0,0 +1,91 @@
/*
* Copyright (C) 2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <nand.h>
#include <asm/io.h>
#include <../drivers/mtd/nand/denali.h>
static void nand_denali_wp_disable(void)
{
#ifdef CONFIG_NAND_DENALI
/*
* Since the boot rom enables the write protection for NAND boot mode,
* it must be disabled somewhere for "nand write", "nand erase", etc.
* The workaround is here to not disturb the Denali NAND controller
* driver just for a really SoC-specific thing.
*/
void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
writel(WRITE_PROTECT__FLAG, denali_reg + WRITE_PROTECT);
#endif
}
static void nand_denali_fixup(void)
{
#if defined(CONFIG_NAND_DENALI) && \
(defined(CONFIG_MACH_PH1_SLD8) || defined(CONFIG_MACH_PH1_PRO4))
/*
* The Denali NAND controller on some of UniPhier SoCs does not
* automatically query the device parameters. For those SoCs,
* some registers must be set after the device is probed.
*/
void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
struct mtd_info *mtd;
struct nand_chip *chip;
if (nand_curr_device < 0 ||
nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE) {
/* NAND was not detected. Just return. */
return;
}
mtd = &nand_info[nand_curr_device];
chip = mtd->priv;
writel(mtd->erasesize / mtd->writesize, denali_reg + PAGES_PER_BLOCK);
writel(0, denali_reg + DEVICE_WIDTH);
writel(mtd->writesize, denali_reg + DEVICE_MAIN_AREA_SIZE);
writel(mtd->oobsize, denali_reg + DEVICE_SPARE_AREA_SIZE);
writel(1, denali_reg + DEVICES_CONNECTED);
/*
* chip->scan_bbt in nand_scan_tail() has been skipped.
* It should be done in here.
*/
chip->scan_bbt(mtd);
#endif
}
int board_late_init(void)
{
puts("MODE: ");
switch (spl_boot_device()) {
case BOOT_DEVICE_MMC1:
printf("eMMC Boot\n");
setenv("bootmode", "emmcboot");
nand_denali_fixup();
break;
case BOOT_DEVICE_NAND:
printf("NAND Boot\n");
setenv("bootmode", "nandboot");
nand_denali_wp_disable();
break;
case BOOT_DEVICE_NOR:
printf("NOR Boot\n");
setenv("bootmode", "norboot");
nand_denali_fixup();
break;
default:
printf("Unsupported Boot Mode\n");
return -1;
}
return 0;
}

154
arch/arm/cpu/armv7/uniphier/cache_uniphier.c Normal file
View file

@ -0,0 +1,154 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/armv7.h>
#include <asm/arch/ssc-regs.h>
#ifdef CONFIG_UNIPHIER_L2CACHE_ON
static void uniphier_cache_maint_all(u32 operation)
{
/* try until the command is successfully set */
do {
writel(SSCOQM_S_ALL | SSCOQM_CE | operation, SSCOQM);
} while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE));
/* wait until the operation is completed */
while (readl(SSCOLPQS) != SSCOLPQS_EF)
;
/* clear the complete notification flag */
writel(SSCOLPQS_EF, SSCOLPQS);
writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
readl(SSCOPE); /* need a read back to confirm */
}
void v7_outer_cache_flush_all(void)
{
uniphier_cache_maint_all(SSCOQM_CM_WB_INV);
}
void v7_outer_cache_inval_all(void)
{
uniphier_cache_maint_all(SSCOQM_CM_INV);
}
static void __uniphier_cache_maint_range(u32 start, u32 size, u32 operation)
{
/* try until the command is successfully set */
do {
writel(SSCOQM_S_ADDRESS | SSCOQM_CE | operation, SSCOQM);
writel(start, SSCOQAD);
writel(size, SSCOQSZ);
} while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE));
/* wait until the operation is completed */
while (readl(SSCOLPQS) != SSCOLPQS_EF)
;
/* clear the complete notification flag */
writel(SSCOLPQS_EF, SSCOLPQS);
}
static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation)
{
u32 size;
/*
* If start address is not aligned to cache-line,
* do cache operation for the first cache-line
*/
start = start & ~(SSC_LINE_SIZE - 1);
if (start == 0 && end >= (u32)(-SSC_LINE_SIZE)) {
/* this means cache operation for all range */
uniphier_cache_maint_all(operation);
return;
}
/*
* If end address is not aligned to cache-line,
* do cache operation for the last cache-line
*/
size = (end - start + SSC_LINE_SIZE - 1) & ~(SSC_LINE_SIZE - 1);
while (size) {
u32 chunk_size = size > SSC_RANGE_OP_MAX_SIZE ?
SSC_RANGE_OP_MAX_SIZE : size;
__uniphier_cache_maint_range(start, chunk_size, operation);
start += chunk_size;
size -= chunk_size;
}
writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
readl(SSCOPE); /* need a read back to confirm */
}
void v7_outer_cache_flush_range(u32 start, u32 end)
{
uniphier_cache_maint_range(start, end, SSCOQM_CM_WB_INV);
}
void v7_outer_cache_inval_range(u32 start, u32 end)
{
uniphier_cache_maint_range(start, end, SSCOQM_CM_INV);
}
void v7_outer_cache_enable(void)
{
u32 tmp;
tmp = readl(SSCC);
tmp |= SSCC_ON;
writel(tmp, SSCC);
}
#endif
void v7_outer_cache_disable(void)
{
u32 tmp;
tmp = readl(SSCC);
tmp &= ~SSCC_ON;
writel(tmp, SSCC);
}
void wakeup_secondary(void);
void enable_caches(void)
{
uint32_t reg;
#ifdef CONFIG_UNIPHIER_SMP
/*
* The secondary CPU must move to DDR,
* before L2 disable.
* On SPL, the Page Table is located on the L2.
*/
wakeup_secondary();
#endif
/*
* UniPhier SoCs must use L2 cache for init stack pointer.
* We disable L2 and L1 in this order.
* If CONFIG_SYS_DCACHE_OFF is not defined,
* caches are enabled again with a new page table.
*/
/* L2 disable */
v7_outer_cache_disable();
/* L1 disable */
reg = get_cr();
reg &= ~(CR_C | CR_M);
set_cr(reg);
#ifndef CONFIG_SYS_DCACHE_OFF
dcache_enable();
#endif
}

33
arch/arm/cpu/armv7/uniphier/cmd_pinmon.c Normal file
View file

@ -0,0 +1,33 @@
/*
* Copyright (C) 2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/boot-device.h>
static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct boot_device_info *table;
u32 mode_sel, n = 0;
mode_sel = get_boot_mode_sel();
puts("Boot Mode Pin:\n");
for (table = boot_device_table; strlen(table->info); table++) {
printf(" %c %02x %s\n", n == mode_sel ? '*' : ' ', n,
table->info);
n++;
}
return 0;
}
U_BOOT_CMD(
pinmon, 1, 1, do_pinmon,
"pin monitor",
""
);

59
arch/arm/cpu/armv7/uniphier/cpu_info.c Normal file
View file

@ -0,0 +1,59 @@
/*
* Copyright (C) 2013-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sg-regs.h>
int print_cpuinfo(void)
{
u32 revision, type, model, rev, required_model = 1, required_rev = 1;
revision = readl(SG_REVISION);
type = (revision & SG_REVISION_TYPE_MASK) >> SG_REVISION_TYPE_SHIFT;
model = (revision & SG_REVISION_MODEL_MASK) >> SG_REVISION_MODEL_SHIFT;
rev = (revision & SG_REVISION_REV_MASK) >> SG_REVISION_REV_SHIFT;
puts("CPU: ");
switch (type) {
case 0x25:
puts("PH1-sLD3 (MN2WS0220)");
required_model = 2;
break;
case 0x26:
puts("PH1-LD4 (MN2WS0250)");
required_rev = 2;
break;
case 0x28:
puts("PH1-Pro4 (MN2WS0230)");
break;
case 0x29:
puts("PH1-sLD8 (MN2WS0270)");
break;
default:
printf("Unknown Processor ID (0x%x)\n", revision);
return -1;
}
if (model > 1)
printf(" model %d", model);
printf(" (rev. %d)\n", rev);
if (model < required_model) {
printf("Sorry, this model is not supported.\n");
printf("Required model is %d.", required_model);
return -1;
} else if (rev < required_rev) {
printf("Sorry, this revision is not supported.\n");
printf("Required revision is %d.", required_rev);
return -1;
}
return 0;
}

37
arch/arm/cpu/armv7/uniphier/dram_init.c Normal file
View file

@ -0,0 +1,37 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/led.h>
int umc_init(void);
void enable_dpll_ssc(void);
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
led_write(B, 4, , );
{
int res;
res = umc_init();
if (res < 0)
return res;
}
led_write(B, 5, , );
enable_dpll_ssc();
#endif
led_write(B, 6, , );
return 0;
}

1068
arch/arm/cpu/armv7/uniphier/init_page_table.c Normal file
View file

File diff suppressed because it is too large Load diff

159
arch/arm/cpu/armv7/uniphier/lowlevel_init.S Normal file
View file

@ -0,0 +1,159 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/system.h>
#include <asm/arch/led.h>
#include <asm/arch/arm-mpcore.h>
#include <asm/arch/sbc-regs.h>
ENTRY(lowlevel_init)
mov r8, lr @ persevere link reg across call
/*
* The UniPhier Boot ROM loads SPL code to the L2 cache.
* But CPUs can only do instruction fetch now because start.S has
* cleared C and M bits.
* First we need to turn on MMU and Dcache again to get back
* data access to L2.
*/
mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
mcr p15, 0, r0, c1, c0, 0
/*
* Now we are using the page table embedded in the Boot ROM.
* It is not handy since it is not a straight mapped table for sLD3.
* What we need to do next is to switch over to the page table in SPL.
*/
ldr r3, =init_page_table @ page table must be 16KB aligned
/* Disable MMU and Dcache before switching Page Table */
mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache
mcr p15, 0, r0, c1, c0, 0
bl enable_mmu
#ifdef CONFIG_UNIPHIER_SMP
/*
* ACTLR (Auxiliary Control Register) for Cortex-A9
* bit[9] Parity on
* bit[8] Alloc in one way
* bit[7] EXCL (Exclusive cache bit)
* bit[6] SMP
* bit[3] Write full line of zeros mode
* bit[2] L1 Prefetch enable
* bit[1] L2 prefetch enable
* bit[0] FW (Cache and TLB maintenance broadcast)
*/
mrc p15, 0, r0, c1, c0, 1 @ ACTLR (Auxiliary Control Register)
orr r0, r0, #0x41 @ enable SMP, FW bit
mcr p15, 0, r0, c1, c0, 1
/* branch by CPU ID */
mrc p15, 0, r0, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Register)
and r0, r0, #0x3
cmp r0, #0x0
beq primary_cpu
ldr r1, =ROM_BOOT_ROMRSV2
mov r0, #0
str r0, [r1]
0: wfe
ldr r0, [r1]
cmp r0, #0
beq 0b
bx r0 @ r0: entry point of U-Boot main for the secondary CPU
primary_cpu:
ldr r1, =ROM_BOOT_ROMRSV2
ldr r0, =_start @ entry for the secondary CPU
str r0, [r1]
ldr r0, [r1] @ make sure str is complete before sev
sev @ kick the sedoncary CPU
mrc p15, 4, r1, c15, c0, 0 @ Configuration Base Address Register
bfc r1, #0, #13 @ clear bit 12-0
mov r0, #-1
str r0, [r1, #SCU_INV_ALL] @ SCU Invalidate All Register
mov r0, #1 @ SCU enable
str r0, [r1, #SCU_CTRL] @ SCU Control Register
#endif
bl setup_init_ram @ RAM area for temporary stack pointer
mov lr, r8 @ restore link
mov pc, lr @ back to my caller
ENDPROC(lowlevel_init)
ENTRY(enable_mmu)
mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
bic r0, r0, #0x37
orr r0, r0, #0x20 @ disable TTBR1
mcr p15, 0, r0, c2, c0, 2
orr r0, r3, #0x8 @ Outer Cacheability for table walks: WBWA
mcr p15, 0, r0, c2, c0, 0 @ TTBR0
mov r0, #0
mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
mov r0, #-1 @ manager for all domains (No permission check)
mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
dsb
isb
/*
* MMU on:
* TLBs was already invalidated in "../start.S"
* So, we don't need to invalidate it here.
*/
mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable
mcr p15, 0, r0, c1, c0, 0
mov pc, lr
ENDPROC(enable_mmu)
#include <asm/arch/ssc-regs.h>
#define BOOT_RAM_SIZE (SSC_WAY_SIZE)
#define BOOT_WAY_BITS (0x00000100) /* way 8 */
ENTRY(setup_init_ram)
/*
* Touch to zero for the boot way
*/
0:
/*
* set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order
*/
ldr r0, = 0x00408006 @ touch to zero with address range
ldr r1, = SSCOQM
str r0, [r1]
ldr r0, = (CONFIG_SYS_INIT_SP_ADDR - BOOT_RAM_SIZE) @ base address
ldr r1, = SSCOQAD
str r0, [r1]
ldr r0, = BOOT_RAM_SIZE
ldr r1, = SSCOQSZ
str r0, [r1]
ldr r0, = BOOT_WAY_BITS
ldr r1, = SSCOQWN
str r0, [r1]
ldr r1, = SSCOPPQSEF
ldr r0, [r1]
cmp r0, #0 @ check if the command is successfully set
bne 0b @ try again if an error occurres
ldr r1, = SSCOLPQS
1:
ldr r0, [r1]
cmp r0, #0x4
bne 1b @ wait until the operation is completed
str r0, [r1] @ clear the complete notification flag
mov pc, lr
ENDPROC(setup_init_ram)

10
arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile Normal file
View file

@ -0,0 +1,10 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-y += boot-mode.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \
umc_init.o

33
arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c Normal file
View file

@ -0,0 +1,33 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/bcu-regs.h>
#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
void bcu_init(void)
{
int shift;
writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */
writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
/* Specify DDR channel */
shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4;
writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
shift -= 32;
writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
shift -= 32;
writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
}

16
arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c Normal file
View file

@ -0,0 +1,16 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/board.h>
int checkboard(void)
{
puts("Board: PH1-LD4 Board\n");
return check_support_card();
}

42
arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c Normal file
View file

@ -0,0 +1,42 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/led.h>
#include <asm/arch/board.h>
void bcu_init(void);
void sbc_init(void);
void sg_init(void);
void pll_init(void);
void pin_init(void);
void clkrst_init(void);
int board_postclk_init(void)
{
bcu_init();
sbc_init();
sg_init();
pll_init();
uniphier_board_init();
led_write(B, 1, , );
clkrst_init();
led_write(B, 2, , );
pin_init();
led_write(B, 3, , );
return 0;
}

1
arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c Normal file
View file

@ -0,0 +1 @@
#include "../ph1-pro4/boot-mode.c"

29
arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c Normal file
View file

@ -0,0 +1,29 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sc-regs.h>
void clkrst_init(void)
{
u32 tmp;
/* deassert reset */
tmp = readl(SC_RSTCTRL);
tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
| SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
writel(tmp, SC_RSTCTRL);
readl(SC_RSTCTRL); /* dummy read */
/* privide clocks */
tmp = readl(SC_CLKCTRL);
tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
| SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
writel(tmp, SC_CLKCTRL);
readl(SC_CLKCTRL); /* dummy read */
}

63
arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c Normal file
View file

@ -0,0 +1,63 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sg-regs.h>
void pin_init(void)
{
u32 tmp;
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_UNIPHIER_SERIAL
sg_set_pinsel(85, 1); /* HSDOUT3 -> RXD0 */
sg_set_pinsel(88, 1); /* HDDOUT6 -> TXD0 */
sg_set_pinsel(69, 23); /* PCIOWR -> TXD1 */
sg_set_pinsel(70, 23); /* PCIORD -> RXD1 */
sg_set_pinsel(128, 13); /* XIRQ6 -> TXD2 */
sg_set_pinsel(129, 13); /* XIRQ7 -> RXD2 */
sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */
sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */
#endif
#ifdef CONFIG_NAND_DENALI
sg_set_pinsel(158, 0); /* XNFRE -> XNFRE_GB */
sg_set_pinsel(159, 0); /* XNFWE -> XNFWE_GB */
sg_set_pinsel(160, 0); /* XFALE -> NFALE_GB */
sg_set_pinsel(161, 0); /* XFCLE -> NFCLE_GB */
sg_set_pinsel(162, 0); /* XNFWP -> XFNWP_GB */
sg_set_pinsel(163, 0); /* XNFCE0 -> XNFCE0_GB */
sg_set_pinsel(164, 0); /* NANDRYBY0 -> NANDRYBY0_GB */
sg_set_pinsel(22, 0); /* MMCCLK -> XFNCE1_GB */
sg_set_pinsel(23, 0); /* MMCCMD -> NANDRYBY1_GB */
sg_set_pinsel(24, 0); /* MMCDAT0 -> NFD0_GB */
sg_set_pinsel(25, 0); /* MMCDAT1 -> NFD1_GB */
sg_set_pinsel(26, 0); /* MMCDAT2 -> NFD2_GB */
sg_set_pinsel(27, 0); /* MMCDAT3 -> NFD3_GB */
sg_set_pinsel(28, 0); /* MMCDAT4 -> NFD4_GB */
sg_set_pinsel(29, 0); /* MMCDAT5 -> NFD5_GB */
sg_set_pinsel(30, 0); /* MMCDAT6 -> NFD6_GB */
sg_set_pinsel(31, 0); /* MMCDAT7 -> NFD7_GB */
#endif
#ifdef CONFIG_USB_EHCI_UNIPHIER
sg_set_pinsel(53, 0); /* USB0VBUS -> USB0VBUS */
sg_set_pinsel(54, 0); /* USB0OD -> USB0OD */
sg_set_pinsel(55, 0); /* USB1VBUS -> USB1VBUS */
sg_set_pinsel(56, 0); /* USB1OD -> USB1OD */
/* sg_set_pinsel(67, 23); */ /* PCOE -> USB2VBUS */
/* sg_set_pinsel(68, 23); */ /* PCWAIT -> USB2OD */
#endif
tmp = readl(SG_IECTRL);
tmp |= 0x41;
writel(tmp, SG_IECTRL);
}

189
arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c Normal file
View file

@ -0,0 +1,189 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sc-regs.h>
#include <asm/arch/sg-regs.h>
#undef DPLL_SSC_RATE_1PER
void dpll_init(void)
{
u32 tmp;
/*
* Set Frequency
* Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
* to FOUT (DPLLCTRL.bit[29:20])
*/
tmp = readl(SC_DPLLCTRL);
tmp &= ~0x000f0000;
#if CONFIG_DDR_FREQ == 1600
tmp |= 0x000c0000;
#elif CONFIG_DDR_FREQ == 1333
tmp |= 0x000d0000;
#else
# error "Unknown frequency"
#endif
#if defined(DPLL_SSC_RATE_1PER)
tmp &= ~SC_DPLLCTRL_SSC_RATE;
#else
tmp |= SC_DPLLCTRL_SSC_RATE;
#endif
writel(tmp, SC_DPLLCTRL);
tmp = readl(SC_DPLLCTRL2);
tmp |= SC_DPLLCTRL2_NRSTDS;
writel(tmp, SC_DPLLCTRL2);
}
void upll_init(void)
{
u32 tmp, clk_mode_upll, clk_mode_axosel;
tmp = readl(SG_PINMON0);
clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
tmp = readl(SC_UPLLCTRL);
tmp &= ~0x18000000;
writel(tmp, SC_UPLLCTRL);
if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
/* AXO: 25MHz */
tmp &= ~0x07ffffff;
tmp |= 0x0228f5c0;
} else {
/* AXO: default 24.576MHz */
tmp &= ~0x07ffffff;
tmp |= 0x02328000;
}
}
writel(tmp, SC_UPLLCTRL);
/* set 1 to K_LD(UPLLCTRL.bit[27]) */
tmp |= 0x08000000;
writel(tmp, SC_UPLLCTRL);
/* wait 10 usec */
udelay(10);
/* set 1 to SNRT(UPLLCTRL.bit[28]) */
tmp |= 0x10000000;
writel(tmp, SC_UPLLCTRL);
}
void vpll_init(void)
{
u32 tmp, clk_mode_axosel;
tmp = readl(SG_PINMON0);
clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
/* set 1 to VPLA27WP and VPLA27WP */
tmp = readl(SC_VPLL27ACTRL);
tmp |= 0x00000001;
writel(tmp, SC_VPLL27ACTRL);
tmp = readl(SC_VPLL27BCTRL);
tmp |= 0x00000001;
writel(tmp, SC_VPLL27BCTRL);
/* Set 0 to VPLA_K_LD and VPLB_K_LD */
tmp = readl(SC_VPLL27ACTRL3);
tmp &= ~0x10000000;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp &= ~0x10000000;
writel(tmp, SC_VPLL27BCTRL3);
/* Set 0 to VPLA_SNRST and VPLB_SNRST */
tmp = readl(SC_VPLL27ACTRL2);
tmp &= ~0x10000000;
writel(tmp, SC_VPLL27ACTRL2);
tmp = readl(SC_VPLL27BCTRL2);
tmp &= ~0x10000000;
writel(tmp, SC_VPLL27BCTRL2);
/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
tmp = readl(SC_VPLL27ACTRL2);
tmp &= ~0x0000007f;
tmp |= 0x00000020;
writel(tmp, SC_VPLL27ACTRL2);
tmp = readl(SC_VPLL27BCTRL2);
tmp &= ~0x0000007f;
tmp |= 0x00000020;
writel(tmp, SC_VPLL27BCTRL2);
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
/* AXO: 25MHz */
tmp = readl(SC_VPLL27ACTRL3);
tmp &= ~0x000fffff;
tmp |= 0x00066664;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp &= ~0x000fffff;
tmp |= 0x00066664;
writel(tmp, SC_VPLL27BCTRL3);
} else {
/* AXO: default 24.576MHz */
tmp = readl(SC_VPLL27ACTRL3);
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
writel(tmp, SC_VPLL27BCTRL3);
}
/* Set 1 to VPLA_K_LD and VPLB_K_LD */
tmp = readl(SC_VPLL27ACTRL3);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27BCTRL3);
/* wait 10 usec */
udelay(10);
/* Set 0 to VPLA_SNRST and VPLB_SNRST */
tmp = readl(SC_VPLL27ACTRL2);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27ACTRL2);
tmp = readl(SC_VPLL27BCTRL2);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27BCTRL2);
/* set 0 to VPLA27WP and VPLA27WP */
tmp = readl(SC_VPLL27ACTRL);
tmp &= ~0x00000001;
writel(tmp, SC_VPLL27ACTRL);
tmp = readl(SC_VPLL27BCTRL);
tmp |= ~0x00000001;
writel(tmp, SC_VPLL27BCTRL);
}
void pll_init(void)
{
dpll_init();
upll_init();
vpll_init();
/*
* Wait 500 usec until dpll get stable
* We wait 10 usec in upll_init() and vpll_init()
* so 20 usec can be saved here.
*/
udelay(480);
}

1
arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c Normal file
View file

@ -0,0 +1 @@
#include "../ph1-pro4/pll_spectrum.c"

44
arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c Normal file
View file

@ -0,0 +1,44 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sbc-regs.h>
#include <asm/arch/sg-regs.h>
void sbc_init(void)
{
/* XECS1: sub/boot memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
#if !defined(CONFIG_SPL_BUILD)
/* XECS0: boot/sub memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
#endif
/* XECS3: peripherals */
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
/* base address regsiters */
writel(0x0000bc01, SBBASE0);
writel(0x0400bc01, SBBASE1);
writel(0x0800bf01, SBBASE3);
#if !defined(CONFIG_SPL_BUILD)
/* enable access to sub memory when boot swap is on */
sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
#endif
sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
}

28
arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c Normal file
View file

@ -0,0 +1,28 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sg-regs.h>
void sg_init(void)
{
u32 tmp;
/* Set DDR size */
tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
tmp |= SG_MEMCONF_SPARSEMEM;
#endif
writel(tmp, SG_MEMCONF);
/* Input ports must be enabled deasserting reset of cores */
tmp = readl(SG_IECTRL);
tmp |= 0x1;
writel(tmp, SG_IECTRL);
}

162
arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c Normal file
View file

@ -0,0 +1,162 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/umc-regs.h>
static inline void umc_start_ssif(void __iomem *ssif_base)
{
writel(0x00000000, ssif_base + 0x0000b004);
writel(0xffffffff, ssif_base + 0x0000c004);
writel(0x000fffcf, ssif_base + 0x0000c008);
writel(0x00000001, ssif_base + 0x0000b000);
writel(0x00000001, ssif_base + 0x0000c000);
writel(0x03010101, ssif_base + UMC_MDMCHSEL);
writel(0x03010100, ssif_base + UMC_DMDCHSEL);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
writel(0x00000001, ssif_base + UMC_CPURST);
writel(0x00000001, ssif_base + UMC_IDSRST);
writel(0x00000001, ssif_base + UMC_IXMRST);
writel(0x00000001, ssif_base + UMC_MDMRST);
writel(0x00000001, ssif_base + UMC_MDDRST);
writel(0x00000001, ssif_base + UMC_SIORST);
writel(0x00000001, ssif_base + UMC_VIORST);
writel(0x00000001, ssif_base + UMC_FRCRST);
writel(0x00000001, ssif_base + UMC_RGLRST);
writel(0x00000001, ssif_base + UMC_AIORST);
writel(0x00000001, ssif_base + UMC_DMDRST);
}
void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
int size, int freq)
{
if (freq == 1333) {
writel(0x45990b11, dramcont + UMC_CMDCTLA);
writel(0x16958924, dramcont + UMC_CMDCTLB);
writel(0x5101046A, dramcont + UMC_INITCTLA);
if (size == 1)
writel(0x27028B0A, dramcont + UMC_INITCTLB);
else if (size == 2)
writel(0x38028B0A, dramcont + UMC_INITCTLB);
writel(0x000FF0FF, dramcont + UMC_INITCTLC);
writel(0x00000b51, dramcont + UMC_DRMMR0);
} else if (freq == 1600) {
writel(0x36BB0F17, dramcont + UMC_CMDCTLA);
writel(0x18C6AA24, dramcont + UMC_CMDCTLB);
writel(0x5101387F, dramcont + UMC_INITCTLA);
if (size == 1)
writel(0x2F030D3F, dramcont + UMC_INITCTLB);
else if (size == 2)
writel(0x43030D3F, dramcont + UMC_INITCTLB);
writel(0x00FF00FF, dramcont + UMC_INITCTLC);
writel(0x00000d71, dramcont + UMC_DRMMR0);
}
writel(0x00000006, dramcont + UMC_DRMMR1);
if (freq == 1333)
writel(0x00000290, dramcont + UMC_DRMMR2);
else if (freq == 1600)
writel(0x00000298, dramcont + UMC_DRMMR2);
writel(0x00000800, dramcont + UMC_DRMMR3);
if (freq == 1333) {
if (size == 1)
writel(0x00240512, dramcont + UMC_SPCCTLA);
else if (size == 2)
writel(0x00350512, dramcont + UMC_SPCCTLA);
writel(0x00ff0006, dramcont + UMC_SPCCTLB);
writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
} else if (freq == 1600) {
if (size == 1)
writel(0x002B0617, dramcont + UMC_SPCCTLA);
else if (size == 2)
writel(0x003F0617, dramcont + UMC_SPCCTLA);
writel(0x00ff0008, dramcont + UMC_SPCCTLB);
writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
}
writel(0x04060806, dramcont + UMC_WDATACTL_D0);
writel(0x04a02000, dramcont + UMC_DATASET);
writel(0x00000000, ca_base + 0x2300);
writel(0x00400020, dramcont + UMC_DCCGCTL);
writel(0x00000003, dramcont + 0x7000);
writel(0x0000000f, dramcont + 0x8000);
writel(0x000000c3, dramcont + 0x8004);
writel(0x00000071, dramcont + 0x8008);
writel(0x0000003b, dramcont + UMC_DICGCTLA);
writel(0x020a0808, dramcont + UMC_DICGCTLB);
writel(0x00000004, dramcont + UMC_FLOWCTLG);
writel(0x80000201, ca_base + 0xc20);
writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
writel(0x00200000, dramcont + UMC_FLOWCTLB);
writel(0x00004444, dramcont + UMC_FLOWCTLC);
writel(0x200a0a00, dramcont + UMC_SPCSETB);
writel(0x00000000, dramcont + UMC_SPCSETD);
writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
}
static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
{
void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
umc_dram_init_start(dramcont0);
umc_dram_init_start(dramcont1);
umc_dram_init_poll(dramcont0);
umc_dram_init_poll(dramcont1);
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
umc_start_ssif(ssif_base);
return 0;
}
int umc_init(void)
{
return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
CONFIG_SDRAM1_SIZE / 0x08000000);
}
#if CONFIG_DDR_FREQ != 1333 && CONFIG_DDR_FREQ != 1600
#error Unsupported DDR Frequency.
#endif
#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
(CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
/* OK */
#else
#error Unsupported DDR configuration.
#endif

10
arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile Normal file
View file

@ -0,0 +1,10 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-y += boot-mode.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \
sg_init.o pll_init.o clkrst_init.o pinctrl.o
obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \
umc_init.o

16
arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c Normal file
View file

@ -0,0 +1,16 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/board.h>
int checkboard(void)
{
puts("Board: PH1-Pro4 Board\n");
return check_support_card();
}

39
arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c Normal file
View file

@ -0,0 +1,39 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/led.h>
#include <asm/arch/board.h>
void sbc_init(void);
void sg_init(void);
void pll_init(void);
void pin_init(void);
void clkrst_init(void);
int board_postclk_init(void)
{
sbc_init();
sg_init();
pll_init();
uniphier_board_init();
led_write(B, 1, , );
clkrst_init();
led_write(B, 2, , );
pin_init();
led_write(B, 3, , );
return 0;
}

66
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c Normal file
View file

@ -0,0 +1,66 @@
/*
* Copyright (C) 2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/boot-device.h>
#include <asm/arch/sg-regs.h>
#include <asm/arch/sbc-regs.h>
struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI, Addr 5)"},
{BOOT_DEVICE_MMC1, "eMMC Boot (3.3V)"},
{BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, ""}
};
u32 get_boot_mode_sel(void)
{
return (readl(SG_PINMON0) >> 1) & 0x1f;
}
u32 spl_boot_device(void)
{
u32 boot_mode;
if (boot_is_swapped())
return BOOT_DEVICE_NOR;
boot_mode = get_boot_mode_sel();
return boot_device_table[boot_mode].type;
}

29
arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c Normal file
View file

@ -0,0 +1,29 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sc-regs.h>
void clkrst_init(void)
{
u32 tmp;
/* deassert reset */
tmp = readl(SC_RSTCTRL);
tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
| SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
writel(tmp, SC_RSTCTRL);
readl(SC_RSTCTRL); /* dummy read */
/* privide clocks */
tmp = readl(SC_CLKCTRL);
tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
| SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
writel(tmp, SC_CLKCTRL);
readl(SC_CLKCTRL); /* dummy read */
}

45
arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c Normal file
View file

@ -0,0 +1,45 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sg-regs.h>
void pin_init(void)
{
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_UNIPHIER_SERIAL
sg_set_pinsel(127, 0); /* RXD0 -> RXD0 */
sg_set_pinsel(128, 0); /* TXD0 -> TXD0 */
sg_set_pinsel(129, 0); /* RXD1 -> RXD1 */
sg_set_pinsel(130, 0); /* TXD1 -> TXD1 */
sg_set_pinsel(131, 0); /* RXD2 -> RXD2 */
sg_set_pinsel(132, 0); /* TXD2 -> TXD2 */
sg_set_pinsel(88, 2); /* CH6CLK -> RXD3 */
sg_set_pinsel(89, 2); /* CH6VAL -> TXD3 */
#endif
#ifdef CONFIG_NAND_DENALI
sg_set_pinsel(40, 0); /* NFD0 -> NFD0 */
sg_set_pinsel(41, 0); /* NFD1 -> NFD1 */
sg_set_pinsel(42, 0); /* NFD2 -> NFD2 */
sg_set_pinsel(43, 0); /* NFD3 -> NFD3 */
sg_set_pinsel(44, 0); /* NFD4 -> NFD4 */
sg_set_pinsel(45, 0); /* NFD5 -> NFD5 */
sg_set_pinsel(46, 0); /* NFD6 -> NFD6 */
sg_set_pinsel(47, 0); /* NFD7 -> NFD7 */
sg_set_pinsel(48, 0); /* NFALE -> NFALE */
sg_set_pinsel(49, 0); /* NFCLE -> NFCLE */
sg_set_pinsel(50, 0); /* XNFRE -> XNFRE */
sg_set_pinsel(51, 0); /* XNFWE -> XNFWE */
sg_set_pinsel(52, 0); /* XNFWP -> XNFWP */
sg_set_pinsel(53, 0); /* XNFCE0 -> XNFCE0 */
sg_set_pinsel(54, 0); /* NRYBY0 -> NRYBY0 */
#endif
writel(1, SG_LOADPINCTRL);
}

168
arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c Normal file
View file

@ -0,0 +1,168 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sc-regs.h>
#include <asm/arch/sg-regs.h>
#undef DPLL_SSC_RATE_1PER
void dpll_init(void)
{
u32 tmp;
/*
* Set Frequency
* Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
* to FOUT ( DPLLCTRL.bit[29:20] )
*/
tmp = readl(SC_DPLLCTRL);
tmp &= ~(0x000f0000);
#if CONFIG_DDR_FREQ == 1600
tmp |= 0x000c0000;
#elif CONFIG_DDR_FREQ == 1333
tmp |= 0x000d0000;
#else
# error "Unsupported frequency"
#endif
/*
* Set Moduration rate
* Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
*/
#if defined(DPLL_SSC_RATE_1PER)
tmp &= ~0x00008000;
#else
tmp |= 0x00008000;
#endif
writel(tmp, SC_DPLLCTRL);
tmp = readl(SC_DPLLCTRL2);
tmp |= SC_DPLLCTRL2_NRSTDS;
writel(tmp, SC_DPLLCTRL2);
}
void stop_mpll(void)
{
u32 tmp;
tmp = readl(SC_MPLLOSCCTL);
if (!(tmp & SC_MPLLOSCCTL_MPLLST))
return; /* already stopped */
tmp &= ~SC_MPLLOSCCTL_MPLLEN;
writel(tmp, SC_MPLLOSCCTL);
while (readl(SC_MPLLOSCCTL) & SC_MPLLOSCCTL_MPLLST)
;
}
void vpll_init(void)
{
u32 tmp, clk_mode_axosel;
/* Set VPLL27A & VPLL27B */
tmp = readl(SG_PINMON0);
clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
#if defined(CONFIG_MACH_PH1_PRO4)
/* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
return;
#endif
/* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
tmp = readl(SC_VPLL27ACTRL);
tmp |= 0x00000001;
writel(tmp, SC_VPLL27ACTRL);
tmp = readl(SC_VPLL27BCTRL);
tmp |= 0x00000001;
writel(tmp, SC_VPLL27BCTRL);
/* Unset VPLA_K_LD and VPLB_K_LD bit */
tmp = readl(SC_VPLL27ACTRL3);
tmp &= ~0x10000000;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp &= ~0x10000000;
writel(tmp, SC_VPLL27BCTRL3);
/* Set VPLA_M and VPLB_M to 0x20 */
tmp = readl(SC_VPLL27ACTRL2);
tmp &= ~0x0000007f;
tmp |= 0x00000020;
writel(tmp, SC_VPLL27ACTRL2);
tmp = readl(SC_VPLL27BCTRL2);
tmp &= ~0x0000007f;
tmp |= 0x00000020;
writel(tmp, SC_VPLL27BCTRL2);
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
/* Set VPLA_K and VPLB_K for AXO: 25MHz */
tmp = readl(SC_VPLL27ACTRL3);
tmp &= ~0x000fffff;
tmp |= 0x00066666;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp &= ~0x000fffff;
tmp |= 0x00066666;
writel(tmp, SC_VPLL27BCTRL3);
} else {
/* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
tmp = readl(SC_VPLL27ACTRL3);
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
writel(tmp, SC_VPLL27BCTRL3);
}
/* wait 1 usec */
udelay(1);
/* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
tmp = readl(SC_VPLL27ACTRL3);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27BCTRL3);
/* Unset VPLA_SNRST and VPLB_SNRST bit */
tmp = readl(SC_VPLL27ACTRL2);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27ACTRL2);
tmp = readl(SC_VPLL27BCTRL2);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27BCTRL2);
/* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
tmp = readl(SC_VPLL27ACTRL);
tmp &= ~0x00000001;
writel(tmp, SC_VPLL27ACTRL);
tmp = readl(SC_VPLL27BCTRL);
tmp &= ~0x00000001;
writel(tmp, SC_VPLL27BCTRL);
}
void pll_init(void)
{
dpll_init();
stop_mpll();
vpll_init();
/*
* Wait 500 usec until dpll get stable
* We wait 1 usec in vpll_init() so 1 usec can be saved here.
*/
udelay(499);
}

18
arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c Normal file
View file

@ -0,0 +1,18 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sc-regs.h>
void enable_dpll_ssc(void)
{
u32 tmp;
tmp = readl(SC_DPLLCTRL);
tmp |= SC_DPLLCTRL_SSC_EN;
writel(tmp, SC_DPLLCTRL);
}

75
arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c Normal file
View file

@ -0,0 +1,75 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sbc-regs.h>
#include <asm/arch/sg-regs.h>
void sbc_init(void)
{
#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
/*
* Only CS1 is connected to support card.
* BKSZ[1:0] should be set to "01".
*/
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
if (readl(SBBASE0) & 0x1) {
/*
* Boot Swap Off: boot from mask ROM
* 0x00000000-0x01ffffff: mask ROM
* 0x02000000-0x3effffff: memory bank (31MB)
* 0x03f00000-0x3fffffff: peripherals (1MB)
*/
writel(0x0000be01, SBBASE0); /* dummy */
writel(0x0200be01, SBBASE1);
} else {
/*
* Boot Swap On: boot from external NOR/SRAM
* 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
*
* 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
* 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
*/
writel(0x0000bc01, SBBASE0);
}
#elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
#if !defined(CONFIG_SPL_BUILD)
/* XECS0: boot/sub memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
#endif
/* XECS1: sub/boot memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
/* XECS3: peripherals */
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
writel(0x0000bc01, SBBASE0); /* boot memory */
writel(0x0400bc01, SBBASE1); /* sub memory */
writel(0x0800bf01, SBBASE3); /* peripherals */
#if !defined(CONFIG_SPL_BUILD)
sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
#endif
sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
writel(0x00000001, SG_LOADPINCTRL);
#endif /* CONFIG_XXX_MICRO_SUPPORT_CARD */
}

28
arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c Normal file
View file

@ -0,0 +1,28 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sg-regs.h>
void sg_init(void)
{
u32 tmp;
/* Set DDR size */
tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
tmp |= SG_MEMCONF_SPARSEMEM;
#endif
writel(tmp, SG_MEMCONF);
/* Input ports must be enabled deasserting reset of cores */
tmp = readl(SG_IECTRL);
tmp |= 0x1;
writel(tmp, SG_IECTRL);
}

136
arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c Normal file
View file

@ -0,0 +1,136 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/umc-regs.h>
static inline void umc_start_ssif(void __iomem *ssif_base)
{
writel(0x00000001, ssif_base + 0x0000b004);
writel(0xffffffff, ssif_base + 0x0000c004);
writel(0x07ffffff, ssif_base + 0x0000c008);
writel(0x00000001, ssif_base + 0x0000b000);
writel(0x00000001, ssif_base + 0x0000c000);
writel(0x03010100, ssif_base + UMC_HDMCHSEL);
writel(0x03010101, ssif_base + UMC_MDMCHSEL);
writel(0x03010100, ssif_base + UMC_DVCCHSEL);
writel(0x03010100, ssif_base + UMC_DMDCHSEL);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
writel(0x00000000, ssif_base + 0x0000c044); /* DCGIV_SSIF_REG */
writel(0x00000001, ssif_base + UMC_CPURST);
writel(0x00000001, ssif_base + UMC_IDSRST);
writel(0x00000001, ssif_base + UMC_IXMRST);
writel(0x00000001, ssif_base + UMC_HDMRST);
writel(0x00000001, ssif_base + UMC_MDMRST);
writel(0x00000001, ssif_base + UMC_HDDRST);
writel(0x00000001, ssif_base + UMC_MDDRST);
writel(0x00000001, ssif_base + UMC_SIORST);
writel(0x00000001, ssif_base + UMC_GIORST);
writel(0x00000001, ssif_base + UMC_HD2RST);
writel(0x00000001, ssif_base + UMC_VIORST);
writel(0x00000001, ssif_base + UMC_DVCRST);
writel(0x00000001, ssif_base + UMC_RGLRST);
writel(0x00000001, ssif_base + UMC_VPERST);
writel(0x00000001, ssif_base + UMC_AIORST);
writel(0x00000001, ssif_base + UMC_DMDRST);
}
void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
int size, int freq)
{
writel(0x66bb0f17, dramcont + UMC_CMDCTLA);
writel(0x18c6aa44, dramcont + UMC_CMDCTLB);
writel(0x5101387f, dramcont + UMC_INITCTLA);
writel(0x43030d3f, dramcont + UMC_INITCTLB);
writel(0x00ff00ff, dramcont + UMC_INITCTLC);
writel(0x00000d71, dramcont + UMC_DRMMR0);
writel(0x00000006, dramcont + UMC_DRMMR1);
writel(0x00000298, dramcont + UMC_DRMMR2);
writel(0x00000000, dramcont + UMC_DRMMR3);
writel(0x003f0617, dramcont + UMC_SPCCTLA);
writel(0x00ff0008, dramcont + UMC_SPCCTLB);
writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
writel(0x000c00ae, dramcont + UMC_RDATACTL_D1);
writel(0x04060802, dramcont + UMC_WDATACTL_D0);
writel(0x04060802, dramcont + UMC_WDATACTL_D1);
writel(0x04a02000, dramcont + UMC_DATASET);
writel(0x00000000, ca_base + 0x2300);
writel(0x00400020, dramcont + UMC_DCCGCTL);
writel(0x0000000f, dramcont + 0x7000);
writel(0x0000000f, dramcont + 0x8000);
writel(0x000000c3, dramcont + 0x8004);
writel(0x00000071, dramcont + 0x8008);
writel(0x00000004, dramcont + UMC_FLOWCTLG);
writel(0x00000000, dramcont + 0x0060);
writel(0x80000201, ca_base + 0xc20);
writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
writel(0x00200000, dramcont + UMC_FLOWCTLB);
writel(0x00004444, dramcont + UMC_FLOWCTLC);
writel(0x200a0a00, dramcont + UMC_SPCSETB);
writel(0x00010000, dramcont + UMC_SPCSETD);
writel(0x80000020, dramcont + UMC_DFICUPDCTLA);
}
static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
{
void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
umc_dram_init_start(dramcont0);
umc_dram_init_start(dramcont1);
umc_dram_init_poll(dramcont0);
umc_dram_init_poll(dramcont1);
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
writel(0x00000103, dramcont0 + UMC_DIOCTLA);
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
writel(0x00000103, dramcont1 + UMC_DIOCTLA);
umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
umc_start_ssif(ssif_base);
return 0;
}
int umc_init(void)
{
return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
CONFIG_SDRAM1_SIZE / 0x08000000);
}
#if CONFIG_DDR_FREQ != 1600
#error Unsupported DDR frequency.
#endif
#if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \
(CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \
((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \
(CONFIG_SDRAM1_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH1 == 1))
/* OK */
#else
#error Unsupported DDR configuration.
#endif

10
arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile Normal file
View file

@ -0,0 +1,10 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-y += boot-mode.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \
umc_init.o

1
arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c Normal file
View file

@ -0,0 +1 @@
#include "../ph1-ld4/bcu_init.c"

16
arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c Normal file
View file

@ -0,0 +1,16 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/board.h>
int checkboard(void)
{
puts("Board: PH1-sLD8 Board\n");
return check_support_card();
}

1
arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c Normal file
View file

@ -0,0 +1 @@
#include "../ph1-ld4/board_postclk_init.c"

1
arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c Normal file
View file

@ -0,0 +1 @@
#include "../ph1-pro4/boot-mode.c"

29
arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c Normal file
View file

@ -0,0 +1,29 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sc-regs.h>
void clkrst_init(void)
{
u32 tmp;
/* deassert reset */
tmp = readl(SC_RSTCTRL);
tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
| SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
writel(tmp, SC_RSTCTRL);
readl(SC_RSTCTRL); /* dummy read */
/* privide clocks */
tmp = readl(SC_CLKCTRL);
tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
| SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
writel(tmp, SC_CLKCTRL);
readl(SC_CLKCTRL); /* dummy read */
}

57
arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c Normal file
View file

@ -0,0 +1,57 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sg-regs.h>
void pin_init(void)
{
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_UNIPHIER_SERIAL
sg_set_pinsel(70, 3); /* HDDOUT0 -> TXD0 */
sg_set_pinsel(71, 3); /* HSDOUT1 -> RXD0 */
sg_set_pinsel(114, 0); /* TXD1 -> TXD1 */
sg_set_pinsel(115, 0); /* RXD1 -> RXD1 */
sg_set_pinsel(112, 1); /* SBO1 -> TXD2 */
sg_set_pinsel(113, 1); /* SBI1 -> RXD2 */
sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */
sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */
#endif
#ifdef CONFIG_NAND_DENALI
sg_set_pinsel(15, 0); /* XNFRE_GB -> XNFRE_GB */
sg_set_pinsel(16, 0); /* XNFWE_GB -> XNFWE_GB */
sg_set_pinsel(17, 0); /* XFALE_GB -> NFALE_GB */
sg_set_pinsel(18, 0); /* XFCLE_GB -> NFCLE_GB */
sg_set_pinsel(19, 0); /* XNFWP_GB -> XFNWP_GB */
sg_set_pinsel(20, 0); /* XNFCE0_GB -> XNFCE0_GB */
sg_set_pinsel(21, 0); /* NANDRYBY0_GB -> NANDRYBY0_GB */
sg_set_pinsel(22, 0); /* XFNCE1_GB -> XFNCE1_GB */
sg_set_pinsel(23, 0); /* NANDRYBY1_GB -> NANDRYBY1_GB */
sg_set_pinsel(24, 0); /* NFD0_GB -> NFD0_GB */
sg_set_pinsel(25, 0); /* NFD1_GB -> NFD1_GB */
sg_set_pinsel(26, 0); /* NFD2_GB -> NFD2_GB */
sg_set_pinsel(27, 0); /* NFD3_GB -> NFD3_GB */
sg_set_pinsel(28, 0); /* NFD4_GB -> NFD4_GB */
sg_set_pinsel(29, 0); /* NFD5_GB -> NFD5_GB */
sg_set_pinsel(30, 0); /* NFD6_GB -> NFD6_GB */
sg_set_pinsel(31, 0); /* NFD7_GB -> NFD7_GB */
#endif
#ifdef CONFIG_USB_EHCI_UNIPHIER
sg_set_pinsel(41, 0); /* USB0VBUS -> USB0VBUS */
sg_set_pinsel(42, 0); /* USB0OD -> USB0OD */
sg_set_pinsel(43, 0); /* USB1VBUS -> USB1VBUS */
sg_set_pinsel(44, 0); /* USB1OD -> USB1OD */
/* sg_set_pinsel(114, 4); */ /* TXD1 -> USB2VBUS (shared with UART) */
/* sg_set_pinsel(115, 4); */ /* RXD1 -> USB2OD */
#endif
}

201
arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c Normal file
View file

@ -0,0 +1,201 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sc-regs.h>
#include <asm/arch/sg-regs.h>
void dpll_init(void)
{
u32 tmp;
/*
* Set DPLL SSC parameters for DPLLCTRL3
* [23] DIVN_TEST 0x1
* [22:16] DIVN 0x50
* [10] FREFSEL_TEST 0x1
* [9:8] FREFSEL 0x2
* [4] ICPD_TEST 0x1
* [3:0] ICPD 0xb
*/
tmp = readl(SC_DPLLCTRL3);
tmp &= ~0x00ff0717;
tmp |= 0x00d0061b;
writel(tmp, SC_DPLLCTRL3);
/*
* Set DPLL SSC parameters for DPLLCTRL
* <-1%> <-2%>
* [29:20] SSC_UPCNT 132 (0x084) 132 (0x084)
* [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6)
*/
tmp = readl(SC_DPLLCTRL);
tmp &= ~0x3ff07fff;
#ifdef CONFIG_DPLL_SSC_RATE_1PER
tmp |= 0x084018bf;
#else
tmp |= 0x084031a6;
#endif
writel(tmp, SC_DPLLCTRL);
/*
* Set DPLL SSC parameters for DPLLCTRL2
* [31:29] SSC_STEP 0
* [27] SSC_REG_REF 1
* [26:20] SSC_M 79 (0x4f)
* [19:0] SSC_K 964689 (0xeb851)
*/
tmp = readl(SC_DPLLCTRL2);
tmp &= ~0xefffffff;
tmp |= 0x0cfeb851;
writel(tmp, SC_DPLLCTRL2);
}
void upll_init(void)
{
u32 tmp, clk_mode_upll, clk_mode_axosel;
tmp = readl(SG_PINMON0);
clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
tmp = readl(SC_UPLLCTRL);
tmp &= ~0x18000000;
writel(tmp, SC_UPLLCTRL);
if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
/* AXO: 25MHz */
tmp &= ~0x07ffffff;
tmp |= 0x0228f5c0;
} else {
/* AXO: default 24.576MHz */
tmp &= ~0x07ffffff;
tmp |= 0x02328000;
}
}
writel(tmp, SC_UPLLCTRL);
/* set 1 to K_LD(UPLLCTRL.bit[27]) */
tmp |= 0x08000000;
writel(tmp, SC_UPLLCTRL);
/* wait 10 usec */
udelay(10);
/* set 1 to SNRT(UPLLCTRL.bit[28]) */
tmp |= 0x10000000;
writel(tmp, SC_UPLLCTRL);
}
void vpll_init(void)
{
u32 tmp, clk_mode_axosel;
tmp = readl(SG_PINMON0);
clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
/* set 1 to VPLA27WP and VPLA27WP */
tmp = readl(SC_VPLL27ACTRL);
tmp |= 0x00000001;
writel(tmp, SC_VPLL27ACTRL);
tmp = readl(SC_VPLL27BCTRL);
tmp |= 0x00000001;
writel(tmp, SC_VPLL27BCTRL);
/* Set 0 to VPLA_K_LD and VPLB_K_LD */
tmp = readl(SC_VPLL27ACTRL3);
tmp &= ~0x10000000;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp &= ~0x10000000;
writel(tmp, SC_VPLL27BCTRL3);
/* Set 0 to VPLA_SNRST and VPLB_SNRST */
tmp = readl(SC_VPLL27ACTRL2);
tmp &= ~0x10000000;
writel(tmp, SC_VPLL27ACTRL2);
tmp = readl(SC_VPLL27BCTRL2);
tmp &= ~0x10000000;
writel(tmp, SC_VPLL27BCTRL2);
/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
tmp = readl(SC_VPLL27ACTRL2);
tmp &= ~0x0000007f;
tmp |= 0x00000020;
writel(tmp, SC_VPLL27ACTRL2);
tmp = readl(SC_VPLL27BCTRL2);
tmp &= ~0x0000007f;
tmp |= 0x00000020;
writel(tmp, SC_VPLL27BCTRL2);
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
/* AXO: 25MHz */
tmp = readl(SC_VPLL27ACTRL3);
tmp &= ~0x000fffff;
tmp |= 0x00066664;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp &= ~0x000fffff;
tmp |= 0x00066664;
writel(tmp, SC_VPLL27BCTRL3);
} else {
/* AXO: default 24.576MHz */
tmp = readl(SC_VPLL27ACTRL3);
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
writel(tmp, SC_VPLL27BCTRL3);
}
/* Set 1 to VPLA_K_LD and VPLB_K_LD */
tmp = readl(SC_VPLL27ACTRL3);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27BCTRL3);
/* wait 10 usec */
udelay(10);
/* Set 0 to VPLA_SNRST and VPLB_SNRST */
tmp = readl(SC_VPLL27ACTRL2);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27ACTRL2);
tmp = readl(SC_VPLL27BCTRL2);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27BCTRL2);
/* set 0 to VPLA27WP and VPLA27WP */
tmp = readl(SC_VPLL27ACTRL);
tmp &= ~0x00000001;
writel(tmp, SC_VPLL27ACTRL);
tmp = readl(SC_VPLL27BCTRL);
tmp |= ~0x00000001;
writel(tmp, SC_VPLL27BCTRL);
}
void pll_init(void)
{
dpll_init();
upll_init();
vpll_init();
/*
* Wait 500 usec until dpll get stable
* We wait 10 usec in upll_init() and vpll_init()
* so 20 usec can be saved here.
*/
udelay(480);
}

1
arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c Normal file
View file

@ -0,0 +1 @@
#include "../ph1-ld4/pll_spectrum.c"

51
arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c Normal file
View file

@ -0,0 +1,51 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sbc-regs.h>
#include <asm/arch/sg-regs.h>
void sbc_init(void)
{
#if !defined(CONFIG_SPL_BUILD)
/* XECS0 : dummy */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
#endif
/* XECS1 : boot memory (always boot swap = on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
/* XECS4 : sub memory */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
/* XECS5 : peripherals */
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
/* base address regsiters */
writel(0x0000bc01, SBBASE0); /* boot memory */
writel(0x0900bfff, SBBASE1); /* dummy */
writel(0x0400bc01, SBBASE4); /* sub memory */
writel(0x0800bf01, SBBASE5); /* peripherals */
sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
/* dummy read to assure write process */
readl(SG_PINCTRL(33));
}

1
arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c Normal file
View file

@ -0,0 +1 @@
#include "../ph1-ld4/sg_init.c"

142
arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c Normal file
View file

@ -0,0 +1,142 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/umc-regs.h>
static inline void umc_start_ssif(void __iomem *ssif_base)
{
writel(0x00000000, ssif_base + 0x0000b004);
writel(0xffffffff, ssif_base + 0x0000c004);
writel(0x000fffcf, ssif_base + 0x0000c008);
writel(0x00000001, ssif_base + 0x0000b000);
writel(0x00000001, ssif_base + 0x0000c000);
writel(0x03010101, ssif_base + UMC_MDMCHSEL);
writel(0x03010100, ssif_base + UMC_DMDCHSEL);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
writel(0x00000001, ssif_base + UMC_CPURST);
writel(0x00000001, ssif_base + UMC_IDSRST);
writel(0x00000001, ssif_base + UMC_IXMRST);
writel(0x00000001, ssif_base + UMC_MDMRST);
writel(0x00000001, ssif_base + UMC_MDDRST);
writel(0x00000001, ssif_base + UMC_SIORST);
writel(0x00000001, ssif_base + UMC_VIORST);
writel(0x00000001, ssif_base + UMC_FRCRST);
writel(0x00000001, ssif_base + UMC_RGLRST);
writel(0x00000001, ssif_base + UMC_AIORST);
writel(0x00000001, ssif_base + UMC_DMDRST);
}
void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
int size, int freq)
{
#ifdef CONFIG_DDR_STANDARD
writel(0x55990b11, dramcont + UMC_CMDCTLA);
writel(0x16958944, dramcont + UMC_CMDCTLB);
#else
writel(0x45990b11, dramcont + UMC_CMDCTLA);
writel(0x16958924, dramcont + UMC_CMDCTLB);
#endif
writel(0x5101046A, dramcont + UMC_INITCTLA);
if (size == 1)
writel(0x27028B0A, dramcont + UMC_INITCTLB);
else if (size == 2)
writel(0x38028B0A, dramcont + UMC_INITCTLB);
writel(0x00FF00FF, dramcont + UMC_INITCTLC);
writel(0x00000b51, dramcont + UMC_DRMMR0);
writel(0x00000006, dramcont + UMC_DRMMR1);
writel(0x00000290, dramcont + UMC_DRMMR2);
#ifdef CONFIG_DDR_STANDARD
writel(0x00000000, dramcont + UMC_DRMMR3);
#else
writel(0x00000800, dramcont + UMC_DRMMR3);
#endif
if (size == 1)
writel(0x00240512, dramcont + UMC_SPCCTLA);
else if (size == 2)
writel(0x00350512, dramcont + UMC_SPCCTLA);
writel(0x00ff0006, dramcont + UMC_SPCCTLB);
writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
writel(0x04060806, dramcont + UMC_WDATACTL_D0);
writel(0x04a02000, dramcont + UMC_DATASET);
writel(0x00000000, ca_base + 0x2300);
writel(0x00400020, dramcont + UMC_DCCGCTL);
writel(0x00000003, dramcont + 0x7000);
writel(0x0000004f, dramcont + 0x8000);
writel(0x000000c3, dramcont + 0x8004);
writel(0x00000077, dramcont + 0x8008);
writel(0x0000003b, dramcont + UMC_DICGCTLA);
writel(0x020a0808, dramcont + UMC_DICGCTLB);
writel(0x00000004, dramcont + UMC_FLOWCTLG);
writel(0x80000201, ca_base + 0xc20);
writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
writel(0x00200000, dramcont + UMC_FLOWCTLB);
writel(0x00004444, dramcont + UMC_FLOWCTLC);
writel(0x200a0a00, dramcont + UMC_SPCSETB);
writel(0x00000000, dramcont + UMC_SPCSETD);
writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
}
static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
{
void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
umc_dram_init_start(dramcont0);
umc_dram_init_start(dramcont1);
umc_dram_init_poll(dramcont0);
umc_dram_init_poll(dramcont1);
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
umc_start_ssif(ssif_base);
return 0;
}
int umc_init(void)
{
return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
CONFIG_SDRAM1_SIZE / 0x08000000);
}
#if CONFIG_DDR_FREQ != 1333
#error Unsupported DDR frequency.
#endif
#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
(CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
/* OK */
#else
#error Unsupported DDR configuration.
#endif

29
arch/arm/cpu/armv7/uniphier/reset.c Normal file
View file

@ -0,0 +1,29 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sc-regs.h>
#include <asm/arch/board.h>
void reset_cpu(unsigned long ignored)
{
u32 tmp;
uniphier_board_reset();
writel(5, SC_IRQTIMSET); /* default value */
tmp = readl(SC_SLFRSTSEL);
tmp &= ~0x3; /* mask [1:0] */
tmp |= 0x0; /* XRST reboot */
writel(tmp, SC_SLFRSTSEL);
tmp = readl(SC_SLFRSTCTL);
tmp |= 0x1;
writel(tmp, SC_SLFRSTCTL);
}

54
arch/arm/cpu/armv7/uniphier/smp.S Normal file
View file

@ -0,0 +1,54 @@
/*
* Copyright (C) 2013 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/system.h>
#include <asm/arch/led.h>
#include <asm/arch/sbc-regs.h>
/* Entry point of U-Boot main program for the secondary CPU */
LENTRY(secondary_entry)
mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
bic r0, r0, #(CR_C | CR_M) @ MMU and Dcache disable
mcr p15, 0, r0, c1, c0, 0
mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
dsb
led_write(C,0,,)
ldr r1, =ROM_BOOT_ROMRSV2
mov r0, #0
str r0, [r1]
0: wfe
ldr r4, [r1] @ r4: entry point for secondary CPUs
cmp r4, #0
beq 0b
led_write(C, P, U, 1)
bx r4 @ secondary CPUs jump to linux
ENDPROC(secondary_entry)
ENTRY(wakeup_secondary)
ldr r1, =ROM_BOOT_ROMRSV2
0: ldr r0, [r1]
cmp r0, #0
bne 0b
/* set entry address and send event to the secondary CPU */
ldr r0, =secondary_entry
str r0, [r1]
ldr r0, [r1] @ make sure store is complete
mov r0, #0x100
0: subs r0, r0, #1 @ I don't know the reason, but without this wait
bne 0b @ fails to wake up the secondary CPU
sev
/* wait until the secondary CPU reach to secondary_entry */
0: ldr r0, [r1]
cmp r0, #0
bne 0b
bx lr
ENDPROC(wakeup_secondary)

17
arch/arm/cpu/armv7/uniphier/spl.c Normal file
View file

@ -0,0 +1,17 @@
/*
* Copyright (C) 2013-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
void spl_board_init(void)
{
#if defined(CONFIG_BOARD_POSTCLK_INIT)
board_postclk_init();
#endif
dram_init();
}

180
arch/arm/cpu/armv7/uniphier/support_card.c Normal file
View file

@ -0,0 +1,180 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/board.h>
#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
#define PFC_MICRO_SUPPORT_CARD_RESET \
((CONFIG_SUPPORT_CARD_BASE) + 0x000D0034)
#define PFC_MICRO_SUPPORT_CARD_REVISION \
((CONFIG_SUPPORT_CARD_BASE) + 0x000D00E0)
/*
* 0: reset deassert, 1: reset
*
* bit[0]: LAN, I2C, LED
* bit[1]: UART
*/
void support_card_reset_deassert(void)
{
writel(0, PFC_MICRO_SUPPORT_CARD_RESET);
}
void support_card_reset(void)
{
writel(3, PFC_MICRO_SUPPORT_CARD_RESET);
}
static int support_card_show_revision(void)
{
u32 revision;
revision = readl(PFC_MICRO_SUPPORT_CARD_REVISION);
printf("(PFC CPLD version %d.%d)\n", revision >> 4, revision & 0xf);
return 0;
}
#endif
#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
#define DCC_MICRO_SUPPORT_CARD_RESET_LAN \
((CONFIG_SUPPORT_CARD_BASE) + 0x00401300)
#define DCC_MICRO_SUPPORT_CARD_RESET_UART \
((CONFIG_SUPPORT_CARD_BASE) + 0x00401304)
#define DCC_MICRO_SUPPORT_CARD_RESET_I2C \
((CONFIG_SUPPORT_CARD_BASE) + 0x00401308)
#define DCC_MICRO_SUPPORT_CARD_REVISION \
((CONFIG_SUPPORT_CARD_BASE) + 0x005000E0)
void support_card_reset_deassert(void)
{
writel(1, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */
writel(1, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */
writel(1, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */
}
void support_card_reset(void)
{
writel(0, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */
writel(0, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */
writel(0, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */
}
static int support_card_show_revision(void)
{
u32 revision;
revision = readl(DCC_MICRO_SUPPORT_CARD_REVISION);
if (revision >= 0x67) {
printf("(DCC CPLD version 3.%d.%d)\n",
revision >> 4, revision & 0xf);
return 0;
} else {
printf("(DCC CPLD unknown version)\n");
return -1;
}
}
#endif
void support_card_init(void)
{
/*
* After power on, we need to keep the LAN controller in reset state
* for a while. (200 usec)
* Fortunatelly, enough wait time is already inserted in pll_init()
* function. So we do not have to wait here.
*/
support_card_reset_deassert();
}
int check_support_card(void)
{
printf("SC: Micro Support Card ");
return support_card_show_revision();
}
#if defined(CONFIG_SMC911X)
#include <netdev.h>
int board_eth_init(bd_t *bis)
{
return smc911x_initialize(0, CONFIG_SMC911X_BASE);
}
#endif
#if !defined(CONFIG_SYS_NO_FLASH)
#include <mtd/cfi_flash.h>
#if CONFIG_SYS_MAX_FLASH_BANKS > 1
static phys_addr_t flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS] =
CONFIG_SYS_FLASH_BANKS_LIST;
phys_addr_t cfi_flash_bank_addr(int i)
{
return flash_banks_list[i];
}
#endif
int mem_is_flash(phys_addr_t base)
{
const int loop = 128;
u32 *scratch_addr;
u32 saved_value;
int ret = 1;
int i;
scratch_addr = map_physmem(base + 0x01e00000,
sizeof(u32) * loop, MAP_NOCACHE);
for (i = 0; i < loop; i++, scratch_addr++) {
saved_value = readl(scratch_addr);
writel(~saved_value, scratch_addr);
if (readl(scratch_addr) != saved_value) {
/* We assume no memory or SRAM here. */
writel(saved_value, scratch_addr);
ret = 0;
break;
}
}
unmap_physmem(scratch_addr, MAP_NOCACHE);
return ret;
}
int board_flash_wp_on(void)
{
int i;
int ret = 1;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
if (mem_is_flash(cfi_flash_bank_addr(i))) {
/*
* We found at least one flash.
* We need to return 0 and call flash_init().
*/
ret = 0;
}
#if CONFIG_SYS_MAX_FLASH_BANKS > 1
else {
/*
* We might have a SRAM here.
* To prevent SRAM data from being destroyed,
* we set dummy address (SDRAM).
*/
flash_banks_list[i] = 0x80000000 + 0x10000 * i;
}
#endif
}
return ret;
}
#endif

39
arch/arm/cpu/armv7/uniphier/timer.c Normal file
View file

@ -0,0 +1,39 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/arm-mpcore.h>
#define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */
#define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1)
static void *get_global_timer_base(void)
{
void *val;
asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (val) : : "memory");
return val + GLOBAL_TIMER_OFFSET;
}
unsigned long timer_read_counter(void)
{
/*
* ARM 64bit Global Timer is too much for our purpose.
* We use only lower 32 bit of the timer counter.
*/
return readl(get_global_timer_base() + GTIMER_CNT_L);
}
int timer_init(void)
{
/* enable timer */
writel(PRESCALER << 8 | 1, get_global_timer_base() + GTIMER_CTRL);
return 0;
}

6
arch/arm/cpu/armv8/Kconfig Normal file
View file

@ -0,0 +1,6 @@
if ARM64
config SYS_CPU
default "armv8"
endif

2
arch/arm/cpu/armv8/fsl-lsch3/Makefile
View file

@ -7,3 +7,5 @@
obj-y += cpu.o
obj-y += lowlevel.o
obj-y += speed.o
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o

13
arch/arm/cpu/armv8/fsl-lsch3/cpu.c
View file

@ -11,6 +11,7 @@
#include <asm/io.h>
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
#include "cpu.h"
#include "mp.h"
#include "speed.h"
#include <fsl_mc.h>
@ -434,3 +435,15 @@ int cpu_eth_init(bd_t *bis)
#endif
return error;
}
int arch_early_init_r(void)
{
int rv;
rv = fsl_lsch3_wake_seconday_cores();
if (rv)
printf("Did not wake secondary cores\n");
return 0;
}

1
arch/arm/cpu/armv8/fsl-lsch3/cpu.h
View file

@ -5,3 +5,4 @@
*/
int fsl_qoriq_core_to_cluster(unsigned int core);
u32 cpu_mask(void);

58
arch/arm/cpu/armv8/fsl-lsch3/fdt.c Normal file
View file

@ -0,0 +1,58 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <libfdt.h>
#include <fdt_support.h>
#include "mp.h"
#ifdef CONFIG_MP
void ft_fixup_cpu(void *blob)
{
int off;
__maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr();
fdt32_t *reg;
int addr_cells;
u64 val;
size_t *boot_code_size = &(__secondary_boot_code_size);
off = fdt_path_offset(blob, "/cpus");
if (off < 0) {
puts("couldn't find /cpus node\n");
return;
}
of_bus_default_count_cells(blob, off, &addr_cells, NULL);
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
while (off != -FDT_ERR_NOTFOUND) {
reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
if (reg) {
val = spin_tbl_addr;
val += id_to_core(of_read_number(reg, addr_cells))
* SPIN_TABLE_ELEM_SIZE;
val = cpu_to_fdt64(val);
fdt_setprop_string(blob, off, "enable-method",
"spin-table");
fdt_setprop(blob, off, "cpu-release-addr",
&val, sizeof(val));
} else {
puts("Warning: found cpu node without reg property\n");
}
off = fdt_node_offset_by_prop_value(blob, off, "device_type",
"cpu", 4);
}
fdt_add_mem_rsv(blob, (uintptr_t)&secondary_boot_code,
*boot_code_size);
}
#endif
void ft_cpu_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_MP
ft_fixup_cpu(blob);
#endif
}

131
arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
View file

@ -8,7 +8,9 @@
#include <config.h>
#include <linux/linkage.h>
#include <asm/gic.h>
#include <asm/macro.h>
#include "mp.h"
ENTRY(lowlevel_init)
mov x29, lr /* Save LR */
@ -35,31 +37,114 @@ ENTRY(lowlevel_init)
#endif
#endif
branch_if_master x0, x1, 1f
branch_if_master x0, x1, 2f
/*
* Slave should wait for master clearing spin table.
* This sync prevent salves observing incorrect
* value of spin table and jumping to wrong place.
*/
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
#ifdef CONFIG_GICV2
ldr x0, =GICC_BASE
#endif
bl gic_wait_for_interrupt
#endif
/*
* All processors will enter EL2 and optionally EL1.
*/
bl armv8_switch_to_el2
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
bl armv8_switch_to_el1
#endif
b 2f
1:
ldr x0, =secondary_boot_func
blr x0
2:
mov lr, x29 /* Restore LR */
ret
ENDPROC(lowlevel_init)
/* Keep literals not used by the secondary boot code outside it */
.ltorg
/* Using 64 bit alignment since the spin table is accessed as data */
.align 4
.global secondary_boot_code
/* Secondary Boot Code starts here */
secondary_boot_code:
.global __spin_table
__spin_table:
.space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE
.align 2
ENTRY(secondary_boot_func)
/*
* MPIDR_EL1 Fields:
* MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
* MPIDR[7:2] = AFF0_RES
* MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
* MPIDR[23:16] = AFF2_CLUSTERID
* MPIDR[24] = MT
* MPIDR[29:25] = RES0
* MPIDR[30] = U
* MPIDR[31] = ME
* MPIDR[39:32] = AFF3
*
* Linear Processor ID (LPID) calculation from MPIDR_EL1:
* (We only use AFF0_CPUID and AFF1_CLUSTERID for now
* until AFF2_CLUSTERID and AFF3 have non-zero values)
*
* LPID = MPIDR[15:8] | MPIDR[1:0]
*/
mrs x0, mpidr_el1
ubfm x1, x0, #8, #15
ubfm x2, x0, #0, #1
orr x10, x2, x1, lsl #2 /* x10 has LPID */
ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */
/*
* offset of the spin table element for this core from start of spin
* table (each elem is padded to 64 bytes)
*/
lsl x1, x10, #6
ldr x0, =__spin_table
/* physical address of this cpus spin table element */
add x11, x1, x0
str x9, [x11, #16] /* LPID */
mov x4, #1
str x4, [x11, #8] /* STATUS */
dsb sy
#if defined(CONFIG_GICV3)
gic_wait_for_interrupt_m x0
#elif defined(CONFIG_GICV2)
ldr x0, =GICC_BASE
gic_wait_for_interrupt_m x0, w1
#endif
bl secondary_switch_to_el2
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
bl secondary_switch_to_el1
#endif
slave_cpu:
wfe
ldr x0, [x11]
cbz x0, slave_cpu
#ifndef CONFIG_ARMV8_SWITCH_TO_EL1
mrs x1, sctlr_el2
#else
mrs x1, sctlr_el1
#endif
tbz x1, #25, cpu_is_le
rev x0, x0 /* BE to LE conversion */
cpu_is_le:
br x0 /* branch to the given address */
ENDPROC(secondary_boot_func)
ENTRY(secondary_switch_to_el2)
switch_el x0, 1f, 0f, 0f
0: ret
1: armv8_switch_to_el2_m x0
ENDPROC(secondary_switch_to_el2)
ENTRY(secondary_switch_to_el1)
switch_el x0, 0f, 1f, 0f
0: ret
1: armv8_switch_to_el1_m x0, x1
ENDPROC(secondary_switch_to_el1)
/* Ensure that the literals used by the secondary boot code are
* assembled within it (this is required so that we can protect
* this area with a single memreserve region
*/
.ltorg
/* 64 bit alignment for elements accessed as data */
.align 4
.globl __secondary_boot_code_size
.type __secondary_boot_code_size, %object
/* Secondary Boot Code ends here */
__secondary_boot_code_size:
.quad .-secondary_boot_code

168
arch/arm/cpu/armv8/fsl-lsch3/mp.c Normal file
View file

@ -0,0 +1,168 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
#include "mp.h"
DECLARE_GLOBAL_DATA_PTR;
void *get_spin_tbl_addr(void)
{
return &__spin_table;
}
phys_addr_t determine_mp_bootpg(void)
{
return (phys_addr_t)&secondary_boot_code;
}
int fsl_lsch3_wake_seconday_cores(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
u32 cores, cpu_up_mask = 1;
int i, timeout = 10;
u64 *table = get_spin_tbl_addr();
cores = cpu_mask();
/* Clear spin table so that secondary processors
* observe the correct value after waking up from wfe.
*/
memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE);
flush_dcache_range((unsigned long)table,
(unsigned long)table +
(CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
printf("Waking secondary cores to start from %lx\n", gd->relocaddr);
out_le32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
out_le32(&gur->bootlocptrl, (u32)gd->relocaddr);
out_le32(&gur->scratchrw[6], 1);
asm volatile("dsb st" : : : "memory");
rst->brrl = cores;
asm volatile("dsb st" : : : "memory");
/* This is needed as a precautionary measure.
* If some code before this has accidentally released the secondary
* cores then the pre-bootloader code will trap them in a "wfe" unless
* the scratchrw[6] is set. In this case we need a sev here to get these
* cores moving again.
*/
asm volatile("sev");
while (timeout--) {
flush_dcache_range((unsigned long)table, (unsigned long)table +
CONFIG_MAX_CPUS * 64);
for (i = 1; i < CONFIG_MAX_CPUS; i++) {
if (table[i * WORDS_PER_SPIN_TABLE_ENTRY +
SPIN_TABLE_ELEM_STATUS_IDX])
cpu_up_mask |= 1 << i;
}
if (hweight32(cpu_up_mask) == hweight32(cores))
break;
udelay(10);
}
if (timeout <= 0) {
printf("Not all cores (0x%x) are up (0x%x)\n",
cores, cpu_up_mask);
return 1;
}
printf("All (%d) cores are up.\n", hweight32(cores));
return 0;
}
int is_core_valid(unsigned int core)
{
return !!((1 << core) & cpu_mask());
}
int cpu_reset(int nr)
{
puts("Feature is not implemented.\n");
return 0;
}
int cpu_disable(int nr)
{
puts("Feature is not implemented.\n");
return 0;
}
int core_to_pos(int nr)
{
u32 cores = cpu_mask();
int i, count = 0;
if (nr == 0) {
return 0;
} else if (nr >= hweight32(cores)) {
puts("Not a valid core number.\n");
return -1;
}
for (i = 1; i < 32; i++) {
if (is_core_valid(i)) {
count++;
if (count == nr)
break;
}
}
return count;
}
int cpu_status(int nr)
{
u64 *table;
int pos;
if (nr == 0) {
table = (u64 *)get_spin_tbl_addr();
printf("table base @ 0x%p\n", table);
} else {
pos = core_to_pos(nr);
if (pos < 0)
return -1;
table = (u64 *)get_spin_tbl_addr() + pos *
WORDS_PER_SPIN_TABLE_ENTRY;
printf("table @ 0x%p\n", table);
printf(" addr - 0x%016llx\n",
table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]);
printf(" status - 0x%016llx\n",
table[SPIN_TABLE_ELEM_STATUS_IDX]);
printf(" lpid - 0x%016llx\n",
table[SPIN_TABLE_ELEM_LPID_IDX]);
}
return 0;
}
int cpu_release(int nr, int argc, char * const argv[])
{
u64 boot_addr;
u64 *table = (u64 *)get_spin_tbl_addr();
int pos;
pos = core_to_pos(nr);
if (pos <= 0)
return -1;
table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
boot_addr = simple_strtoull(argv[0], NULL, 16);
table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr;
flush_dcache_range((unsigned long)table,
(unsigned long)table + SPIN_TABLE_ELEM_SIZE);
asm volatile("dsb st");
smp_kick_all_cpus(); /* only those with entry addr set will run */
return 0;
}

36
arch/arm/cpu/armv8/fsl-lsch3/mp.h Normal file
View file

@ -0,0 +1,36 @@
/*
* Copyright 2014, Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _FSL_CH3_MP_H
#define _FSL_CH3_MP_H
/*
* Each spin table element is defined as
* struct {
* uint64_t entry_addr;
* uint64_t status;
* uint64_t lpid;
* };
* we pad this struct to 64 bytes so each entry is in its own cacheline
* the actual spin table is an array of these structures
*/
#define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0
#define SPIN_TABLE_ELEM_STATUS_IDX 1
#define SPIN_TABLE_ELEM_LPID_IDX 2
#define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */
#define SPIN_TABLE_ELEM_SIZE 64
#define id_to_core(x) ((x & 3) | (x >> 6))
#ifndef __ASSEMBLY__
extern u64 __spin_table[];
extern u64 *secondary_boot_code;
extern size_t __secondary_boot_code_size;
int fsl_lsch3_wake_seconday_cores(void);
void *get_spin_tbl_addr(void);
phys_addr_t determine_mp_bootpg(void);
void secondary_boot_func(void);
#endif
#endif /* _FSL_CH3_MP_H */

63
arch/arm/cpu/armv8/transition.S
View file

@ -14,70 +14,11 @@
ENTRY(armv8_switch_to_el2)
switch_el x0, 1f, 0f, 0f
0: ret
1:
mov x0, #0x5b1 /* Non-secure EL0/EL1 | HVC | 64bit EL2 */
msr scr_el3, x0
msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */
mov x0, #0x33ff
msr cptr_el2, x0 /* Disable coprocessor traps to EL2 */
/* Initialize SCTLR_EL2 */
msr sctlr_el2, xzr
/* Return to the EL2_SP2 mode from EL3 */
mov x0, sp
msr sp_el2, x0 /* Migrate SP */
mrs x0, vbar_el3
msr vbar_el2, x0 /* Migrate VBAR */
mov x0, #0x3c9
msr spsr_el3, x0 /* EL2_SP2 | D | A | I | F */
msr elr_el3, lr
eret
1: armv8_switch_to_el2_m x0
ENDPROC(armv8_switch_to_el2)
ENTRY(armv8_switch_to_el1)
switch_el x0, 0f, 1f, 0f
0: ret
1:
/* Initialize Generic Timers */
mrs x0, cnthctl_el2
orr x0, x0, #0x3 /* Enable EL1 access to timers */
msr cnthctl_el2, x0
msr cntvoff_el2, xzr
mrs x0, cntkctl_el1
orr x0, x0, #0x3 /* Enable EL0 access to timers */
msr cntkctl_el1, x0
/* Initilize MPID/MPIDR registers */
mrs x0, midr_el1
mrs x1, mpidr_el1
msr vpidr_el2, x0
msr vmpidr_el2, x1
/* Disable coprocessor traps */
mov x0, #0x33ff
msr cptr_el2, x0 /* Disable coprocessor traps to EL2 */
msr hstr_el2, xzr /* Disable coprocessor traps to EL2 */
mov x0, #3 << 20
msr cpacr_el1, x0 /* Enable FP/SIMD at EL1 */
/* Initialize HCR_EL2 */
mov x0, #(1 << 31) /* 64bit EL1 */
orr x0, x0, #(1 << 29) /* Disable HVC */
msr hcr_el2, x0
/* SCTLR_EL1 initialization */
mov x0, #0x0800
movk x0, #0x30d0, lsl #16
msr sctlr_el1, x0
/* Return to the EL1_SP1 mode from EL2 */
mov x0, sp
msr sp_el1, x0 /* Migrate SP */
mrs x0, vbar_el2
msr vbar_el1, x0 /* Migrate VBAR */
mov x0, #0x3c5
msr spsr_el2, x0 /* EL1_SP1 | D | A | I | F */
msr elr_el2, lr
eret
1: armv8_switch_to_el1_m x0, x1
ENDPROC(armv8_switch_to_el1)

1
arch/arm/dts/Makefile
View file

@ -9,7 +9,6 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5420-smdk5420.dtb \
exynos5420-peach-pit.dtb
dtb-$(CONFIG_MX6) += imx6q-sabreauto.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \

13
arch/arm/dts/imx6q-sabreauto.dts
View file

@ -1,13 +0,0 @@
/*
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
/ {
model = "Freescale i.MX6 Quad SABRE Automotive Board";
compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
};

6
arch/arm/include/asm/arch-at91/at91_pmc.h
View file

@ -54,7 +54,7 @@ typedef struct at91_pmc {
u32 reserved5[21];
u32 wpmr; /* 0xE4 Write Protect Mode Register (CAP0) */
u32 wpsr; /* 0xE8 Write Protect Status Register (CAP0) */
#ifdef CONFIG_SAMA5D3
#ifdef CPU_HAS_PCR
u32 reserved6[8];
u32 pcer1; /* 0x100 Periperial Clock Enable Register 1 */
u32 pcdr1; /* 0x104 Periperial Clock Disable Register 1 */
@ -147,6 +147,10 @@ typedef struct at91_pmc {
#define AT91_PMC_IXR_PCKRDY3 0x00000800
#define AT91_PMC_IXR_MOSCSELS 0x00010000
#define AT91_PMC_PCR_PID_MASK (0x3f)
#define AT91_PMC_PCR_CMD_WRITE (0x1 << 12)
#define AT91_PMC_PCR_EN (0x1 << 28)
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */

1
arch/arm/include/asm/arch-at91/clk.h
View file

@ -80,4 +80,5 @@ static inline unsigned long get_mci_clk_rate(void)
int at91_clock_init(unsigned long main_clock);
void at91_periph_clk_enable(int id);
void at91_periph_clk_disable(int id);
#endif /* __ASM_ARM_ARCH_CLK_H__ */

1
arch/arm/include/asm/arch-at91/sama5d3.h
View file

@ -188,6 +188,7 @@
#define ATMEL_PIO_PORTS 5
#define CPU_HAS_PIO3
#define PIO_SCDR_DIV 0x3fff
#define CPU_HAS_PCR
/*
* PMECC table in ROM

3
arch/arm/include/asm/arch-at91/sama5d3_smc.h
View file

@ -14,7 +14,8 @@
#define AT91_ASM_SMC_SETUP0 (ATMEL_BASE_SMC + 0x600)
#define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x604)
#define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x608)
#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x60C)
#define AT91_ASM_SMC_TIMINGS0 (ATMEL_BASE_SMC + 0x60c)
#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x610)
#else
struct at91_cs {
u32 setup; /* 0x600 SMC Setup Register */

6
arch/arm/include/asm/arch-fsl-lsch3/config.h
View file

@ -8,7 +8,7 @@
#define _ASM_ARMV8_FSL_LSCH3_CONFIG_
#include <fsl_ddrc_version.h>
#define CONFIG_MP
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
@ -16,8 +16,10 @@
#define CONFIG_SYS_IMMR 0x01000000
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
@ -60,7 +62,7 @@
#ifdef CONFIG_LS2085A
#define CONFIG_MAX_CPUS 16
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_NUM_DDR_CONTROLLERS 3
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
#else
#error SoC not defined

35
arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
View file

@ -113,4 +113,39 @@ struct ccsr_clk_ctrl {
u8 res_04[0x20-0x04];
} clkcncsr[8];
};
struct ccsr_reset {
u32 rstcr; /* 0x000 */
u32 rstcrsp; /* 0x004 */
u8 res_008[0x10-0x08]; /* 0x008 */
u32 rstrqmr1; /* 0x010 */
u32 rstrqmr2; /* 0x014 */
u32 rstrqsr1; /* 0x018 */
u32 rstrqsr2; /* 0x01c */
u32 rstrqwdtmrl; /* 0x020 */
u32 rstrqwdtmru; /* 0x024 */
u8 res_028[0x30-0x28]; /* 0x028 */
u32 rstrqwdtsrl; /* 0x030 */
u32 rstrqwdtsru; /* 0x034 */
u8 res_038[0x60-0x38]; /* 0x038 */
u32 brrl; /* 0x060 */
u32 brru; /* 0x064 */
u8 res_068[0x80-0x68]; /* 0x068 */
u32 pirset; /* 0x080 */
u32 pirclr; /* 0x084 */
u8 res_088[0x90-0x88]; /* 0x088 */
u32 brcorenbr; /* 0x090 */
u8 res_094[0x100-0x94]; /* 0x094 */
u32 rcw_reqr; /* 0x100 */
u32 rcw_completion; /* 0x104 */
u8 res_108[0x110-0x108]; /* 0x108 */
u32 pbi_reqr; /* 0x110 */
u32 pbi_completion; /* 0x114 */
u8 res_118[0xa00-0x118]; /* 0x118 */
u32 qmbm_warmrst; /* 0xa00 */
u32 soc_warmrst; /* 0xa04 */
u8 res_a08[0xbf8-0xa08]; /* 0xa08 */
u32 ip_rev1; /* 0xbf8 */
u32 ip_rev2; /* 0xbfc */
};
#endif /* __ARCH_FSL_LSCH3_IMMAP_H */

1
arch/arm/include/asm/arch-keystone/ddr3.h
View file

@ -50,6 +50,7 @@ struct ddr3_emif_config {
void ddr3_init(void);
void ddr3_reset_ddrphy(void);
void ddr3_err_reset_workaround(void);
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);

2
arch/arm/include/asm/arch-keystone/hardware.h
View file

@ -121,9 +121,11 @@ typedef volatile unsigned int *dv_reg_p;
#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE
#define KS2_RSTCTRL_RSTYPE (KS2_PLL_CNTRL_BASE + 0xe4)
#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8)
#define KS2_RSTCTRL_RSCFG (KS2_PLL_CNTRL_BASE + 0xec)
#define KS2_RSTCTRL_KEY 0x5a69
#define KS2_RSTCTRL_MASK 0xffff0000
#define KS2_RSTCTRL_SWRST 0xfffe0000
#define KS2_RSTYPE_PLL_SOFT BIT(13)
/* SPI */
#define KS2_SPI0_BASE 0x21000400

8
arch/arm/include/asm/arch-kirkwood/spi.h
View file

@ -43,10 +43,10 @@ struct kwspi_registers {
#define KWSPI_XFERLEN_2BYTE (1 << 5)
#define KWSPI_XFERLEN_MASK (1 << 5)
#define KWSPI_ADRLEN_1BYTE 0
#define KWSPI_ADRLEN_2BYTE 1 << 8
#define KWSPI_ADRLEN_3BYTE 2 << 8
#define KWSPI_ADRLEN_4BYTE 3 << 8
#define KWSPI_ADRLEN_MASK 3 << 8
#define KWSPI_ADRLEN_2BYTE (1 << 8)
#define KWSPI_ADRLEN_3BYTE (2 << 8)
#define KWSPI_ADRLEN_4BYTE (3 << 8)
#define KWSPI_ADRLEN_MASK (3 << 8)
#define KWSPI_TIMEOUT 10000
#endif /* __KW_SPI_H__ */

5
arch/arm/include/asm/arch-ls102xa/config.h
View file

@ -50,7 +50,11 @@
#ifdef CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR_BE
#define CONFIG_VERY_BIG_RAM
#ifdef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDRC_GEN4
#else
#define CONFIG_SYS_FSL_DDRC_ARM_GEN3
#endif
#define CONFIG_SYS_FSL_DDR
#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
@ -71,6 +75,7 @@
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#else
#error SoC not defined
#endif

5
arch/arm/include/asm/arch-mx6/clock.h
View file

@ -52,12 +52,17 @@ enum enet_freq {
u32 imx_get_uartclk(void);
u32 imx_get_fecclk(void);
unsigned int mxc_get_clock(enum mxc_clock clk);
void setup_gpmi_io_clk(u32 cfg);
void enable_ocotp_clk(unsigned char enable);
void enable_usboh3_clk(unsigned char enable);
void enable_uart_clk(unsigned char enable);
int enable_cspi_clock(unsigned char enable, unsigned spi_num);
int enable_usdhc_clk(unsigned char enable, unsigned bus_num);
int enable_sata_clock(void);
int enable_pcie_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
int enable_spi_clk(unsigned char enable, unsigned spi_num);
void enable_ipu_clock(void);
int enable_fec_anatop_clock(enum enet_freq freq);
void enable_enet_clk(unsigned char enable);
#endif /* __ASM_ARCH_CLOCK_H */

13
arch/arm/include/asm/arch-mx6/imx-regs.h
View file

@ -419,6 +419,19 @@ struct iomuxc {
u32 gpr[14];
};
struct gpc {
u32 cntr;
u32 pgr;
u32 imr1;
u32 imr2;
u32 imr3;
u32 imr4;
u32 isr1;
u32 isr2;
u32 isr3;
u32 isr4;
};
#define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20
#define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
#define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16

9
arch/arm/include/asm/arch-mx6/iomux.h
View file

@ -18,6 +18,12 @@
#define IOMUXC_GPR1_REF_SSP_EN (1 << 16)
#define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18)
/*
* IOMUXC_GPR5 bit fields
*/
#define IOMUXC_GPR5_PCIE_BTNRST (1 << 19)
#define IOMUXC_GPR5_PCIE_PERST (1 << 18)
/*
* IOMUXC_GPR8 bit fields
*/
@ -35,12 +41,15 @@
/*
* IOMUXC_GPR12 bit fields
*/
#define IOMUXC_GPR12_RX_EQ_2 (0x2 << 0)
#define IOMUXC_GPR12_RX_EQ_MASK (0x7 << 0)
#define IOMUXC_GPR12_LOS_LEVEL_9 (0x9 << 4)
#define IOMUXC_GPR12_LOS_LEVEL_MASK (0x1f << 4)
#define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10)
#define IOMUXC_GPR12_DEVICE_TYPE_EP (0x0 << 12)
#define IOMUXC_GPR12_DEVICE_TYPE_RC (0x4 << 12)
#define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12)
#define IOMUXC_GPR12_TEST_POWERDOWN (1 << 30)
/*
* IOMUXC_GPR13 bit fields

5
arch/arm/include/asm/arch-mx6/sys_proto.h
View file

@ -20,8 +20,9 @@ u32 get_cpu_rev(void);
/* returns MXC_CPU_ value */
#define cpu_type(rev) (((rev) >> 12)&0xff)
/* use with MXC_CPU_ constants */
#define is_cpu_type(cpu) (cpu_type(get_cpu_rev()) == cpu)
/* both macros return/take MXC_CPU_ constants */
#define get_cpu_type() (cpu_type(get_cpu_rev()))
#define is_cpu_type(cpu) (get_cpu_type() == cpu)
const char *get_imx_type(u32 imxtype);
unsigned imx_ddr_size(void);

46
arch/arm/include/asm/arch-uniphier/arm-mpcore.h Normal file
View file

@ -0,0 +1,46 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_ARM_MPCORE_H
#define ARCH_ARM_MPCORE_H
/* Snoop Control Unit */
#define SCU_OFFSET 0x00
/* SCU Control Register */
#define SCU_CTRL 0x00
/* SCU Configuration Register */
#define SCU_CONF 0x04
/* SCU CPU Power Status Register */
#define SCU_PWR_STATUS 0x08
/* SCU Invalidate All Registers in Secure State */
#define SCU_INV_ALL 0x0C
/* SCU Filtering Start Address Register */
#define SCU_FILTER_START 0x40
/* SCU Filtering End Address Register */
#define SCU_FILTER_END 0x44
/* SCU Access Control Register */
#define SCU_SAC 0x50
/* SCU Non-secure Access Control Register */
#define SCU_SNSAC 0x54
/* Global Timer */
#define GLOBAL_TIMER_OFFSET 0x200
/* Global Timer Counter Registers */
#define GTIMER_CNT_L 0x00
#define GTIMER_CNT_H 0x04
/* Global Timer Control Register */
#define GTIMER_CTRL 0x08
/* Global Timer Interrupt Status Register */
#define GTIMER_STAT 0x0C
/* Comparator Value Registers */
#define GTIMER_CMP_L 0x10
#define GTIMER_CMP_H 0x14
/* Auto-increment Register */
#define GTIMER_INC 0x18
#endif /* ARCH_ARM_MPCORE_H */

30
arch/arm/include/asm/arch-uniphier/bcu-regs.h Normal file
View file

@ -0,0 +1,30 @@
/*
* UniPhier BCU (Bus Control Unit) registers
*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_BCU_REGS_H
#define ARCH_BCU_REGS_H
#define BCU_BASE 0x50080000
#define BCSCR(x) (BCU_BASE + 0x180 + (x) * 4)
#define BCSCR0 (BCSCR(0))
#define BCSCR1 (BCSCR(1))
#define BCSCR2 (BCSCR(2))
#define BCSCR3 (BCSCR(3))
#define BCSCR4 (BCSCR(4))
#define BCSCR5 (BCSCR(5))
#define BCIPPCCHR(x) (BCU_BASE + 0x0280 + (x) * 4)
#define BCIPPCCHR0 (BCIPPCCHR(0))
#define BCIPPCCHR1 (BCIPPCCHR(1))
#define BCIPPCCHR2 (BCIPPCCHR(2))
#define BCIPPCCHR3 (BCIPPCCHR(3))
#define BCIPPCCHR4 (BCIPPCCHR(4))
#define BCIPPCCHR5 (BCIPPCCHR(5))
#endif /* ARCH_BCU_REGS_H */

35
arch/arm/include/asm/arch-uniphier/board.h Normal file
View file

@ -0,0 +1,35 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_BOARD_H
#define ARCH_BOARD_H
#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) || \
defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
void support_card_reset(void);
void support_card_init(void);
int check_support_card(void);
#else
#define support_card_reset() do {} while (0)
#define support_card_init() do {} while (0)
static inline int check_support_card(void)
{
return 0;
}
#endif
static inline void uniphier_board_reset(void)
{
support_card_reset();
}
static inline void uniphier_board_init(void)
{
support_card_init();
}
#endif /* ARCH_BOARD_H */

20
arch/arm/include/asm/arch-uniphier/boot-device.h Normal file
View file

@ -0,0 +1,20 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_BOOT_DEVICE_H_
#define _ASM_BOOT_DEVICE_H_
u32 get_boot_mode_sel(void);
struct boot_device_info {
u32 type;
char *info;
};
extern struct boot_device_info boot_device_table[];
#endif /* _ASM_BOOT_DEVICE_H_ */

101
arch/arm/include/asm/arch-uniphier/led.h Normal file
View file

@ -0,0 +1,101 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_LED_H
#define ARCH_LED_H
#include <config.h>
#define LED_CHAR_0 0x7e
#define LED_CHAR_1 0x0c
#define LED_CHAR_2 0xb6
#define LED_CHAR_3 0x9e
#define LED_CHAR_4 0xcc
#define LED_CHAR_5 0xda
#define LED_CHAR_6 0xfa
#define LED_CHAR_7 0x4e
#define LED_CHAR_8 0xfe
#define LED_CHAR_9 0xde
#define LED_CHAR_A 0xee
#define LED_CHAR_B 0xf8
#define LED_CHAR_C 0x72
#define LED_CHAR_D 0xbc
#define LED_CHAR_E 0xf2
#define LED_CHAR_F 0xe2
#define LED_CHAR_G 0x7a
#define LED_CHAR_H 0xe8
#define LED_CHAR_I 0x08
#define LED_CHAR_J 0x3c
#define LED_CHAR_K 0xea
#define LED_CHAR_L 0x70
#define LED_CHAR_M 0x6e
#define LED_CHAR_N 0xa8
#define LED_CHAR_O 0xb8
#define LED_CHAR_P 0xe6
#define LED_CHAR_Q 0xce
#define LED_CHAR_R 0xa0
#define LED_CHAR_S 0xc8
#define LED_CHAR_T 0x8c
#define LED_CHAR_U 0x7c
#define LED_CHAR_V 0x54
#define LED_CHAR_W 0xfc
#define LED_CHAR_X 0xec
#define LED_CHAR_Y 0xdc
#define LED_CHAR_Z 0xa4
#define LED_CHAR_SPACE 0x00
#define LED_CHAR_DOT 0x01
#define LED_CHAR_ (LED_CHAR_SPACE)
/** Macro to translate 4 characters into integer to display led */
#define LED_C2I(C0, C1, C2, C3) \
(~( \
(LED_CHAR_##C0 << 24) | \
(LED_CHAR_##C1 << 16) | \
(LED_CHAR_##C2 << 8) | \
(LED_CHAR_##C3) \
))
#if defined(CONFIG_SUPPORT_CARD_LED_BASE)
#define LED_ADDR CONFIG_SUPPORT_CARD_LED_BASE
#ifdef __ASSEMBLY__
#define led_write(C0, C1, C2, C3) raw_led_write LED_C2I(C0, C1, C2, C3)
.macro raw_led_write data
ldr r0, =\data
ldr r1, =LED_ADDR
str r0, [r1]
.endm
#else /* __ASSEMBLY__ */
#include <asm/io.h>
#define led_write(C0, C1, C2, C3) \
do { \
raw_led_write(LED_C2I(C0, C1, C2, C3)); \
} while (0)
static inline void raw_led_write(u32 data)
{
writel(data, LED_ADDR);
}
#endif /* __ASSEMBLY__ */
#else /* CONFIG_SUPPORT_CARD_LED_BASE */
#define led_write(C0, C1, C2, C3)
#define raw_led_write(x)
#endif /* CONFIG_SUPPORT_CARD_LED_BASE */
#endif /* ARCH_LED_H */

108
arch/arm/include/asm/arch-uniphier/sbc-regs.h Normal file
View file

@ -0,0 +1,108 @@
/*
* UniPhier SBC (System Bus Controller) registers
*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_SBC_REGS_H
#define ARCH_SBC_REGS_H
#define SBBASE_BASE 0x58c00100
#define SBBASE(x) (SBBASE_BASE + (x) * 0x10)
#define SBBASE0 (SBBASE(0))
#define SBBASE1 (SBBASE(1))
#define SBBASE2 (SBBASE(2))
#define SBBASE3 (SBBASE(3))
#define SBBASE4 (SBBASE(4))
#define SBBASE5 (SBBASE(5))
#define SBBASE6 (SBBASE(6))
#define SBBASE7 (SBBASE(7))
#define SBBASE_BANK_ENABLE (0x00000001)
#define SBCTRL_BASE 0x58c00200
#define SBCTRL(x, y) (SBCTRL_BASE + (x) * 0x10 + (y) * 4)
#define SBCTRL00 SBCTRL(0, 0)
#define SBCTRL01 SBCTRL(0, 1)
#define SBCTRL02 SBCTRL(0, 2)
#define SBCTRL03 SBCTRL(0, 3)
#define SBCTRL04 (SBCTRL_BASE + 0x100)
#define SBCTRL10 SBCTRL(1, 0)
#define SBCTRL11 SBCTRL(1, 1)
#define SBCTRL12 SBCTRL(1, 2)
#define SBCTRL13 SBCTRL(1, 3)
#define SBCTRL14 (SBCTRL_BASE + 0x110)
#define SBCTRL20 SBCTRL(2, 0)
#define SBCTRL21 SBCTRL(2, 1)
#define SBCTRL22 SBCTRL(2, 2)
#define SBCTRL23 SBCTRL(2, 3)
#define SBCTRL24 (SBCTRL_BASE + 0x120)
#define SBCTRL30 SBCTRL(3, 0)
#define SBCTRL31 SBCTRL(3, 1)
#define SBCTRL32 SBCTRL(3, 2)
#define SBCTRL33 SBCTRL(3, 3)
#define SBCTRL34 (SBCTRL_BASE + 0x130)
#define SBCTRL40 SBCTRL(4, 0)
#define SBCTRL41 SBCTRL(4, 1)
#define SBCTRL42 SBCTRL(4, 2)
#define SBCTRL43 SBCTRL(4, 3)
#define SBCTRL44 (SBCTRL_BASE + 0x140)
#define SBCTRL50 SBCTRL(5, 0)
#define SBCTRL51 SBCTRL(5, 1)
#define SBCTRL52 SBCTRL(5, 2)
#define SBCTRL53 SBCTRL(5, 3)
#define SBCTRL54 (SBCTRL_BASE + 0x150)
#define SBCTRL60 SBCTRL(6, 0)
#define SBCTRL61 SBCTRL(6, 1)
#define SBCTRL62 SBCTRL(6, 2)
#define SBCTRL63 SBCTRL(6, 3)
#define SBCTRL64 (SBCTRL_BASE + 0x160)
#define SBCTRL70 SBCTRL(7, 0)
#define SBCTRL71 SBCTRL(7, 1)
#define SBCTRL72 SBCTRL(7, 2)
#define SBCTRL73 SBCTRL(7, 3)
#define SBCTRL74 (SBCTRL_BASE + 0x170)
/* slower but LED works */
#define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000
#define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00
#define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009
#define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110
/* faster but LED does not work */
#define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000
#define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700
/* NOR flash needs more wait counts than SRAM */
#define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009
#define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210
#define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000
#define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500
#define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020
#define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000
#define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500
#define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010
#define ROM_BOOT_ROMRSV2 0x59801208
#ifndef __ASSEMBLY__
#include <asm/io.h>
static inline int boot_is_swapped(void)
{
return !(readl(SBBASE0) & SBBASE_BANK_ENABLE);
}
#endif
#endif /* ARCH_SBC_REGS_H */

62
arch/arm/include/asm/arch-uniphier/sc-regs.h Normal file
View file

@ -0,0 +1,62 @@
/*
* UniPhier SC (System Control) block registers
*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_SC_REGS_H
#define ARCH_SC_REGS_H
#define SC_BASE_ADDR 0x61840000
#define SC_MPLLOSCCTL (SC_BASE_ADDR | 0x1184)
#define SC_MPLLOSCCTL_MPLLEN (0x1 << 0)
#define SC_MPLLOSCCTL_MPLLST (0x1 << 1)
#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200)
#define SC_DPLLCTRL_SSC_EN (0x1 << 31)
#define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16)
#define SC_DPLLCTRL_SSC_RATE (0x1 << 15)
#define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204)
#define SC_DPLLCTRL2_NRSTDS (0x1 << 28)
#define SC_DPLLCTRL3 (SC_BASE_ADDR | 0x1208)
#define SC_DPLLCTRL3_LPFSEL_COEF2 (0x0 << 31)
#define SC_DPLLCTRL3_LPFSEL_COEF3 (0x1 << 31)
#define SC_UPLLCTRL (SC_BASE_ADDR | 0x1210)
#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1270)
#define SC_VPLL27ACTRL2 (SC_BASE_ADDR | 0x1274)
#define SC_VPLL27ACTRL3 (SC_BASE_ADDR | 0x1278)
#define SC_VPLL27BCTRL (SC_BASE_ADDR | 0x1290)
#define SC_VPLL27BCTRL2 (SC_BASE_ADDR | 0x1294)
#define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298)
#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
#define SC_RSTCTRL_NRST_ETHER (0x1 << 12)
#define SC_RSTCTRL_NRST_UMC1 (0x1 << 5)
#define SC_RSTCTRL_NRST_UMC0 (0x1 << 4)
#define SC_RSTCTRL_NRST_NAND (0x1 << 2)
#define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004)
#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104)
#define SC_CLKCTRL_CLK_ETHER (0x1 << 12)
#define SC_CLKCTRL_CLK_MIO (0x1 << 11)
#define SC_CLKCTRL_CLK_UMC (0x1 << 4)
#define SC_CLKCTRL_CLK_NAND (0x1 << 2)
#define SC_CLKCTRL_CLK_SBC (0x1 << 1)
#define SC_CLKCTRL_CLK_PERI (0x1 << 0)
/* System reset control register */
#define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000)
#define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010)
#define SC_SLFRSTCTL (SC_BASE_ADDR | 0x3014)
#endif /* ARCH_SC_REGS_H */

182
arch/arm/include/asm/arch-uniphier/sg-regs.h Normal file
View file

@ -0,0 +1,182 @@
/*
* UniPhier SG (SoC Glue) block registers
*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_SG_REGS_H
#define ARCH_SG_REGS_H
/* Base Address */
#define SG_CTRL_BASE 0x5f800000
#define SG_DBG_BASE 0x5f900000
/* Revision */
#define SG_REVISION (SG_CTRL_BASE | 0x0000)
#define SG_REVISION_TYPE_SHIFT 16
#define SG_REVISION_TYPE_MASK (0xff << SG_REVISION_TYPE_SHIFT)
#define SG_REVISION_MODEL_SHIFT 8
#define SG_REVISION_MODEL_MASK (0x3 << SG_REVISION_MODEL_SHIFT)
#define SG_REVISION_REV_SHIFT 0
#define SG_REVISION_REV_MASK (0x1f << SG_REVISION_REV_SHIFT)
/* Memory Configuration */
#define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
#define SG_MEMCONF_CH0_SIZE_64MB ((0x0 << 10) | (0x01 << 0))
#define SG_MEMCONF_CH0_SIZE_128MB ((0x0 << 10) | (0x02 << 0))
#define SG_MEMCONF_CH0_SIZE_256MB ((0x0 << 10) | (0x03 << 0))
#define SG_MEMCONF_CH0_SIZE_512MB ((0x1 << 10) | (0x00 << 0))
#define SG_MEMCONF_CH0_SIZE_1024MB ((0x1 << 10) | (0x01 << 0))
#define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
#define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
#define SG_MEMCONF_CH1_SIZE_64MB ((0x0 << 11) | (0x01 << 2))
#define SG_MEMCONF_CH1_SIZE_128MB ((0x0 << 11) | (0x02 << 2))
#define SG_MEMCONF_CH1_SIZE_256MB ((0x0 << 11) | (0x03 << 2))
#define SG_MEMCONF_CH1_SIZE_512MB ((0x1 << 11) | (0x00 << 2))
#define SG_MEMCONF_CH1_SIZE_1024MB ((0x1 << 11) | (0x01 << 2))
#define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
#define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
#define SG_MEMCONF_SPARSEMEM (0x1 << 4)
/* Pin Control */
#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000)
#if defined(CONFIG_MACH_PH1_PRO4)
# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 8)
#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 4)
#endif
#if defined(CONFIG_MACH_PH1_PRO4)
#define SG_PINSELBITS 4
#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
#define SG_PINSELBITS 8
#endif
#define SG_PINSEL_ADDR(n) (SG_PINCTRL((n) * (SG_PINSELBITS) / 32))
#define SG_PINSEL_MASK(n) (~(((1 << (SG_PINSELBITS)) - 1) << \
((n) * (SG_PINSELBITS) % 32)))
#define SG_PINSEL_MODE(n, mode) ((mode) << ((n) * (SG_PINSELBITS) % 32))
/* Only for PH1-Pro4 */
#define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700)
/* Input Enable */
#define SG_IECTRL (SG_CTRL_BASE | 0x1d00)
/* Pin Monitor */
#define SG_PINMON0 (SG_DBG_BASE | 0x0100)
#define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19)
#define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19)
#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A (0x2 << 19)
#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B (0x3 << 19)
#define SG_PINMON0_CLK_MODE_AXOSEL_MASK (0x3 << 16)
#define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ (0x0 << 16)
#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ (0x1 << 16)
#define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ (0x2 << 16)
#define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ (0x3 << 16)
#define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT (0x0 << 16)
#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U (0x1 << 16)
#define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16)
#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16)
#ifndef __ASSEMBLY__
#include <linux/types.h>
#include <asm/io.h>
static inline void sg_set_pinsel(int n, int value)
{
writel((readl(SG_PINSEL_ADDR(n)) & SG_PINSEL_MASK(n))
| SG_PINSEL_MODE(n, value), SG_PINSEL_ADDR(n));
}
static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
{
int size_mb = (size >> 20) / num;
u32 ret;
switch (size_mb) {
case 64:
ret = SG_MEMCONF_CH0_SIZE_64MB;
break;
case 128:
ret = SG_MEMCONF_CH0_SIZE_128MB;
break;
case 256:
ret = SG_MEMCONF_CH0_SIZE_256MB;
break;
case 512:
ret = SG_MEMCONF_CH0_SIZE_512MB;
break;
case 1024:
ret = SG_MEMCONF_CH0_SIZE_1024MB;
break;
default:
BUG();
break;
}
switch (num) {
case 1:
ret |= SG_MEMCONF_CH0_NUM_1;
break;
case 2:
ret |= SG_MEMCONF_CH0_NUM_2;
break;
default:
BUG();
break;
}
return ret;
}
static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
{
int size_mb = (size >> 20) / num;
u32 ret;
switch (size_mb) {
case 64:
ret = SG_MEMCONF_CH1_SIZE_64MB;
break;
case 128:
ret = SG_MEMCONF_CH1_SIZE_128MB;
break;
case 256:
ret = SG_MEMCONF_CH1_SIZE_256MB;
break;
case 512:
ret = SG_MEMCONF_CH1_SIZE_512MB;
break;
case 1024:
ret = SG_MEMCONF_CH1_SIZE_1024MB;
break;
default:
BUG();
break;
}
switch (num) {
case 1:
ret |= SG_MEMCONF_CH1_NUM_1;
break;
case 2:
ret |= SG_MEMCONF_CH1_NUM_2;
break;
default:
BUG();
break;
}
return ret;
}
#endif /* __ASSEMBLY__ */
#endif /* ARCH_SG_REGS_H */

67
arch/arm/include/asm/arch-uniphier/ssc-regs.h Normal file
View file

@ -0,0 +1,67 @@
/*
* UniPhier System Cache (L2 Cache) registers
*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_SSC_REGS_H
#define ARCH_SSC_REGS_H
#define SSCC 0x500c0000
#define SSCC_BST (0x1 << 20)
#define SSCC_ACT (0x1 << 19)
#define SSCC_WTG (0x1 << 18)
#define SSCC_PRD (0x1 << 17)
#define SSCC_WBWA (0x1 << 16)
#define SSCC_EX (0x1 << 13)
#define SSCC_ON (0x1 << 0)
#define SSCLPDAWCR 0x500c0030
#define SSCOPE 0x506c0244
#define SSCOPE_CM_SYNC 0x00000008
#define SSCOQM 0x506c0248
#define SSCOQM_TID_MASK (0x3 << 21)
#define SSCOQM_TID_BY_WAY (0x2 << 21)
#define SSCOQM_TID_BY_INST_WAY (0x1 << 21)
#define SSCOQM_TID_BY_DATA_WAY (0x0 << 21)
#define SSCOQM_S_MASK (0x3 << 17)
#define SSCOQM_S_WAY (0x2 << 17)
#define SSCOQM_S_ALL (0x1 << 17)
#define SSCOQM_S_ADDRESS (0x0 << 17)
#define SSCOQM_CE (0x1 << 15)
#define SSCOQM_CW (0x1 << 14)
#define SSCOQM_CM_MASK (0x7)
#define SSCOQM_CM_DIRT_TOUCH (0x7)
#define SSCOQM_CM_ZERO_TOUCH (0x6)
#define SSCOQM_CM_NORM_TOUCH (0x5)
#define SSCOQM_CM_PREF_FETCH (0x4)
#define SSCOQM_CM_SSC_FETCH (0x3)
#define SSCOQM_CM_WB_INV (0x2)
#define SSCOQM_CM_WB (0x1)
#define SSCOQM_CM_INV (0x0)
#define SSCOQAD 0x506c024c
#define SSCOQSZ 0x506c0250
#define SSCOQWN 0x506c0258
#define SSCOPPQSEF 0x506c025c
#define SSCOPPQSEF_FE (0x1 << 1)
#define SSCOPPQSEF_OE (0x1 << 0)
#define SSCOLPQS 0x506c0260
#define SSCOLPQS_EF (0x1 << 2)
#define SSCOLPQS_EST (0x1 << 1)
#define SSCOLPQS_QST (0x1 << 0)
#define SSCOQCE0 0x506c0270
#define SSC_LINE_SIZE 128
#define SSC_NUM_ENTRIES 256
#define SSC_WAY_SIZE ((SSC_LINE_SIZE) * (SSC_NUM_ENTRIES))
#define SSC_RANGE_OP_MAX_SIZE (0x00400000 - (SSC_LINE_SIZE))
#endif /* ARCH_SSC_REGS_H */

119
arch/arm/include/asm/arch-uniphier/umc-regs.h Normal file
View file

@ -0,0 +1,119 @@
/*
* UniPhier UMC (Universal Memory Controller) registers
*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_UMC_REGS_H
#define ARCH_UMC_REGS_H
#define UMC_BASE 0x5b800000
/* SSIF registers */
#define UMC_SSIF_BASE UMC_BASE
#define UMC_CPURST 0x00000700
#define UMC_IDSRST 0x0000070C
#define UMC_IXMRST 0x00000714
#define UMC_HDMRST 0x00000718
#define UMC_MDMRST 0x0000071C
#define UMC_HDDRST 0x00000720
#define UMC_MDDRST 0x00000724
#define UMC_SIORST 0x00000728
#define UMC_GIORST 0x0000072C
#define UMC_HD2RST 0x00000734
#define UMC_VIORST 0x0000073C
#define UMC_FRCRST 0x00000748 /* LD4/sLD8 */
#define UMC_DVCRST 0x00000748 /* Pro4 */
#define UMC_RGLRST 0x00000750
#define UMC_VPERST 0x00000758
#define UMC_AIORST 0x00000764
#define UMC_DMDRST 0x00000770
#define UMC_HDMCHSEL 0x00000898
#define UMC_MDMCHSEL 0x0000089C
#define UMC_DVCCHSEL 0x000008C8
#define UMC_DMDCHSEL 0x000008F0
#define UMC_CLKEN_SSIF_FETCH 0x0000C060
#define UMC_CLKEN_SSIF_COMQUE0 0x0000C064
#define UMC_CLKEN_SSIF_COMWC0 0x0000C068
#define UMC_CLKEN_SSIF_COMRC0 0x0000C06C
#define UMC_CLKEN_SSIF_COMQUE1 0x0000C070
#define UMC_CLKEN_SSIF_COMWC1 0x0000C074
#define UMC_CLKEN_SSIF_COMRC1 0x0000C078
#define UMC_CLKEN_SSIF_WC 0x0000C07C
#define UMC_CLKEN_SSIF_RC 0x0000C080
#define UMC_CLKEN_SSIF_DST 0x0000C084
/* CA registers */
#define UMC_CA_BASE(ch) (UMC_BASE + 0x00001000 + 0x00001000 * (ch))
/* DRAM controller registers */
#define UMC_DRAMCONT_BASE(ch) (UMC_BASE + 0x00400000 + 0x00200000 * (ch))
#define UMC_CMDCTLA 0x00000000
#define UMC_CMDCTLB 0x00000004
#define UMC_INITCTLA 0x00000008
#define UMC_INITCTLB 0x0000000C
#define UMC_INITCTLC 0x00000010
#define UMC_INITSET 0x00000014
#define UMC_INITSTAT 0x00000018
#define UMC_DRMMR0 0x0000001C
#define UMC_DRMMR1 0x00000020
#define UMC_DRMMR2 0x00000024
#define UMC_DRMMR3 0x00000028
#define UMC_SPCCTLA 0x00000030
#define UMC_SPCCTLB 0x00000034
#define UMC_SPCSETA 0x00000038
#define UMC_SPCSETB 0x0000003C
#define UMC_SPCSETC 0x00000040
#define UMC_SPCSETD 0x00000044
#define UMC_SPCSTATA 0x00000050
#define UMC_SPCSTATB 0x00000054
#define UMC_SPCSTATC 0x00000058
#define UMC_ACSSETA 0x00000060
#define UMC_FLOWCTLA 0x00000400
#define UMC_FLOWCTLB 0x00000404
#define UMC_FLOWCTLC 0x00000408
#define UMC_FLOWCTLG 0x00000508
#define UMC_RDATACTL_D0 0x00000600
#define UMC_WDATACTL_D0 0x00000604
#define UMC_RDATACTL_D1 0x00000608
#define UMC_WDATACTL_D1 0x0000060C
#define UMC_DATASET 0x00000610
#define UMC_DCCGCTL 0x00000720
#define UMC_DICGCTLA 0x00000724
#define UMC_DICGCTLB 0x00000728
#define UMC_DIOCTLA 0x00000C00
#define UMC_DFICUPDCTLA 0x00000C20
#ifndef __ASSEMBLY__
#include <linux/types.h>
static inline void umc_polling(u32 address, u32 expval, u32 mask)
{
u32 nmask = ~mask;
u32 data;
do {
data = readl(address) & nmask;
} while (data != expval);
}
static inline void umc_dram_init_start(void __iomem *dramcont)
{
writel(0x00000002, dramcont + UMC_INITSET);
}
static inline void umc_dram_init_poll(void __iomem *dramcont)
{
while ((readl(dramcont + UMC_INITSTAT) & 0x00000002))
;
}
#endif
#endif

33
arch/arm/include/asm/imx-common/mxc_i2c.h
View file

@ -19,6 +19,39 @@ struct i2c_pads_info {
struct i2c_pin_ctrl sda;
};
#if defined(CONFIG_MX6QDL)
#define I2C_PADS(name, scl_i2c, scl_gpio, scl_gp, sda_i2c, sda_gpio, sda_gp) \
struct i2c_pads_info mx6q_##name = { \
.scl = { \
.i2c_mode = MX6Q_##scl_i2c, \
.gpio_mode = MX6Q_##scl_gpio, \
.gp = scl_gp, \
}, \
.sda = { \
.i2c_mode = MX6Q_##sda_i2c, \
.gpio_mode = MX6Q_##sda_gpio, \
.gp = sda_gp, \
} \
}; \
struct i2c_pads_info mx6s_##name = { \
.scl = { \
.i2c_mode = MX6DL_##scl_i2c, \
.gpio_mode = MX6DL_##scl_gpio, \
.gp = scl_gp, \
}, \
.sda = { \
.i2c_mode = MX6DL_##sda_i2c, \
.gpio_mode = MX6DL_##sda_gpio, \
.gp = sda_gp, \
} \
};
#define I2C_PADS_INFO(name) \
(is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) ? \
&mx6q_##name : &mx6s_##name
#endif
void setup_i2c(unsigned i2c_index, int speed, int slave_addr,
struct i2c_pads_info *p);
void bus_i2c_init(void *base, int speed, int slave_addr,

93
arch/arm/include/asm/macro.h
View file

@ -105,6 +105,99 @@ lr .req x30
cbz \xreg1, \master_label
.endm
.macro armv8_switch_to_el2_m, xreg1
/* 64bit EL2 | HCE | SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1 */
mov \xreg1, #0x5b1
msr scr_el3, \xreg1
msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */
mov \xreg1, #0x33ff
msr cptr_el2, \xreg1 /* Disable coprocessor traps to EL2 */
/* Initialize SCTLR_EL2
*
* setting RES1 bits (29,28,23,22,18,16,11,5,4) to 1
* and RES0 bits (31,30,27,26,24,21,20,17,15-13,10-6) +
* EE,WXN,I,SA,C,A,M to 0
*/
mov \xreg1, #0x0830
movk \xreg1, #0x30C5, lsl #16
msr sctlr_el2, \xreg1
/* Return to the EL2_SP2 mode from EL3 */
mov \xreg1, sp
msr sp_el2, \xreg1 /* Migrate SP */
mrs \xreg1, vbar_el3
msr vbar_el2, \xreg1 /* Migrate VBAR */
mov \xreg1, #0x3c9
msr spsr_el3, \xreg1 /* EL2_SP2 | D | A | I | F */
msr elr_el3, lr
eret
.endm
.macro armv8_switch_to_el1_m, xreg1, xreg2
/* Initialize Generic Timers */
mrs \xreg1, cnthctl_el2
orr \xreg1, \xreg1, #0x3 /* Enable EL1 access to timers */
msr cnthctl_el2, \xreg1
msr cntvoff_el2, xzr
/* Initilize MPID/MPIDR registers */
mrs \xreg1, midr_el1
mrs \xreg2, mpidr_el1
msr vpidr_el2, \xreg1
msr vmpidr_el2, \xreg2
/* Disable coprocessor traps */
mov \xreg1, #0x33ff
msr cptr_el2, \xreg1 /* Disable coprocessor traps to EL2 */
msr hstr_el2, xzr /* Disable coprocessor traps to EL2 */
mov \xreg1, #3 << 20
msr cpacr_el1, \xreg1 /* Enable FP/SIMD at EL1 */
/* Initialize HCR_EL2 */
mov \xreg1, #(1 << 31) /* 64bit EL1 */
orr \xreg1, \xreg1, #(1 << 29) /* Disable HVC */
msr hcr_el2, \xreg1
/* SCTLR_EL1 initialization
*
* setting RES1 bits (29,28,23,22,20,11) to 1
* and RES0 bits (31,30,27,21,17,13,10,6) +
* UCI,EE,EOE,WXN,nTWE,nTWI,UCT,DZE,I,UMA,SED,ITD,
* CP15BEN,SA0,SA,C,A,M to 0
*/
mov \xreg1, #0x0800
movk \xreg1, #0x30d0, lsl #16
msr sctlr_el1, \xreg1
/* Return to the EL1_SP1 mode from EL2 */
mov \xreg1, sp
msr sp_el1, \xreg1 /* Migrate SP */
mrs \xreg1, vbar_el2
msr vbar_el1, \xreg1 /* Migrate VBAR */
mov \xreg1, #0x3c5
msr spsr_el2, \xreg1 /* EL1_SP1 | D | A | I | F */
msr elr_el2, lr
eret
.endm
#if defined(CONFIG_GICV3)
.macro gic_wait_for_interrupt_m xreg1
0 : wfi
mrs \xreg1, ICC_IAR1_EL1
msr ICC_EOIR1_EL1, \xreg1
cbnz \xreg1, 0b
.endm
#elif defined(CONFIG_GICV2)
.macro gic_wait_for_interrupt_m xreg1, wreg2
0 : wfi
ldr \wreg2, [\xreg1, GICC_AIAR]
str \wreg2, [\xreg1, GICC_AEOIR]
and \wreg2, \wreg2, #3ff
cbnz \wreg2, 0b
.endm
#endif
#endif /* CONFIG_ARM64 */
#endif /* __ASSEMBLY__ */

Some files were not shown because too many files have changed in this diff Show more