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Merge branch 'u-boot/master' into 'u-boot-arm/master'

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This commit is contained in:
Albert ARIBAUD 2014-10-11 01:20:30 +02:00
commit 790af81543
202 changed files with 2819 additions and 12270 deletions
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2
Makefile
View file

@ -8,7 +8,7 @@
VERSION = 2014
PATCHLEVEL = 10
SUBLEVEL =
EXTRAVERSION = -rc2
EXTRAVERSION = -rc3
NAME =
# *DOCUMENTATION*

8
arch/arm/cpu/armv7/omap-common/sata.c
View file

@ -70,7 +70,13 @@ int init_sata(int dev)
writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
ret = ahci_init(DWC_AHSATA_BASE);
scsi_scan(1);
return ret;
}
/* On OMAP platforms SATA provides the SCSI subsystem */
void scsi_init(void)
{
init_sata(0);
scsi_scan(1);
}

3
arch/arm/cpu/armv7/socfpga/Makefile
View file

@ -8,5 +8,6 @@
#
obj-y := lowlevel_init.o
obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o
obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
fpga_manager.o
obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o

338
arch/arm/cpu/armv7/socfpga/clock_manager.c
View file

@ -8,38 +8,28 @@
#include <asm/io.h>
#include <asm/arch/clock_manager.h>
DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_clock_manager *clock_manager_base =
(void *)SOCFPGA_CLKMGR_ADDRESS;
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
#define CLKMGR_BYPASS_ENABLE 1
#define CLKMGR_BYPASS_DISABLE 0
#define CLKMGR_STAT_IDLE 0
#define CLKMGR_STAT_BUSY 1
#define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1 0
#define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX 1
#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1 0
#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX 1
#define CLEAR_BGP_EN_PWRDN \
(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
#define VCO_EN_BASE \
(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
static inline void cm_wait_for_lock(uint32_t mask)
static void cm_wait_for_lock(uint32_t mask)
{
register uint32_t inter_val;
uint32_t retry = 0;
do {
inter_val = readl(&clock_manager_base->inter) & mask;
} while (inter_val != mask);
if (inter_val == mask)
retry++;
else
retry = 0;
if (retry >= 10)
break;
} while (1);
}
/* function to poll in the fsm busy bit */
static inline void cm_wait_for_fsm(void)
static void cm_wait_for_fsm(void)
{
while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
;
@ -49,22 +39,22 @@ static inline void cm_wait_for_fsm(void)
* function to write the bypass register which requires a poll of the
* busy bit
*/
static inline void cm_write_bypass(uint32_t val)
static void cm_write_bypass(uint32_t val)
{
writel(val, &clock_manager_base->bypass);
cm_wait_for_fsm();
}
/* function to write the ctrl register which requires a poll of the busy bit */
static inline void cm_write_ctrl(uint32_t val)
static void cm_write_ctrl(uint32_t val)
{
writel(val, &clock_manager_base->ctrl);
cm_wait_for_fsm();
}
/* function to write a clock register that has phase information */
static inline void cm_write_with_phase(uint32_t value,
uint32_t reg_address, uint32_t mask)
static void cm_write_with_phase(uint32_t value,
uint32_t reg_address, uint32_t mask)
{
/* poll until phase is zero */
while (readl(reg_address) & mask)
@ -128,24 +118,18 @@ void cm_basic_init(const cm_config_t *cfg)
writel(0, &clock_manager_base->per_pll.en);
/* Put all plls in bypass */
cm_write_bypass(
CLKMGR_BYPASS_PERPLLSRC_SET(
CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
CLKMGR_BYPASS_SDRPLLSRC_SET(
CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) |
CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) |
CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE));
cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
CLKMGR_BYPASS_MAINPLL);
/*
* Put all plls VCO registers back to reset value.
* Some code might have messed with them.
*/
writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
/* Put all plls VCO registers back to reset value. */
writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
&clock_manager_base->main_pll.vco);
writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
&clock_manager_base->per_pll.vco);
writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
&clock_manager_base->sdr_pll.vco);
/*
@ -170,19 +154,9 @@ void cm_basic_init(const cm_config_t *cfg)
* We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
* with numerator and denominator.
*/
writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN |
CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
&clock_manager_base->main_pll.vco);
writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN |
CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
&clock_manager_base->per_pll.vco);
writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN |
CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
&clock_manager_base->sdr_pll.vco);
writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
/*
* Time starts here
@ -217,6 +191,9 @@ void cm_basic_init(const cm_config_t *cfg)
writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
/* Peri pernandsdmmcclk */
writel(cfg->mainnandsdmmcclk,
&clock_manager_base->main_pll.mainnandsdmmcclk);
writel(cfg->pernandsdmmcclk,
&clock_manager_base->per_pll.pernandsdmmcclk);
@ -232,18 +209,16 @@ void cm_basic_init(const cm_config_t *cfg)
/* Enable vco */
/* main pll vco */
writel(cfg->main_vco_base | VCO_EN_BASE,
writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
&clock_manager_base->main_pll.vco);
/* periferal pll */
writel(cfg->peri_vco_base | VCO_EN_BASE,
writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
&clock_manager_base->per_pll.vco);
/* sdram pll vco */
writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
cfg->sdram_vco_base | VCO_EN_BASE,
&clock_manager_base->sdr_pll.vco);
writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
&clock_manager_base->sdr_pll.vco);
/* L3 MP and L3 SP */
writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
@ -294,8 +269,8 @@ void cm_basic_init(const cm_config_t *cfg)
&clock_manager_base->per_pll.vco);
/* assert sdram outresetall */
writel(cfg->sdram_vco_base | VCO_EN_BASE|
CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
&clock_manager_base->sdr_pll.vco);
/* deassert main outresetall */
@ -307,9 +282,8 @@ void cm_basic_init(const cm_config_t *cfg)
&clock_manager_base->per_pll.vco);
/* deassert sdram outresetall */
writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
cfg->sdram_vco_base | VCO_EN_BASE,
&clock_manager_base->sdr_pll.vco);
writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
&clock_manager_base->sdr_pll.vco);
/*
* now that we've toggled outreset all, all the clocks
@ -333,18 +307,10 @@ void cm_basic_init(const cm_config_t *cfg)
CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
/* Take all three PLLs out of bypass when safe mode is cleared. */
cm_write_bypass(
CLKMGR_BYPASS_PERPLLSRC_SET(
CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
CLKMGR_BYPASS_SDRPLLSRC_SET(
CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) |
CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) |
CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE));
cm_write_bypass(0);
/* clear safe mode */
cm_write_ctrl(readl(&clock_manager_base->ctrl) |
CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK));
cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
/*
* now that safe mode is clear with clocks gated
@ -357,4 +323,224 @@ void cm_basic_init(const cm_config_t *cfg)
writel(~0, &clock_manager_base->main_pll.en);
writel(~0, &clock_manager_base->per_pll.en);
writel(~0, &clock_manager_base->sdr_pll.en);
/* Clear the loss of lock bits (write 1 to clear) */
writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
CLKMGR_INTER_MAINPLLLOST_MASK,
&clock_manager_base->inter);
}
static unsigned int cm_get_main_vco_clk_hz(void)
{
uint32_t reg, clock;
/* get the main VCO clock */
reg = readl(&clock_manager_base->main_pll.vco);
clock = CONFIG_HPS_CLK_OSC1_HZ;
clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1;
return clock;
}
static unsigned int cm_get_per_vco_clk_hz(void)
{
uint32_t reg, clock = 0;
/* identify PER PLL clock source */
reg = readl(&clock_manager_base->per_pll.vco);
reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
if (reg == CLKMGR_VCO_SSRC_EOSC1)
clock = CONFIG_HPS_CLK_OSC1_HZ;
else if (reg == CLKMGR_VCO_SSRC_EOSC2)
clock = CONFIG_HPS_CLK_OSC2_HZ;
else if (reg == CLKMGR_VCO_SSRC_F2S)
clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
/* get the PER VCO clock */
reg = readl(&clock_manager_base->per_pll.vco);
clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1;
return clock;
}
unsigned long cm_get_mpu_clk_hz(void)
{
uint32_t reg, clock;
clock = cm_get_main_vco_clk_hz();
/* get the MPU clock */
reg = readl(&clock_manager_base->altera.mpuclk);
clock /= (reg + 1);
reg = readl(&clock_manager_base->main_pll.mpuclk);
clock /= (reg + 1);
return clock;
}
unsigned long cm_get_sdram_clk_hz(void)
{
uint32_t reg, clock = 0;
/* identify SDRAM PLL clock source */
reg = readl(&clock_manager_base->sdr_pll.vco);
reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
if (reg == CLKMGR_VCO_SSRC_EOSC1)
clock = CONFIG_HPS_CLK_OSC1_HZ;
else if (reg == CLKMGR_VCO_SSRC_EOSC2)
clock = CONFIG_HPS_CLK_OSC2_HZ;
else if (reg == CLKMGR_VCO_SSRC_F2S)
clock = CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
/* get the SDRAM VCO clock */
reg = readl(&clock_manager_base->sdr_pll.vco);
clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
/* get the SDRAM (DDR_DQS) clock */
reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
clock /= (reg + 1);
return clock;
}
unsigned int cm_get_l4_sp_clk_hz(void)
{
uint32_t reg, clock = 0;
/* identify the source of L4 SP clock */
reg = readl(&clock_manager_base->main_pll.l4src);
reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
clock = cm_get_main_vco_clk_hz();
/* get the clock prior L4 SP divider (main clk) */
reg = readl(&clock_manager_base->altera.mainclk);
clock /= (reg + 1);
reg = readl(&clock_manager_base->main_pll.mainclk);
clock /= (reg + 1);
} else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
clock = cm_get_per_vco_clk_hz();
/* get the clock prior L4 SP divider (periph_base_clk) */
reg = readl(&clock_manager_base->per_pll.perbaseclk);
clock /= (reg + 1);
}
/* get the L4 SP clock which supplied to UART */
reg = readl(&clock_manager_base->main_pll.maindiv);
reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
clock = clock / (1 << reg);
return clock;
}
unsigned int cm_get_mmc_controller_clk_hz(void)
{
uint32_t reg, clock = 0;
/* identify the source of MMC clock */
reg = readl(&clock_manager_base->per_pll.src);
reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
} else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
clock = cm_get_main_vco_clk_hz();
/* get the SDMMC clock */
reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
clock /= (reg + 1);
} else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
clock = cm_get_per_vco_clk_hz();
/* get the SDMMC clock */
reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
clock /= (reg + 1);
}
/* further divide by 4 as we have fixed divider at wrapper */
clock /= 4;
return clock;
}
unsigned int cm_get_qspi_controller_clk_hz(void)
{
uint32_t reg, clock = 0;
/* identify the source of QSPI clock */
reg = readl(&clock_manager_base->per_pll.src);
reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
} else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
clock = cm_get_main_vco_clk_hz();
/* get the qspi clock */
reg = readl(&clock_manager_base->main_pll.mainqspiclk);
clock /= (reg + 1);
} else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
clock = cm_get_per_vco_clk_hz();
/* get the qspi clock */
reg = readl(&clock_manager_base->per_pll.perqspiclk);
clock /= (reg + 1);
}
return clock;
}
static void cm_print_clock_quick_summary(void)
{
printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
printf("DDR %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
printf("EOSC1 %8d kHz\n", CONFIG_HPS_CLK_OSC1_HZ / 1000);
printf("EOSC2 %8d kHz\n", CONFIG_HPS_CLK_OSC2_HZ / 1000);
printf("F2S_SDR_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_SDR_REF_HZ / 1000);
printf("F2S_PER_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_PER_REF_HZ / 1000);
printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
printf("UART %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
}
int set_cpu_clk_info(void)
{
/* Calculate the clock frequencies required for drivers */
cm_get_l4_sp_clk_hz();
cm_get_mmc_controller_clk_hz();
gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
gd->bd->bi_dsp_freq = 0;
gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
return 0;
}
int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
cm_print_clock_quick_summary();
return 0;
}
U_BOOT_CMD(
clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks,
"display clocks",
""
);

78
arch/arm/cpu/armv7/socfpga/fpga_manager.c Normal file
View file

@ -0,0 +1,78 @@
/*
* Copyright (C) 2012 Altera Corporation <www.altera.com>
* All rights reserved.
*
* This file contains only support functions used also by the SoCFPGA
* platform code, the real meat is located in drivers/fpga/socfpga.c .
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/fpga_manager.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
DECLARE_GLOBAL_DATA_PTR;
/* Timeout count */
#define FPGA_TIMEOUT_CNT 0x1000000
static struct socfpga_fpga_manager *fpgamgr_regs =
(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
/* Check whether FPGA Init_Done signal is high */
static int is_fpgamgr_initdone_high(void)
{
unsigned long val;
val = readl(&fpgamgr_regs->gpio_ext_porta);
return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK;
}
/* Get the FPGA mode */
int fpgamgr_get_mode(void)
{
unsigned long val;
val = readl(&fpgamgr_regs->stat);
return val & FPGAMGRREGS_STAT_MODE_MASK;
}
/* Check whether FPGA is ready to be accessed */
int fpgamgr_test_fpga_ready(void)
{
/* Check for init done signal */
if (!is_fpgamgr_initdone_high())
return 0;
/* Check again to avoid false glitches */
if (!is_fpgamgr_initdone_high())
return 0;
if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE)
return 0;
return 1;
}
/* Poll until FPGA is ready to be accessed or timeout occurred */
int fpgamgr_poll_fpga_ready(void)
{
unsigned long i;
/* If FPGA is blank, wait till WD invoke warm reset */
for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
/* check for init done signal */
if (!is_fpgamgr_initdone_high())
continue;
/* check again to avoid false glitches */
if (!is_fpgamgr_initdone_high())
continue;
return 1;
}
return 0;
}

240
arch/arm/cpu/armv7/socfpga/misc.c
View file

@ -6,24 +6,103 @@
#include <common.h>
#include <asm/io.h>
#include <altera.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
#include <asm/arch/dwmmc.h>
#include <asm/arch/nic301.h>
#include <asm/arch/scu.h>
#include <asm/pl310.h>
DECLARE_GLOBAL_DATA_PTR;
static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
static struct socfpga_reset_manager *reset_manager_base =
(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
return 0;
}
void enable_caches(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF
icache_enable();
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
dcache_enable();
#endif
}
/*
* DesignWare Ethernet initialization
*/
#ifdef CONFIG_DESIGNWARE_ETH
int cpu_eth_init(bd_t *bis)
{
#if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
#elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
#else
#error "Incorrect CONFIG_EMAC_BASE value!"
#endif
/* Initialize EMAC. This needs to be done at least once per boot. */
/*
* Putting the EMAC controller to reset when configuring the PHY
* interface select at System Manager
*/
socfpga_emac_reset(1);
/* Clearing emac0 PHY interface select to 0 */
clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
/* configure to PHY interface select choosed */
setbits_le32(&sysmgr_regs->emacgrp_ctrl,
SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
/* Release the EMAC controller from reset */
socfpga_emac_reset(0);
/* initialize and register the emac */
return designware_initialize(CONFIG_EMAC_BASE,
CONFIG_PHY_INTERFACE_MODE);
}
#endif
#ifdef CONFIG_DWMMC
/*
* Initializes MMC controllers.
* to override, implement board_mmc_init()
*/
int cpu_mmc_init(bd_t *bis)
{
return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
CONFIG_HPS_SDMMC_BUSWIDTH, 0);
}
#endif
#if defined(CONFIG_DISPLAY_CPUINFO)
/*
* Print CPU information
*/
int print_cpuinfo(void)
{
puts("CPU : Altera SOCFPGA Platform\n");
puts("CPU: Altera SoCFPGA Platform\n");
return 0;
}
#endif
@ -36,22 +115,159 @@ int overwrite_console(void)
}
#endif
int misc_init_r(void)
#ifdef CONFIG_FPGA
/*
* FPGA programming support for SoC FPGA Cyclone V
*/
static Altera_desc altera_fpga[] = {
{
/* Family */
Altera_SoCFPGA,
/* Interface type */
fast_passive_parallel,
/* No limitation as additional data will be ignored */
-1,
/* No device function table */
NULL,
/* Base interface address specified in driver */
NULL,
/* No cookie implementation */
0
},
};
/* add device descriptor to FPGA device table */
static void socfpga_fpga_add(void)
{
int i;
fpga_init();
for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
fpga_add(fpga_altera, &altera_fpga[i]);
}
#else
static inline void socfpga_fpga_add(void) {}
#endif
int arch_cpu_init(void)
{
/*
* If the HW watchdog is NOT enabled, make sure it is not running,
* for example because it was enabled in the preloader. This might
* trigger a watchdog-triggered reboot of Linux kernel later.
*/
#ifndef CONFIG_HW_WATCHDOG
socfpga_watchdog_reset();
#endif
return 0;
}
/*
* DesignWare Ethernet initialization
* Convert all NIC-301 AMBA slaves from secure to non-secure
*/
int cpu_eth_init(bd_t *bis)
static void socfpga_nic301_slave_ns(void)
{
#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD)
/* initialize and register the emac */
return designware_initialize(CONFIG_EMAC_BASE,
CONFIG_PHY_INTERFACE_MODE);
#else
return 0;
#endif
writel(0x1, &nic301_regs->lwhps2fpgaregs);
writel(0x1, &nic301_regs->hps2fpgaregs);
writel(0x1, &nic301_regs->acp);
writel(0x1, &nic301_regs->rom);
writel(0x1, &nic301_regs->ocram);
writel(0x1, &nic301_regs->sdrdata);
}
static uint32_t iswgrp_handoff[8];
int misc_init_r(void)
{
int i;
for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
socfpga_bridges_reset(1);
socfpga_nic301_slave_ns();
/*
* Private components security:
* U-Boot : configure private timer, global timer and cpu component
* access as non secure for kernel stage (as required by Linux)
*/
setbits_le32(&scu_regs->sacr, 0xfff);
/* Configure the L2 controller to make SDRAM start at 0 */
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
writel(0x2, &nic301_regs->remap);
#else
writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
writel(0x1, &pl310->pl310_addr_filter_start);
#endif
/* Add device descriptor to FPGA device table */
socfpga_fpga_add();
return 0;
}
static void socfpga_sdram_apply_static_cfg(void)
{
const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c;
const uint32_t applymask = 0x8;
uint32_t val = readl(staticcfg) | applymask;
/*
* SDRAM staticcfg register specific:
* When applying the register setting, the CPU must not access
* SDRAM. Luckily for us, we can abuse i-cache here to help us
* circumvent the SDRAM access issue. The idea is to make sure
* that the code is in one full i-cache line by branching past
* it and back. Once it is in the i-cache, we execute the core
* of the code and apply the register settings.
*
* The code below uses 7 instructions, while the Cortex-A9 has
* 32-byte cachelines, thus the limit is 8 instructions total.
*/
asm volatile(
".align 5 \n"
" b 2f \n"
"1: str %0, [%1] \n"
" dsb \n"
" isb \n"
" b 3f \n"
"2: b 1b \n"
"3: nop \n"
: : "r"(val), "r"(staticcfg) : "memory", "cc");
}
int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
if (argc != 2)
return CMD_RET_USAGE;
argv++;
switch (*argv[0]) {
case 'e': /* Enable */
writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
socfpga_sdram_apply_static_cfg();
writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080);
writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
writel(iswgrp_handoff[1], &nic301_regs->remap);
break;
case 'd': /* Disable */
writel(0, &sysmgr_regs->fpgaintfgrp_module);
writel(0, SOCFPGA_SDR_ADDRESS + 0x5080);
socfpga_sdram_apply_static_cfg();
writel(0, &reset_manager_base->brg_mod_reset);
writel(1, &nic301_regs->remap);
break;
default:
return CMD_RET_USAGE;
}
return 0;
}
U_BOOT_CMD(
bridge, 2, 1, do_bridge,
"SoCFPGA HPS FPGA bridge control",
"enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
"bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
""
);

67
arch/arm/cpu/armv7/socfpga/reset_manager.c
View file

@ -8,12 +8,25 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/fpga_manager.h>
DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
void socfpga_watchdog_reset(void)
{
/* assert reset for watchdog */
setbits_le32(&reset_manager_base->per_mod_reset,
1 << RSTMGR_PERMODRST_L4WD0_LSB);
/* deassert watchdog from reset (watchdog in not running state) */
clrbits_le32(&reset_manager_base->per_mod_reset,
1 << RSTMGR_PERMODRST_L4WD0_LSB);
}
/*
* Write the reset manager register to cause reset
*/
@ -37,3 +50,57 @@ void reset_deassert_peripherals_handoff(void)
{
writel(0, &reset_manager_base->per_mod_reset);
}
#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
void socfpga_bridges_reset(int enable)
{
/* For SoCFPGA-VT, this is NOP. */
}
#else
#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
#define L3REGS_REMAP_HPS2FPGA_MASK 0x08
#define L3REGS_REMAP_OCRAM_MASK 0x01
void socfpga_bridges_reset(int enable)
{
const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
L3REGS_REMAP_HPS2FPGA_MASK |
L3REGS_REMAP_OCRAM_MASK;
if (enable) {
/* brdmodrst */
writel(0xffffffff, &reset_manager_base->brg_mod_reset);
} else {
/* Check signal from FPGA. */
if (fpgamgr_poll_fpga_ready()) {
/* FPGA not ready. Wait for watchdog timeout. */
printf("%s: fpga not ready, hanging.\n", __func__);
hang();
}
/* brdmodrst */
writel(0, &reset_manager_base->brg_mod_reset);
/* Remap the bridges into memory map */
writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
}
}
#endif
/* Change the reset state for EMAC 0 and EMAC 1 */
void socfpga_emac_reset(int enable)
{
const void *reset = &reset_manager_base->per_mod_reset;
if (enable) {
setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
} else {
#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
#endif
}
}

174
arch/arm/cpu/armv7/socfpga/spl.c
View file

@ -19,6 +19,31 @@
DECLARE_GLOBAL_DATA_PTR;
#define MAIN_VCO_BASE ( \
(CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \
CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \
(CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \
CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \
)
#define PERI_VCO_BASE ( \
(CONFIG_HPS_PERPLLGRP_VCO_PSRC << \
CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \
(CONFIG_HPS_PERPLLGRP_VCO_DENOM << \
CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \
(CONFIG_HPS_PERPLLGRP_VCO_NUMER << \
CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \
)
#define SDR_VCO_BASE ( \
(CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \
CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \
(CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \
CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \
(CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \
CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \
)
u32 spl_boot_device(void)
{
return BOOT_DEVICE_RAM;
@ -33,86 +58,87 @@ void spl_board_init(void)
cm_config_t cm_default_cfg = {
/* main group */
MAIN_VCO_BASE,
CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(
CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT),
CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(
CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT),
CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(
CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT),
CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(
CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT),
CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT),
CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(
CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT),
CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(
CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) |
CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(
CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) |
CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(
CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) |
CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(
CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK),
CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(
CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) |
CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(
CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK),
CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(
CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK),
CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(
CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) |
CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(
CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP),
(CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
(CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
(CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
(CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
(CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
(CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
(CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
(CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
(CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
/* peripheral group */
PERI_VCO_BASE,
CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(
CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT),
CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(
CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT),
CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(
CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT),
CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT),
CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(
CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT),
CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(
CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT),
CLKMGR_PERPLLGRP_DIV_USBCLK_SET(
CONFIG_HPS_PERPLLGRP_DIV_USBCLK) |
CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(
CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) |
CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(
CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) |
CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(
CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK),
CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(
CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK),
CLKMGR_PERPLLGRP_SRC_QSPI_SET(
CONFIG_HPS_PERPLLGRP_SRC_QSPI) |
CLKMGR_PERPLLGRP_SRC_NAND_SET(
CONFIG_HPS_PERPLLGRP_SRC_NAND) |
CLKMGR_PERPLLGRP_SRC_SDMMC_SET(
CONFIG_HPS_PERPLLGRP_SRC_SDMMC),
(CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
(CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
(CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
(CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
(CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
(CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
(CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
(CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
(CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
(CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
(CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
(CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
(CONFIG_HPS_PERPLLGRP_SRC_NAND <<
CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
(CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
/* sdram pll group */
SDR_VCO_BASE,
CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(
CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) |
CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(
CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT),
CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(
CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) |
CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(
CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT),
CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(
CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) |
CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(
CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT),
CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(
CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) |
CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(
CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT),
(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
};
debug("Freezing all I/O banks\n");

57
arch/arm/cpu/armv7/socfpga/system_manager.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (C) 2013 Altera Corporation <www.altera.com>
* Copyright (C) 2013 Altera Corporation <www.altera.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -7,21 +7,62 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/system_manager.h>
#include <asm/arch/fpga_manager.h>
DECLARE_GLOBAL_DATA_PTR;
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
/*
* Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
* The value is not wrote to SYSMGR.FPGAINTF.MODULE but
* CONFIG_SYSMGR_ISWGRP_HANDOFF.
*/
static void populate_sysmgr_fpgaintf_module(void)
{
uint32_t handoff_val = 0;
/* ISWGRP_HANDOFF_FPGAINTF */
writel(0, &sysmgr_regs->iswgrp_handoff[2]);
/* Enable the signal for those HPS peripherals that use FPGA. */
if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
handoff_val |= SYSMGR_FPGAINTF_NAND;
if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
handoff_val |= SYSMGR_FPGAINTF_EMAC1;
if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
handoff_val |= SYSMGR_FPGAINTF_SDMMC;
if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
handoff_val |= SYSMGR_FPGAINTF_EMAC0;
if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
handoff_val |= SYSMGR_FPGAINTF_SPIM0;
if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
handoff_val |= SYSMGR_FPGAINTF_SPIM1;
/* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE
based on pinmux setting */
setbits_le32(&sysmgr_regs->iswgrp_handoff[2], handoff_val);
handoff_val = readl(&sysmgr_regs->iswgrp_handoff[2]);
if (fpgamgr_test_fpga_ready()) {
/* Enable the required signals only */
writel(handoff_val, &sysmgr_regs->fpgaintfgrp_module);
}
}
/*
* Configure all the pin muxes
*/
void sysmgr_pinmux_init(void)
{
unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET;
uint32_t regs = (uint32_t)&sysmgr_regs->emacio[0];
int i;
const unsigned long *pval = sys_mgr_init_table;
unsigned long i;
for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table);
i++, offset += sizeof(unsigned long)) {
writel(*pval++, (SOCFPGA_SYSMGR_ADDRESS + offset));
for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table); i++) {
writel(sys_mgr_init_table[i], regs);
regs += sizeof(regs);
}
populate_sysmgr_fpgaintf_module();
}

2
arch/arm/cpu/armv7/socfpga/timer.c
View file

@ -8,6 +8,8 @@
#include <asm/io.h>
#include <asm/arch/timer.h>
#define TIMER_LOAD_VAL 0xFFFFFFFF
static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
/*

10
arch/arm/include/asm/arch-keystone/clock_defs.h
View file

@ -102,10 +102,10 @@ static struct pllctl_regs *pllctl_regs[] = {
#define PLL_BWADJ_LO_SMASK (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT)
#define PLL_BWADJ_HI_MASK 0xf
#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0)
#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0)
#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 1)
#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 4)
#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 17)
#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0x0)
#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0x0)
#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 0x1)
#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 0x4)
#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 0x17)
#endif /* _CLOCK_DEFS_H_ */

300
arch/arm/include/asm/arch-socfpga/clock_manager.h
View file

@ -7,6 +7,15 @@
#ifndef _CLOCK_MANAGER_H_
#define _CLOCK_MANAGER_H_
#ifndef __ASSEMBLER__
/* Clock speed accessors */
unsigned long cm_get_mpu_clk_hz(void);
unsigned long cm_get_sdram_clk_hz(void);
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
#endif
typedef struct {
/* main group */
uint32_t main_vco_base;
@ -89,6 +98,11 @@ struct socfpga_clock_manager_sdr_pll {
u32 stat;
};
struct socfpga_clock_manager_altera {
u32 mpuclk;
u32 mainclk;
};
struct socfpga_clock_manager {
u32 ctrl;
u32 bypass;
@ -100,112 +114,194 @@ struct socfpga_clock_manager {
struct socfpga_clock_manager_main_pll main_pll;
struct socfpga_clock_manager_per_pll per_pll;
struct socfpga_clock_manager_sdr_pll sdr_pll;
u32 _pad_0xe0_0x200[72];
struct socfpga_clock_manager_altera altera;
u32 _pad_0xe8_0x200[70];
};
#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070)
#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380)
#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001)
#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002)
#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030)
#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c)
#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003)
#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004)
#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002)
#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001)
#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000)
#define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
#define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000)
#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000)
#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) \
(((x) << 0) & 0x000001ff)
#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) \
(((x) << 0) & 0x000001ff)
#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c)
#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003)
#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007)
#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003)
#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c)
#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008)
#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002)
#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001)
#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007)
#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0)
#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00)
#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001
#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001)
#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff)
#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010)
#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004)
#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00
#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00
#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00
#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
#define CLKMGR_CTRL_SAFEMODE (1 << 0)
#define CLKMGR_CTRL_SAFEMODE_OFFSET 0
#define MAIN_VCO_BASE \
(CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) | \
CLKMGR_MAINPLLGRP_VCO_NUMER_SET(CONFIG_HPS_MAINPLLGRP_VCO_NUMER))
#define CLKMGR_BYPASS_PERPLLSRC (1 << 4)
#define CLKMGR_BYPASS_PERPLLSRC_OFFSET 4
#define CLKMGR_BYPASS_PERPLL (1 << 3)
#define CLKMGR_BYPASS_PERPLL_OFFSET 3
#define CLKMGR_BYPASS_SDRPLLSRC (1 << 2)
#define CLKMGR_BYPASS_SDRPLLSRC_OFFSET 2
#define CLKMGR_BYPASS_SDRPLL (1 << 1)
#define CLKMGR_BYPASS_SDRPLL_OFFSET 1
#define CLKMGR_BYPASS_MAINPLL (1 << 0)
#define CLKMGR_BYPASS_MAINPLL_OFFSET 0
#define PERI_VCO_BASE \
(CLKMGR_PERPLLGRP_VCO_PSRC_SET(CONFIG_HPS_PERPLLGRP_VCO_PSRC) | \
CLKMGR_PERPLLGRP_VCO_DENOM_SET(CONFIG_HPS_PERPLLGRP_VCO_DENOM) | \
CLKMGR_PERPLLGRP_VCO_NUMER_SET(CONFIG_HPS_PERPLLGRP_VCO_NUMER))
#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000010
#define CLKMGR_INTER_SDRPLLLOST_MASK 0x00000020
#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000008
#define SDR_VCO_BASE \
(CLKMGR_SDRPLLGRP_VCO_SSRC_SET(CONFIG_HPS_SDRPLLGRP_VCO_SSRC) | \
CLKMGR_SDRPLLGRP_VCO_DENOM_SET(CONFIG_HPS_SDRPLLGRP_VCO_DENOM) | \
CLKMGR_SDRPLLGRP_VCO_NUMER_SET(CONFIG_HPS_SDRPLLGRP_VCO_NUMER))
#define CLKMGR_STAT_BUSY (1 << 0)
/* Main PLL */
#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN (1 << 0)
#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0
#define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET 16
#define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000
#define CLKMGR_MAINPLLGRP_VCO_EN (1 << 1)
#define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET 1
#define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET 3
#define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8
#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
#define CLKMGR_MAINPLLGRP_VCO_PWRDN (1 << 2)
#define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET 2
#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET 0
#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK 0x000001ff
#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET 0
#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK 0x000001ff
#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET 0
#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK 0x000001ff
#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET 0
#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK 0x000001ff
#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET 0
#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK 0x000001ff
#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET 0
#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK 0x000001ff
#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET 0
#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK 0x00000003
#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET 2
#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK 0x0000000c
#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET 4
#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK 0x00000070
#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET 7
#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK 0x00000380
#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET 0
#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK 0x00000003
#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET 2
#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK 0x0000000c
#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET 0
#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK 0x00000007
#define CLKMGR_MAINPLLGRP_L4SRC_L4MP (1 << 0)
#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET 0
#define CLKMGR_MAINPLLGRP_L4SRC_L4SP (1 << 1)
#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1
#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
#define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0
#define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1
/* Per PLL */
#define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET 16
#define CLKMGR_PERPLLGRP_VCO_DENOM_MASK 0x003f0000
#define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET 3
#define CLKMGR_PERPLLGRP_VCO_NUMER_MASK 0x0000fff8
#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
#define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET 22
#define CLKMGR_PERPLLGRP_VCO_PSRC_MASK 0x00c00000
#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
#define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET 22
#define CLKMGR_PERPLLGRP_VCO_SSRC_MASK 0x00c00000
#define CLKMGR_VCO_SSRC_EOSC1 0x0
#define CLKMGR_VCO_SSRC_EOSC2 0x1
#define CLKMGR_VCO_SSRC_F2S 0x2
#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET 0
#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK 0x000001ff
#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET 0
#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK 0x000001ff
#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET 0
#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK 0x000001ff
#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET 0
#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK 0x000001ff
#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET 0
#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK 0x000001ff
#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET 0
#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK 0x000001ff
#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100
#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET 6
#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK 0x000001c0
#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET 9
#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK 0x00000e00
#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3
#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3
#define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET 0
#define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK 0x00000007
#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET 0
#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK 0x00ffffff
#define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET 2
#define CLKMGR_PERPLLGRP_SRC_NAND_MASK 0x0000000c
#define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET 4
#define CLKMGR_PERPLLGRP_SRC_QSPI_MASK 0x00000030
#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
#define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET 0
#define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK 0x00000003
#define CLKMGR_SDMMC_CLK_SRC_F2S 0x0
#define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1
#define CLKMGR_SDMMC_CLK_SRC_PER 0x2
#define CLKMGR_QSPI_CLK_SRC_F2S 0x0
#define CLKMGR_QSPI_CLK_SRC_MAIN 0x1
#define CLKMGR_QSPI_CLK_SRC_PER 0x2
/* SDR PLL */
#define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET 16
#define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK 0x003f0000
#define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET 3
#define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK 0x0000fff8
#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL (1 << 24)
#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET 24
#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET 25
#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
#define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET 22
#define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK 0x00c00000
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET 9
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x00000e00
#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET 0
#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET 9
#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x00000e00
#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET 0
#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET 9
#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x00000e00
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET 0
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x00000e00
#endif /* _CLOCK_MANAGER_H_ */

77
arch/arm/include/asm/arch-socfpga/fpga_manager.h Normal file
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@ -0,0 +1,77 @@
/*
* Copyright (C) 2012 Altera Corporation <www.altera.com>
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FPGA_MANAGER_H_
#define _FPGA_MANAGER_H_
#include <altera.h>
struct socfpga_fpga_manager {
/* FPGA Manager Module */
u32 stat; /* 0x00 */
u32 ctrl;
u32 dclkcnt;
u32 dclkstat;
u32 gpo; /* 0x10 */
u32 gpi;
u32 misci; /* 0x18 */
u32 _pad_0x1c_0x82c[517];
/* Configuration Monitor (MON) Registers */
u32 gpio_inten; /* 0x830 */
u32 gpio_intmask;
u32 gpio_inttype_level;
u32 gpio_int_polarity;
u32 gpio_intstatus; /* 0x840 */
u32 gpio_raw_intstatus;
u32 _pad_0x848;
u32 gpio_porta_eoi;
u32 gpio_ext_porta; /* 0x850 */
u32 _pad_0x854_0x85c[3];
u32 gpio_1s_sync; /* 0x860 */
u32 _pad_0x864_0x868[2];
u32 gpio_ver_id_code;
u32 gpio_config_reg2; /* 0x870 */
u32 gpio_config_reg1;
};
#define FPGAMGRREGS_STAT_MODE_MASK 0x7
#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
#define FPGAMGRREGS_STAT_MSEL_LSB 3
#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200
#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4
#define FPGAMGRREGS_CTRL_NCE_MASK 0x2
#define FPGAMGRREGS_CTRL_EN_MASK 0x1
#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8
#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
/* FPGA Mode */
#define FPGAMGRREGS_MODE_FPGAOFF 0x0
#define FPGAMGRREGS_MODE_RESETPHASE 0x1
#define FPGAMGRREGS_MODE_CFGPHASE 0x2
#define FPGAMGRREGS_MODE_INITPHASE 0x3
#define FPGAMGRREGS_MODE_USERMODE 0x4
#define FPGAMGRREGS_MODE_UNKNOWN 0x5
/* FPGA CD Ratio Value */
#define CDRATIO_x1 0x0
#define CDRATIO_x2 0x1
#define CDRATIO_x4 0x2
#define CDRATIO_x8 0x3
/* SoCFPGA support functions */
int fpgamgr_test_fpga_ready(void);
int fpgamgr_poll_fpga_ready(void);
int fpgamgr_get_mode(void);
#endif /* _FPGA_MANAGER_H_ */

195
arch/arm/include/asm/arch-socfpga/nic301.h Normal file
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@ -0,0 +1,195 @@
/*
* Copyright (C) 2014 Marek Vasut <marex@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _NIC301_REGISTERS_H_
#define _NIC301_REGISTERS_H_
struct nic301_registers {
u32 remap; /* 0x0 */
/* Security Register Group */
u32 _pad_0x4_0x8[1];
u32 l4main;
u32 l4sp;
u32 l4mp; /* 0x10 */
u32 l4osc1;
u32 l4spim;
u32 stm;
u32 lwhps2fpgaregs; /* 0x20 */
u32 _pad_0x24_0x28[1];
u32 usb1;
u32 nanddata;
u32 _pad_0x30_0x80[20];
u32 usb0; /* 0x80 */
u32 nandregs;
u32 qspidata;
u32 fpgamgrdata;
u32 hps2fpgaregs; /* 0x90 */
u32 acp;
u32 rom;
u32 ocram;
u32 sdrdata; /* 0xA0 */
u32 _pad_0xa4_0x1fd0[1995];
/* ID Register Group */
u32 periph_id_4; /* 0x1FD0 */
u32 _pad_0x1fd4_0x1fe0[3];
u32 periph_id_0; /* 0x1FE0 */
u32 periph_id_1;
u32 periph_id_2;
u32 periph_id_3;
u32 comp_id_0; /* 0x1FF0 */
u32 comp_id_1;
u32 comp_id_2;
u32 comp_id_3;
u32 _pad_0x2000_0x2008[2];
/* L4 MAIN */
u32 l4main_fn_mod_bm_iss;
u32 _pad_0x200c_0x3008[1023];
/* L4 SP */
u32 l4sp_fn_mod_bm_iss;
u32 _pad_0x300c_0x4008[1023];
/* L4 MP */
u32 l4mp_fn_mod_bm_iss;
u32 _pad_0x400c_0x5008[1023];
/* L4 OSC1 */
u32 l4osc_fn_mod_bm_iss;
u32 _pad_0x500c_0x6008[1023];
/* L4 SPIM */
u32 l4spim_fn_mod_bm_iss;
u32 _pad_0x600c_0x7008[1023];
/* STM */
u32 stm_fn_mod_bm_iss;
u32 _pad_0x700c_0x7108[63];
u32 stm_fn_mod;
u32 _pad_0x710c_0x8008[959];
/* LWHPS2FPGA */
u32 lwhps2fpga_fn_mod_bm_iss;
u32 _pad_0x800c_0x8108[63];
u32 lwhps2fpga_fn_mod;
u32 _pad_0x810c_0xa008[1983];
/* USB1 */
u32 usb1_fn_mod_bm_iss;
u32 _pad_0xa00c_0xa044[14];
u32 usb1_ahb_cntl;
u32 _pad_0xa048_0xb008[1008];
/* NANDDATA */
u32 nanddata_fn_mod_bm_iss;
u32 _pad_0xb00c_0xb108[63];
u32 nanddata_fn_mod;
u32 _pad_0xb10c_0x20008[21439];
/* USB0 */
u32 usb0_fn_mod_bm_iss;
u32 _pad_0x2000c_0x20044[14];
u32 usb0_ahb_cntl;
u32 _pad_0x20048_0x21008[1008];
/* NANDREGS */
u32 nandregs_fn_mod_bm_iss;
u32 _pad_0x2100c_0x21108[63];
u32 nandregs_fn_mod;
u32 _pad_0x2110c_0x22008[959];
/* QSPIDATA */
u32 qspidata_fn_mod_bm_iss;
u32 _pad_0x2200c_0x22044[14];
u32 qspidata_ahb_cntl;
u32 _pad_0x22048_0x23008[1008];
/* FPGAMGRDATA */
u32 fpgamgrdata_fn_mod_bm_iss;
u32 _pad_0x2300c_0x23040[13];
u32 fpgamgrdata_wr_tidemark; /* 0x23040 */
u32 _pad_0x23044_0x23108[49];
u32 fn_mod;
u32 _pad_0x2310c_0x24008[959];
/* HPS2FPGA */
u32 hps2fpga_fn_mod_bm_iss;
u32 _pad_0x2400c_0x24040[13];
u32 hps2fpga_wr_tidemark; /* 0x24040 */
u32 _pad_0x24044_0x24108[49];
u32 hps2fpga_fn_mod;
u32 _pad_0x2410c_0x25008[959];
/* ACP */
u32 acp_fn_mod_bm_iss;
u32 _pad_0x2500c_0x25108[63];
u32 acp_fn_mod;
u32 _pad_0x2510c_0x26008[959];
/* Boot ROM */
u32 bootrom_fn_mod_bm_iss;
u32 _pad_0x2600c_0x26108[63];
u32 bootrom_fn_mod;
u32 _pad_0x2610c_0x27008[959];
/* On-chip RAM */
u32 ocram_fn_mod_bm_iss;
u32 _pad_0x2700c_0x27040[13];
u32 ocram_wr_tidemark; /* 0x27040 */
u32 _pad_0x27044_0x27108[49];
u32 ocram_fn_mod;
u32 _pad_0x2710c_0x42024[27590];
/* DAP */
u32 dap_fn_mod2;
u32 dap_fn_mod_ahb;
u32 _pad_0x4202c_0x42100[53];
u32 dap_read_qos; /* 0x42100 */
u32 dap_write_qos;
u32 dap_fn_mod;
u32 _pad_0x4210c_0x43100[1021];
/* MPU */
u32 mpu_read_qos; /* 0x43100 */
u32 mpu_write_qos;
u32 mpu_fn_mod;
u32 _pad_0x4310c_0x44028[967];
/* SDMMC */
u32 sdmmc_fn_mod_ahb;
u32 _pad_0x4402c_0x44100[53];
u32 sdmmc_read_qos; /* 0x44100 */
u32 sdmmc_write_qos;
u32 sdmmc_fn_mod;
u32 _pad_0x4410c_0x45100[1021];
/* DMA */
u32 dma_read_qos; /* 0x45100 */
u32 dma_write_qos;
u32 dma_fn_mod;
u32 _pad_0x4510c_0x46040[973];
/* FPGA2HPS */
u32 fpga2hps_wr_tidemark; /* 0x46040 */
u32 _pad_0x46044_0x46100[47];
u32 fpga2hps_read_qos; /* 0x46100 */
u32 fpga2hps_write_qos;
u32 fpga2hps_fn_mod;
u32 _pad_0x4610c_0x47100[1021];
/* ETR */
u32 etr_read_qos; /* 0x47100 */
u32 etr_write_qos;
u32 etr_fn_mod;
u32 _pad_0x4710c_0x48100[1021];
/* EMAC0 */
u32 emac0_read_qos; /* 0x48100 */
u32 emac0_write_qos;
u32 emac0_fn_mod;
u32 _pad_0x4810c_0x49100[1021];
/* EMAC1 */
u32 emac1_read_qos; /* 0x49100 */
u32 emac1_write_qos;
u32 emac1_fn_mod;
u32 _pad_0x4910c_0x4a028[967];
/* USB0 */
u32 usb0_fn_mod_ahb;
u32 _pad_0x4a02c_0x4a100[53];
u32 usb0_read_qos; /* 0x4A100 */
u32 usb0_write_qos;
u32 usb0_fn_mod;
u32 _pad_0x4a10c_0x4b100[1021];
/* NAND */
u32 nand_read_qos; /* 0x4B100 */
u32 nand_write_qos;
u32 nand_fn_mod;
u32 _pad_0x4b10c_0x4c028[967];
/* USB1 */
u32 usb1_fn_mod_ahb;
u32 _pad_0x4c02c_0x4c100[53];
u32 usb1_read_qos; /* 0x4C100 */
u32 usb1_write_qos;
u32 usb1_fn_mod;
};
#endif /* _NIC301_REGISTERS_H_ */

9
arch/arm/include/asm/arch-socfpga/reset_manager.h
View file

@ -10,6 +10,11 @@
void reset_cpu(ulong addr);
void reset_deassert_peripherals_handoff(void);
void socfpga_bridges_reset(int enable);
void socfpga_emac_reset(int enable);
void socfpga_watchdog_reset(void);
struct socfpga_reset_manager {
u32 status;
u32 ctrl;
@ -27,4 +32,8 @@ struct socfpga_reset_manager {
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
#endif
#define RSTMGR_PERMODRST_EMAC0_LSB 0
#define RSTMGR_PERMODRST_EMAC1_LSB 1
#define RSTMGR_PERMODRST_L4WD0_LSB 6
#endif /* _RESET_MANAGER_H_ */

23
arch/arm/include/asm/arch-socfpga/scu.h Normal file
View file

@ -0,0 +1,23 @@
/*
* Copyright (C) 2014 Marek Vasut <marex@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __SOCFPGA_SCU_H__
#define __SOCFPGA_SCU_H__
struct scu_registers {
u32 ctrl; /* 0x00 */
u32 cfg;
u32 cpsr;
u32 iassr;
u32 _pad_0x10_0x3c[12]; /* 0x10 */
u32 fsar; /* 0x40 */
u32 fear;
u32 _pad_0x48_0x50[2];
u32 acr; /* 0x54 */
u32 sacr;
};
#endif /* __SOCFPGA_SCU_H__ */

62
arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
View file

@ -7,16 +7,56 @@
#ifndef _SOCFPGA_BASE_ADDRS_H_
#define _SOCFPGA_BASE_ADDRS_H_
#define SOCFPGA_L3REGS_ADDRESS 0xff800000
#define SOCFPGA_UART0_ADDRESS 0xffc02000
#define SOCFPGA_UART1_ADDRESS 0xffc03000
#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
#define SOCFPGA_L4WD0_ADDRESS 0xffd02000
#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000
#define SOCFPGA_EMAC0_ADDRESS 0xff700000
#define SOCFPGA_EMAC1_ADDRESS 0xff702000
#define SOCFPGA_STM_ADDRESS 0xfc000000
#define SOCFPGA_DAP_ADDRESS 0xff000000
#define SOCFPGA_EMAC0_ADDRESS 0xff700000
#define SOCFPGA_EMAC1_ADDRESS 0xff702000
#define SOCFPGA_SDMMC_ADDRESS 0xff704000
#define SOCFPGA_QSPI_ADDRESS 0xff705000
#define SOCFPGA_GPIO0_ADDRESS 0xff708000
#define SOCFPGA_GPIO1_ADDRESS 0xff709000
#define SOCFPGA_GPIO2_ADDRESS 0xff70a000
#define SOCFPGA_L3REGS_ADDRESS 0xff800000
#define SOCFPGA_USB0_ADDRESS 0xffb00000
#define SOCFPGA_USB1_ADDRESS 0xffb40000
#define SOCFPGA_CAN0_ADDRESS 0xffc00000
#define SOCFPGA_CAN1_ADDRESS 0xffc01000
#define SOCFPGA_UART0_ADDRESS 0xffc02000
#define SOCFPGA_UART1_ADDRESS 0xffc03000
#define SOCFPGA_I2C0_ADDRESS 0xffc04000
#define SOCFPGA_I2C1_ADDRESS 0xffc05000
#define SOCFPGA_I2C2_ADDRESS 0xffc06000
#define SOCFPGA_I2C3_ADDRESS 0xffc07000
#define SOCFPGA_SDR_ADDRESS 0xffc20000
#define SOCFPGA_L4WD0_ADDRESS 0xffd02000
#define SOCFPGA_L4WD1_ADDRESS 0xffd03000
#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
#define SOCFPGA_SPIS0_ADDRESS 0xffe02000
#define SOCFPGA_SPIS1_ADDRESS 0xffe03000
#define SOCFPGA_SPIM0_ADDRESS 0xfff00000
#define SOCFPGA_SPIM1_ADDRESS 0xfff01000
#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000
#define SOCFPGA_ROM_ADDRESS 0xfffd0000
#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000
#define SOCFPGA_MPUL2_ADDRESS 0xfffef000
#define SOCFPGA_OCRAM_ADDRESS 0xffff0000
#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff200000
#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff400000
#define SOCFPGA_HPS2FPGAREGS_ADDRESS 0xff500000
#define SOCFPGA_FPGA2HPSREGS_ADDRESS 0xff600000
#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000
#define SOCFPGA_ACPIDMAP_ADDRESS 0xff707000
#define SOCFPGA_NANDDATA_ADDRESS 0xff900000
#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000
#define SOCFPGA_NANDREGS_ADDRESS 0xffb80000
#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb90000
#define SOCFPGA_SPTIMER0_ADDRESS 0xffc08000
#define SOCFPGA_SPTIMER1_ADDRESS 0xffc09000
#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd01000
#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000
#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000
#endif /* _SOCFPGA_BASE_ADDRS_H_ */

111
arch/arm/include/asm/arch-socfpga/system_manager.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (C) 2013 Altera Corporation <www.altera.com>
* Copyright (C) 2013 Altera Corporation <www.altera.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -16,72 +16,131 @@ extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM];
#endif
#define CONFIG_SYSMGR_PINMUXGRP_OFFSET (0x400)
#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
struct socfpga_system_manager {
u32 siliconid1;
/* System Manager Module */
u32 siliconid1; /* 0x00 */
u32 siliconid2;
u32 _pad_0x8_0xf[2];
u32 wddbg;
u32 wddbg; /* 0x10 */
u32 bootinfo;
u32 hpsinfo;
u32 parityinj;
u32 fpgaintfgrp_gbl;
/* FPGA Interface Group */
u32 fpgaintfgrp_gbl; /* 0x20 */
u32 fpgaintfgrp_indiv;
u32 fpgaintfgrp_module;
u32 _pad_0x2c_0x2f;
u32 scanmgrgrp_ctrl;
/* Scan Manager Group */
u32 scanmgrgrp_ctrl; /* 0x30 */
u32 _pad_0x34_0x3f[3];
u32 frzctrl_vioctrl;
/* Freeze Control Group */
u32 frzctrl_vioctrl; /* 0x40 */
u32 _pad_0x44_0x4f[3];
u32 frzctrl_hioctrl;
u32 frzctrl_hioctrl; /* 0x50 */
u32 frzctrl_src;
u32 frzctrl_hwctrl;
u32 _pad_0x5c_0x5f;
u32 emacgrp_ctrl;
/* EMAC Group */
u32 emacgrp_ctrl; /* 0x60 */
u32 emacgrp_l3master;
u32 _pad_0x68_0x6f[2];
u32 dmagrp_ctrl;
/* DMA Controller Group */
u32 dmagrp_ctrl; /* 0x70 */
u32 dmagrp_persecurity;
u32 _pad_0x78_0x7f[2];
u32 iswgrp_handoff[8];
u32 _pad_0xa0_0xbf[8];
u32 romcodegrp_ctrl;
/* Preloader (initial software) Group */
u32 iswgrp_handoff[8]; /* 0x80 */
u32 _pad_0xa0_0xbf[8]; /* 0xa0 */
/* Boot ROM Code Register Group */
u32 romcodegrp_ctrl; /* 0xc0 */
u32 romcodegrp_cpu1startaddr;
u32 romcodegrp_initswstate;
u32 romcodegrp_initswlastld;
u32 romcodegrp_bootromswstate;
u32 romcodegrp_bootromswstate; /* 0xd0 */
u32 __pad_0xd4_0xdf[3];
u32 romcodegrp_warmramgrp_enable;
/* Warm Boot from On-Chip RAM Group */
u32 romcodegrp_warmramgrp_enable; /* 0xe0 */
u32 romcodegrp_warmramgrp_datastart;
u32 romcodegrp_warmramgrp_length;
u32 romcodegrp_warmramgrp_execution;
u32 romcodegrp_warmramgrp_crc;
u32 romcodegrp_warmramgrp_crc; /* 0xf0 */
u32 __pad_0xf4_0xff[3];
u32 romhwgrp_ctrl;
/* Boot ROM Hardware Register Group */
u32 romhwgrp_ctrl; /* 0x100 */
u32 _pad_0x104_0x107;
/* SDMMC Controller Group */
u32 sdmmcgrp_ctrl;
u32 sdmmcgrp_l3master;
u32 nandgrp_bootstrap;
/* NAND Flash Controller Register Group */
u32 nandgrp_bootstrap; /* 0x110 */
u32 nandgrp_l3master;
/* USB Controller Group */
u32 usbgrp_l3master;
u32 _pad_0x11c_0x13f[9];
u32 eccgrp_l2;
/* ECC Management Register Group */
u32 eccgrp_l2; /* 0x140 */
u32 eccgrp_ocram;
u32 eccgrp_usb0;
u32 eccgrp_usb1;
u32 eccgrp_emac0;
u32 eccgrp_emac0; /* 0x150 */
u32 eccgrp_emac1;
u32 eccgrp_dma;
u32 eccgrp_can0;
u32 eccgrp_can1;
u32 eccgrp_can1; /* 0x160 */
u32 eccgrp_nand;
u32 eccgrp_qspi;
u32 eccgrp_sdmmc;
u32 _pad_0x170_0x3ff[164];
/* Pin Mux Control Group */
u32 emacio[20]; /* 0x400 */
u32 flashio[12]; /* 0x450 */
u32 generalio[28]; /* 0x480 */
u32 _pad_0x4f0_0x4ff[4];
u32 mixed1io[22]; /* 0x500 */
u32 mixed2io[8]; /* 0x558 */
u32 gplinmux[23]; /* 0x578 */
u32 gplmux[71]; /* 0x5d4 */
u32 nandusefpga; /* 0x6f0 */
u32 _pad_0x6f4;
u32 rgmii1usefpga; /* 0x6f8 */
u32 _pad_0x6fc_0x700[2];
u32 i2c0usefpga; /* 0x704 */
u32 sdmmcusefpga; /* 0x708 */
u32 _pad_0x70c_0x710[2];
u32 rgmii0usefpga; /* 0x714 */
u32 _pad_0x718_0x720[3];
u32 i2c3usefpga; /* 0x724 */
u32 i2c2usefpga; /* 0x728 */
u32 i2c1usefpga; /* 0x72c */
u32 spim1usefpga; /* 0x730 */
u32 _pad_0x734;
u32 spim0usefpga; /* 0x738 */
};
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX (1 << 0)
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO (1 << 1)
#define SYSMGR_ECC_OCRAM_EN (1 << 0)
#define SYSMGR_ECC_OCRAM_SERR (1 << 3)
#define SYSMGR_ECC_OCRAM_DERR (1 << 4)
#define SYSMGR_FPGAINTF_USEFPGA 0x1
#define SYSMGR_FPGAINTF_SPIM0 (1 << 0)
#define SYSMGR_FPGAINTF_SPIM1 (1 << 1)
#define SYSMGR_FPGAINTF_EMAC0 (1 << 2)
#define SYSMGR_FPGAINTF_EMAC1 (1 << 3)
#define SYSMGR_FPGAINTF_NAND (1 << 4)
#define SYSMGR_FPGAINTF_SDMMC (1 << 5)
/* FIXME: This is questionable macro. */
#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
/* EMAC Group Bit definitions */
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3
#endif /* _SYSTEM_MANAGER_H_ */

1
arch/arm/include/asm/system.h
View file

@ -185,6 +185,7 @@ enum dcache_option {
DCACHE_OFF = 0x12,
DCACHE_WRITETHROUGH = 0x1a,
DCACHE_WRITEBACK = 0x1e,
DCACHE_WRITEALLOC = 0x16,
};
/* Size of an MMU section */

2
arch/arm/lib/cache-cp15.c
View file

@ -73,6 +73,8 @@ __weak void dram_bank_mmu_setup(int bank)
i++) {
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
set_section_dcache(i, DCACHE_WRITETHROUGH);
#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
set_section_dcache(i, DCACHE_WRITEALLOC);
#else
set_section_dcache(i, DCACHE_WRITEBACK);
#endif

8
arch/powerpc/cpu/mpc5xxx/Kconfig
View file

@ -97,12 +97,6 @@ config TARGET_MUCMC52
config TARGET_UC101
bool "Support uc101"
config TARGET_MVBC_P
bool "Support MVBC_P"
config TARGET_MVSMR
bool "Support MVSMR"
config TARGET_PCM030
bool "Support pcm030"
@ -139,8 +133,6 @@ source "board/jupiter/Kconfig"
source "board/manroland/hmi1001/Kconfig"
source "board/manroland/mucmc52/Kconfig"
source "board/manroland/uc101/Kconfig"
source "board/matrix_vision/mvbc_p/Kconfig"
source "board/matrix_vision/mvsmr/Kconfig"
source "board/mcc200/Kconfig"
source "board/motionpro/Kconfig"
source "board/munices/Kconfig"

8
arch/powerpc/cpu/mpc83xx/Kconfig
View file

@ -64,12 +64,6 @@ config TARGET_SUVD3
config TARGET_TUXX1
bool "Support tuxx1"
config TARGET_MERGERBOX
bool "Support MERGERBOX"
config TARGET_MVBLM7
bool "Support MVBLM7"
config TARGET_TQM834X
bool "Support TQM834x"
@ -89,8 +83,6 @@ source "board/freescale/mpc837xemds/Kconfig"
source "board/freescale/mpc837xerdb/Kconfig"
source "board/ids/ids8313/Kconfig"
source "board/keymile/km83xx/Kconfig"
source "board/matrix_vision/mergerbox/Kconfig"
source "board/matrix_vision/mvblm7/Kconfig"
source "board/mpc8308_p1m/Kconfig"
source "board/sbc8349/Kconfig"
source "board/tqc/tqm834x/Kconfig"

16
arch/powerpc/cpu/ppc4xx/Kconfig
View file

@ -52,9 +52,6 @@ config TARGET_ACADIA
config TARGET_BAMBOO
bool "Support bamboo"
config TARGET_BLUESTONE
bool "Support bluestone"
config TARGET_BUBINGA
bool "Support bubinga"
@ -106,9 +103,6 @@ config TARGET_FX12MM
config TARGET_V5FX30TEVAL
bool "Support v5fx30teval"
config TARGET_CRAYL1
bool "Support CRAYL1"
config TARGET_CATCENTER
bool "Support CATcenter"
@ -226,12 +220,6 @@ config TARGET_ALPR
config TARGET_P3P440
bool "Support p3p440"
config TARGET_KAREF
bool "Support KAREF"
config TARGET_METROBOX
bool "Support METROBOX"
config TARGET_XPEDITE1000
bool "Support xpedite1000"
@ -248,7 +236,6 @@ endchoice
source "board/amcc/acadia/Kconfig"
source "board/amcc/bamboo/Kconfig"
source "board/amcc/bluestone/Kconfig"
source "board/amcc/bubinga/Kconfig"
source "board/amcc/canyonlands/Kconfig"
source "board/amcc/ebony/Kconfig"
@ -266,7 +253,6 @@ source "board/amcc/yosemite/Kconfig"
source "board/amcc/yucca/Kconfig"
source "board/avnet/fx12mm/Kconfig"
source "board/avnet/v5fx30teval/Kconfig"
source "board/cray/L1/Kconfig"
source "board/csb272/Kconfig"
source "board/csb472/Kconfig"
source "board/dave/PPChameleonEVB/Kconfig"
@ -306,8 +292,6 @@ source "board/mpl/pip405/Kconfig"
source "board/pcs440ep/Kconfig"
source "board/prodrive/alpr/Kconfig"
source "board/prodrive/p3p440/Kconfig"
source "board/sandburst/karef/Kconfig"
source "board/sandburst/metrobox/Kconfig"
source "board/sbc405/Kconfig"
source "board/sc3/Kconfig"
source "board/t3corp/Kconfig"

14
arch/powerpc/cpu/ppc4xx/cpu.c
View file

@ -234,20 +234,6 @@ static char *bootstrap_str[] = {
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
#endif
#if defined(CONFIG_APM821XX)
#define SDR0_PINSTP_SHIFT 29
static char *bootstrap_str[] = {
"RESERVED",
"RESERVED",
"RESERVED",
"NAND (8 bits)",
"NOR (8 bits)",
"NOR (8 bits) w/PLL Bypassed",
"I2C (Addr 0x54)",
"I2C (Addr 0x52)",
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
#endif
#if defined(SDR0_PINSTP_SHIFT)
static int bootstrap_option(void)

4
arch/powerpc/cpu/ppc4xx/cpu_init.c
View file

@ -284,7 +284,7 @@ cpu_init_f (void)
reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \
!defined(CONFIG_APM821XX) &&!defined(CONFIG_SYS_4xx_GPIO_TABLE)
!defined(CONFIG_SYS_4xx_GPIO_TABLE)
/*
* GPIO0 setup (select GPIO or alternate function)
*/
@ -440,7 +440,7 @@ cpu_init_f (void)
#if defined(CONFIG_405EX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
defined(CONFIG_460SX)
/*
* Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
*/

75
arch/powerpc/cpu/ppc4xx/speed.c
View file

@ -171,7 +171,7 @@ ulong get_PCI_freq (void)
#elif defined(CONFIG_440)
#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
defined(CONFIG_460SX)
static u8 pll_fwdv_multi_bits[] = {
/* values for: 1 - 16 */
0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c,
@ -232,78 +232,6 @@ u32 get_cpr0_fbdv(unsigned long cpr_reg_fbdv)
return 0;
}
#if defined(CONFIG_APM821XX)
void get_sys_info(sys_info_t *sysInfo)
{
unsigned long plld;
unsigned long temp;
unsigned long mul;
unsigned long cpudv;
unsigned long plb2dv;
unsigned long ddr2dv;
/* Calculate Forward divisor A and Feeback divisor */
mfcpr(CPR0_PLLD, plld);
temp = CPR0_PLLD_FWDVA(plld);
sysInfo->pllFwdDivA = get_cpr0_fwdv(temp);
temp = CPR0_PLLD_FDV(plld);
sysInfo->pllFbkDiv = get_cpr0_fbdv(temp);
/* Calculate OPB clock divisor */
mfcpr(CPR0_OPBD, temp);
temp = CPR0_OPBD_OPBDV(temp);
sysInfo->pllOpbDiv = temp ? temp : 4;
/* Calculate Peripheral clock divisor */
mfcpr(CPR0_PERD, temp);
temp = CPR0_PERD_PERDV(temp);
sysInfo->pllExtBusDiv = temp ? temp : 4;
/* Calculate CPU clock divisor */
mfcpr(CPR0_CPUD, temp);
temp = CPR0_CPUD_CPUDV(temp);
cpudv = temp ? temp : 8;
/* Calculate PLB2 clock divisor */
mfcpr(CPR0_PLB2D, temp);
temp = CPR0_PLB2D_PLB2DV(temp);
plb2dv = temp ? temp : 4;
/* Calculate DDR2 clock divisor */
mfcpr(CPR0_DDR2D, temp);
temp = CPR0_DDR2D_DDR2DV(temp);
ddr2dv = temp ? temp : 4;
/* Calculate 'M' based on feedback source */
mfcpr(CPR0_PLLC, temp);
temp = CPR0_PLLC_SEL(temp);
if (temp == 0) {
/* PLL internal feedback */
mul = sysInfo->pllFbkDiv;
} else {
/* PLL PerClk feedback */
mul = sysInfo->pllFwdDivA * sysInfo->pllFbkDiv * cpudv
* plb2dv * 2 * sysInfo->pllOpbDiv *
sysInfo->pllExtBusDiv;
}
/* Now calculate the individual clocks */
sysInfo->freqVCOMhz = (mul * CONFIG_SYS_CLK_FREQ) + (mul >> 1);
sysInfo->freqProcessor = sysInfo->freqVCOMhz /
sysInfo->pllFwdDivA / cpudv;
sysInfo->freqPLB = sysInfo->freqVCOMhz /
sysInfo->pllFwdDivA / cpudv / plb2dv / 2;
sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv;
sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv;
sysInfo->freqDDR = sysInfo->freqVCOMhz /
sysInfo->pllFwdDivA / cpudv / ddr2dv / 2;
sysInfo->freqUART = sysInfo->freqPLB;
}
#else
/*
* AMCC_TODO: verify this routine against latest EAS, cause stuff changed
* with latest EAS
@ -361,7 +289,6 @@ void get_sys_info (sys_info_t * sysInfo)
return;
}
#endif
#elif defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)

8
arch/powerpc/cpu/ppc4xx/start.S
View file

@ -664,8 +664,7 @@ _start:
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460SX)
mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_APM821XX)
#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
lis r1, 0x0000
ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
mtdcr L2_CACHE_CFG,r1
@ -694,7 +693,7 @@ _start:
ori r1,r1, 0x0980 /* fourth 64k */
mtdcr ISRAM0_SB3CR,r1
#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
defined(CONFIG_460GT) || defined(CONFIG_APM821XX)
defined(CONFIG_460GT)
lis r1,0x0000 /* BAS = X_0000_0000 */
ori r1,r1,0x0984 /* first 64k */
mtdcr ISRAM0_SB0CR,r1
@ -707,8 +706,7 @@ _start:
lis r1, 0x0003
ori r1,r1, 0x0984 /* fourth 64k */
mtdcr ISRAM0_SB3CR,r1
#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_APM821XX)
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
lis r2,0x7fff
ori r2,r2,0xffff
mfdcr r1,ISRAM1_DPC

59
arch/powerpc/include/asm/apm821xx.h
View file

@ -1,59 +0,0 @@
/*
* Copyright (c) 2010, Applied Micro Circuits Corporation
* Author: Tirumala R Marri <tmarri@apm.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _APM821XX_H_
#define _APM821XX_H_
#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
/* Memory mapped registers */
#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
#define SDR0_SRST0_DMC 0x00200000
#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */
/* AHB config. */
#define AHB_TOP 0xA4
#define AHB_BOT 0xA5
/* clk divisors */
#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */
#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */
#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */
#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */
#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */
#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */
#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000/* PLB Early Clk Div*/
#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */
/*
+ * Clocking Controller
+ */
#define CPR0_CLKUPD 0x0020
#define CPR0_PLLC 0x0040
#define CPR0_PLLC_SEL(pllc) (((pllc) & 0x01000000) >> 24)
#define CPR0_PLLD 0x0060
#define CPR0_PLLD_FDV(plld) (((plld) & 0xff000000) >> 24)
#define CPR0_PLLD_FWDVA(plld) (((plld) & 0x000f0000) >> 16)
#define CPR0_CPUD 0x0080
#define CPR0_CPUD_CPUDV(cpud) (((cpud) & 0x07000000) >> 24)
#define CPR0_PLB2D 0x00a0
#define CPR0_PLB2D_PLB2DV(plb2d) (((plb2d) & 0x06000000) >> 25)
#define CPR0_OPBD 0x00c0
#define CPR0_OPBD_OPBDV(opbd) (((opbd) & 0x03000000) >> 24)
#define CPR0_PERD 0x00e0
#define CPR0_PERD_PERDV(perd) (((perd) & 0x03000000) >> 24)
#define CPR0_DDR2D 0x0100
#define CPR0_DDR2D_DDR2DV(ddr2d) (((ddr2d) & 0x06000000) >> 25)
#define CLK_ICFG 0x0140
#endif /* _APM821XX_H_ */

3
arch/powerpc/include/asm/ppc4xx-ebc.h
View file

@ -53,8 +53,7 @@
#define EBC_NUM_BANKS 6
#endif
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_APM821XX)
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define EBC_NUM_BANKS 3
#endif

10
arch/powerpc/include/asm/ppc4xx-isram.h
View file

@ -8,8 +8,7 @@
/*
* Internal SRAM
*/
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_APM821XX)
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define ISRAM0_DCR_BASE 0x380
#else
#define ISRAM0_DCR_BASE 0x020
@ -26,8 +25,7 @@
#define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
#define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_APM821XX)
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define ISRAM1_DCR_BASE 0x0B0
#define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/
#define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */
@ -41,8 +39,6 @@
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define ISRAM1_SIZE 0x0984 /* OCM size 64k */
#elif defined(CONFIG_APM821XX)
#define ISRAM1_SIZE 0x0784 /* OCM size 32k */
#endif
/*
@ -51,7 +47,7 @@
#if defined (CONFIG_440GX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
defined(CONFIG_460SX)
#define L2_CACHE_BASE 0x030
#define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */
#define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */

12
arch/powerpc/include/asm/ppc4xx-sdram.h
View file

@ -276,7 +276,7 @@
*/
#if defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
defined(CONFIG_460SX)
#define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */
#define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000))
#define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2)
@ -349,7 +349,7 @@
/*
* Memory controller registers
*/
#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX)
#if defined(CONFIG_405EX)
#define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */
#define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */
#define SDRAM_BEARL 0x02 /* PLB bus error address low */
@ -359,9 +359,9 @@
#define SDRAM_PLBOPT 0x08 /* PLB slave options */
#define SDRAM_PUABA 0x09 /* PLB upper address base */
#define SDRAM_MCSTAT 0x1F /* memory controller status */
#else /* CONFIG_405EX || CONFIG_APM821XX */
#else /* CONFIG_405EX */
#define SDRAM_MCSTAT 0x14 /* memory controller status */
#endif /* CONFIG_405EX || CONFIG_APM821XX */
#endif /* CONFIG_405EX */
#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
@ -407,12 +407,12 @@
#define SDRAM_MEMODE 0x89 /* memory extended mode */
#define SDRAM_ECCES 0x98 /* ECC error status */
#define SDRAM_CID 0xA4 /* core ID */
#if !defined(CONFIG_405EX) && !defined(CONFIG_APM821XX)
#if !defined(CONFIG_405EX)
#define SDRAM_RID 0xA8 /* revision ID */
#endif
#define SDRAM_FCSR 0xB0 /* feedback calibration status */
#define SDRAM_RTSR 0xB1 /* run time status tracking */
#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX)
#if defined(CONFIG_405EX)
#define SDRAM_RID 0xF8 /* revision ID */
#endif

5
arch/powerpc/include/asm/ppc4xx-uic.h
View file

@ -15,7 +15,7 @@
*/
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
defined(CONFIG_460SX)
#define UIC_MAX 4
#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
@ -236,8 +236,7 @@
#define VECNUM_ETH0 (32 + 28)
#endif /* CONFIG_440SPE */
#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_APM821XX)
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
/* UIC 0 */
#define VECNUM_UIC2NCI 10
#define VECNUM_UIC2CI 11

4
arch/powerpc/include/asm/ppc4xx.h
View file

@ -56,10 +56,6 @@
#include <asm/ppc460sx.h>
#endif
#if defined(CONFIG_APM821XX)
#include <asm/apm821xx.h>
#endif
/*
* Common registers for all SoC's
*/

2
board/BuR/kwb/mux.c
View file

@ -105,6 +105,8 @@ static struct module_pin_mux i2c0_pin_mux[] = {
};
static struct module_pin_mux mii1_pin_mux[] = {
{OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
{OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */
{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */

3
board/BuR/tseries/mux.c
View file

@ -64,6 +64,8 @@ static struct module_pin_mux spi0_pin_mux[] = {
};
static struct module_pin_mux mii1_pin_mux[] = {
{OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
{OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */
{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
@ -96,6 +98,7 @@ static struct module_pin_mux mii2_pin_mux[] = {
{OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */
{OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */
{OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */
{OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)},
/*
* MII2_CRS is shared with
* NAND_WAIT0

3
board/altera/socfpga/pll_config.h
View file

@ -94,6 +94,9 @@
/* Info for driver */
#define CONFIG_HPS_CLK_OSC1_HZ (25000000)
#define CONFIG_HPS_CLK_OSC2_HZ 0
#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
#ifdef CONFIG_SOCFPGA_ARRIA5

6
board/altera/socfpga/socfpga_cyclone5.c
View file

@ -17,7 +17,7 @@ DECLARE_GLOBAL_DATA_PTR;
*/
int checkboard(void)
{
puts("BOARD : Altera SOCFPGA Cyclone5 Board\n");
puts("BOARD: Altera SoCFPGA Cyclone5 Board\n");
return 0;
}
@ -34,6 +34,8 @@ int board_early_init_f(void)
*/
int board_init(void)
{
icache_enable();
/* Address of boot parameters for ATAG (if ATAG is used) */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}

12
board/amcc/bluestone/Kconfig
View file

@ -1,12 +0,0 @@
if TARGET_BLUESTONE
config SYS_BOARD
default "bluestone"
config SYS_VENDOR
default "amcc"
config SYS_CONFIG_NAME
default "bluestone"
endif

6
board/amcc/bluestone/MAINTAINERS
View file

@ -1,6 +0,0 @@
BLUESTONE BOARD
#M: Tirumala Marri <tmarri@apm.com>
S: Orphan (since 2014-03)
F: board/amcc/bluestone/
F: include/configs/bluestone.h
F: configs/bluestone_defconfig

9
board/amcc/bluestone/Makefile
View file

@ -1,9 +0,0 @@
#
# Copyright (c) 2010, Applied Micro Circuits Corporation
# Author: Tirumala R Marri <tmarri@apm.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := bluestone.o
extra-y += init.o

99
board/amcc/bluestone/bluestone.c
View file

@ -1,99 +0,0 @@
/*
* Bluestone board support
*
* Copyright (c) 2010, Applied Micro Circuits Corporation
* Author: Tirumala R Marri <tmarri@apm.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/apm821xx.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <i2c.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/ppc4xx-gpio.h>
int board_early_init_f(void)
{
/*
* Setup the interrupt controller polarities, triggers, etc.
*/
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC2ER, 0x00000000); /* disable all */
mtdcr(UIC2CR, 0x00000000); /* all non-critical */
mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC3SR, 0xffffffff); /* clear all */
mtdcr(UIC3ER, 0x00000000); /* disable all */
mtdcr(UIC3CR, 0x00000000); /* all non-critical */
mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC3SR, 0xffffffff); /* clear all */
/*
* Configure PFC (Pin Function Control) registers
* UART0: 2 pins
*/
mtsdr(SDR0_PFC1, 0x0000000);
return 0;
}
int checkboard(void)
{
char buf[64];
int i = getenv_f("serial#", buf, sizeof(buf));
puts("Board: Bluestone Evaluation Board");
if (i > 0) {
puts(", serial# ");
puts(buf);
}
putc('\n');
return 0;
}
int misc_init_r(void)
{
u32 sdr0_srst1 = 0;
/* Setup PLB4-AHB bridge based on the system address map */
mtdcr(AHB_TOP, 0x8000004B);
mtdcr(AHB_BOT, 0x8000004B);
/*
* The AHB Bridge core is held in reset after power-on or reset
* so enable it now
*/
mfsdr(SDR0_SRST1, sdr0_srst1);
sdr0_srst1 &= ~SDR0_SRST1_AHB;
mtsdr(SDR0_SRST1, sdr0_srst1);
return 0;
}

18
board/amcc/bluestone/config.mk
View file

@ -1,18 +0,0 @@
#
# Copyright (c) 2010, Applied Micro Circuits Corporation
# Author: Tirumala R Marri <tmarri@apm.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
# Applied Micro APM821XX Evaluation board.
#
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif

45
board/amcc/bluestone/init.S
View file

@ -1,45 +0,0 @@
/*
* Copyright (c) 2010, Applied Micro Circuits Corporation
* Author: Tirumala R Marri <tmarri@apm.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm/mmu.h>
#include <asm/ppc4xx.h>
/**************************************************************************
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*
*************************************************************************/
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
tlbtab_start
/* TLB 0 */
tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
4, AC_RWX | SA_G)
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,
0, AC_RWX | SA_G)
/* TLB-entry for OCM */
tlbentry(CONFIG_SYS_OCM_BASE, SZ_64K, 0x00040000, 4,
AC_RWX | SA_I)
/* TLB-entry for Local Configuration registers => peripherals */
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K,
CONFIG_SYS_PERIPHERAL_BASE, 4, AC_RWX | SA_IG)
tlbtab_end

2
board/cray/L1/.gitignore vendored
View file

@ -1,2 +0,0 @@
bootscript.c
bootscript.image

12
board/cray/L1/Kconfig
View file

@ -1,12 +0,0 @@
if TARGET_CRAYL1
config SYS_BOARD
default "L1"
config SYS_VENDOR
default "cray"
config SYS_CONFIG_NAME
default "CRAYL1"
endif

350
board/cray/L1/L1.c
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@ -1,350 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/ppc4xx-i2c.h>
#include <command.h>
#include <rtc.h>
#include <post.h>
#include <net.h>
#include <malloc.h>
#define L1_MEMSIZE (32*1024*1024)
/* the std. DHCP stufff */
#define DHCP_ROUTER 3
#define DHCP_NETMASK 1
#define DHCP_BOOTFILE 67
#define DHCP_ROOTPATH 17
#define DHCP_HOSTNAME 12
/* some extras used by CRAY
*
* on the server this looks like:
*
* option L1-initrd-image code 224 = string;
* option L1-initrd-image "/opt/craysv2/craymcu/l1/flash/initrd.image"
*/
#define DHCP_L1_INITRD 224
/* new, [better?] way via official vendor-extensions, defining an option
* space.
* on the server this looks like:
*
* option space CRAYL1;
* option CRAYL1.initrd code 3 = string;
* ..etc...
*/
#define DHCP_VENDOR_SPECX 43
#define DHCP_VX_INITRD 3
#define DHCP_VX_BOOTCMD 4
#define DHCP_VX_BOOTARGS 5
#define DHCP_VX_ROOTDEV 6
#define DHCP_VX_FROMFLASH 7
#define DHCP_VX_BOOTSCRIPT 8
#define DHCP_VX_RCFILE 9
#define DHCP_VX_MAGIC 10
/* Things DHCP server can tellme about. If there's no flash address, then
* they dont participate in 'update' to flash, and we force their values
* back to '0' every boot to be sure to get them fresh from DHCP. Yes, I
* know this is a pain...
*
* If I get no bootfile, boot from flash. If rootpath, use that. If no
* rootpath use initrd in flash.
*/
typedef struct dhcp_item_s {
u8 dhcp_option;
u8 dhcp_vendor_option;
char *dhcpvalue;
char *envname;
} dhcp_item_t;
static dhcp_item_t Things[] = {
{DHCP_ROUTER, 0, NULL, "gateway"},
{DHCP_NETMASK, 0, NULL, "netmask"},
{DHCP_BOOTFILE, 0, NULL, "bootfile"},
{DHCP_ROOTPATH, 0, NULL, "rootpath"},
{DHCP_HOSTNAME, 0, NULL, "hostname"},
{DHCP_L1_INITRD, 0, NULL, "initrd"},
/* and the other way.. */
{DHCP_VENDOR_SPECX, DHCP_VX_INITRD, NULL, "initrd"},
{DHCP_VENDOR_SPECX, DHCP_VX_BOOTCMD, NULL, "bootcmd"},
{DHCP_VENDOR_SPECX, DHCP_VX_FROMFLASH, NULL, "fromflash"},
{DHCP_VENDOR_SPECX, DHCP_VX_BOOTSCRIPT, NULL, "bootscript"},
{DHCP_VENDOR_SPECX, DHCP_VX_RCFILE, NULL, "rcfile"},
{DHCP_VENDOR_SPECX, DHCP_VX_BOOTARGS, NULL, "xbootargs"},
{DHCP_VENDOR_SPECX, DHCP_VX_ROOTDEV, NULL, NULL},
{DHCP_VENDOR_SPECX, DHCP_VX_MAGIC, NULL, NULL}
};
#define N_THINGS ((sizeof(Things))/(sizeof(dhcp_item_t)))
extern char bootscript[];
/* Here is the boot logic as HUSH script. Overridden by any TFP provided
* bootscript file.
*/
static void init_sdram (void);
/* ------------------------------------------------------------------------- */
int board_early_init_f (void)
{
/* Running from ROM: global data is still READONLY */
init_sdram ();
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */
mtdcr (UIC0PR, 0xFFFFFFE0); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}
/* ------------------------------------------------------------------------- */
int checkboard (void)
{
return (0);
}
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
int misc_init_r (void)
{
char *s, *e;
image_header_t *hdr;
time_t timestamp;
struct rtc_time tm;
char bootcmd[32];
hdr = (image_header_t *) (CONFIG_SYS_MONITOR_BASE - image_get_header_size ());
#if defined(CONFIG_FIT)
if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
puts ("Non legacy image format not supported\n");
return -1;
}
#endif
timestamp = (time_t)image_get_time (hdr);
to_tm (timestamp, &tm);
printf ("Welcome to U-Boot on Cray L1. Compiled %4d-%02d-%02d %2d:%02d:%02d (UTC)\n", tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec);
#define FACTORY_SETTINGS 0xFFFC0000
if ((s = getenv ("ethaddr")) == NULL) {
e = (char *) (FACTORY_SETTINGS);
if (*(e + 0) != '0'
|| *(e + 1) != '0'
|| *(e + 2) != ':'
|| *(e + 3) != '4' || *(e + 4) != '0' || *(e + 17) != '\0') {
printf ("No valid MAC address in flash location 0x3C0000!\n");
} else {
printf ("Factory MAC: %s\n", e);
setenv ("ethaddr", e);
}
}
sprintf (bootcmd,"source %X",(unsigned)bootscript);
setenv ("bootcmd", bootcmd);
return (0);
}
/* ------------------------------------------------------------------------- */
/* stubs so we can print dates w/o any nvram RTC.*/
int rtc_get (struct rtc_time *tmp)
{
return 0;
}
int rtc_set (struct rtc_time *tmp)
{
return 0;
}
void rtc_reset (void)
{
return;
}
/* ------------------------------------------------------------------------- */
/* Do sdram bank init in C so I can read it..no console to print to yet!
*/
static void init_sdram (void)
{
unsigned long tmp;
/* write SDRAM bank 0 register */
mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
mtdcr (SDRAM0_CFGDATA, 0x00062001);
/* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */
/* To set the appropriate timings, we need to know the SDRAM speed. */
/* We can use the PLB speed since the SDRAM speed is the same as */
/* the PLB speed. The PLB speed is the FBK divider times the */
/* 405GP reference clock, which on the L1 is 25MHz. */
/* Thus, if FBK div is 2, SDRAM is 50MHz; if FBK div is 3, SDRAM is */
/* 150MHz; if FBK is 3, SDRAM is 150MHz. */
/* divisor = ((mfdcr(strap)>> 28) & 0x3); */
/* write SDRAM timing for 100MHz. */
mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
mtdcr (SDRAM0_CFGDATA, 0x0086400D);
/* write SDRAM refresh interval register */
mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
mtdcr (SDRAM0_CFGDATA, 0x05F00000);
udelay (200);
/* sdram controller.*/
mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, 0x90800000);
udelay (200);
/* initially, disable ECC on all banks */
udelay (200);
mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
tmp = mfdcr (SDRAM0_CFGDATA);
tmp &= 0xff0fffff;
mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
mtdcr (SDRAM0_CFGDATA, tmp);
return;
}
extern int memory_post_test (int flags);
int testdram (void)
{
unsigned long tmp;
uint *pstart = (uint *) 0x00000000;
uint *pend = (uint *) L1_MEMSIZE;
uint *p;
if (getenv_f("booted",NULL,0) <= 0)
{
printf ("testdram..");
/*AA*/
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
(uint) p, *p, 0xaaaaaaaa);
return 1;
}
}
/*55*/
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
(uint) p, *p, 0x55555555);
return 1;
}
}
/*addr*/
for (p = pstart; p < pend; p++)
*p = (unsigned)p;
for (p = pstart; p < pend; p++) {
if (*p != (unsigned)p) {
printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
(uint) p, *p, (uint)p);
return 1;
}
}
printf ("Success. ");
}
printf ("Enable ECC..");
mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, tmp);
udelay (600);
for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L)
;
udelay (400);
mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
tmp = mfdcr (SDRAM0_CFGDATA);
tmp |= 0x00800000;
mtdcr (SDRAM0_CFGDATA, tmp);
udelay (400);
printf ("enabled.\n");
return (0);
}
/* ------------------------------------------------------------------------- */
static u8 *dhcp_env_update (u8 thing, u8 * pop)
{
u8 i, oplen;
oplen = *(pop + 1);
if ((Things[thing].dhcpvalue = malloc (oplen)) == NULL) {
printf ("Whoops! failed to malloc space for DHCP thing %s\n",
Things[thing].envname);
return NULL;
}
for (i = 0; (i < oplen); i++)
if ((*(Things[thing].dhcpvalue + i) = *(pop + 2 + i)) == ' ')
break;
*(Things[thing].dhcpvalue + i) = '\0';
/* set env. */
if (Things[thing].envname)
{
setenv (Things[thing].envname, Things[thing].dhcpvalue);
}
return ((u8 *)(Things[thing].dhcpvalue));
}
/* ------------------------------------------------------------------------- */
u8 *dhcp_vendorex_prep (u8 * e)
{
u8 thing;
/* ask for the things I want. */
*e++ = 55; /* Parameter Request List */
*e++ = N_THINGS;
for (thing = 0; thing < N_THINGS; thing++)
*e++ = Things[thing].dhcp_option;
*e++ = 255;
return e;
}
/* ------------------------------------------------------------------------- */
/* .. return NULL means it wasnt mine, non-null means I got it..*/
u8 *dhcp_vendorex_proc (u8 * pop)
{
u8 oplen, *sub_op, sub_oplen, *retval;
u8 thing = 0;
retval = NULL;
oplen = *(pop + 1);
/* if pop is vender spec indicator, there are sub-options. */
if (*pop == DHCP_VENDOR_SPECX) {
for (sub_op = pop + 2;
oplen && (sub_oplen = *(sub_op + 1));
oplen -= sub_oplen, sub_op += (sub_oplen + 2)) {
for (thing = 0; thing < N_THINGS; thing++) {
if (*sub_op == Things[thing].dhcp_vendor_option) {
if (!(retval = dhcp_env_update (thing, sub_op))) {
return NULL;
}
}
}
}
} else {
for (thing = 0; thing < N_THINGS; thing++) {
if (*pop == Things[thing].dhcp_option)
if (!(retval = dhcp_env_update (thing, pop)))
return NULL;
}
}
return (pop);
}

6
board/cray/L1/MAINTAINERS
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@ -1,6 +0,0 @@
L1 BOARD
#M: David Updegraff <dave@cray.com>
S: Orphan (since 2014-03)
F: board/cray/L1/
F: include/configs/CRAYL1.h
F: configs/CRAYL1_defconfig

23
board/cray/L1/Makefile
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@ -1,23 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = L1.o flash.o
obj-y += init.o
obj-y += bootscript.o
quiet_cmd_awk = AWK $@
cmd_awk = od -t x1 -v -A x $< | $(AWK) -f $(filter-out $<,$^) > $@
$(obj)/bootscript.c: $(obj)/bootscript.image $(src)/x2c.awk
$(call cmd,awk)
MKIMAGEFLAGS_bootscript.image := -A ppc -O linux -T script -C none \
-a 0 -e 0 -n bootscript
$(obj)/bootscript.image: $(src)/bootscript.hush
$(call cmd,mkimage)
clean-files := bootscript.c bootscript.image

117
board/cray/L1/bootscript.hush
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@ -1,117 +0,0 @@
# $Header$
# hush bootscript for PPCBOOT on L1
# note: all #s are in hex, do _NOT_ prefix it with 0x
flash_rfs=ffc00000
flash_krl=fff00000
tftp_addr=100000
tftp2_addr=1000000
if printenv booted
then
echo already booted before
else
echo first boot in environment, create and save settings
setenv booted OK
saveenv
fi
setenv autoload no
# clear out stale env stuff, so we get fresh from dhcp.
for setting in initrd fromflash kernel rootfs rootpath
do
setenv $setting
done
dhcp
# if host provides us with a different bootscript, us it.
if printenv bootscript
then
tftp $tftp_addr $bootcript
if imi $tftp_addr
then
source $tftp_addr
fi
fi
# default base kernel arguments.
setenv bootargs $xbootargs devfs=mount ip=$ipaddr:$serverip:$gatewayip:$netmask:L1:eth0:off wdt=120
# Have a kernel in flash?
if imi $flash_krl
then
echo ok kernel to boot from $flash_krl
setenv kernel $flash_krl
else
echo no kernel to boot from $flash_krl, need tftp
fi
# Have a rootfs in flash?
echo test for SQUASHfs at $flash_rfs
if imi $flash_rfs
then
echo appears to be a good initrd image at base of flash OK
setenv rootfs $flash_rfs
else
echo no image at base of flash, need nfsroot or initrd
fi
# I boot from flash if told to and I can.
if printenv fromflash && printenv kernel && printenv rootfs
then
echo booting entirely from flash
setenv bootargs root=/dev/ram0 rw $bootargs
bootm $kernel $rootfs
echo oh no failed so I try some other stuff
fi
# TFTP down a kernel
if printenv bootfile
then
tftp $tftp_addr $bootfile
setenv kernel $tftp_addr
echo I will boot the TFTP kernel
else
if printenv kernel
then
echo no bootfile specified, will use one from flash
else
setenv bootfile /opt/crayx1/craymcu/l1/flash/linux.image
echo OH NO! we have no bootfile,nor flash kernel! try default: $bootfile
tftp $tftp_addr $bootfile
setenv kernel $tftp_addr
fi
fi
# the rootfs.
if printenv rootpath
then
echo rootpath is $rootpath
if printenv initrd
then
echo initrd is also specified, so use $initrd
tftp $tftp2_addr $initrd
setenv bootargs root=/dev/ram0 rw cwsroot=$serverip:$rootpath $bootargs
bootm $kernel $tftp2_addr
else
echo initrd is not specified, so use NFSROOT $rootpat
setenv bootargs root=/dev/nfs ro nfsroot=$serverip:$rootpath $bootargs
bootm $kernel
fi
else
echo we have no rootpath check for one in flash
if printenv rootfs
then
echo I will use the one in flash
setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs
bootm $kernel
else
setenv rootpath /export/crayl1
echo OH NO! we have no rootpath,nor flash kernel! try default: $rootpath
setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs
bootm $kernel
fi
fi
reset

451
board/cray/L1/flash.c
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@ -1,451 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* Modified 4/5/2001
* Wait for completion of each sector erase command issued
* 4/5/2001
* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
*/
/*
* Modified July 20, 2001
* Strip down to support ONLY the AMD29F032B.
* Dave Updegraff - Cray, Inc. dave@cray.com
*/
#include <common.h>
#include <asm/ppc4xx.h>
#include <asm/processor.h>
/* The flash chip we use... */
#define AMD_ID_F032B 0x41 /* 29F032B ID 32 Mbit,64 64Kx8 sectors */
#define FLASH_AM320B 0x0009
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
static void flash_get_offsets (ulong base, flash_info_t *info);
#define ADDR0 0x5555
#define ADDR1 0x2aaa
#define FLASH_WORD_SIZE unsigned char
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
unsigned long size_b0, size_b1;
int i;
/* Init: no FLASHes known */
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0<<20);
}
/* Only one bank */
if (CONFIG_SYS_MAX_FLASH_BANKS == 1)
{
/* Setup offsets */
flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
#if 0
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
FLASH_BASE0_PRELIM,
FLASH_BASE0_PRELIM+monitor_flash_len-1,
&flash_info[0]);
#endif
size_b1 = 0 ;
flash_info[0].size = size_b0;
}
return (size_b0 + size_b1);
}
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets (ulong base, flash_info_t *info)
{
int i;
/* set up sector start address table */
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
int k;
int size;
int erased;
volatile unsigned long *flash;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD: printf ("AMD "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM320B:printf ("AM29F032B (32 Mbit 64x64KB uniform sectors)\n");
break;
default: printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld KB in %d Sectors\n",
info->size >> 10, info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
/*
* Check if whole sector is erased
*/
if (i != (info->sector_count-1))
size = info->start[i+1] - info->start[i];
else
size = info->start[0] + info->size - info->start[i];
erased = 1;
flash = (volatile unsigned long *)info->start[i];
size = size >> 2; /* divide by 4 for longword access */
for (k=0; k<size; k++)
{
if (*flash++ != 0xffffffff)
{
erased = 0;
break;
}
}
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s%s",
info->start[i],
erased ? " E" : " ",
info->protect[i] ? "RO " : " "
);
}
printf ("\n");
}
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
{
short i;
FLASH_WORD_SIZE value;
ulong base = (ulong)addr;
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
/* Write auto select command: read Manufacturer ID */
addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
value = addr2[0];
switch (value) {
case (FLASH_WORD_SIZE)AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
value = addr2[1]; /* device ID */
switch (value) {
case (FLASH_WORD_SIZE)AMD_ID_F032B:
info->flash_id += FLASH_AM320B;
info->sector_count = 64;
info->size = 0x0400000; /* => 4 MB */
break;
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
/* set up sector start address table */
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
info->protect[i] = addr2[2] & 1;
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
addr2 = (FLASH_WORD_SIZE *)info->start[0];
*addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
}
return (info->size);
}
int wait_for_DQ7(flash_info_t *info, int sect)
{
ulong start, now, last;
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
start = get_timer (0);
last = start;
while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return -1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
return 0;
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
volatile FLASH_WORD_SIZE *addr2;
int flag, prot, sect;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if (info->flash_id == FLASH_UNKNOWN) {
printf ("Can't erase unknown flash type - aborted\n");
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
printf("Erasing sector %p\n", addr2);
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
* issue all erase commands within a specified
* timeout. This has been seen to fail, especially
* if printf()s are included (for debug)!!
*/
wait_for_DQ7(info, sect);
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/* reset to read mode */
addr = (FLASH_WORD_SIZE *)info->start[0];
addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
printf (" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
for (; i<4 && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i=0; i<4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
return (write_word(info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
{
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
ulong start;
int flag;
int i;
/* Check if Flash is (sufficiently) erased */
if ((*((volatile FLASH_WORD_SIZE *)dest) &
(FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
{
addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0;
dest2[i] = data2[i];
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer (0);
while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
(data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
return (1);
}
}
}
return (0);
}
/*-----------------------------------------------------------------------
*/

117
board/cray/L1/init.S
View file

@ -1,117 +0,0 @@
/*
* SPDX-License-Identifier: GPL-2.0 IBM-pibs
*/
/*----------------------------------------------------------------------------- */
/* Function: ext_bus_cntlr_init */
/* Description: Initializes the External Bus Controller for the external */
/* peripherals. IMPORTANT: For pass1 this code must run from */
/* cache since you can not reliably change a peripheral banks */
/* timing register (pbxap) while running code from that bank. */
/* For ex., since we are running from ROM on bank 0, we can NOT */
/* execute the code that modifies bank 0 timings from ROM, so */
/* we run it from cache. */
/* Bank 0 - Flash and SRAM */
/* Bank 1 - NVRAM/RTC */
/* Bank 2 - Keyboard/Mouse controller */
/* Bank 3 - IR controller */
/* Bank 4 - not used */
/* Bank 5 - not used */
/* Bank 6 - not used */
/* Bank 7 - FPGA registers */
/*-----------------------------------------------------------------------------#include <config.h> */
#include <asm/ppc4xx.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
/* CRAY - L1: only nominally a 'walnut', since ext.Bus.Cntlr is all empty */
/* except for #1 which we use for DMA'ing to IOCA-like things, so the */
/* control registers to set that up are determined by what we've */
/* empirically discovered work there. */
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
mflr r4 /* save link register */
bl ..getAddr
..getAddr:
mflr r3 /* get address of ..getAddr */
mtlr r4 /* restore link register */
addi r4,0,14 /* set ctr to 10; used to prefetch */
mtctr r4 /* 10 cache lines to fit this function */
/* in cache (gives us 8x10=80 instrctns) */
..ebcloop:
icbt r0,r3 /* prefetch cache line for addr in r3 */
addi r3,r3,32 /* move to next cache line */
bdnz ..ebcloop /* continue for 10 cache lines */
/*------------------------------------------------------------------- */
/* Delay to ensure all accesses to ROM are complete before changing */
/* bank 0 timings. 200usec should be enough. */
/* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
/*------------------------------------------------------------------- */
addis r3,0,0x0
ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
mtctr r3
..spinlp:
bdnz ..spinlp /* spin loop */
/*---------------------------------------------------------------------- */
/* Peripheral Bank 0 (Flash) initialization */
/*---------------------------------------------------------------------- */
/* 0x7F8FFE80 slowest boot */
addi r4,0,PB1AP
mtdcr EBC0_CFGADDR,r4
addis r4,0,0x9B01
ori r4,r4,0x5480
mtdcr EBC0_CFGDATA,r4
addi r4,0,PB0CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */
ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
mtdcr EBC0_CFGDATA,r4
blr
/*---------------------------------------------------------------------- */
/* Peripheral Bank 1 (NVRAM/RTC) initialization */
/* CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead */
/* and we do DMA on it. The ConfigurationRegister part is threfore */
/* almost arbitrary, except that our linux driver needs to know the */
/* address, but it can query, it.. */
/* */
/* The AccessParameter is CRITICAL, */
/* thouch, since it needs to agree with the electrical timings on the */
/* IOCA parallel interface. That value is: 0x0185,4380 */
/* BurstModeEnable BME=0 */
/* TransferWait TWT=3 */
/* ChipSelectOnTiming CSN=1 */
/* OutputEnableOnTimimg OEN=1 */
/* WriteByteEnableOnTiming WBN=1 */
/* WriteByteEnableOffTiming WBF=0 */
/* TransferHold TH=1 */
/* ReadyEnable RE=1 */
/* SampleOnReady SOR=1 */
/* ByteEnableMode BEM=0 */
/* ParityEnable PEN=0 */
/* all reserved bits=0 */
/*---------------------------------------------------------------------- */
/*---------------------------------------------------------------------- */
addi r4,0,PB1AP
mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0185 /* hiword */
ori r4,r4,0x4380 /* loword */
mtdcr EBC0_CFGDATA,r4
addi r4,0,PB1CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */
ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
mtdcr EBC0_CFGDATA,r4
blr

30
board/cray/L1/patchme
View file

@ -1,30 +0,0 @@
# master confi.mk
echo "CROSS_COMPILE = powerpc-linux-" >>include/config.mk
# patch the examples/Makefile to ignore return value from OBJCOPY
sed -e 's/$(OBJCOPY)/-&/' < examples/Makefile > examples/makefile
# add a built target for mkimage on the target architecture
sed -e 's/^all:.*$/all: .depend envcrc mkimage mkimage.ppc/' < tools/Makefile > tools/makefile
cat <<EOF >>tools/makefile
mkimage.ppc : mkimage.o.ppc crc32.o.ppc
powerpc-linux-gcc -msoft-float -Wall -Wstrict-prototypes -o \$@ \$^
powerpc-linux-strip $@
XFLAGS="-D__KERNEL__ -I../include -DCONFIG_4xx -Wall -Wstict-prototypes"
mkimage.o.ppc: mkimage.c
powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^
crc32.o.ppc: crc32.c
powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^
EOF
# make an image by default out of the u-boot image
sed -e 's/^all:.*$/all: u-boot.image /' < Makefile > makefile
cat <<EOF >>makefile
u-boot.image: u-boot.bin
tools/mkimage -A ppc -O linux -T firmware -C none -a 0 -e 0 -n U-Boot -d \$^ \$@
EOF

121
board/cray/L1/u-boot.lds.debug
View file

@ -1,121 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
arch/powerpc/lib/extable.o (.text)
common/env_embedded.o(.text)
*(.text)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
__bss_end = . ;
PROVIDE (end = .);
}

6
board/cray/L1/x2c.awk
View file

@ -1,6 +0,0 @@
#!/bin/awk
BEGIN { print "unsigned char bootscript[] = { \n"}
{ for (i = 2; i <= NF ; i++ ) printf "0x"$i","
print ""
}
END { print "\n};\n" }

12
board/matrix_vision/mergerbox/Kconfig
View file

@ -1,12 +0,0 @@
if TARGET_MERGERBOX
config SYS_BOARD
default "mergerbox"
config SYS_VENDOR
default "matrix_vision"
config SYS_CONFIG_NAME
default "MERGERBOX"
endif

6
board/matrix_vision/mergerbox/MAINTAINERS
View file

@ -1,6 +0,0 @@
MERGERBOX BOARD
#M: Andre Schwarz <andre.schwarz@matrix-vision.de>
S: Orphan (since 2014-03)
F: board/matrix_vision/mergerbox/
F: include/configs/MERGERBOX.h
F: configs/MERGERBOX_defconfig

8
board/matrix_vision/mergerbox/Makefile
View file

@ -1,8 +0,0 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += mergerbox.o pci.o fpga.o sm107.o

59
board/matrix_vision/mergerbox/README
View file

@ -1,59 +0,0 @@
Matrix Vision MergerBox
-----------------------
1. Board Description
The MergerBox is a 120x160mm single board computing platform
for 3D Full-HD digital video processing.
Power Supply is 10-32VDC.
2 System Components
2.1 CPU
Freescale MPC8377 CPU running at 800MHz core and 333MHz csb.
256 MByte DDR-II memory @ 333MHz data rate.
64 MByte Nor Flash on local bus.
1 GByte Nand Flash on FCM.
1 Vitesse VSC8601 RGMII ethernet Phys.
1 USB host controller over ULPI I/F with 4-Port hub.
2 serial ports. Console running on ttyS0 @ 115200 8N1.
1 mPCIe expansion slot (PCIe x1 + USB) used for Wifi/Bt.
2 PCIe x1 busses on local mPCIe and cutom expansion connector.
2 SATA host ports.
System configuration (HRCW) is taken from I2C EEPROM.
2.2 Graphics
SM107 emebedded video controller driving a 5" 800x480 TFT panel.
Connected over 32-Bit/66MHz PCI utilizing 4 MByte embedded memory.
2.3 FPGA
Altera Cyclone-IV EP4C115 with several PCI DMA engines.
Connects to 7x Gennum 3G-SDI transceivers as video interconnect
as well as a HDMI v1.4 compliant output for 3D monitoring.
Utilizes two more DDR-II controllers providing 256MB memory.
2.4 I2C
Bus1:
AD7418 @ 0x50 for voltage/temp. monitoring.
SX8650 @ 0x90 touch controller for HMI.
EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics.
Bus2:
mPCIe SMBus
SiI9022A @ 0x72/0xC0 HDMI transmitter.
TCA6416A @ 0x40 + 0x42 16-Bit I/O expander.
LMH1983 @ 0xCA video PLL.
DS1338C @ 0xD0 real-time clock with embedded crystal.
9FG104 @ 0xDC 4x 100MHz LVDS SerDes reference clock.
3 Flash layout.
reset vector is 0x00000100, i.e. low boot.
00000000 u-boot binary.
00100000 FPGA raw bit file.
00300000 FIT image holding kernel, dtb and rescue squashfs.
03d00000 u-boot environment.
03e00000 splash image
mtd partitions are propagated to linux kernel via device tree blob.

158
board/matrix_vision/mergerbox/fpga.c
View file

@ -1,158 +0,0 @@
/*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
* Keith Outwater, keith_outwater@mvis.com.
*
* (C) Copyright 2011
* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <ACEX1K.h>
#include <command.h>
#include "mergerbox.h"
#include "fpga.h"
Altera_CYC2_Passive_Serial_fns altera_fns = {
fpga_null_fn,
fpga_config_fn,
fpga_status_fn,
fpga_done_fn,
fpga_wr_fn,
fpga_null_fn,
fpga_null_fn,
};
Altera_desc cyclone2 = {
Altera_CYC2,
passive_serial,
Altera_EP2C20_SIZE,
(void *) &altera_fns,
NULL,
0
};
DECLARE_GLOBAL_DATA_PTR;
int mergerbox_init_fpga(void)
{
debug("Initialize FPGA interface\n");
fpga_init();
fpga_add(fpga_altera, &cyclone2);
return 1;
}
int fpga_null_fn(int cookie)
{
return 0;
}
int fpga_config_fn(int assert, int flush, int cookie)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
u32 dvo = gpio->dat;
dvo &= ~FPGA_CONFIG;
gpio->dat = dvo;
udelay(5);
dvo |= FPGA_CONFIG;
gpio->dat = dvo;
return assert;
}
int fpga_done_fn(int cookie)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
int result = 0;
udelay(10);
debug("CONF_DONE check ... ");
if (gpio->dat & FPGA_CONF_DONE) {
debug("high\n");
result = 1;
} else
debug("low\n");
return result;
}
int fpga_status_fn(int cookie)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
int result = 0;
debug("STATUS check ... ");
if (gpio->dat & FPGA_STATUS) {
debug("high\n");
result = 1;
} else
debug("low\n");
return result;
}
int fpga_clk_fn(int assert_clk, int flush, int cookie)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
u32 dvo = gpio->dat;
debug("CLOCK %s\n", assert_clk ? "high" : "low");
if (assert_clk)
dvo |= FPGA_CCLK;
else
dvo &= ~FPGA_CCLK;
if (flush)
gpio->dat = dvo;
return assert_clk;
}
static inline int _write_fpga(u8 val, int dump)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
int i;
u32 dvo = gpio->dat;
if (dump)
debug(" %02x -> ", val);
for (i = 0; i < 8; i++) {
dvo &= ~FPGA_CCLK;
gpio->dat = dvo;
dvo &= ~FPGA_DIN;
if (dump)
debug("%d ", val&1);
if (val & 1)
dvo |= FPGA_DIN;
gpio->dat = dvo;
dvo |= FPGA_CCLK;
gpio->dat = dvo;
val >>= 1;
}
if (dump)
debug("\n");
return 0;
}
int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
{
unsigned char *data = (unsigned char *) buf;
int i;
debug("fpga_wr: buf %p / size %d\n", buf, len);
for (i = 0; i < len; i++)
_write_fpga(data[i], 0);
debug("\n");
return FPGA_SUCCESS;
}

13
board/matrix_vision/mergerbox/fpga.h
View file

@ -1,13 +0,0 @@
/*
* SPDX-License-Identifier: GPL-2.0+
*/
extern int mergerbox_init_fpga(void);
extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
extern int fpga_status_fn(int cookie);
extern int fpga_config_fn(int assert, int flush, int cookie);
extern int fpga_done_fn(int cookie);
extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
extern int fpga_null_fn(int cookie);

235
board/matrix_vision/mergerbox/mergerbox.c
View file

@ -1,235 +0,0 @@
/*
* Copyright (C) 2007 Freescale Semiconductor, Inc.
*
* Copyright (C) 2011 Matrix Vision GmbH
* Andre Schwarz <andre.schwarz@matrix-vision.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <hwconfig.h>
#include <i2c.h>
#include <spi.h>
#include <asm/io.h>
#include <asm/fsl_mpc83xx_serdes.h>
#include <fdt_support.h>
#include <spd_sdram.h>
#include "mergerbox.h"
#include "fpga.h"
#include "../common/mv_common.h"
static void setup_serdes(void)
{
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
}
#if defined(CONFIG_SYS_DRAM_TEST)
int testdram(void)
{
uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
uint *p;
printf("Testing DRAM from 0x%08x to 0x%08x\n",
CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
printf("DRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf("DRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("DRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf("DRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("DRAM test passed.\n");
return 0;
}
#endif
phys_size_t initdram(int board_type)
{
u32 msize;
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk;
/* Enable PCI_CLK[0:1] */
clk->occr |= 0xc0000000;
udelay(2000);
#if defined(CONFIG_SPD_EEPROM)
msize = spd_sdram();
#else
immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize_log2;
msize = CONFIG_SYS_DDR_SIZE;
msize_log2 = __ilog2(msize);
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
udelay(50000);
im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
udelay(1000);
im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
udelay(1000);
im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
__asm__ __volatile__("sync");
udelay(1000);
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
udelay(2000);
#endif
setup_serdes();
return msize << 20;
}
int checkboard(void)
{
puts("Board: Matrix Vision MergerBox\n");
return 0;
}
int misc_init_r(void)
{
u16 dim;
int result;
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
volatile gpio83xx_t *gpio = (gpio83xx_t *)&immr->gpio[1];
unsigned char mac[6], mac_verify[6];
char *s = getenv("reset_env");
for (dim = 10; dim < 180; dim += 5) {
mergerbox_tft_dim(dim);
udelay(100000);
}
if (s)
mv_reset_environment();
i2c_read(SPD_EEPROM_ADDRESS, 0x80, 2, mac, sizeof(mac));
/* check if Matrix Vision prefix present and export to env */
if (mac[0] == 0x00 && mac[1] == 0x0c && mac[2] == 0x8d) {
printf("valid MAC found in eeprom: %pM\n", mac);
eth_setenv_enetaddr("ethaddr", mac);
} else {
printf("no valid MAC found in eeprom.\n");
/* no: check the env */
if (!eth_getenv_enetaddr("ethaddr", mac)) {
printf("no valid MAC found in env either.\n");
/* TODO: ask for valid MAC */
} else {
printf("valid MAC found in env: %pM\n", mac);
printf("updating MAC in eeprom.\n");
do {
result = test_and_clear_bit(20, &gpio->dat);
if (result)
printf("unprotect EEPROM failed !\n");
udelay(20000);
} while(result);
i2c_write(SPD_EEPROM_ADDRESS, 0x80, 2, mac, 6);
udelay(20000);
do {
result = test_and_set_bit(20, &gpio->dat);
if (result)
printf("protect EEPROM failed !\n");
udelay(20000);
} while(result);
printf("verify MAC %pM ... ", mac);
i2c_read(SPD_EEPROM_ADDRESS, 0x80, 2, mac_verify, 6);
if (!strncmp((char *)mac, (char *)mac_verify, 6))
printf("ok.\n");
else
/* TODO: retry or do something useful */
printf("FAILED (got %pM) !\n", mac_verify);
}
}
return 0;
}
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus == 0 && cs == 0;
}
void spi_cs_activate(struct spi_slave *slave)
{
volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
iopd->dat &= ~TFT_SPI_CPLD_CS;
}
void spi_cs_deactivate(struct spi_slave *slave)
{
volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
iopd->dat |= TFT_SPI_CPLD_CS;
}
/* control backlight pwm (display brightness).
* allow values 0-250 with 0 = turn off and 250 = max brightness
*/
void mergerbox_tft_dim(u16 value)
{
struct spi_slave *slave;
u16 din;
u16 dout = 0;
if (value > 0 && value < 250)
dout = 0x4000 | value;
slave = spi_setup_slave(0, 0, 1000000, SPI_MODE_0 | SPI_CS_HIGH);
spi_claim_bus(slave);
spi_xfer(slave, 16, &dout, &din, SPI_XFER_BEGIN | SPI_XFER_END);
spi_release_bus(slave);
spi_free_slave(slave);
}
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
fdt_fixup_dr_usb(blob, bd);
ft_pci_setup(blob, bd);
}

61
board/matrix_vision/mergerbox/mergerbox.h
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@ -1,61 +0,0 @@
/*
* Copyright (C) 2011 Matrix Vision GmbH
* Andre Schwarz <andre.schwarz@matrix-vision.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MERGERBOX_H__
#define __MERGERBOX_H__
#define MV_GPIO
/*
* GPIO Bank 1
*/
#define TFT_SPI_EN (0x80000000>>0)
#define FPGA_CONFIG (0x80000000>>1)
#define FPGA_STATUS (0x80000000>>2)
#define FPGA_CONF_DONE (0x80000000>>3)
#define FPGA_DIN (0x80000000>>4)
#define FPGA_CCLK (0x80000000>>5)
#define MAN_RST (0x80000000>>6)
#define FPGA_SYS_RST (0x80000000>>7)
#define WD_WDI (0x80000000>>8)
#define TFT_RST (0x80000000>>9)
#define HISCON_GPIO1 (0x80000000>>10)
#define HISCON_GPIO2 (0x80000000>>11)
#define B2B_GPIO2 (0x80000000>>12)
#define CCU_GPIN (0x80000000>>13)
#define CCU_GPOUT (0x80000000>>14)
#define TFT_GPIO0 (0x80000000>>15)
#define TFT_GPIO1 (0x80000000>>16)
#define TFT_GPIO2 (0x80000000>>17)
#define TFT_GPIO3 (0x80000000>>18)
#define B2B_GPIO0 (0x80000000>>19)
#define B2B_GPIO1 (0x80000000>>20)
#define TFT_SPI_CPLD_CS (0x80000000>>21)
#define TFT_SPI_CS (0x80000000>>22)
#define CCU_PWR_EN (0x80000000>>23)
#define B2B_GPIO3 (0x80000000>>24)
#define CCU_PWR_STAT (0x80000000>>25)
#define MV_GPIO1_DAT (FPGA_CONFIG|CCU_PWR_EN|TFT_SPI_CPLD_CS)
#define MV_GPIO1_OUT (TFT_SPI_EN|FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|CCU_PWR_EN| \
TFT_SPI_CPLD_CS)
#define MV_GPIO1_ODE (FPGA_CONFIG|MAN_RST)
/*
* GPIO Bank 2
*/
#define SPI_FLASH_WP (0x80000000>>10)
#define SYS_EEPROM_WP (0x80000000>>11)
#define SPI_FLASH_CS (0x80000000>>22)
#define MV_GPIO2_DAT (SYS_EEPROM_WP|SPI_FLASH_CS)
#define MV_GPIO2_OUT (SPI_FLASH_WP|SYS_EEPROM_WP|SPI_FLASH_CS)
#define MV_GPIO2_ODE 0
void mergerbox_tft_dim(u16 value);
#endif

128
board/matrix_vision/mergerbox/pci.c
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@ -1,128 +0,0 @@
/*
* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* Copyright (C) 2011 Matrix Vision GmbH
* Andre Schwarz <andre.schwarz@matrix-vision.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mpc83xx.h>
#include <pci.h>
#include <asm/io.h>
#include <asm/fsl_mpc83xx_serdes.h>
#include "mergerbox.h"
#include "fpga.h"
#include "../common/mv_common.h"
static struct pci_region pci_regions[] = {
{
.bus_start = CONFIG_SYS_PCI_MEM_BASE,
.phys_start = CONFIG_SYS_PCI_MEM_PHYS,
.size = CONFIG_SYS_PCI_MEM_SIZE,
.flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
.bus_start = CONFIG_SYS_PCI_MMIO_BASE,
.phys_start = CONFIG_SYS_PCI_MMIO_PHYS,
.size = CONFIG_SYS_PCI_MMIO_SIZE,
.flags = PCI_REGION_MEM
},
{
.bus_start = CONFIG_SYS_PCI_IO_BASE,
.phys_start = CONFIG_SYS_PCI_IO_PHYS,
.size = CONFIG_SYS_PCI_IO_SIZE,
.flags = PCI_REGION_IO
}
};
static struct pci_region pcie_regions_0[] = {
{
.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
.size = CONFIG_SYS_PCIE1_MEM_SIZE,
.flags = PCI_REGION_MEM,
},
{
.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
.size = CONFIG_SYS_PCIE1_IO_SIZE,
.flags = PCI_REGION_IO,
},
};
static struct pci_region pcie_regions_1[] = {
{
.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
.size = CONFIG_SYS_PCIE2_MEM_SIZE,
.flags = PCI_REGION_MEM,
},
{
.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
.size = CONFIG_SYS_PCIE2_IO_SIZE,
.flags = PCI_REGION_IO,
},
};
void pci_init_board(void)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
volatile sysconf83xx_t *sysconf = &immr->sysconf;
volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
volatile law83xx_t *pcie_law = sysconf->pcielaw;
struct pci_region *reg[] = { pci_regions };
struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
volatile gpio83xx_t *gpio;
gpio = (gpio83xx_t *)&immr->gpio[0];
gpio->dat = MV_GPIO1_DAT;
gpio->odr = MV_GPIO1_ODE;
gpio->dir = MV_GPIO1_OUT;
gpio = (gpio83xx_t *)&immr->gpio[1];
gpio->dat = MV_GPIO2_DAT;
gpio->odr = MV_GPIO2_ODE;
gpio->dir = MV_GPIO2_OUT;
printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
immr->sysconf.sicrl);
/* Enable PCI_CLK[0:1] */
clk->occr |= 0xc0000000;
udelay(2000);
mergerbox_init_fpga();
mv_load_fpga();
mergerbox_tft_dim(0);
/* Configure PCI Local Access Windows */
pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
udelay(2000);
mpc83xx_pci_init(1, reg);
/* Deassert the resets in the control register */
out_be32(&sysconf->pecr1, 0xE0008000);
out_be32(&sysconf->pecr2, 0xE0008000);
udelay(2000);
out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
mpc83xx_pcie_init(2, pcie_reg);
}

120
board/matrix_vision/mergerbox/sm107.c
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@ -1,120 +0,0 @@
/*
* Copyright (C) 2011 Matrix Vision GmbH
* Andre Schwarz <andre.schwarz@matrix-vision.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <ns16550.h>
#include <netdev.h>
#include <sm501.h>
#include <pci.h>
#include "../common/mv_common.h"
#ifdef CONFIG_VIDEO
static const SMI_REGS init_regs_800x480[] = {
/* set endianess to little endian */
{0x0005c, 0x00000000},
/* PCI drive 12mA */
{0x00004, 0x42401001},
/* current clock */
{0x0003c, 0x310a1818},
/* clocks for pm0... */
{0x00040, 0x0002184f},
{0x00044, 0x2a1a0a01},
/* GPIO */
{0x10008, 0x00000000},
{0x1000C, 0x00000000},
/* panel control regs */
{0x80000, 0x0f017106},
{0x80004, 0x0},
{0x80008, 0x0},
{0x8000C, 0x00000000},
{0x80010, 0x0c800c80},
/* width 0x320 */
{0x80014, 0x03200000},
/* height 0x1e0 */
{0x80018, 0x01E00000},
{0x8001C, 0x0},
{0x80020, 0x01df031f},
{0x80024, 0x041f031f},
{0x80028, 0x00800347},
{0x8002C, 0x020c01df},
{0x80030, 0x000201e9},
{0x80200, 0x00000000},
/* ZV[0:7] */
{0x00008, 0x00ff0000},
/* 24-Bit TFT */
{0x0000c, 0x3f000000},
{0, 0}
};
/*
* Returns SM107 register base address. First thing called in the driver.
*/
unsigned int board_video_init(void)
{
pci_dev_t devbusfn;
u32 addr;
devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
if (devbusfn != -1) {
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1,
(u32 *)&addr);
return addr & 0xfffffffe;
}
return 0;
}
/*
* Called after initializing the SM501 and before clearing the screen.
*/
void board_validate_screen(unsigned int base)
{
}
/*
* Returns SM107 framebuffer address
*/
unsigned int board_video_get_fb(void)
{
pci_dev_t devbusfn;
u32 addr;
devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
if (devbusfn != -1) {
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0,
(u32 *)&addr);
addr &= 0xfffffffe;
#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET
addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET;
#endif
return addr;
}
printf("board_video_get_fb(): FAILED\n");
return 0;
}
/*
* Return a pointer to the initialization sequence.
*/
const SMI_REGS *board_get_regs(void)
{
return init_regs_800x480;
}
int board_get_width(void)
{
return 800;
}
int board_get_height(void)
{
return 480;
}
#endif

12
board/matrix_vision/mvbc_p/Kconfig
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@ -1,12 +0,0 @@
if TARGET_MVBC_P
config SYS_BOARD
default "mvbc_p"
config SYS_VENDOR
default "matrix_vision"
config SYS_CONFIG_NAME
default "MVBC_P"
endif

6
board/matrix_vision/mvbc_p/MAINTAINERS
View file

@ -1,6 +0,0 @@
MVBC_P BOARD
#M: Andre Schwarz <andre.schwarz@matrix-vision.de>
S: Orphan (since 2014-03)
F: board/matrix_vision/mvbc_p/
F: include/configs/MVBC_P.h
F: configs/MVBC_P_defconfig

11
board/matrix_vision/mvbc_p/Makefile
View file

@ -1,11 +0,0 @@
#
# (C) Copyright 2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2004-2008
# Matrix-Vision GmbH, info@matrix-vision.de
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := mvbc_p.o fpga.o

73
board/matrix_vision/mvbc_p/README.mvbc_p
View file

@ -1,73 +0,0 @@
Matrix Vision mvBlueCOUGAR-P (mvBC-P)
-------------------------------------
1. Board Description
The mvBC-P is a 70x40x40mm multi board gigabit ethernet network camera
with main focus on GigEVision protocol in combination with local image
preprocessing.
Power Supply is either VDC 48V or Pover over Ethernet (PoE).
2 System Components
2.1 CPU
Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB.
64MB SDRAM @ 133MHz.
8 MByte Nor Flash on local bus.
1 serial ports. Console running on ttyS0 @ 115200 8N1.
2.2 PCI
PCI clock fixed at 66MHz. Arbitration inside FPGA.
Intel GD82541ER network MAC/PHY and FPGA connected.
2.3 FPGA
Altera Cyclone-II EP2C8 with PCI DMA engine.
Connects to Matrix Vision specific CCD/CMOS sensor interface.
Utilizes 64MB Nand Flash.
2.3.1 I/O @ FPGA
2 Outputs : photo coupler
2 Inputs : photo coupler
2.4 I2C
LM75 @ 0x90 for temperature monitoring.
EEPROM @ 0xA0 for vendor specifics.
image sensor interface (slave addresses depend on sensor)
3 Flash layout.
reset vector is 0x00000100, i.e. "LOWBOOT".
FF800000 u-boot
FF840000 u-boot script image
FF850000 redundant u-boot script image
FF860000 FPGA raw bit file
FF8A0000 tbd.
FF900000 root FS
FFC00000 kernel
FFFC0000 device tree blob
FFFD0000 redundant device tree blob
FFFE0000 environment
FFFF0000 redundant environment
mtd partitions are propagated to linux kernel via device tree blob.
4 Booting
On startup the bootscript @ FF840000 is executed. This script can be
exchanged easily. Default boot mode is "boot from flash", i.e. system
works stand-alone.
This behaviour depends on some environment variables :
"netboot" : yes ->try dhcp/bootp and boot from network.
A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
DHCP server configuration, e.g. to provide different images to
different devices.
During netboot the system tries to get 3 image files:
1. Kernel - name + data is given during BOOTP.
2. Initrd - name is stored in "initrd_name"
3. device tree blob - name is stored in "dtb_name"
Fallback files are the flash versions.

157
board/matrix_vision/mvbc_p/fpga.c
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@ -1,157 +0,0 @@
/*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
* Keith Outwater, keith_outwater@mvis.com.
*
* (C) Copyright 2008
* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <ACEX1K.h>
#include <command.h>
#include "fpga.h"
#include "mvbc_p.h"
#ifdef FPGA_DEBUG
#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args)
#else
#define fpga_debug(fmt, args...)
#endif
Altera_CYC2_Passive_Serial_fns altera_fns = {
fpga_null_fn,
fpga_config_fn,
fpga_status_fn,
fpga_done_fn,
fpga_wr_fn,
fpga_null_fn,
fpga_null_fn,
};
Altera_desc cyclone2 = {
Altera_CYC2,
passive_serial,
Altera_EP2C8_SIZE,
(void *) &altera_fns,
NULL,
};
DECLARE_GLOBAL_DATA_PTR;
int mvbc_p_init_fpga(void)
{
fpga_debug("Initialize FPGA interface\n");
fpga_init();
fpga_add(fpga_altera, &cyclone2);
fpga_config_fn(0, 1, 0);
udelay(60);
return 1;
}
int fpga_null_fn(int cookie)
{
return 0;
}
int fpga_config_fn(int assert, int flush, int cookie)
{
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
u32 dvo = gpio->simple_dvo;
fpga_debug("SET config : %s\n", assert ? "low" : "high");
if (assert)
dvo |= FPGA_CONFIG;
else
dvo &= ~FPGA_CONFIG;
if (flush)
gpio->simple_dvo = dvo;
return assert;
}
int fpga_done_fn(int cookie)
{
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
int result = 0;
udelay(10);
fpga_debug("CONF_DONE check ... ");
if (gpio->simple_ival & FPGA_CONF_DONE) {
fpga_debug("high\n");
result = 1;
} else
fpga_debug("low\n");
return result;
}
int fpga_status_fn(int cookie)
{
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
int result = 0;
fpga_debug("STATUS check ... ");
if (gpio->sint_ival & FPGA_STATUS) {
fpga_debug("high\n");
result = 1;
} else
fpga_debug("low\n");
return result;
}
int fpga_clk_fn(int assert_clk, int flush, int cookie)
{
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
u32 dvo = gpio->simple_dvo;
fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
if (assert_clk)
dvo |= FPGA_CCLK;
else
dvo &= ~FPGA_CCLK;
if (flush)
gpio->simple_dvo = dvo;
return assert_clk;
}
static inline int _write_fpga(u8 val)
{
int i;
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
u32 dvo = gpio->simple_dvo;
for (i=0; i<8; i++) {
dvo &= ~FPGA_CCLK;
gpio->simple_dvo = dvo;
dvo &= ~FPGA_DIN;
if (val & 1)
dvo |= FPGA_DIN;
gpio->simple_dvo = dvo;
dvo |= FPGA_CCLK;
gpio->simple_dvo = dvo;
val >>= 1;
}
return 0;
}
int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
{
unsigned char *data = (unsigned char *) buf;
int i;
fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
for (i = 0; i < len; i++)
_write_fpga(data[i]);
fpga_debug("\n");
return FPGA_SUCCESS;
}

17
board/matrix_vision/mvbc_p/fpga.h
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@ -1,17 +0,0 @@
/*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
* Keith Outwater, keith_outwater@mvis.com.
*
* SPDX-License-Identifier: GPL-2.0+
*/
extern int mvbc_p_init_fpga(void);
extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
extern int fpga_status_fn(int cookie);
extern int fpga_config_fn(int assert, int flush, int cookie);
extern int fpga_done_fn(int cookie);
extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
extern int fpga_null_fn(int cookie);

255
board/matrix_vision/mvbc_p/mvbc_p.c
View file

@ -1,255 +0,0 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* (C) Copyright 2005-2007
* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mpc5xxx.h>
#include <malloc.h>
#include <pci.h>
#include <i2c.h>
#include <fpga.h>
#include <environment.h>
#include <fdt_support.h>
#include <netdev.h>
#include <asm/io.h>
#include "fpga.h"
#include "mvbc_p.h"
#include "../common/mv_common.h"
#define SDRAM_MODE 0x00CD0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xD2322800
#define SDRAM_CONFIG2 0x8AD70000
DECLARE_GLOBAL_DATA_PTR;
static void sdram_start (int hi_addr)
{
long hi_bit = hi_addr ? 0x01000000 : 0;
/* unlock mode register */
out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | hi_bit);
/* precharge all banks */
out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
/* precharge all banks */
out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
/* auto refresh */
out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | hi_bit);
/* set mode register */
out_be32((u32*)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
/* normal operation */
out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
}
phys_addr_t initdram (int board_type)
{
ulong dramsize = 0;
ulong test1,
test2;
/* setup SDRAM chip selects */
out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
/* setup config registers */
out_be32((u32*)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
out_be32((u32*)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
sdram_start(1);
test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
} else
dramsize = test2;
if (dramsize < (1 << 20))
dramsize = 0;
if (dramsize > 0)
out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x13 +
__builtin_ffs(dramsize >> 20) - 1);
else
out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0);
return dramsize;
}
void mvbc_init_gpio(void)
{
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
printf("Ports : 0x%08x\n", gpio->port_config);
printf("PORCFG: 0x%08lx\n", *(vu_long*)MPC5XXX_CDM_PORCFG);
out_be32(&gpio->simple_ddr, SIMPLE_DDR);
out_be32(&gpio->simple_dvo, SIMPLE_DVO);
out_be32(&gpio->simple_ode, SIMPLE_ODE);
out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
out_8(&gpio->sint_ode, SINT_ODE);
out_8(&gpio->sint_ddr, SINT_DDR);
out_8(&gpio->sint_dvo, SINT_DVO);
out_8(&gpio->sint_inten, SINT_INTEN);
out_be16(&gpio->sint_itype, SINT_ITYPE);
out_8(&gpio->sint_gpioe, SINT_GPIOEN);
out_8((u8*)MPC5XXX_WU_GPIO_ODE, WKUP_ODE);
out_8((u8*)MPC5XXX_WU_GPIO_DIR, WKUP_DIR);
out_8((u8*)MPC5XXX_WU_GPIO_DATA_O, WKUP_DO);
out_8((u8*)MPC5XXX_WU_GPIO_ENABLE, WKUP_EN);
printf("simple_gpioe: 0x%08x\n", gpio->simple_gpioe);
printf("sint_gpioe : 0x%08x\n", gpio->sint_gpioe);
}
int misc_init_r(void)
{
char *s = getenv("reset_env");
if (!s) {
if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
return 0;
udelay(50000);
if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
return 0;
udelay(50000);
if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
return 0;
}
printf(" === FACTORY RESET ===\n");
mv_reset_environment();
saveenv();
return -1;
}
int checkboard(void)
{
mvbc_init_gpio();
printf("Board: Matrix Vision mvBlueCOUGAR-P\n");
return 0;
}
void flash_preinit(void)
{
/*
* Now, when we are in RAM, enable flash write
* access for detection process.
* Note that CS_BOOT cannot be cleared when
* executing in flash.
*/
clrbits_be32((u32*)MPC5XXX_BOOTCS_CFG, 0x1);
}
void flash_afterinit(ulong size)
{
out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_BOOTCS_START |
size));
out_be32((u32*)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_BOOTCS_START |
size));
out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
size));
out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
size));
}
void pci_mvbc_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
unsigned char line = 0xff;
char *s = getenv("pci_latency");
u32 base;
u8 val = 0;
if (s)
val = simple_strtoul(s, NULL, 16);
if (PCI_BUS(dev) == 0) {
switch (PCI_DEV (dev)) {
case 0xa: /* FPGA */
line = 3;
pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &base);
printf("found FPGA - enable arbitration\n");
writel(0x03, (u32*)(base + 0x80c0));
writel(0xf0, (u32*)(base + 0x8080));
if (val)
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val);
break;
case 0xb: /* LAN */
line = 2;
if (val)
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val);
break;
case 0x1a:
break;
default:
printf ("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV (dev));
break;
}
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line);
}
}
struct pci_controller hose = {
fixup_irq:pci_mvbc_fixup_irq
};
extern void pci_mpc5xxx_init(struct pci_controller *);
void pci_init_board(void)
{
mvbc_p_init_fpga();
mv_load_fpga();
pci_mpc5xxx_init(&hose);
}
void show_boot_progress(int val)
{
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
switch(val) {
case BOOTSTAGE_ID_START: /* FPGA ok */
setbits_be32(&gpio->simple_dvo, LED_G0);
break;
case BOOTSTAGE_ID_NET_ETH_INIT:
setbits_be32(&gpio->simple_dvo, LED_G1);
break;
case BOOTSTAGE_ID_COPY_RAMDISK:
setbits_be32(&gpio->simple_dvo, LED_Y);
break;
case BOOTSTAGE_ID_RUN_OS:
setbits_be32(&gpio->simple_dvo, LED_R);
break;
default:
break;
}
}
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
}
int board_eth_init(bd_t *bis)
{
cpu_eth_init(bis); /* Built in FEC comes first */
return pci_eth_init(bis);
}

43
board/matrix_vision/mvbc_p/mvbc_p.h
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@ -1,43 +0,0 @@
#ifndef __MVBC_H__
#define __MVBC_H__
#define LED_G0 MPC5XXX_GPIO_SIMPLE_PSC2_0
#define LED_G1 MPC5XXX_GPIO_SIMPLE_PSC2_1
#define LED_Y MPC5XXX_GPIO_SIMPLE_PSC2_2
#define LED_R MPC5XXX_GPIO_SIMPLE_PSC2_3
#define ARB_X_EN MPC5XXX_GPIO_WKUP_PSC2_4
#define FPGA_DIN MPC5XXX_GPIO_SIMPLE_PSC3_0
#define FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_1
#define FPGA_CONF_DONE MPC5XXX_GPIO_SIMPLE_PSC3_2
#define FPGA_CONFIG MPC5XXX_GPIO_SIMPLE_PSC3_3
#define FPGA_STATUS MPC5XXX_GPIO_SINT_PSC3_4
#define MAN_RST MPC5XXX_GPIO_WKUP_PSC6_0
#define WD_TS MPC5XXX_GPIO_WKUP_PSC6_1
#define WD_WDI MPC5XXX_GPIO_SIMPLE_PSC6_2
#define COP_PRESENT MPC5XXX_GPIO_SIMPLE_PSC6_3
#define FACT_RST MPC5XXX_GPIO_WKUP_6
#define FLASH_RBY MPC5XXX_GPIO_WKUP_7
#define SIMPLE_DDR (LED_G0 | LED_G1 | LED_Y | LED_R | \
FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI)
#define SIMPLE_DVO (FPGA_CONFIG)
#define SIMPLE_ODE (FPGA_CONFIG | LED_G0 | LED_G1 | LED_Y | LED_R)
#define SIMPLE_GPIOEN (LED_G0 | LED_G1 | LED_Y | LED_R | \
FPGA_DIN | FPGA_CCLK | FPGA_CONF_DONE | FPGA_CONFIG |\
WD_WDI | COP_PRESENT)
#define SINT_ODE 0
#define SINT_DDR 0
#define SINT_DVO 0
#define SINT_INTEN 0
#define SINT_ITYPE 0
#define SINT_GPIOEN (FPGA_STATUS)
#define WKUP_ODE (MAN_RST)
#define WKUP_DIR (ARB_X_EN|MAN_RST|WD_TS)
#define WKUP_DO (ARB_X_EN|MAN_RST|WD_TS)
#define WKUP_EN (ARB_X_EN|MAN_RST|WD_TS|FACT_RST|FLASH_RBY)
#endif

48
board/matrix_vision/mvbc_p/mvbc_p_autoscript
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@ -1,48 +0,0 @@
echo
echo "==== running autoscript ===="
echo
setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram}
setenv ramkernel setenv kernel_boot \${loadaddr}
setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length}
setenv bootfromflash run flashkernel cpird ramparam addcons e1000para addprofile bootdtb
setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name}
setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000
setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup
setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel
if test ${console} = yes;
then
setenv addcons setenv bootargs \${bootargs} console=ttyPSC\${console_nr},\${baudrate}N8
else
setenv addcons setenv bootargs \${bootargs} console=tty0
fi
setenv e1000para setenv bootargs \${bootargs} e1000.TxDescriptors=256 e1000.SmartPowerDownEnable=1
setenv set_static_ip setenv ipaddr \${static_ipaddr}
setenv set_static_nm setenv netmask \${static_netmask}
setenv set_static_gw setenv gatewayip \${static_gateway}
setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask}
setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs
if test ${oprofile} = yes;
then
setenv addprofile setenv bootargs \${bootargs} profile=\${profile}
fi
if test ${autoscript_boot} != no;
then
if test ${netboot} = yes;
then
bootp
if test $? = 0;
then
echo "=== bootp succeeded -> netboot ==="
run set_ip
run getdtb rundtb bootfromnet ramparam addcons e1000para addprofile bootdtb
else
echo "=== netboot failed ==="
fi
fi
run set_static_ip set_static_nm set_static_gw set_ip
echo "=== bootfromflash ==="
run cpdtb rundtb bootfromflash
else
echo "=== boot stopped with autoscript_boot no ==="
fi

1
board/matrix_vision/mvblm7/.gitignore vendored
View file

@ -1 +0,0 @@
bootscript.img

12
board/matrix_vision/mvblm7/Kconfig
View file

@ -1,12 +0,0 @@
if TARGET_MVBLM7
config SYS_BOARD
default "mvblm7"
config SYS_VENDOR
default "matrix_vision"
config SYS_CONFIG_NAME
default "MVBLM7"
endif

6
board/matrix_vision/mvblm7/MAINTAINERS
View file

@ -1,6 +0,0 @@
MVBLM7 BOARD
#M: Andre Schwarz <andre.schwarz@matrix-vision.de>
S: Orphan (since 2014-03)
F: board/matrix_vision/mvblm7/
F: include/configs/MVBLM7.h
F: configs/MVBLM7_defconfig

14
board/matrix_vision/mvblm7/Makefile
View file

@ -1,14 +0,0 @@
#
# Copyright (C) Freescale Semiconductor, Inc. 2006.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := mvblm7.o pci.o fpga.o
extra-y := bootscript.img
MKIMAGEFLAGS_bootscript.image := -T script -C none -n M7_script
$(obj)/bootscript.img: $(src)/bootscript
$(call cmd,mkimage)

84
board/matrix_vision/mvblm7/README.mvblm7
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@ -1,84 +0,0 @@
Matrix Vision mvBlueLYNX-M7 (mvBL-M7)
-------------------------------------
1. Board Description
The mvBL-M7 is a 120x120mm single board computing platform
with strong focus on stereo image processing applications.
Power Supply is either VDC 12-48V or Pover over Ethernet (PoE)
on any port (requires add-on board).
2 System Components
2.1 CPU
Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb.
512MByte DDR-II memory @ 133MHz.
8 MByte Nor Flash on local bus.
2 Vitesse VSC8601 RGMII ethernet Phys.
1 USB host controller over ULPI I/F.
2 serial ports. Console running on ttyS0 @ 115200 8N1.
1 SD-Card slot connected to SPI.
System configuration (HRCW) is taken from I2C EEPROM.
2.2 PCI
A miniPCI Type-III socket is present. PCI clock fixed at 66MHz.
2.3 FPGA
Altera Cyclone-II EP2C20/35 with PCI DMA engines.
Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces.
Utilizes another 256MB DDR-II memory and 32-128MB Nand Flash.
2.3.1 I/O @ FPGA
2x8 Outputs : Infineon High-Side Switches to Main Supply.
2x8 Inputs : Programmable input threshold + trigger capabilities
2 dedicated flash interfaces for illuminator boards.
Cross trigger for chaining several boards.
2.4 I2C
Bus1:
MAX5381 DAC @ 0x60 for 1st digital input threshold.
LM75 @ 0x90 for temperature monitoring.
EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics.
1st image sensor interface (slave addresses depend on sensor)
Bus2:
MAX5381 DAC @ 0x60 for 2nd digital input threshold.
2nd image sensor interface (slave addresses depend on sensor)
3 Flash layout.
reset vector is 0xFFF00100, i.e. "HIGHBOOT".
FF800000 environment
FF802000 redundant environment
FF804000 u-boot script image
FF806000 redundant u-boot script image
FF808000 device tree blob
FF80A000 redundant device tree blob
FF80C000 tbd.
FF80E000 tbd.
FF810000 kernel
FFC00000 root FS
FFF00000 u-boot
FFF80000 FPGA raw bit file
mtd partitions are propagated to linux kernel via device tree blob.
4 Booting
On startup the bootscript @ FF804000 is executed. This script can be
exchanged easily. Default boot mode is "boot from flash", i.e. system
works stand-alone.
This behaviour depends on some environment variables :
"netboot" : yes ->try dhcp/bootp and boot from network.
A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
DHCP server configuration, e.g. to provide different images to
different devices.
During netboot the system tries to get 3 image files:
1. Kernel - name + data is given during BOOTP.
2. Initrd - name is stored in "initrd_name"
3. device tree blob - name is stored in "dtb_name"
Fallback files are the flash versions.

43
board/matrix_vision/mvblm7/bootscript
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@ -1,43 +0,0 @@
echo
echo "==== running autoscript ===="
echo
setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram}
setenv ramkernel setenv kernel_boot \${loadaddr}
setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length}
setenv bootfromflash run flashkernel cpird ramparam addcons bootdtb
setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name}
setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000
setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup
setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel
if test ${console} = yes;
then
setenv addcons setenv bootargs \${bootargs} console=ttyS\${console_nr},\${baudrate}N8
else
setenv addcons setenv bootargs \${bootargs} console=tty0
fi
setenv set_static_ip setenv ipaddr \${static_ipaddr}
setenv set_static_nm setenv netmask \${static_netmask}
setenv set_static_gw setenv gatewayip \${static_gateway}
setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask}
setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs
if test ${autoscript_boot} != no;
then
if test ${netboot} = yes;
then
bootp
if test $? = 0;
then
echo "=== bootp succeeded -> netboot ==="
run set_ip
run getdtb rundtb bootfromnet ramparam addcons bootdtb
else
echo "=== netboot failed ==="
fi
fi
run set_static_ip set_static_nm set_static_gw set_ip
echo "=== bootfromflash ==="
run cpdtb rundtb bootfromflash
else
echo "=== boot stopped with autoscript_boot no ==="
fi

169
board/matrix_vision/mvblm7/fpga.c
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@ -1,169 +0,0 @@
/*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
* Keith Outwater, keith_outwater@mvis.com.
*
* (C) Copyright 2008
* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <ACEX1K.h>
#include <command.h>
#include "fpga.h"
#include "mvblm7.h"
#ifdef FPGA_DEBUG
#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args)
#else
#define fpga_debug(fmt, args...)
#endif
Altera_CYC2_Passive_Serial_fns altera_fns = {
fpga_null_fn,
fpga_config_fn,
fpga_status_fn,
fpga_done_fn,
fpga_wr_fn,
fpga_null_fn,
fpga_null_fn,
};
Altera_desc cyclone2 = {
Altera_CYC2,
passive_serial,
Altera_EP2C20_SIZE,
(void *) &altera_fns,
NULL,
0
};
DECLARE_GLOBAL_DATA_PTR;
int mvblm7_init_fpga(void)
{
fpga_debug("Initialize FPGA interface\n");
fpga_init();
fpga_add(fpga_altera, &cyclone2);
fpga_config_fn(0, 1, 0);
udelay(60);
return 1;
}
int fpga_null_fn(int cookie)
{
return 0;
}
int fpga_config_fn(int assert, int flush, int cookie)
{
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
u32 dvo = gpio->dat;
fpga_debug("SET config : %s\n", assert ? "low" : "high");
if (assert)
dvo |= FPGA_CONFIG;
else
dvo &= ~FPGA_CONFIG;
if (flush)
gpio->dat = dvo;
return assert;
}
int fpga_done_fn(int cookie)
{
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
int result = 0;
udelay(10);
fpga_debug("CONF_DONE check ... ");
if (gpio->dat & FPGA_CONF_DONE) {
fpga_debug("high\n");
result = 1;
} else
fpga_debug("low\n");
return result;
}
int fpga_status_fn(int cookie)
{
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
int result = 0;
fpga_debug("STATUS check ... ");
if (gpio->dat & FPGA_STATUS) {
fpga_debug("high\n");
result = 1;
} else
fpga_debug("low\n");
return result;
}
int fpga_clk_fn(int assert_clk, int flush, int cookie)
{
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
u32 dvo = gpio->dat;
fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
if (assert_clk)
dvo |= FPGA_CCLK;
else
dvo &= ~FPGA_CCLK;
if (flush)
gpio->dat = dvo;
return assert_clk;
}
static inline int _write_fpga(u8 val, int dump)
{
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
int i;
u32 dvo = gpio->dat;
if (dump)
fpga_debug(" %02x -> ", val);
for (i = 0; i < 8; i++) {
dvo &= ~FPGA_CCLK;
gpio->dat = dvo;
dvo &= ~FPGA_DIN;
if (dump)
fpga_debug("%d ", val&1);
if (val & 1)
dvo |= FPGA_DIN;
gpio->dat = dvo;
dvo |= FPGA_CCLK;
gpio->dat = dvo;
val >>= 1;
}
if (dump)
fpga_debug("\n");
return 0;
}
int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
{
unsigned char *data = (unsigned char *) buf;
int i;
fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
for (i = 0; i < len; i++)
_write_fpga(data[i], 0);
fpga_debug("\n");
return FPGA_SUCCESS;
}

17
board/matrix_vision/mvblm7/fpga.h
View file

@ -1,17 +0,0 @@
/*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
* Keith Outwater, keith_outwater@mvis.com.
*
* SPDX-License-Identifier: GPL-2.0+
*/
extern int mvblm7_init_fpga(void);
extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
extern int fpga_status_fn(int cookie);
extern int fpga_config_fn(int assert, int flush, int cookie);
extern int fpga_done_fn(int cookie);
extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
extern int fpga_null_fn(int cookie);

136
board/matrix_vision/mvblm7/mvblm7.c
View file

@ -1,136 +0,0 @@
/*
* Copyright (C) Freescale Semiconductor, Inc. 2006.
*
* (C) Copyright 2008
* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <asm/mpc8349_pci.h>
#include <pci.h>
#include <spi.h>
#include <asm/mmu.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#include "../common/mv_common.h"
#include "mvblm7.h"
int fixed_sdram(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
u32 ddr_size;
u32 ddr_size_log2;
char *s = getenv("ddr_size");
msize = CONFIG_SYS_DDR_SIZE;
if (s) {
u32 env_ddr_size = simple_strtoul(s, NULL, 10);
if (env_ddr_size == 512)
msize = 512;
}
for (ddr_size = msize << 20, ddr_size_log2 = 0;
(ddr_size > 1);
ddr_size = ddr_size >> 1, ddr_size_log2++) {
if (ddr_size & 1)
return -1;
}
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
LAWAR_SIZE);
im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
asm("sync;isync");
udelay(600);
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
asm("sync;isync");
udelay(500);
return msize;
}
phys_size_t initdram(int board_type)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
return -1;
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
msize = fixed_sdram();
/* return total bus RAM size(bytes) */
return msize * 1024 * 1024;
}
int misc_init_r(void)
{
char *s = getenv("reset_env");
if (s) {
mv_reset_environment();
}
return 0;
}
int checkboard(void)
{
puts("Board: Matrix Vision mvBlueLYNX-M7\n");
return 0;
}
#ifdef CONFIG_HARD_SPI
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus == 0 && cs == 0;
}
void spi_cs_activate(struct spi_slave *slave)
{
volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
iopd->dat &= ~MVBLM7_MMC_CS;
}
void spi_cs_deactivate(struct spi_slave *slave)
{
volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
iopd->dat |= ~MVBLM7_MMC_CS;
}
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
}
#endif

20
board/matrix_vision/mvblm7/mvblm7.h
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@ -1,20 +0,0 @@
#ifndef __MVBC_H__
#define __MVBC_H__
#define MV_GPIO
#define FPGA_CONFIG 0x80000000
#define FPGA_CCLK 0x40000000
#define FPGA_DIN 0x20000000
#define FPGA_STATUS 0x10000000
#define FPGA_CONF_DONE 0x08000000
#define WD_WDI 0x00400000
#define WD_TS 0x00200000
#define MAN_RST 0x00100000
#define MV_GPIO_DAT (WD_TS)
#define MV_GPIO_OUT (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|MVBLM7_MMC_CS)
#define MV_GPIO_ODE (FPGA_CONFIG|MAN_RST)
#endif

89
board/matrix_vision/mvblm7/pci.c
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@ -1,89 +0,0 @@
/*
* Copyright (C) Freescale Semiconductor, Inc. 2006.
*
* (C) Copyright 2008
* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#include <pci.h>
#include <mpc83xx.h>
#include <fpga.h>
#include "mvblm7.h"
#include "fpga.h"
#include "../common/mv_common.h"
DECLARE_GLOBAL_DATA_PTR;
static struct pci_region pci_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
size: CONFIG_SYS_PCI1_MEM_SIZE,
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
size: CONFIG_SYS_PCI1_MMIO_SIZE,
flags: PCI_REGION_MEM
},
{
bus_start: CONFIG_SYS_PCI1_IO_BASE,
phys_start: CONFIG_SYS_PCI1_IO_PHYS,
size: CONFIG_SYS_PCI1_IO_SIZE,
flags: PCI_REGION_IO
}
};
void pci_init_board(void)
{
int i;
volatile immap_t *immr;
volatile pcictrl83xx_t *pci_ctrl;
volatile gpio83xx_t *gpio;
volatile clk83xx_t *clk;
volatile law83xx_t *pci_law;
struct pci_region *reg[] = { pci_regions };
immr = (immap_t *) CONFIG_SYS_IMMR;
clk = (clk83xx_t *) &immr->clk;
pci_ctrl = immr->pci_ctrl;
pci_law = immr->sysconf.pcilaw;
gpio = (volatile gpio83xx_t *)&immr->gpio[0];
gpio->dat = MV_GPIO_DAT;
gpio->odr = MV_GPIO_ODE;
gpio->dir = MV_GPIO_OUT;
printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
immr->sysconf.sicrl);
mvblm7_init_fpga();
mv_load_fpga();
gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK);
/* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */
clk->occr = 0xc0000000;
pci_ctrl[0].gcr = 0;
udelay(2000);
pci_ctrl[0].gcr = 1;
for (i = 0; i < 1000; ++i)
udelay(1000);
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB;
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
mpc83xx_pci_init(1, reg);
}

1
board/matrix_vision/mvsmr/.gitignore vendored
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@ -1 +0,0 @@
bootscript.img

12
board/matrix_vision/mvsmr/Kconfig
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@ -1,12 +0,0 @@
if TARGET_MVSMR
config SYS_BOARD
default "mvsmr"
config SYS_VENDOR
default "matrix_vision"
config SYS_CONFIG_NAME
default "MVSMR"
endif

6
board/matrix_vision/mvsmr/MAINTAINERS
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@ -1,6 +0,0 @@
MVSMR BOARD
#M: Andre Schwarz <andre.schwarz@matrix-vision.de>
S: Orphan (since 2014-03)
F: board/matrix_vision/mvsmr/
F: include/configs/MVSMR.h
F: configs/MVSMR_defconfig

18
board/matrix_vision/mvsmr/Makefile
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@ -1,18 +0,0 @@
#
# (C) Copyright 2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2004-2008
# Matrix-Vision GmbH, info@matrix-vision.de
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := mvsmr.o fpga.o
extra-y := bootscript.img
MKIMAGEFLAGS_bootscript.image := -T script -C none -n mvSMR_Script
$(obj)/bootscript.img: $(src)/bootscript
$(call cmd,mkimage)

55
board/matrix_vision/mvsmr/README.mvsmr
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@ -1,55 +0,0 @@
Matrix Vision mvSMR
-------------------
1. Board Description
The mvSMR is a 75x130mm single image processing board used
in automation. Power Supply is 24VDC.
2 System Components
2.1 CPU
Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB.
64MB DDR-I @ 133MHz.
8 MByte Nor Flash on local bus.
2 serial ports. Console running on ttyS0 @ 115200 8N1.
2.2 PCI
PCI clock fixed at 33MHz due to old'n'slow Xilinx PCI core.
2.3 FPGA
Xilinx Spartan-3 XC3S200 with PCI DMA engine.
Connects to Matrix Vision specific CCD/CMOS sensor interface.
2.4 I2C
EEPROM @ 0xA0 for vendor specifics.
image sensor interface (slave addresses depend on sensor)
3 Flash layout.
reset vector is 0x00000100, i.e. "LOWBOOT".
FF800000 u-boot
FF806000 u-boot script image
FF808000 u-boot environment
FF840000 FPGA raw bit file
FF880000 root FS
FFF00000 kernel
4 Booting
On startup the bootscript @ FF806000 is executed. This script can be
exchanged easily. Default boot mode is "boot from flash", i.e. system
works stand-alone.
This behaviour depends on some environment variables :
"netboot" : yes ->try dhcp/bootp and boot from network.
A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
DHCP server configuration, e.g. to provide different images to
different devices.
During netboot the system tries to get 3 image files:
1. Kernel - name + data is given during BOOTP.
2. Initrd - name is stored in "initrd_name"
Fallback files are the flash versions.

42
board/matrix_vision/mvsmr/bootscript
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@ -1,42 +0,0 @@
echo
echo "==== running autoscript ===="
echo
setenv boot24 'bootm ${kernel_boot} ${mv_initrd_addr_ram}'
setenv ramkernel 'setenv kernel_boot ${loadaddr}'
setenv flashkernel 'setenv kernel_boot ${mv_kernel_addr}'
setenv cpird 'cp ${mv_initrd_addr} ${mv_initrd_addr_ram} ${mv_initrd_length}'
setenv bootfromflash run flashkernel cpird addcons boot24
setenv bootfromnet 'tftp ${mv_initrd_addr_ram} ${initrd_name};run ramkernel'
if test ${console} = yes;
then
setenv addcons 'setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8'
else
setenv addcons 'setenv bootargs ${bootargs} console=tty0'
fi
setenv set_static_ip 'setenv ipaddr ${static_ipaddr}'
setenv set_static_nm 'setenv netmask ${static_netmask}'
setenv set_static_gw 'setenv gatewayip ${static_gateway}'
setenv set_ip 'setenv ip ${ipaddr}::${gatewayip}:${netmask}'
if test ${servicemode} != yes;
then
echo "=== forced flash mode ==="
run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
fi
if test ${autoscript_boot} != no;
then
if test ${netboot} = yes;
then
bootp
if test $? = 0;
then
echo "=== bootp succeeded -> netboot ==="
run set_ip bootfromnet addcons boot24
else
echo "=== netboot failed ==="
fi
fi
echo "=== bootfromflash ==="
run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
else
echo "=== boot stopped with autoscript_boot no ==="
fi

112
board/matrix_vision/mvsmr/fpga.c
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/*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
* Keith Outwater, keith_outwater@mvis.com.
*
* (C) Copyright 2010
* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spartan3.h>
#include <command.h>
#include <asm/io.h>
#include "fpga.h"
#include "mvsmr.h"
xilinx_spartan3_slave_serial_fns fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
fpga_init_fn,
fpga_done_fn,
fpga_wr_fn,
0
};
xilinx_desc spartan3 = {
xilinx_spartan2,
slave_serial,
XILINX_XC3S200_SIZE,
(void *) &fpga_fns,
0,
};
DECLARE_GLOBAL_DATA_PTR;
int mvsmr_init_fpga(void)
{
fpga_init();
fpga_add(fpga_xilinx, &spartan3);
return 1;
}
int fpga_init_fn(int cookie)
{
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
if (in_be32(&gpio->simple_ival) & FPGA_CONFIG)
return 0;
return 1;
}
int fpga_done_fn(int cookie)
{
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
int result = 0;
udelay(10);
if (in_be32(&gpio->simple_ival) & FPGA_DONE)
result = 1;
return result;
}
int fpga_pgm_fn(int assert, int flush, int cookie)
{
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
if (!assert)
setbits_8(&gpio->sint_dvo, FPGA_STATUS);
else
clrbits_8(&gpio->sint_dvo, FPGA_STATUS);
return assert;
}
int fpga_clk_fn(int assert_clk, int flush, int cookie)
{
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
if (assert_clk)
setbits_be32(&gpio->simple_dvo, FPGA_CCLK);
else
clrbits_be32(&gpio->simple_dvo, FPGA_CCLK);
return assert_clk;
}
int fpga_wr_fn(int assert_write, int flush, int cookie)
{
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
if (assert_write)
setbits_be32(&gpio->simple_dvo, FPGA_DIN);
else
clrbits_be32(&gpio->simple_dvo, FPGA_DIN);
return assert_write;
}
int fpga_pre_config_fn(int cookie)
{
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
setbits_8(&gpio->sint_dvo, FPGA_STATUS);
return 0;
}

15
board/matrix_vision/mvsmr/fpga.h
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@ -1,15 +0,0 @@
/*
* (C) Copyright 2008
* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
*
* SPDX-License-Identifier: GPL-2.0+
*/
extern int mvsmr_init_fpga(void);
extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
extern int fpga_init_fn(int cookie);
extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
extern int fpga_wr_fn(int assert_write, int flush, int cookie);
extern int fpga_done_fn(int cookie);
extern int fpga_pre_config_fn(int cookie);

248
board/matrix_vision/mvsmr/mvsmr.c
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@ -1,248 +0,0 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* (C) Copyright 2005-2010
* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mpc5xxx.h>
#include <malloc.h>
#include <pci.h>
#include <i2c.h>
#include <fpga.h>
#include <environment.h>
#include <netdev.h>
#include <asm/io.h>
#include "fpga.h"
#include "mvsmr.h"
#include "../common/mv_common.h"
#define SDRAM_DDR 1
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONTROL 0x715f0f00
#define SDRAM_CONFIG1 0xd3722930
#define SDRAM_CONFIG2 0x46770000
DECLARE_GLOBAL_DATA_PTR;
static void sdram_start(int hi_addr)
{
long hi_bit = hi_addr ? 0x01000000 : 0;
/* unlock mode register */
out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 |
hi_bit);
/* precharge all banks */
out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
hi_bit);
/* set mode register: extended mode */
out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
/* set mode register: reset DLL */
out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
/* precharge all banks */
out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
hi_bit);
/* auto refresh */
out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 |
hi_bit);
/* set mode register */
out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
/* normal operation */
out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
}
phys_addr_t initdram(int board_type)
{
ulong dramsize = 0;
ulong test1,
test2;
/* setup SDRAM chip selects */
out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
/* setup config registers */
out_be32((u32 *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
out_be32((u32 *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
sdram_start(1);
test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
} else
dramsize = test2;
if (dramsize < (1 << 20))
dramsize = 0;
if (dramsize > 0)
out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x13 +
__builtin_ffs(dramsize >> 20) - 1);
else
out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0);
return dramsize;
}
void mvsmr_init_gpio(void)
{
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
struct mpc5xxx_wu_gpio *wu_gpio =
(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
struct mpc5xxx_gpt_0_7 *timers = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
printf("Ports : 0x%08x\n", gpio->port_config);
printf("PORCFG: 0x%08x\n", in_be32((unsigned *)MPC5XXX_CDM_PORCFG));
out_be32(&gpio->simple_ddr, SIMPLE_DDR);
out_be32(&gpio->simple_dvo, SIMPLE_DVO);
out_be32(&gpio->simple_ode, SIMPLE_ODE);
out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
out_8(&gpio->sint_ode, SINT_ODE);
out_8(&gpio->sint_ddr, SINT_DDR);
out_8(&gpio->sint_dvo, SINT_DVO);
out_8(&gpio->sint_inten, SINT_INTEN);
out_be16(&gpio->sint_itype, SINT_ITYPE);
out_8(&gpio->sint_gpioe, SINT_GPIOEN);
out_8(&wu_gpio->ode, WKUP_ODE);
out_8(&wu_gpio->ddr, WKUP_DIR);
out_8(&wu_gpio->dvo, WKUP_DO);
out_8(&wu_gpio->enable, WKUP_EN);
out_be32(&timers->gpt0.emsr, 0x00000234); /* OD output high */
out_be32(&timers->gpt1.emsr, 0x00000234);
out_be32(&timers->gpt2.emsr, 0x00000234);
out_be32(&timers->gpt3.emsr, 0x00000234);
out_be32(&timers->gpt4.emsr, 0x00000234);
out_be32(&timers->gpt5.emsr, 0x00000234);
out_be32(&timers->gpt6.emsr, 0x00000024); /* push-pull output low */
out_be32(&timers->gpt7.emsr, 0x00000024);
}
int misc_init_r(void)
{
char *s = getenv("reset_env");
if (s) {
printf(" === FACTORY RESET ===\n");
mv_reset_environment();
saveenv();
}
return -1;
}
void mvsmr_get_dbg_present(void)
{
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
if (in_be32(&gpio->simple_ival) & COP_PRESENT) {
setenv("dbg_present", "no\0");
setenv("bootstopkey", "abcdefghijklmnopqrstuvwxyz\0");
} else {
setenv("dbg_present", "yes\0");
setenv("bootstopkey", "s\0");
setbits_8(&psc->command, PSC_RX_ENABLE);
}
}
void mvsmr_get_service_mode(void)
{
struct mpc5xxx_wu_gpio *wu_gpio =
(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
if (in_8(&wu_gpio->ival) & SERVICE_MODE)
setenv("servicemode", "no\0");
else
setenv("servicemode", "yes\0");
}
int mvsmr_get_mac(void)
{
unsigned char mac[6];
struct mpc5xxx_wu_gpio *wu_gpio =
(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
if (in_8(&wu_gpio->ival) & LAN_PRSNT) {
setenv("lan_present", "no\0");
return -1;
} else
setenv("lan_present", "yes\0");
i2c_read(0x50, 0, 1, mac, 6);
eth_setenv_enetaddr("ethaddr", mac);
return 0;
}
int checkboard(void)
{
mvsmr_init_gpio();
printf("Board: Matrix Vision mvSMR\n");
return 0;
}
void flash_preinit(void)
{
/*
* Now, when we are in RAM, enable flash write
* access for detection process.
* Note that CS_BOOT cannot be cleared when
* executing in flash.
*/
clrbits_be32((u32 *)MPC5XXX_BOOTCS_CFG, 0x1);
}
void flash_afterinit(ulong size)
{
out_be32((u32 *)MPC5XXX_BOOTCS_START,
START_REG(CONFIG_SYS_BOOTCS_START | size));
out_be32((u32 *)MPC5XXX_CS0_START,
START_REG(CONFIG_SYS_BOOTCS_START | size));
out_be32((u32 *)MPC5XXX_BOOTCS_STOP,
STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
out_be32((u32 *)MPC5XXX_CS0_STOP,
STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
}
struct pci_controller hose;
void pci_init_board(void)
{
mvsmr_get_dbg_present();
mvsmr_get_service_mode();
mvsmr_init_fpga();
mv_load_fpga();
pci_mpc5xxx_init(&hose);
}
int board_eth_init(bd_t *bis)
{
if (!mvsmr_get_mac())
return cpu_eth_init(bis);
return pci_eth_init(bis);
}

43
board/matrix_vision/mvsmr/mvsmr.h
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@ -1,43 +0,0 @@
#include <pci.h>
extern void pci_mpc5xxx_init(struct pci_controller *);
#define FPGA_DIN MPC5XXX_GPIO_SIMPLE_PSC3_0
#define FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_1
#define FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_2
#define FPGA_CONFIG MPC5XXX_GPIO_SIMPLE_PSC3_3
#define FPGA_STATUS MPC5XXX_GPIO_SINT_PSC3_4
#define S_FPGA_DIN MPC5XXX_GPIO_SINT_PSC3_5
#define S_FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_6
#define S_FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_7
#define S_FPGA_CONFIG MPC5XXX_GPIO_SINT_PSC3_8
#define S_FPGA_STATUS MPC5XXX_GPIO_WKUP_PSC3_9
#define MAN_RST MPC5XXX_GPIO_WKUP_PSC6_0
#define WD_TS MPC5XXX_GPIO_WKUP_PSC6_1
#define WD_WDI MPC5XXX_GPIO_SIMPLE_PSC6_2
#define COP_PRESENT MPC5XXX_GPIO_SIMPLE_PSC6_3
#define SERVICE_MODE MPC5XXX_GPIO_WKUP_6
#define FLASH_RBY MPC5XXX_GPIO_WKUP_7
#define UART_EN1 MPC5XXX_GPIO_WKUP_PSC1_4
#define LAN_PRSNT MPC5XXX_GPIO_WKUP_PSC2_4
#define SIMPLE_DDR (FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI |\
S_FPGA_CCLK)
#define SIMPLE_DVO (FPGA_CONFIG)
#define SIMPLE_ODE (FPGA_CONFIG)
#define SIMPLE_GPIOEN (FPGA_DIN | FPGA_CCLK | FPGA_DONE | FPGA_CONFIG |\
S_FPGA_CCLK | S_FPGA_DONE | WD_WDI | COP_PRESENT)
#define SINT_ODE 0x1
#define SINT_DDR 0x3
#define SINT_DVO 0x1
#define SINT_INTEN 0
#define SINT_ITYPE 0
#define SINT_GPIOEN (FPGA_STATUS | S_FPGA_DIN | S_FPGA_CONFIG)
#define WKUP_ODE (MAN_RST | S_FPGA_STATUS)
#define WKUP_DIR (MAN_RST | WD_TS | S_FPGA_STATUS)
#define WKUP_DO (MAN_RST | WD_TS | S_FPGA_STATUS)
#define WKUP_EN (MAN_RST | WD_TS | S_FPGA_STATUS | SERVICE_MODE |\
FLASH_RBY | UART_EN1 | LAN_PRSNT)

89
board/matrix_vision/mvsmr/u-boot.lds
View file

@ -1,89 +0,0 @@
/*
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* (C) Copyright 2010
* André Schwarz, Matrix Vision GmbH, as@matrix-vision.de
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the first two sectors (=8KB) of our S29GL flash chip */
arch/powerpc/cpu/mpc5xxx/start.o (.text*)
arch/powerpc/cpu/mpc5xxx/traps.o (.text*)
board/matrix_vision/common/built-in.o (.text*)
/* This is only needed to force failure if size of above code will ever */
/* increase and grow into reserved space. */
. = ALIGN(0x2000); /* location counter has to be 0x4000 now */
. += 0x4000; /* ->0x8000, i.e. move to env_offset */
. = env_offset; /* ld error as soon as above ALIGN misplaces lc */
common/env_embedded.o (.ppcenv)
*(.text*)
. = ALIGN(16);
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.bss*)
*(.sbss*)
. = ALIGN(4);
}
__bss_end = . ;
PROVIDE (end = .);
}

5
board/mpl/pati/pati.c
View file

@ -311,6 +311,11 @@ void user_led1(int led_on)
sysconf->sc_sgpiodt2=reg; /* Data register */
}
int board_early_init_f(void)
{
spi_init_f();
return 0;
}
/****************************************************************
* Last Stage Init

493
board/sandburst/common/flash.c
View file

@ -1,493 +0,0 @@
/*
* (C) Copyright 2002-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
* Add support for Am29F016D and dynamic switch setting.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* Ported from Ebony flash support
* Travis B. Sawyer
* Sandburst Corporation
*/
#include <common.h>
#include <asm/ppc4xx.h>
#include <asm/processor.h>
#undef DEBUG
#ifdef DEBUG
#define DEBUGF(x...) printf(x)
#else
#define DEBUGF(x...)
#endif /* DEBUG */
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = {
{0xfff80000} /* Boot Flash */
};
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
#define ADDR0 0x5555
#define ADDR1 0x2aaa
#define FLASH_WORD_SIZE unsigned char
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
unsigned long total_b = 0;
unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
unsigned short index = 0;
int i;
DEBUGF("\n");
DEBUGF("FLASH: Index: %d\n", index);
/* Init: no FLASHes known */
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
/* check whether the address is 0 */
if (flash_addr_table[index][i] == 0) {
continue;
}
/* call flash_get_size() to initialize sector address */
size_b[i] = flash_get_size(
(vu_long *)flash_addr_table[index][i], &flash_info[i]);
flash_info[i].size = size_b[i];
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
i, size_b[i], size_b[i]<<20);
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
}
total_b += flash_info[i].size;
}
return total_b;
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
int k;
int size;
int erased;
volatile unsigned long *flash;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD: printf ("AMD "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n");
break;
default: printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld KB in %d Sectors\n",
info->size >> 10, info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
/*
* Check if whole sector is erased
*/
if (i != (info->sector_count-1))
size = info->start[i+1] - info->start[i];
else
size = info->start[0] + info->size - info->start[i];
erased = 1;
flash = (volatile unsigned long *)info->start[i];
size = size >> 2; /* divide by 4 for longword access */
for (k=0; k<size; k++)
{
if (*flash++ != 0xffffffff)
{
erased = 0;
break;
}
}
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s%s",
info->start[i],
erased ? " E" : " ",
info->protect[i] ? "RO " : " "
);
}
printf ("\n");
return;
}
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
{
short i;
FLASH_WORD_SIZE value;
ulong base = (ulong)addr;
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr );
/* Write auto select command: read Manufacturer ID */
udelay(10000);
addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
udelay(1000);
addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
udelay(1000);
addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
udelay(1000);
value = addr2[0];
DEBUGF("FLASH MANUFACT: %x\n", value);
switch (value) {
case (FLASH_WORD_SIZE)AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
value = addr2[1]; /* device ID */
DEBUGF("\nFLASH DEVICEID: %x\n", value);
switch (value) {
case (FLASH_WORD_SIZE)AMD_ID_LV040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x00080000; /* => 512 kb */
break;
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
/* set up sector start address table */
if (info->flash_id == FLASH_AM040) {
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
} else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00030000;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
}
}
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
info->protect[i] = 0;
else
info->protect[i] = addr2[2] & 1;
}
/* reset to return to reading data */
addr2[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
addr2 = (FLASH_WORD_SIZE *)info->start[0];
*addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
}
return (info->size);
}
int wait_for_DQ7(flash_info_t *info, int sect)
{
ulong start, now, last;
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
start = get_timer (0);
last = start;
while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return -1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
return 0;
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
volatile FLASH_WORD_SIZE *addr2;
int flag, prot, sect;
int i;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if (info->flash_id == FLASH_UNKNOWN) {
printf ("Can't erase unknown flash type - aborted\n");
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
DEBUGF("Erasing sector %p\n", addr2);
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
for (i=0; i<50; i++)
udelay(1000); /* wait 1 ms */
} else {
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
}
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
* issue all erase commands within a specified
* timeout. This has been seen to fail, especially
* if printf()s are included (for debug)!!
*/
wait_for_DQ7(info, sect);
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/* reset to read mode */
addr = (FLASH_WORD_SIZE *)info->start[0];
addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
printf (" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
for (; i<4 && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i=0; i<4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
return (write_word(info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word (flash_info_t * info, ulong dest, ulong data)
{
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
ulong start;
int i;
/* Check if Flash is (sufficiently) erased */
if ((*((volatile FLASH_WORD_SIZE *) dest) &
(FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
return (2);
}
for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
int flag;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
dest2[i] = data2[i];
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts ();
/* data polling for D7 */
start = get_timer (0);
while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
(data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
return (1);
}
}
}
return (0);
}

349
board/sandburst/common/sb_common.c
View file

@ -1,349 +0,0 @@
/*
* Copyright (C) 2005 Sandburst Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <spd_sdram.h>
#include <i2c.h>
#include "sb_common.h"
DECLARE_GLOBAL_DATA_PTR;
long int fixed_sdram (void);
/*************************************************************************
* metrobox_get_master
*
* PRI_N - active low signal. If the GPIO pin is low we are the master
*
************************************************************************/
int sbcommon_get_master(void)
{
ppc440_gpio_regs_t *gpio_regs;
gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
if (gpio_regs->in & SBCOMMON_GPIO_PRI_N) {
return 0;
}
else {
return 1;
}
}
/*************************************************************************
* metrobox_secondary_present
*
* Figure out if secondary/slave board is present
*
************************************************************************/
int sbcommon_secondary_present(void)
{
ppc440_gpio_regs_t *gpio_regs;
gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
if (gpio_regs->in & SBCOMMON_GPIO_SEC_PRES)
return 0;
else
return 1;
}
/*************************************************************************
* sbcommon_get_serial_number
*
* Retrieve the board serial number via the mac address in eeprom
*
************************************************************************/
unsigned short sbcommon_get_serial_number(void)
{
unsigned char buff[0x100];
unsigned short sernum;
/* Get the board serial number from eeprom */
/* Initialize I2C */
i2c_set_bus_num(0);
/* Read 256 bytes in EEPROM */
i2c_read (0x50, 0, 1, buff, 0x100);
memcpy(&sernum, &buff[0xF4], 2);
sernum /= 32;
return (sernum);
}
/*************************************************************************
* sbcommon_fans
*
* Spin up fans 2 & 3 to get some air moving. OS will take care
* of the rest. This is mostly a precaution...
*
* Assumes i2c bus 1 is ready.
*
************************************************************************/
void sbcommon_fans(void)
{
/*
* Attempt to turn on 2 of the fans...
* Need to go through the bridge
*/
i2c_set_bus_num(1);
puts ("FANS: ");
/* select fan4 through the bridge */
i2c_reg_write(0x73, /* addr */
0x00, /* reg */
0x08); /* val = bus 4 */
/* Turn on FAN 4 */
i2c_reg_write(0x2e,
1,
0x80);
i2c_reg_write(0x2e,
0,
0x19);
/* Deselect bus 4 on the bridge */
i2c_reg_write(0x73,
0x00,
0x00);
/* select fan3 through the bridge */
i2c_reg_write(0x73, /* addr */
0x00, /* reg */
0x04); /* val = bus 3 */
/* Turn on FAN 3 */
i2c_reg_write(0x2e,
1,
0x80);
i2c_reg_write(0x2e,
0,
0x19);
/* Deselect bus 3 on the bridge */
i2c_reg_write(0x73,
0x00,
0x00);
/* select fan2 through the bridge */
i2c_reg_write(0x73, /* addr */
0x00, /* reg */
0x02); /* val = bus 4 */
/* Turn on FAN 2 */
i2c_reg_write(0x2e,
1,
0x80);
i2c_reg_write(0x2e,
0,
0x19);
/* Deselect bus 2 on the bridge */
i2c_reg_write(0x73,
0x00,
0x00);
/* select fan1 through the bridge */
i2c_reg_write(0x73, /* addr */
0x00, /* reg */
0x01); /* val = bus 0 */
/* Turn on FAN 1 */
i2c_reg_write(0x2e,
1,
0x80);
i2c_reg_write(0x2e,
0,
0x19);
/* Deselect bus 1 on the bridge */
i2c_reg_write(0x73,
0x00,
0x00);
puts ("on\n");
i2c_set_bus_num(0);
return;
}
/*************************************************************************
* initdram
*
* Initialize sdram
*
************************************************************************/
phys_size_t initdram (int board_type)
{
long dram_size = 0;
#if defined(CONFIG_SPD_EEPROM)
dram_size = spd_sdram ();
#else
dram_size = fixed_sdram ();
#endif
return dram_size;
}
/*************************************************************************
* testdram
*
*
************************************************************************/
#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
uint *p;
printf("Testing SDRAM: ");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("OK\n");
return 0;
}
#endif
#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
*
* Assumes: 128 MB, non-ECC, non-registered
* PLB @ 133 MHz
*
************************************************************************/
long int fixed_sdram (void)
{
uint reg;
/*--------------------------------------------------------------------
* Setup some default
*------------------------------------------------------------------*/
mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*--------------------------------------------------------------------
* Setup for board-specific specific mem
*------------------------------------------------------------------*/
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
/* RA=10 RD=3 */
mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
udelay (400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
for (;;) {
mfsdram (SDRAM0_MCSTS, reg);
if (reg & 0x80000000)
break;
}
return (128 * 1024 * 1024); /* 128 MB */
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
/*************************************************************************
* board_get_enetaddr
*
* Get the ethernet MAC address for the management ethernet from the
* strap EEPROM. Note that is the BASE address for the range of
* external ethernet MACs on the board. The base + 31 is the actual
* mgmt mac address.
*
************************************************************************/
void board_get_enetaddr(int macaddr_idx, uchar *enet)
{
int i;
unsigned short tmp;
unsigned char buff[0x100], *cp;
if (0 == macaddr_idx) {
/* Initialize I2C */
i2c_set_bus_num(0);
/* Read 256 bytes in EEPROM */
i2c_read (0x50, 0, 1, buff, 0x100);
cp = &buff[0xF0];
for (i = 0; i < 6; i++,cp++)
enet[i] = *cp;
memcpy(&tmp, &enet[4], 2);
tmp += 31;
memcpy(&enet[4], &tmp, 2);
} else {
enet[0] = 0x02;
enet[1] = 0x00;
enet[2] = 0x00;
enet[3] = 0x00;
enet[4] = 0x00;
if (1 == sbcommon_get_master() ) {
/* Master/Primary card */
enet[5] = 0x01;
} else {
/* Slave/Secondary card */
enet [5] = 0x02;
}
}
return;
}
#ifdef CONFIG_POST
/*
* Returns 1 if keys pressed to start the power-on long-running tests
* Called from board_init_f().
*/
int post_hotkeys_pressed(void)
{
return (ctrlc());
}
#endif

60
board/sandburst/common/sb_common.h
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@ -1,60 +0,0 @@
#ifndef __SBCOMMON_H__
#define __SBCOMMON_H__
/*
* Copyright (C) 2005 Sandburst Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <spd_sdram.h>
#include <i2c.h>
/*
* GPIO Settings
*/
/* Chassis settings */
#define SBCOMMON_GPIO_PRI_N 0x00001000 /* 0 = Chassis Master, 1 = Slave */
#define SBCOMMON_GPIO_SEC_PRES 0x00000800 /* 1 = Other board present */
/* Debug LEDs */
#define SBCOMMON_GPIO_DBGLED_0 0x00000400
#define SBCOMMON_GPIO_DBGLED_1 0x00000200
#define SBCOMMON_GPIO_DBGLED_2 0x00100000
#define SBCOMMON_GPIO_DBGLED_3 0x00000100
#define SBCOMMON_GPIO_DBGLEDS (SBCOMMON_GPIO_DBGLED_0 | \
SBCOMMON_GPIO_DBGLED_1 | \
SBCOMMON_GPIO_DBGLED_2 | \
SBCOMMON_GPIO_DBGLED_3)
#define SBCOMMON_GPIO_SYS_FAULT 0x00000080
#define SBCOMMON_GPIO_SYS_OTEMP 0x00000040
#define SBCOMMON_GPIO_SYS_STATUS 0x00000020
#define SBCOMMON_GPIO_SYS_LEDS (SBCOMMON_GPIO_SYS_STATUS)
#define SBCOMMON_GPIO_LEDS (SBCOMMON_GPIO_DBGLED_0 | \
SBCOMMON_GPIO_DBGLED_1 | \
SBCOMMON_GPIO_DBGLED_2 | \
SBCOMMON_GPIO_DBGLED_3 | \
SBCOMMON_GPIO_SYS_STATUS)
typedef struct ppc440_gpio_regs {
volatile unsigned long out;
volatile unsigned long tri_state;
volatile unsigned long dummy[4];
volatile unsigned long open_drain;
volatile unsigned long in;
} __attribute__((packed)) ppc440_gpio_regs_t;
int sbcommon_get_master(void);
int sbcommon_secondary_present(void);
unsigned short sbcommon_get_serial_number(void);
void sbcommon_fans(void);
void board_get_enetaddr(int macaddr_idx, uchar *enet);
#endif /* __SBCOMMON_H__ */

12
board/sandburst/karef/Kconfig
View file

@ -1,12 +0,0 @@
if TARGET_KAREF
config SYS_BOARD
default "karef"
config SYS_VENDOR
default "sandburst"
config SYS_CONFIG_NAME
default "KAREF"
endif

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