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https://github.com/AsahiLinux/u-boot
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arm: marvell: Extract kirkwood gpio functions into new common file gpio.c
This makes is possible to use those gpio functions from other MVEBU SoC's as well. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Luka Perkov <luka@openwrt.org> Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
This commit is contained in:
parent
4aceea2088
commit
d5c5132f87
24 changed files with 93 additions and 79 deletions
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@ -139,23 +139,6 @@ int kw_config_adr_windows(void)
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return 0;
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}
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/*
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* kw_config_gpio - GPIO configuration
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*/
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void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe)
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{
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struct kwgpio_registers *gpio0reg =
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(struct kwgpio_registers *)KW_GPIO0_BASE;
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struct kwgpio_registers *gpio1reg =
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(struct kwgpio_registers *)KW_GPIO1_BASE;
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/* Init GPIOS to default values as per board requirement */
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writel(gpp0_oe_val, &gpio0reg->dout);
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writel(gpp1_oe_val, &gpio1reg->dout);
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writel(gpp0_oe, &gpio0reg->oe);
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writel(gpp1_oe, &gpio1reg->oe);
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}
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/*
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* kw_config_mpp - Multi-Purpose Pins Functionality configuration
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*
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@ -144,7 +144,7 @@ unsigned int kw_sdram_bar(enum memory_bank bank);
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unsigned int kw_sdram_bs(enum memory_bank bank);
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void kw_sdram_size_adjust(enum memory_bank bank);
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int kw_config_adr_windows(void);
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void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
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void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
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unsigned int gpp0_oe, unsigned int gpp1_oe);
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int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,
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unsigned int mpp16_23, unsigned int mpp24_31,
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@ -21,14 +21,14 @@
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#define GPIO_MAX 50
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#define GPIO_OFF(pin) (((pin) >> 5) ? 0x0040 : 0x0000)
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#define GPIO_OUT(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x00)
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#define GPIO_IO_CONF(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x04)
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#define GPIO_BLINK_EN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x08)
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#define GPIO_IN_POL(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x0c)
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#define GPIO_DATA_IN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x10)
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#define GPIO_EDGE_CAUSE(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x14)
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#define GPIO_EDGE_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x18)
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#define GPIO_LEVEL_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x1c)
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#define GPIO_OUT(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x00)
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#define GPIO_IO_CONF(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x04)
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#define GPIO_BLINK_EN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x08)
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#define GPIO_IN_POL(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x0c)
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#define GPIO_DATA_IN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x10)
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#define GPIO_EDGE_CAUSE(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x14)
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#define GPIO_EDGE_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x18)
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#define GPIO_LEVEL_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x1c)
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/*
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* Kirkwood-specific GPIO API
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@ -26,8 +26,8 @@
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#define KW_UART0_BASE (KW_REGISTER(0x12000))
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#define KW_UART1_BASE (KW_REGISTER(0x12100))
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#define KW_MPP_BASE (KW_REGISTER(0x10000))
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#define KW_GPIO0_BASE (KW_REGISTER(0x10100))
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#define KW_GPIO1_BASE (KW_REGISTER(0x10140))
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#define MVEBU_GPIO0_BASE (KW_REGISTER(0x10100))
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#define MVEBU_GPIO1_BASE (KW_REGISTER(0x10140))
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#define KW_RTC_BASE (KW_REGISTER(0x10300))
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#define KW_NANDF_BASE (KW_REGISTER(0x10418))
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#define KW_SPI_BASE (KW_REGISTER(0x10600))
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@ -7,5 +7,6 @@
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#
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obj-y = dram.o
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obj-y += gpio.o
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obj-$(CONFIG_ARMADA_XP) += mbus.o
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obj-y += timer.o
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30
arch/arm/mvebu-common/gpio.c
Normal file
30
arch/arm/mvebu-common/gpio.c
Normal file
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@ -0,0 +1,30 @@
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/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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/*
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* mvebu_config_gpio - GPIO configuration
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*/
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void mvebu_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val,
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u32 gpp0_oe, u32 gpp1_oe)
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{
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struct kwgpio_registers *gpio0reg =
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(struct kwgpio_registers *)MVEBU_GPIO0_BASE;
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struct kwgpio_registers *gpio1reg =
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(struct kwgpio_registers *)MVEBU_GPIO1_BASE;
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/* Init GPIOS to default values as per board requirement */
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writel(gpp0_oe_val, &gpio0reg->dout);
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writel(gpp1_oe_val, &gpio1reg->dout);
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writel(gpp0_oe, &gpio0reg->oe);
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writel(gpp1_oe, &gpio1reg->oe);
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}
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@ -26,8 +26,8 @@ DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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/* GPIO configuration */
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kw_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH,
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NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
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mvebu_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH,
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NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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static const u32 kwmpp_config[] = {
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@ -24,8 +24,8 @@ DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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/* Gpio configuration */
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kw_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH,
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NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
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mvebu_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH,
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NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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static const u32 kwmpp_config[] = {
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@ -97,8 +97,8 @@ struct mv88e61xx_config swcfg = {
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int board_early_init_f(void)
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{
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/* Gpio configuration */
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kw_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH,
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WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH);
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mvebu_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH,
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WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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kirkwood_mpp_conf(kwmpp_config, NULL);
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@ -25,9 +25,9 @@ int board_early_init_f(void)
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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kw_config_gpio(DREAMPLUG_OE_VAL_LOW,
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DREAMPLUG_OE_VAL_HIGH,
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DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
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mvebu_config_gpio(DREAMPLUG_OE_VAL_LOW,
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DREAMPLUG_OE_VAL_HIGH,
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DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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static const u32 kwmpp_config[] = {
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@ -22,9 +22,9 @@ int board_early_init_f(void)
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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kw_config_gpio(GURUPLUG_OE_VAL_LOW,
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GURUPLUG_OE_VAL_HIGH,
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GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
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mvebu_config_gpio(GURUPLUG_OE_VAL_LOW,
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GURUPLUG_OE_VAL_HIGH,
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GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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static const u32 kwmpp_config[] = {
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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kw_config_gpio(MV88F6281GTW_GE_OE_VAL_LOW,
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MV88F6281GTW_GE_OE_VAL_HIGH,
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MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH);
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mvebu_config_gpio(MV88F6281GTW_GE_OE_VAL_LOW,
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MV88F6281GTW_GE_OE_VAL_HIGH,
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MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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static const u32 kwmpp_config[] = {
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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kw_config_gpio(OPENRD_OE_VAL_LOW,
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OPENRD_OE_VAL_HIGH,
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OPENRD_OE_LOW, OPENRD_OE_HIGH);
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mvebu_config_gpio(OPENRD_OE_VAL_LOW,
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OPENRD_OE_VAL_HIGH,
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OPENRD_OE_LOW, OPENRD_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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static const u32 kwmpp_config[] = {
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@ -23,9 +23,9 @@ int board_early_init_f(void)
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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kw_config_gpio(RD6281A_OE_VAL_LOW,
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RD6281A_OE_VAL_HIGH,
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RD6281A_OE_LOW, RD6281A_OE_HIGH);
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mvebu_config_gpio(RD6281A_OE_VAL_LOW,
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RD6281A_OE_VAL_HIGH,
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RD6281A_OE_LOW, RD6281A_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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static const u32 kwmpp_config[] = {
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@ -22,9 +22,9 @@ int board_early_init_f(void)
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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kw_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
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SHEEVAPLUG_OE_VAL_HIGH,
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SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
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mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
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SHEEVAPLUG_OE_VAL_HIGH,
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SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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static const u32 kwmpp_config[] = {
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@ -26,9 +26,9 @@ int board_early_init_f(void)
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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kw_config_gpio(DOCKSTAR_OE_VAL_LOW,
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DOCKSTAR_OE_VAL_HIGH,
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DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH);
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mvebu_config_gpio(DOCKSTAR_OE_VAL_LOW,
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DOCKSTAR_OE_VAL_HIGH,
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DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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static const u32 kwmpp_config[] = {
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@ -143,7 +143,7 @@ void reset_phy(void)
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static void set_leds(u32 leds, u32 blinking)
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{
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struct kwgpio_registers *r = (struct kwgpio_registers *)KW_GPIO1_BASE;
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struct kwgpio_registers *r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
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u32 oe = readl(&r->oe) | BOTH_LEDS;
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writel(oe & ~leds, &r->oe); /* active low */
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u32 bl = readl(&r->blink_en) & ~BOTH_LEDS;
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@ -83,9 +83,9 @@ int board_early_init_f(void)
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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kw_config_gpio(GOFLEXHOME_OE_VAL_LOW,
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GOFLEXHOME_OE_VAL_HIGH,
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GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH);
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mvebu_config_gpio(GOFLEXHOME_OE_VAL_LOW,
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GOFLEXHOME_OE_VAL_HIGH,
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GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH);
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kirkwood_mpp_conf(kwmpp_config, NULL);
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return 0;
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}
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@ -149,7 +149,7 @@ static void set_leds(u32 leds, u32 blinking)
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u32 oe;
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u32 bl;
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r = (struct kwgpio_registers *)KW_GPIO1_BASE;
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r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
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oe = readl(&r->oe) | BOTH_LEDS;
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writel(oe & ~leds, &r->oe); /* active low */
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bl = readl(&r->blink_en) & ~BOTH_LEDS;
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@ -52,9 +52,9 @@ int board_early_init_f(void)
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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kw_config_gpio(LSXL_OE_VAL_LOW,
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LSXL_OE_VAL_HIGH,
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LSXL_OE_LOW, LSXL_OE_HIGH);
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mvebu_config_gpio(LSXL_OE_VAL_LOW,
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LSXL_OE_VAL_HIGH,
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LSXL_OE_LOW, LSXL_OE_HIGH);
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/*
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* Multi-Purpose Pins Functionality configuration
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@ -26,9 +26,9 @@ int board_early_init_f(void)
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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kw_config_gpio(POGO_E02_OE_VAL_LOW,
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POGO_E02_OE_VAL_HIGH,
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POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
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mvebu_config_gpio(POGO_E02_OE_VAL_LOW,
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POGO_E02_OE_VAL_HIGH,
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POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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static const u32 kwmpp_config[] = {
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@ -24,8 +24,8 @@ DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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/* Gpio configuration */
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kw_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH,
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DNS325_OE_LOW, DNS325_OE_HIGH);
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mvebu_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH,
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DNS325_OE_LOW, DNS325_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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static const u32 kwmpp_config[] = {
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@ -22,9 +22,9 @@ int board_early_init_f(void)
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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kw_config_gpio(ICONNECT_OE_VAL_LOW,
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ICONNECT_OE_VAL_HIGH,
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ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
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mvebu_config_gpio(ICONNECT_OE_VAL_LOW,
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ICONNECT_OE_VAL_HIGH,
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ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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static const u32 kwmpp_config[] = {
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@ -26,9 +26,9 @@ int board_early_init_f(void)
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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kw_config_gpio(TK71_OE_VAL_LOW,
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TK71_OE_VAL_HIGH,
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TK71_OE_LOW, TK71_OE_HIGH);
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mvebu_config_gpio(TK71_OE_VAL_LOW,
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TK71_OE_VAL_HIGH,
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TK71_OE_LOW, TK71_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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static const u32 kwmpp_config[] = {
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@ -222,8 +222,8 @@ int board_early_init_f(void)
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u32 tmp;
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/* set the 2 bitbang i2c pins as output gpios */
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tmp = readl(KW_GPIO0_BASE + 4);
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writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4);
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tmp = readl(MVEBU_GPIO0_BASE + 4);
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writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4);
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#endif
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/* adjust SDRAM size for bank 0 */
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kw_sdram_size_adjust(0);
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@ -24,9 +24,9 @@ int board_early_init_f(void)
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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kw_config_gpio(IB62x0_OE_VAL_LOW,
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IB62x0_OE_VAL_HIGH,
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||||
IB62x0_OE_LOW, IB62x0_OE_HIGH);
|
||||
mvebu_config_gpio(IB62x0_OE_VAL_LOW,
|
||||
IB62x0_OE_VAL_HIGH,
|
||||
IB62x0_OE_LOW, IB62x0_OE_HIGH);
|
||||
|
||||
/* Set SATA activity LEDs to default off */
|
||||
writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG);
|
||||
|
|
Loading…
Reference in a new issue