arm: marvell: Extract kirkwood gpio functions into new common file gpio.c

This makes is possible to use those gpio functions from other MVEBU SoC's as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
This commit is contained in:
Stefan Roese 2014-10-22 12:13:11 +02:00 committed by Tom Rini
parent 4aceea2088
commit d5c5132f87
24 changed files with 93 additions and 79 deletions

View file

@ -139,23 +139,6 @@ int kw_config_adr_windows(void)
return 0;
}
/*
* kw_config_gpio - GPIO configuration
*/
void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe)
{
struct kwgpio_registers *gpio0reg =
(struct kwgpio_registers *)KW_GPIO0_BASE;
struct kwgpio_registers *gpio1reg =
(struct kwgpio_registers *)KW_GPIO1_BASE;
/* Init GPIOS to default values as per board requirement */
writel(gpp0_oe_val, &gpio0reg->dout);
writel(gpp1_oe_val, &gpio1reg->dout);
writel(gpp0_oe, &gpio0reg->oe);
writel(gpp1_oe, &gpio1reg->oe);
}
/*
* kw_config_mpp - Multi-Purpose Pins Functionality configuration
*

View file

@ -144,7 +144,7 @@ unsigned int kw_sdram_bar(enum memory_bank bank);
unsigned int kw_sdram_bs(enum memory_bank bank);
void kw_sdram_size_adjust(enum memory_bank bank);
int kw_config_adr_windows(void);
void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
unsigned int gpp0_oe, unsigned int gpp1_oe);
int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,
unsigned int mpp16_23, unsigned int mpp24_31,

View file

@ -21,14 +21,14 @@
#define GPIO_MAX 50
#define GPIO_OFF(pin) (((pin) >> 5) ? 0x0040 : 0x0000)
#define GPIO_OUT(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x00)
#define GPIO_IO_CONF(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x04)
#define GPIO_BLINK_EN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x08)
#define GPIO_IN_POL(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x0c)
#define GPIO_DATA_IN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x10)
#define GPIO_EDGE_CAUSE(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x14)
#define GPIO_EDGE_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x18)
#define GPIO_LEVEL_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x1c)
#define GPIO_OUT(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x00)
#define GPIO_IO_CONF(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x04)
#define GPIO_BLINK_EN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x08)
#define GPIO_IN_POL(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x0c)
#define GPIO_DATA_IN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x10)
#define GPIO_EDGE_CAUSE(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x14)
#define GPIO_EDGE_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x18)
#define GPIO_LEVEL_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x1c)
/*
* Kirkwood-specific GPIO API

View file

@ -26,8 +26,8 @@
#define KW_UART0_BASE (KW_REGISTER(0x12000))
#define KW_UART1_BASE (KW_REGISTER(0x12100))
#define KW_MPP_BASE (KW_REGISTER(0x10000))
#define KW_GPIO0_BASE (KW_REGISTER(0x10100))
#define KW_GPIO1_BASE (KW_REGISTER(0x10140))
#define MVEBU_GPIO0_BASE (KW_REGISTER(0x10100))
#define MVEBU_GPIO1_BASE (KW_REGISTER(0x10140))
#define KW_RTC_BASE (KW_REGISTER(0x10300))
#define KW_NANDF_BASE (KW_REGISTER(0x10418))
#define KW_SPI_BASE (KW_REGISTER(0x10600))

View file

@ -7,5 +7,6 @@
#
obj-y = dram.o
obj-y += gpio.o
obj-$(CONFIG_ARMADA_XP) += mbus.o
obj-y += timer.o

View file

@ -0,0 +1,30 @@
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
/*
* mvebu_config_gpio - GPIO configuration
*/
void mvebu_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val,
u32 gpp0_oe, u32 gpp1_oe)
{
struct kwgpio_registers *gpio0reg =
(struct kwgpio_registers *)MVEBU_GPIO0_BASE;
struct kwgpio_registers *gpio1reg =
(struct kwgpio_registers *)MVEBU_GPIO1_BASE;
/* Init GPIOS to default values as per board requirement */
writel(gpp0_oe_val, &gpio0reg->dout);
writel(gpp1_oe_val, &gpio1reg->dout);
writel(gpp0_oe, &gpio0reg->oe);
writel(gpp1_oe, &gpio1reg->oe);
}

View file

@ -26,8 +26,8 @@ DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
/* GPIO configuration */
kw_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH,
NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
mvebu_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH,
NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
static const u32 kwmpp_config[] = {

View file

@ -24,8 +24,8 @@ DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
/* Gpio configuration */
kw_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH,
NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
mvebu_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH,
NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
static const u32 kwmpp_config[] = {

View file

@ -97,8 +97,8 @@ struct mv88e61xx_config swcfg = {
int board_early_init_f(void)
{
/* Gpio configuration */
kw_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH,
WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH);
mvebu_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH,
WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
kirkwood_mpp_conf(kwmpp_config, NULL);

View file

@ -25,9 +25,9 @@ int board_early_init_f(void)
* There are maximum 64 gpios controlled through 2 sets of registers
* the below configuration configures mainly initial LED status
*/
kw_config_gpio(DREAMPLUG_OE_VAL_LOW,
DREAMPLUG_OE_VAL_HIGH,
DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
mvebu_config_gpio(DREAMPLUG_OE_VAL_LOW,
DREAMPLUG_OE_VAL_HIGH,
DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
static const u32 kwmpp_config[] = {

View file

@ -22,9 +22,9 @@ int board_early_init_f(void)
* There are maximum 64 gpios controlled through 2 sets of registers
* the below configuration configures mainly initial LED status
*/
kw_config_gpio(GURUPLUG_OE_VAL_LOW,
GURUPLUG_OE_VAL_HIGH,
GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
mvebu_config_gpio(GURUPLUG_OE_VAL_LOW,
GURUPLUG_OE_VAL_HIGH,
GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
static const u32 kwmpp_config[] = {

View file

@ -24,9 +24,9 @@ int board_early_init_f(void)
* There are maximum 64 gpios controlled through 2 sets of registers
* the below configuration configures mainly initial LED status
*/
kw_config_gpio(MV88F6281GTW_GE_OE_VAL_LOW,
MV88F6281GTW_GE_OE_VAL_HIGH,
MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH);
mvebu_config_gpio(MV88F6281GTW_GE_OE_VAL_LOW,
MV88F6281GTW_GE_OE_VAL_HIGH,
MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
static const u32 kwmpp_config[] = {

View file

@ -27,9 +27,9 @@ int board_early_init_f(void)
* There are maximum 64 gpios controlled through 2 sets of registers
* the below configuration configures mainly initial LED status
*/
kw_config_gpio(OPENRD_OE_VAL_LOW,
OPENRD_OE_VAL_HIGH,
OPENRD_OE_LOW, OPENRD_OE_HIGH);
mvebu_config_gpio(OPENRD_OE_VAL_LOW,
OPENRD_OE_VAL_HIGH,
OPENRD_OE_LOW, OPENRD_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
static const u32 kwmpp_config[] = {

View file

@ -23,9 +23,9 @@ int board_early_init_f(void)
* There are maximum 64 gpios controlled through 2 sets of registers
* the below configuration configures mainly initial LED status
*/
kw_config_gpio(RD6281A_OE_VAL_LOW,
RD6281A_OE_VAL_HIGH,
RD6281A_OE_LOW, RD6281A_OE_HIGH);
mvebu_config_gpio(RD6281A_OE_VAL_LOW,
RD6281A_OE_VAL_HIGH,
RD6281A_OE_LOW, RD6281A_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
static const u32 kwmpp_config[] = {

View file

@ -22,9 +22,9 @@ int board_early_init_f(void)
* There are maximum 64 gpios controlled through 2 sets of registers
* the below configuration configures mainly initial LED status
*/
kw_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
SHEEVAPLUG_OE_VAL_HIGH,
SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
SHEEVAPLUG_OE_VAL_HIGH,
SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
static const u32 kwmpp_config[] = {

View file

@ -26,9 +26,9 @@ int board_early_init_f(void)
* There are maximum 64 gpios controlled through 2 sets of registers
* the below configuration configures mainly initial LED status
*/
kw_config_gpio(DOCKSTAR_OE_VAL_LOW,
DOCKSTAR_OE_VAL_HIGH,
DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH);
mvebu_config_gpio(DOCKSTAR_OE_VAL_LOW,
DOCKSTAR_OE_VAL_HIGH,
DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
static const u32 kwmpp_config[] = {
@ -143,7 +143,7 @@ void reset_phy(void)
static void set_leds(u32 leds, u32 blinking)
{
struct kwgpio_registers *r = (struct kwgpio_registers *)KW_GPIO1_BASE;
struct kwgpio_registers *r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
u32 oe = readl(&r->oe) | BOTH_LEDS;
writel(oe & ~leds, &r->oe); /* active low */
u32 bl = readl(&r->blink_en) & ~BOTH_LEDS;

View file

@ -83,9 +83,9 @@ int board_early_init_f(void)
* There are maximum 64 gpios controlled through 2 sets of registers
* the below configuration configures mainly initial LED status
*/
kw_config_gpio(GOFLEXHOME_OE_VAL_LOW,
GOFLEXHOME_OE_VAL_HIGH,
GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH);
mvebu_config_gpio(GOFLEXHOME_OE_VAL_LOW,
GOFLEXHOME_OE_VAL_HIGH,
GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH);
kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}
@ -149,7 +149,7 @@ static void set_leds(u32 leds, u32 blinking)
u32 oe;
u32 bl;
r = (struct kwgpio_registers *)KW_GPIO1_BASE;
r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
oe = readl(&r->oe) | BOTH_LEDS;
writel(oe & ~leds, &r->oe); /* active low */
bl = readl(&r->blink_en) & ~BOTH_LEDS;

View file

@ -52,9 +52,9 @@ int board_early_init_f(void)
* There are maximum 64 gpios controlled through 2 sets of registers
* the below configuration configures mainly initial LED status
*/
kw_config_gpio(LSXL_OE_VAL_LOW,
LSXL_OE_VAL_HIGH,
LSXL_OE_LOW, LSXL_OE_HIGH);
mvebu_config_gpio(LSXL_OE_VAL_LOW,
LSXL_OE_VAL_HIGH,
LSXL_OE_LOW, LSXL_OE_HIGH);
/*
* Multi-Purpose Pins Functionality configuration

View file

@ -26,9 +26,9 @@ int board_early_init_f(void)
* There are maximum 64 gpios controlled through 2 sets of registers
* the below configuration configures mainly initial LED status
*/
kw_config_gpio(POGO_E02_OE_VAL_LOW,
POGO_E02_OE_VAL_HIGH,
POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
mvebu_config_gpio(POGO_E02_OE_VAL_LOW,
POGO_E02_OE_VAL_HIGH,
POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
static const u32 kwmpp_config[] = {

View file

@ -24,8 +24,8 @@ DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
/* Gpio configuration */
kw_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH,
DNS325_OE_LOW, DNS325_OE_HIGH);
mvebu_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH,
DNS325_OE_LOW, DNS325_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
static const u32 kwmpp_config[] = {

View file

@ -22,9 +22,9 @@ int board_early_init_f(void)
* There are maximum 64 gpios controlled through 2 sets of registers
* the below configuration configures mainly initial LED status
*/
kw_config_gpio(ICONNECT_OE_VAL_LOW,
ICONNECT_OE_VAL_HIGH,
ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
mvebu_config_gpio(ICONNECT_OE_VAL_LOW,
ICONNECT_OE_VAL_HIGH,
ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
static const u32 kwmpp_config[] = {

View file

@ -26,9 +26,9 @@ int board_early_init_f(void)
* There are maximum 64 gpios controlled through 2 sets of registers
* the below configuration configures mainly initial LED status
*/
kw_config_gpio(TK71_OE_VAL_LOW,
TK71_OE_VAL_HIGH,
TK71_OE_LOW, TK71_OE_HIGH);
mvebu_config_gpio(TK71_OE_VAL_LOW,
TK71_OE_VAL_HIGH,
TK71_OE_LOW, TK71_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
static const u32 kwmpp_config[] = {

View file

@ -222,8 +222,8 @@ int board_early_init_f(void)
u32 tmp;
/* set the 2 bitbang i2c pins as output gpios */
tmp = readl(KW_GPIO0_BASE + 4);
writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4);
tmp = readl(MVEBU_GPIO0_BASE + 4);
writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4);
#endif
/* adjust SDRAM size for bank 0 */
kw_sdram_size_adjust(0);

View file

@ -24,9 +24,9 @@ int board_early_init_f(void)
* There are maximum 64 gpios controlled through 2 sets of registers
* the below configuration configures mainly initial LED status
*/
kw_config_gpio(IB62x0_OE_VAL_LOW,
IB62x0_OE_VAL_HIGH,
IB62x0_OE_LOW, IB62x0_OE_HIGH);
mvebu_config_gpio(IB62x0_OE_VAL_LOW,
IB62x0_OE_VAL_HIGH,
IB62x0_OE_LOW, IB62x0_OE_HIGH);
/* Set SATA activity LEDs to default off */
writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG);