Commit graph

17066 commits

Author SHA1 Message Date
Heiko Stuebner
03f98b75e4 rockchip: misc: read the correct number of bytes from the efuse
Originally the cpuid var the value gets read into was defined as
    u8 cpuid[RK3399_CPUID_LEN];
hence the sizeof(cpuid) would return the correct the correct number
of array elements.

With the move to a separate function cpuid becomes a pointer and
sizeof(cpuid) hence returns the pointer size - 8 in the arm64 case.

We do have the actual id length available as function param so use
it for actual amount of bytes to read.

Fixes: 0482538499 ("rockchip: rk3399: derive ethaddr from cpuid")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2019-09-28 22:26:32 +08:00
Michael Trimarchi
f810ea6acb rockchip: rk3288-tinker: Attach missing peripherals at SPL
Tinker board needs to mux all the sdmmc gpio and
activate the regulator connected to bank 7. Remove
all the bank that are not in use and mark them as dm,spl
so-that it would initialize at SPL.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2019-09-19 09:35:31 +08:00
Jagan Teki
891d4d1fca rockchip: spi-boot-order: Trival fix to newline missing
newline \n was missed in fdt_path_offset, error loop.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2019-09-19 09:35:31 +08:00
Jagan Teki
bacad567ac rockchip: rk3288: vyasa: Drop ROCKCHIP_BROM_HELPER selection
ROCKCHIP_BROM_HELPER is selected as if TPL/SPL ROCKCHIP_BACK_TO_BROM
has been defined, so drop the explicit enablement for vyasa board.

This change is supposed to missed during config move to
other locations, and missed to drop the same.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2019-09-19 09:35:31 +08:00
Tom Rini
a9fa70b7b7 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Add emmc hs200 support
- Few bug fixes related to serdes, I2C, ethernet, etc
2019-09-16 13:13:45 -04:00
Tom Rini
a314ec1bfd Merge branch 'master' of git://git.denx.de/u-boot-sh 2019-09-15 21:14:26 -04:00
Marek Vasut
a12c90a28d sh: r2dplus: Fix missing PCI range
Add missing PCI range for translating DRAM to bus addresses.
This fixes e.g. PCI NIC interface and allows network to work
in QEMU.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-09-14 21:28:55 +02:00
Marek Vasut
fa7cff834f sh: Fix SH4 build with GCC versions without -m4-nofpu
Pass -m4 instead of -m4-nofpu to GCC versions which do not support
the -m4-nofpu option.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-09-14 21:28:55 +02:00
Marek Vasut
e914109de4 sh: Fix incorrect linking with new binutils
Since binutils 2.30 , the resulting U-Boot binary was incorrectly linked
against address 0 instead of text base, fix it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-09-14 21:28:54 +02:00
Faiz Abbas
16f14b930d ARM: dts: dra74x: Fix iodelay configuration for mmc3
According to the latest am572x[1] and dra74x[2] data manuals, mmc3
default, hs, sdr12 and sdr25 modes use iodelay values given in
MMC3_MANUAL1. Set the MODE_SELECT bit for these so that manual mode is
selected and correct iodelay values are configured.

[1] http://www.ti.com/lit/ds/symlink/am5728.pdf
[2] http://www.ti.com/lit/ds/symlink/dra746.pdf

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-09-13 11:56:30 -04:00
Lokesh Vutla
78e512129b arm: k3: Use get_ti_sci_handle() where ever possible
Instead of calling uclass apis everywhere, use get_ti_sci_handle()
when ever ti_sci is needed.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-09-13 11:56:30 -04:00
Lokesh Vutla
e8d3a18639 arm: k3: Fix getting ti_sci handle
API get_ti_sci_handle() is relying on the device-tree node name
to be "dmsc" for probing the ti_sci device. But with the introduction
of debug messages for dmsc, the node name changed to dmsc@44083000.
Because of this ti_sci is never probed cause a boot failure. Instead
of relying on device-tree node name, use the first available firmware
node for probing ti_sci.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-09-13 11:56:30 -04:00
Adam Ford
ca62f2ba15 ARM: omapl138_lcdk: Enable DM_GPIO and DM and GPIO Commands
The da8xx GPIO driver is available with DM_GPIO support.  This
patch enables the CMD_GPIO, CMD_DM, and DM_GPIO and DA8XX_GPIO.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-09-13 11:56:08 -04:00
Suniel Mahesh
d60eb8e49e arm: am437x: cm-t43: Add device tree, enable OF_CONTROL
Add device tree from Linux for driver model conversion
and enable OF_CONTROL. This will remove the following compile
warning:
==================================================
Device Tree Source is not correctly specified.
Please define 'CONFIG_DEFAULT_DEVICE_TREE'
or build with 'DEVICE_TREE=<device_tree>' argument
===================================================
Target was compile tested, build was clean.

Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
2019-09-13 11:56:08 -04:00
Hou Zhiqiang
116f75c7b3 armv8: ls1028a: Updated serdes configuration for 0x13BB
In SerDes protocol 0x13BB, lane C was erroneously assigned
to PCIE1, this is now updated to PCIE2

Fixes: 36f50b7523 ("armv8: ls1028a: Add other serdes
		     protocal support")

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 16:15:42 +05:30
Hou Zhiqiang
c9ba88bafc armv8: fsl-layerscape: Fix typo in Layerscape PCIe config entry
The correct config entry is CONFIG_PCIE_LAYERSCAPE and this
typo results in skipping the fixup of Linux PCIe DT nodes.

Also enable the fixup when Layerscape Gen4 controller driver
is enabled.

Fixes: 4da0e52c9d (armv8: fsl-layerscape: fix config dependency
		     for layerscape pci code)

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 16:15:42 +05:30
Chuanhua Han
2f2a19757b armv8: fsl-layerscape: Update I2C clock divider
By default, i2c input clock is programmed at
platform clk / 2 in u-boot, but this is not
correct for all the platforms,
Update I2C clock divider's default values as per
SoC (LS1012A, LS1028A, LX2160A and LS1088A).

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 16:15:42 +05:30
Thomas Schaefer
0490cab584 armv8: ls1028a: configure PMU's PCTBENR to enable WDT
The SP805-WDT module on LS1028A requires configuration of PMU's
PCTBENR register to enable watchdog counter decrement and reset
signal generation. The watchdog clock needs to be enabled first.

Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com>
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 16:15:42 +05:30
Alex Marginean
a3ce94b602 arm: dts: ls1028a-qds: define the MDIO MUX
Add the device-tree structure describing the MUX in board dts.

QDS board has an on-board RGMII PHY and 4 slots for extension cards.
All these can be accessed over MDIO through a MDIO MUX controlled
over I2C.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 16:15:31 +05:30
Yinbo Zhu
23da111d5f dts: armv8: add emmc hs200 support for ls1028ardb
Add emmc hs200 support for ls1028ardb

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 14:04:43 +05:30
Yinbo Zhu
0f021c8bde dts: armv8: add emmc hs200 support for lx2160ardb
Add emmc hs200 support for lx2160ardb

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 14:04:09 +05:30
Yinbo Zhu
be852314dc dts: armv8: add emmc hs200 support for ls1012ardb
Add emmc hs200 support for ls1012ardb

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 14:03:10 +05:30
Yinbo Zhu
24cb6f2295 fsl-layerscape: Add fsl_esdhc peripheral clock support
Add esdhc peripheral clock support
for NXP layerscape platforms: LS1046ARDB, LS1043ARDB,
LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 14:00:35 +05:30
Kever Yang
c9ec5fe018 rockchip: clean makefile for misc.c
Use obj-$(config) instead of #ifdef $config to make the code looks
clean, and move the misc_init for U-Boot proper only.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11 16:16:12 +08:00
Kever Yang
45f8b55eca rockchip: not depends on TPL_BUILD for rk3188 makefile including
The rk3188/Makefile already depends on !TPL_BUILD, so no need to add
this again in parent Makefile, remove it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11 16:16:12 +08:00
Kever Yang
86b4a6db68 rockchip: rk3399: dts: add boot order for rockpro64
The rk3399 rockpro64 board can boot from emmc and sdcard.
TODO: add spiflash as boot device.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11 16:16:12 +08:00
Andy Shevchenko
dd4faa964f x86: tangier: Use spaces over TABs in ASL code
For sake of consistency use spaces over TABs in ASL code.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10 16:19:03 +08:00
Andy Shevchenko
980fe1ab2a x86: tangier: Fix off-by-one error when preparing CSRT
Intel iDMA 32-bit controller has 17 bits for the maximum block size value.
Due to nature of the binary number representation the maximum value is
2^17 - 1. The original code misses the latter part in equation.

Fixes: 5e99fde34a ("x86: tangier: Populate CSRT for shared DMA controller")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10 16:19:03 +08:00
Andy Shevchenko
0c6352ec2a x86: tangier: Reserve PCI ECAM in motherboard resources
Per PCI firmware specification the ACPI has to reserve the memory
which is defined as PCI ECAM.

Fixes: 39665beed6 ("x86: tangier: Enable ACPI support for Intel Tangier")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10 16:19:03 +08:00
Andy Shevchenko
19b6e1ba8c x86: acpi: Annotate struct acpi_table_header with __packed
GCC 9.2 starts complaining about possible pointer misalignment of
pointers to the unpacked (alignment=4) structures in the packed
(alignment=1) ones:

  CC      arch/x86/cpu/tangier/acpi.o
arch/x86/cpu/tangier/acpi.c: In function ‘acpi_create_fadt’:
arch/x86/cpu/tangier/acpi.c:22:37: warning: taking address of packed
member of ‘struct acpi_fadt’ may result in an unaligned pointer value
[-Waddress-of-packed-member]
  22 |  struct acpi_table_header *header = &(fadt->header);

  CC      arch/x86/lib/acpi_table.o
arch/x86/lib/acpi_table.c: In function ‘acpi_create_spcr’:
arch/x86/lib/acpi_table.c:366:37: warning: taking address of packed
member of ‘struct acpi_spcr’ may result in an unaligned pointer value
[-Waddress-of-packed-member]
  366 |  struct acpi_table_header *header = &(spcr->header);

Fix the potential issues by annotating embedded structures with
__packed even though they are packed naturally.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: add GCC version number in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10 16:17:55 +08:00
Park, Aiden
5793553fa2 x86: efi_loader: Use efi_add_conventional_memory_map()
Use efi_add_conventional_memory_map() to configure EFI conventional memory
properly with ram_top value. This will give 32-bit mode U-Boot proper
conventional memory regions even if e820 has an entry which is greater than
32-bit address space.

Signed-off-by: Aiden Park <aiden.park@intel.com>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
[bmeng: fixed some typos in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10 14:31:42 +08:00
Heinrich Schuchardt
74b76357df x86: show UEFI images involved in crash
If a crash occurs, show the loaded UEFI images to facilitate analysis.

This is an example output:

=> bootefi 0x1000000
Found 0 disks
Hello world of bugs!
Invalid Opcode (Undefined Opcode)
EIP: 0010:[<06ceb06e>] EFLAGS: 00010206
Original EIP :[<fec9906e>]
EAX: 00000000 EBX: 06cec000 ECX: 00000fd0 EDX: 00000001
ESI: 06ced18a EDI: 07d0fe10 EBP: 07fe27a0 ESP: 07d0fde0
 DS: 0018 ES: 0018 FS: 0020 GS: 0018 SS: 0018
CR0: 00000033 CR2: 00000000 CR3: 00000000 CR4: 00000000
DR0: 00000000 DR1: 00000000 DR2: 00000000 DR3: 00000000
DR6: ffff0ff0 DR7: 00000400
Stack:
    0x07d0fde8 : 0x00000000
    0x07d0fde4 : 0x06ced040
--->0x07d0fde0 : 0x07fe27a0
    0x07d0fddc : 0x00010206
    0x07d0fdd8 : 0x00000010
    0x07d0fdd4 : 0x06ceb06e
UEFI image [0x06cea000:0x06cf0fff] pc=0x106e '/bug-i386.efi'
### ERROR ### Please RESET the board ###

With the additional information provided by this patch we know that the
problem occurred 0x106e after the load address of bug-i386.efi.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10 14:27:15 +08:00
Bin Meng
2495c3a3fd x86: qemu: Report high memory in the E820 table
Now that we are able to get the size of high memory from QEMU,
report its memory range as usable ram.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Aiden Park <aiden.park@intel.com>
2019-09-10 14:19:39 +08:00
Bin Meng
ea67d549b8 x86: qemu: Support getting high memory size
At present only size of memory that is below 4GiB is retrieved from
QEMU. Add a function that gets size of memory that is above 4GiB.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Aiden Park <aiden.park@intel.com>
2019-09-10 14:19:39 +08:00
Bin Meng
f4c0030074 x86: qemu: Extract getting memory size to a separate routine
This extracts getting memory size logic in dram_init() to a separate
routine qemu_get_low_memory_size(). No functional changes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Aiden Park <aiden.park@intel.com>
2019-09-10 14:19:39 +08:00
Bin Meng
d2860c0088 x86: Drop weak version board_get_usable_ram_top()
Every x86 platform provides board_get_usable_ram_top(), hence there
is no need to provide a weak version board_get_usable_ram_top(), not
to mention there is another weak version board_get_usable_ram_top()
in common/board_f.c.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Aiden Park <aiden.park@intel.com>
2019-09-10 14:19:39 +08:00
Andy Shevchenko
03f78868ae x86: acpi: Slightly reduce binary size of ACPI tables for Tangier
Using ACPI predefined macros, such as Zero or One, will reduce a binary
size of resulting ACPI tables.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: manually fixed the conflicts when applying]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10 14:19:39 +08:00
Tom Rini
40e362a9ab Merge tag 'mmc-9-6-2019' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
Bug fixes to mmc_spi
Add Aspeed SD driver
Fix dw_mmc timeout calculation
Fix timeout values passed to mmc_wait_dat0
sdhci dt caps/mask update

[trini: Fix evb-ast2500_defconfig CONFIG_MMC line]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-09-08 21:15:13 -04:00
Tom Rini
2f760735c1 Merge branch 'master' of git://git.denx.de/u-boot-sh
- Initial DM conversion
2019-09-07 13:49:39 -04:00
Tom Rini
ba83753289 - fix mailbox status register used for polling
- fix bcm2835_sdhost to wait long enough for a transfer to complete
 - increase kernel image size from 8 MB to 64 MB on arm64
 - add support for RPi4
 - add prefixes for raspberry pi related stuff to git-mailrc
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Merge tag 'rpi-next-2019.10' of https://github.com/mbgg/u-boot

- fix mailbox status register used for polling
- fix bcm2835_sdhost to wait long enough for a transfer to complete
- increase kernel image size from 8 MB to 64 MB on arm64
- add support for RPi4
- add prefixes for raspberry pi related stuff to git-mailrc
2019-09-06 19:49:51 -04:00
Andrei Gherzan
76bce8c2ad ARM: bcm283x: Include definition for additional emmc clock
This clock has a different mbox ID so have this included in the relevant
header file.

Signed-off-by: Andrei Gherzan <andrei@balena.io>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-09-06 18:16:59 +02:00
Andrei Gherzan
c6bcf05fcd ARM: bcm283x: Define configs for RaspberryPi 4
Define two target configs for Raspberry Pi 4 (32 and 64bit) and the
corresponding BCM2838* configs.

Be aware of the current limitation in firmware which requires an
explicit configuration to force the arm in 64bit mode when the
respective target is used.

Signed-off-by: Andrei Gherzan <andrei@balena.io>
[mb: rename BCM2838 -> BCM2711]
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-09-06 18:16:59 +02:00
Matthias Brugger
1cfac5204c ARM: bcm283x: Add BCM283x_BASE define
Devices of bcm283x have different base address, depending if they are on
bcm2835 or bcm2836/7. Use BCM283x_BASE depending on the SoC you want to
build and only add the offset in the header files.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Andrei Gherzan <andrei@balena.io>
2019-09-06 18:16:59 +02:00
Fabian Vogt
49822442ed ARM: bcm283x mbox: Fix send status register
Before we can send a message to the mailbox we have to check that there
is space to do so. Therefore we poll the status register. But up to now
the wrong status register, the one of mailbox 0, was checked. Fix this
by polling the status regiser of mailbox 1.

Signed-off-by: Fabian Vogt <fvogt@suse.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
[mb: rename registers and update commit message]
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-09-06 18:16:59 +02:00
Eddie James
30231e0ddb ARM: dts: ast2500: Add SDHCI nodes
Add nodes for the Aspeed SD controllers with their necessary properties.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Eddie James <eajames@linux.ibm.com>
2019-09-05 15:27:31 +08:00
Eddie James
7764ee2e83 mmc: Add Aspeed SD controller driver
Add support for the Aspeed SD host controller engine.

Signed-off-by: Eddie James <eajames@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
2019-09-05 15:27:31 +08:00
Eddie James
38c9f08b41 clk: aspeed: Add support for SD clock
Add code to enable the SD clock on the ast2500 SoC.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Eddie James <eajames@linux.ibm.com>
2019-09-05 15:27:31 +08:00
Alex Marginean
7660d5c120 arm: dts: Set custom names for cp110 master/slave MDIO buses
Implicitly Marvell MDIO driver uses DT node names for devices, but in this
case that is not unique.  Set MDIO device names for master/slave to
cpm/cps.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-09-04 11:37:19 -05:00
Florinel Iordache
1bad991205 drivers/fsl-mc: Create Kconfig file to manage driver specific configs better
Create drivers/net/fsl-mc/Kconfig and move fsl-mc specific configs
from arch/arm/cpu/armv8/fsl-layerscape/Kconfig to this new Kconfig

Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-09-04 11:37:19 -05:00
Tom Rini
448f11f750 Merge tag 'arc-for-2019.10-rc4' of https://gitlab.denx.de/u-boot/custodians/u-boot-arc
These are some very late changes mostly required to get 64-bit
division working on ARC boards.

For that we had to import missing parts of libgcc and add compiler
flags to EMSDP which otherwise used very simple profile for compliation.

And while at it another fix for EM SDP initialization is inluded as well.
2019-09-03 12:40:50 -04:00
Alexey Brodkin
fbf8c50163 arc: libgcc: Import __udivdi3 & __udivmoddi4 to allow 64-bit division
As reported by Kever here [1] we were unable to compile 64-bit division
code due to missing definition of __udivdi3().

Import its implementation and __udivmoddi4() as its direct dependency
from today's libgcc [2].

[1] https://patchwork.ozlabs.org/patch/1146845/
[2] 5d8723600b

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
2019-09-03 19:05:34 +03:00
Tom Rini
f65fb411ed Merge tag 'for-v2019.10-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c
i2c bugfixes for 2019.10 take 2
- i2c: mxc: add CONFIG_CLK support
  If CONFIG_CLK is enabled use clk framework for clock settings.
2019-09-03 07:16:05 -04:00
Rick Chen
61ce84b2cf riscv: cache: use CCTL to flush d-cache
Use CCTL command to do d-cache write back
and invalidate instead of fence.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03 09:31:03 +08:00
Rick Chen
cf6ee112d8 riscv: dts: move out AE350 L2 node from cpus node
When L2 node exists inside cpus node, uclass_get_device
can not parse L2 node successfully. So move it outside
from cpus node.

Also add tag-ram-ctl and data-ram-ctl attributes for
v5l2 cache controller driver. This can adjust timing
by requirement from dtb to improve performance.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03 09:31:03 +08:00
Rick Chen
7045ed9f1a riscv: cache: Flush L2 cache before jump to linux
Flush and disable L2 cache in dcache_disable()
which will be called in cleanup_before_linux()
before jump to linux.

The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03 09:31:03 +08:00
Rick Chen
a8323d1816 riscv: ax25: add imply v5l2 cache controller
Select the v5l2 UCLASS_CACHE driver for ax25.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03 09:31:03 +08:00
Rick Chen
d58b0a6ee1 riscv: andes_plic: init plic by scanning each cpu node
Initialize plic driver by ofnode_for_each_subnode() instead
of cpu_get_count().

This way can support to skip some harts which maybe marked as
unavailable, but the cpu node exists indeed.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03 09:30:54 +08:00
Marcus Comstedt
f6cb427fdc riscv: update fix_rela_dyn
The addend is now added for RELOC_TYPE relocs.  Also, changed the loop
structure so that all the R_RISCV_RELATIVE relocs are not required to
be at the beginning of the list.

Signed-off-by: Marcus Comstedt <marcus@mc.pp.se>
Cc: Rick Chen <rick@andestech.com>
2019-09-03 09:30:41 +08:00
Marek Vasut
eaae4ee2bd sh: r2dplus: Switch to DM PCI driver
Add DT entry for the DM PCI driver, update board configs
and drop ad-hoc board init code for the PCI bus. Instead,
let the DM PCI driver initialize and operate the hardware.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-09-02 17:38:43 +02:00
Marek Vasut
8c2c46350d sh: r2dplus: Enable OF control
Enable OF control for SH4 R2Dplus board. This is necessary, because
the PCI uclass is designed in a way that makes it depend on DT and
disallows instanciating devices without DT (e.g. with platdata).

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-09-02 17:38:43 +02:00
Marek Vasut
ee3a4a708a sh: Fix OF_SEPARATE support
If the OF_SEPARATE is enabled, the DT is appended past the _end symbol.
The current code however clears BSS very early, which overwrites the DT
blob with zeroes. Moreover, the early code relocates U-Boot into RAM to
the correct location, but does not relocate the DT.

This patch adds code to relocate the DT and avoids clearing BSS too
early, thus addressing both problems with OF_SEPARATE on SH.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-09-02 17:38:42 +02:00
Marek Vasut
6756762024 sh: tmu: Fix SH4 TCNT0 offset
Fix the offset of TCNT0 register, which is 0xc on SH4.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-09-02 17:38:42 +02:00
Peng Fan
6dba0864ec i2c: mxc: add CONFIG_CLK support
When CONFIG_CLK enabled, use CLK UCLASS for clk related settings.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>

hs: removed hunk in mxc_i2c_probe() as not longer in code
2019-09-02 06:35:08 +02:00
Tom Rini
d22c8be964 Merge branch 'master' of git://git.denx.de/u-boot-sh
- r8a66597 usb changes
2019-09-01 13:33:12 -04:00
Ryan Harkin
296439e0b1 Revert "vexpress64: fvp dram: add DRAM configuration"
This reverts commit fc04b92354 where the
FVP DRAM configuration was added.

Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
2019-08-31 09:27:19 -04:00
Stephen Warren
5e0404ff85 board_f: fix noncached reservation calculation
The current code in reserve_noncached() has two issues:

1) The first update of gd->start_addr_sp always rounds down to a section
start. However, the equivalent calculation in cache.c:noncached_init()
always first rounds up to a section start, then subtracts a section size.
These two calculations differ if the initial value is already rounded to
section alignment.

2) The second update of gd->start_addr_sp subtracts exactly
CONFIG_SYS_NONCACHED_MEMORY, whereas the equivalent calculation in
cache.c:noncached_init() rounds the noncached size up to section
alignment before subtracting it. The two calculations differ if the
noncached region size is not a multiple of the MMU section size.

In practice, one/both of those issues causes a practical problem on
Jetson TX1; U-Boot triggers a synchronous abort during initialization,
likely due to overlapping use of some memory region.

This change fixes both these issues by duplicating the exact calculations
from noncached_init() into reserve_noncached().

However, this fix assumes that gd->start_addr_sp on entry to
reserve_noncached() exactly matches mem_malloc_start on entry to
noncached_init(). I haven't traced the code to see whether it absolutely
guarantees this in all (or indeed any!) cases. Consequently, I added some
comments in the hope that this condition will continue to be true.

Fixes: 5f7adb5b1c ("board_f: reserve noncached space below malloc area")
Cc: Vikas Manocha <vikas.manocha@st.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2019-08-30 14:17:11 -04:00
Tom Rini
25f32e0dff Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx
Enable DM PCI for T2080RDB, T4240RDB, T1024RDB, T1042D4RDB, P1020RDB,
P2020RDB, P2041RDB, P3041DS, P4080DS, and MPC8548CDS
2019-08-29 07:26:13 -04:00
Hou Zhiqiang
00acf26044 MPC8548: dts: Added PCIe DT node
MPC8548 integrated a PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for the PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28 13:47:47 +05:30
Hou Zhiqiang
a1958b118b P5040: dts: Added PCIe DT nodes
P5040 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28 13:47:47 +05:30
Hou Zhiqiang
936339a500 P4080: dts: Added PCIe DT nodes
P4080 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28 13:47:46 +05:30
Hou Zhiqiang
fc81606da9 P3041: dts: Added PCIe DT nodes
P3041 integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28 13:47:46 +05:30
Hou Zhiqiang
48a33645b0 P2041: dts: Added PCIe DT nodes
P2041 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28 13:47:46 +05:30
Hou Zhiqiang
6875149740 P2020: dts: Added PCIe DT nodes
P2020 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28 13:47:46 +05:30
Hou Zhiqiang
594708dd9d P1020: dts: Added PCIe DT nodes
P1020 integrated 2 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28 13:47:46 +05:30
Hou Zhiqiang
3e89360e11 t104x: dts: Added PCIe DT nodes
T104x integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28 13:47:45 +05:30
Hou Zhiqiang
efd7d712dd t102x: dts: Added PCIe DT nodes
T102x integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28 13:47:45 +05:30
Hou Zhiqiang
948d811882 t4240: dts: Added PCIe DT nodes
T4240 integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 3.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28 13:47:45 +05:30
Tom Rini
8c56ea5c1e Merge branch 'u-boot-stm32_20190827' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- Fixes and update related to STM32MP1 platforms
2019-08-27 13:19:47 -04:00
Tom Rini
e4b8dd9b34 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx
Support of device tree model for T2080RDB, T4240RDB, T1024RDB,
T1042D4RDB, P1020RDB, P2020RDB, P2041RDB, P3041DS, P4080DS, P5040DS and
MPC8548CDS. Also support of  i2c dm model.
2019-08-27 07:11:37 -04:00
Patrick Delaunay
5d2901a4b6 stm32mp1: Add remoteproc support for m4 coprocessor
Alignment with kernel patch proposal for binding:

[PATCH v4 0/8] stm32 m4 remoteproc on STM32MP157c
https://lkml.org/lkml/2019/5/14/159

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27 11:19:23 +02:00
Patrick Delaunay
0c8620d2ff bsec: update after MISC u-class update
Since the commit 8729b1ae2c ("misc: Update read() and
write() methods to return bytes xfered"); The misc bsec driver
need to be adapted to reflect the number of transferred bytes.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27 11:19:23 +02:00
Patrick Delaunay
4d401e96cf stm32mp1: Makefile cleanup
Don't compile psci for SPL build.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27 11:19:23 +02:00
Patrick Delaunay
5e959ab85e stm32mp1: board: Update the way vdd-supply is retrieved from DT
Due to kernel DT alignment, pwr-supply is renamed to vdd-supply
and is a subnode of pwr-regulators.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27 11:19:23 +02:00
Patrick Delaunay
dd2810851e stm32mp1: board: support of error led on ed1/ev1 board
Create a function led_error_blink and add node in device
tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27 11:19:23 +02:00
Patrick Delaunay
d573e46168 stm32mp1: board: enable v1v2_hdmi and v3v3_hdmi regulator on dk2 boot
As for Audio codec IC, HDMI IC is not "IO safe".
HDMI regulators (v3v3 and v1v2) must be enabled to allow
I2C1 bus usage. HDMI IC must be under reset during power up
and keep HDMI and AUDIO devices in reset while they are not
used in U-Boot to keep them in low power mode
(each device can be kept in reset independently keeping their
power supplies ON until kernel).

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27 11:19:23 +02:00
Patrick Delaunay
49ef8e134e stm32mp1: configs: add spi load support in spl
Add the boot for NOR, SPL load U-Boot.img at offset
CONFIG_SYS_SPI_U_BOOT_OFFS = 0x80000.
It is the start address of mtd partition ssbl in nor.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27 11:19:23 +02:00
Patrick Delaunay
9cd8b9f0c5 stm32mp1: configs: add condition to activate WATCHDOG in SPL
Only activate WATCHDOG in SPL when CONFIG_WATCHDOG is activated in U-Boot.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27 09:36:56 +02:00
Patrick Delaunay
f219361de1 stm32mp1: configs: imply CONFIG_OF_LIBFDT_OVERLAY
Add imply for FDT overlay that can be usefuill for kernel device tree
management but it is not mandatory (can be removed to gain space)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27 09:36:56 +02:00
Patrick Delaunay
a67d958177 stm32mp1: configs: Activate DISABLE_CONSOLE
Activate DISABLE_CONSOLE needed for stm32prog support on uart.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27 09:36:56 +02:00
Patrick Delaunay
16a0722320 stm32mp1: configs: select CONFIG_STM32_SERIAL
Select the serial driver mandatory for the console.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27 09:36:56 +02:00
Patrick Delaunay
6755198001 stm32mp1: configs: activate PRE_CONSOLE_BUFFER
Correctly handle silent=1 in the default environment.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27 09:36:56 +02:00
Patrick Delaunay
c50c928064 stm32mp1: configs: activate CONFIG_SILENT_CONSOLE
Allow to disable console with environment variable 'silent':
> env set silent 1; env save

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27 09:36:56 +02:00
Patrick Delaunay
178a415534 stpmic1: program pmic to keep only the debug unit on
Depending on backup register value, we maintain the debug unit
powered-on for debugging purpose.
Only BUCK1 is required for powering the debug unit, so revert
the setting for all the other power lanes, except BUCK3 that
has to be always on.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27 09:36:56 +02:00
Patrick Delaunay
7acda7eae5 ARM: dts: stm32mp1: add pull-up on serial rx of console connected to STLINK
Avoid U-Boot auto-boot interruption for line break detection
on console when the RX line connected to STLINK is floating
(-IO error in getc cause by framing error and testc return 1)
Same workaround is applied on all the STMicroelectonics board.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27 09:36:56 +02:00
Patrick Delaunay
9c2214b489 ARM: dts: stm32mp1: add key support on DK1/DK2
Allow to use PA13 and PA14 to force fastboot mode or STM32CubeProgrammer
mode.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27 09:36:56 +02:00
Patrick Delaunay
2c2580984a ARM: dts: stm32mp1: add ldtc pre-reloc proper in SOC file
The pre-relocation probe is needed to reserve video frame buffer
in video_reserve() for all the board;
LDTC must be tagged prereloc in SOC U-Boot dtsi file.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27 09:36:56 +02:00
Patrick Delaunay
67b7684f8c ARM: dts: stm32mp1: Add PSCI node access before relocation
Add node in DT and avoid error to search UCLASS_SYSRESET in
board_f.c::print_resetinfo() and lost 1.6s in U-Boot
for the trusted boot chain.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27 09:36:56 +02:00
Patrick Delaunay
6d923007d6 ARM: dts: stm32mp1: Add iwdg2 support for SPL
This patch adds independent watchdog support for stm32mp157c
in SPL.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27 09:36:56 +02:00
Patrick Delaunay
be16c41f85 ARM: dts: stm32mp1: DDR config v1.45
Update DDR configuration with the latest update:
- Change DQSGE to 1 for DDR3, to cure missing DQS preamble.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27 09:36:56 +02:00
Patrick Delaunay
fe91533644 ARM: dts: stm32mp1: sync device tree with v5.3-rc2
Synchronize device tree with v5.3-rc2 label and
update the associated u-boot dtsi.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27 09:36:56 +02:00
Patrice Chotard
0203050e57 ARM: dts: stih410-b2260: Sync DT with kernel v5.2
Synchronize U-boot DT with kernel v5.2 for stih410-b2260.
Update stih410-b2260-u-boot.dtsi accordingly.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-08-27 09:36:56 +02:00
Tom Rini
12277acda0 Merge branch '2019-08-26-master-imports'
- Assorted minor bugfixes
2019-08-26 17:45:20 -04:00
Hou Zhiqiang
f83c7788a7 powerpc: Enable device tree support for MPC8548CDS
Add device tree for MPC8548CDS board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-26 21:33:46 +05:30
Hou Zhiqiang
10336061e2 powerpc: dts: add default definition of CONFIG_RESET_VECTOR_ADDRESS
Add CONFIG_RESET_VECTOR_ADDRESS definition with the default value
in u-boot.dtsi to fix the build error below. In the configuration
header file of some MPC85xx boards, there is not the definition
of CONFIG_RESET_VECTOR_ADDRESS, while CONFIG_SYS_MPC85XX_NO_RESETVEC
is also not defined. In this case, it will lack of definition of
CONFIG_RESET_VECTOR_ADDRESS in u-boot.dtsi, and the address
0xfffffffc will be used as the boot page by default.

Error log:
  DTC     arch/powerpc/dts/mpc8548cds.dtb
  DTC     arch/powerpc/dts/mpc8548cds_36b.dtb
Error: arch/powerpc/dts/u-boot.dtsi:28.15-16 syntax error
FATAL ERROR: Unable to parse input tree
Error: arch/powerpc/dts/u-boot.dtsi:28.15-16 syntax error
FATAL ERROR: Unable to parse input tree
scripts/Makefile.lib:308: recipe for target
'arch/powerpc/dts/mpc8548cds.dtb' failed
make[2]: *** [arch/powerpc/dts/mpc8548cds.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
scripts/Makefile.lib:308: recipe for target
'arch/powerpc/dts/mpc8548cds_36b.dtb' failed
make[2]: *** [arch/powerpc/dts/mpc8548cds_36b.dtb] Error 1
dts/Makefile:38: recipe for target 'arch-dtbs' failed
make[1]: *** [arch-dtbs] Error 2
Makefile:1038: recipe for target 'dts/dt.dtb' failed
make: *** [dts/dt.dtb] Error 2

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-26 21:31:01 +05:30
Hou Zhiqiang
c6dd3fa74f powerpc: Enable device tree support for P5040DS
Add device tree for P5040DS board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-26 21:31:00 +05:30
Hou Zhiqiang
23975db5e9 powerpc: Enable device tree support for P4080DS
Add device tree for P4080DS board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-26 21:29:01 +05:30
Hou Zhiqiang
bebc0727fe powerpc: Enable device tree support for P3041DS
Add device tree for P3041DS board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-26 21:27:31 +05:30
Hou Zhiqiang
c36643ff48 powerpc: Enable device tree support for P2041RDB
Add device tree for P1041RDB board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-26 21:25:23 +05:30
Hou Zhiqiang
caa756975c powerpc: Enable device tree support for P2020RDB
Add device tree for P1020RDB boards and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-26 21:23:22 +05:30
Hou Zhiqiang
ec70cedbce powerpc: Enable device tree support for P1020RDB
Add device tree for P1020RDB boards and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-26 21:23:21 +05:30
Hou Zhiqiang
fa3602859f powerpc: Enable device tree support for T1042D4RDB
Add device tree for T1042D4RDB board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-26 21:23:20 +05:30
Hou Zhiqiang
bd74ea1908 powerpc: Enable device tree support for T1024RDB
Add device tree for T1024RDB board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-26 21:21:02 +05:30
Hou Zhiqiang
b0abde1caf powerpc: Enable device tree support for T4240RDB
Add device tree for T4240RDB board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-26 21:21:00 +05:30
Hou Zhiqiang
bf4e0ff321 powerpc: Enable device tree support for T2080RDB
Add device tree for T2080RDB board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-26 21:16:32 +05:30
Adam Ford
5adbc0e5ca ARM: dts: logicpd-som-lv: Fix i2c2 and i2c3 Pin mux
When the pinmux configuration was added, it was accidentally placed into
the omap3_pmx_wkup node  when it should have been placed into the
omap3_pmx_core.  This error was accidentally propagated to U-Boot by
me when I blindly copied the device tree from Linux.

This patch moves the i2c2_pins and i2c3_pins to the correct node
which should eliminate i2c bus errors and timeouts due to the fact
the bootloader uses the save device tree that no longer properly
assigns these pins.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-08-26 11:46:20 -04:00
Tom Rini
7a4b0bc5fe Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- Support SPL and OpenSBI (FW_DYNAMIC firmware) boot.
- Fix qemu kconfig build warning.
2019-08-26 09:50:46 -04:00
Lukas Auer
89fe196c99 riscv: add a generic FIT generator script
Add a generic FIT generator script for RISC-V to generate images
containing U-Boot, OpenSBI FW_DYNAMIC firmware, and optionally one or
more device trees. The location of the OpenSBI firmware binary can be
specified with the OPENSBI environment variable. By default, it is
assumed to be "fw_dynamic.bin", located in the U-Boot top-level. Device
trees are passed as arguments to the generator script. A separate
configuration entry is created for each device tree.

The load addresses of U-Boot and OpenSBI are parsed from the U-Boot
configuration. They can be overwritten with the UBOOT_LOAD_ADDR and
OPENSBI_LOAD_ADDR environment variables.

The script is based on the i.MX (arch/arm/mach-imx/mkimage_fit_atf.sh)
and Allwinner sunxi (board/sunxi/mksunxi_fit_atf.sh) FIT generator
scripts.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-08-26 16:07:42 +08:00
Lukas Auer
c7e1effb96 riscv: support SPL stack and global data relocation
To support relocation of the stack and global data on RISC-V, the
secondary harts must be notified of the change using IPIs. We can reuse
the hart relocation code for this purpose. It uses global data to store
the new stack pointer and global data pointer for the secondary harts.
This means that we cannot update the global data pointer of the main
hart in spl_relocate_stack_gd(), because the secondary harts have not
yet been relocated at this point. It is updated after the secondary
harts have been notified.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-08-26 16:07:42 +08:00
Lukas Auer
8c59f2023c riscv: add SPL support
U-Boot SPL on the generic RISC-V CPU supports two boot flows, directly
jumping to the image and via OpenSBI firmware. In the first case, both
U-Boot SPL and proper must be compiled to run in the same privilege
mode. Using OpenSBI firmware, U-Boot SPL must be compiled for machine
mode and U-Boot proper for supervisor mode.

To be able to use SPL, boards have to provide a supported SPL boot
device.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-08-26 16:07:42 +08:00
Lukas Auer
fbfd92bf9b riscv: add run mode configuration for SPL
U-Boot SPL can be run in a different privilege mode from U-Boot proper.
Add new configuration entries for SPL to allow the run mode to be
configured independently of U-Boot proper.

Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE
configuration symbols to also cover the SPL equivalents. Ensure that
files compatible with only one privilege mode are not included in builds
targeting an incompatible privilege mode.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-08-26 16:07:42 +08:00
Adam Ford
1bf330150c Convert CONFIG_ARCH_CPU_INIT to Kconfig
This converts the following to Kconfig:
   CONFIG_ARCH_CPU_INIT

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Tested-by: Felix Brack <fb@ltec.ch>
2019-08-25 19:32:55 -04:00
Tom Rini
50b4b80f59 Merge tag 'u-boot-rockchip-20190823' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- remove rk3288 fennec board
- remove SPL raw image support for Rockchip SoCs
- add common misc_init_r() for ethaddr from cpuid
- enable USB HOST support for rk3328
- unify code for finding a valid gpt in part driver
2019-08-24 08:33:27 -04:00
Adam Ford
057055660f Kconfigs: Various: Fix some SPL, TPL and ARM64 dependencies
Several options are presenting themselves on a various boards
where the options are clearly not used.  (ie, arm64 options on
arm9, or SPL/TPL options when SPL or TPL are not defined)

This patch is not attempting to be a complete list of items, but
more like low hanging fruit.

This patch attempts to reduce some of the menuconfig noise
by defining dependencies so they don't appear when not used.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-08-23 13:59:06 -04:00
Rohan Garg
0482538499 rockchip: rk3399: derive ethaddr from cpuid
Generate a MAC address based on the cpuid available in the efuse
block: Use the first 6 byte of the cpuid's SHA256 hash and set the
locally administered bits. Also ensure that the multicast bit is
cleared.

The MAC address is only generated and set if there is no ethaddr
present in the saved environment.

This is based off of Klaus Goger's work in 8adc9d

Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-23 18:15:31 +08:00
Kever Yang
cb8c492f20 rockchip: rk3288: remove fennec board support
Since there is no one using this board, remove it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-23 15:27:40 +08:00
Kever Yang
08bbe44424 rockchip: dts: rk3328-rock64: fix usb power supply
According to rock64 schemetic, both VCC_HOST1_5V and VCC_HOST_5V are
controlled by USB20_HOST_DRV(GPIO0A2), fix it so that we can get correct
power supply for USB HOST ports.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-23 15:27:40 +08:00
Kever Yang
2e91e2025c rockchip: rk3328: migrate u-boot node to -u-boot.dtsi
Move all the nodes only shown in u-boot to -u-boot.dtsi to make
rk3328.dtsi clean.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-23 15:27:40 +08:00
Kever Yang
8e5c8571fe rockchip: dts: rk3328-rock64: enable usb3 xhci controller
Rock64 has a USB3.0 port, enable the controller so that we can use it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-23 15:27:40 +08:00
Marek Vasut
be1e9dc080 ARM: renesas: Enable R8A66597 USB host on GR Peach
Enable USB host support on GR Peach board.

To use USB host on GR Peach, it might be necessary to solder JP3 header
onto the board first and then short it. Shorting JP3 is mandatory to let
the U5 regulator to supply VBUS to the CN3 USB port.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
2019-08-22 18:23:37 +02:00
Laurentiu Tudor
b249fcba00 armv8: ls1028a: add icid setup for platform devices
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, edma, qdma, gpu, display and sec.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Laurentiu Tudor
5c6dc6c9a9 armv8: ls1088a: add icid setup for platform devices
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec. The ICID macros for SEC needed to be adapted because
the format of the registers is different.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Laurentiu Tudor
aef654a2ed armv8: fsl-layerscape: make icid setup endianness aware
The current implementation assumes that the registers holding the ICIDs
are universally big endian. That's no longer the case on newer
platforms so update the code to take into account the endianness of
each register.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Laurentiu Tudor
08f9bc9f43 armv8: fsl-layerscape: add base addresses for several devices
Add CCSR base addresses for ESDHC2, EDMA QDMA, DISPLAY and GPU devices.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Laurentiu Tudor
ef3f364a75 armv8: fsl-layerscape: add missing sec jr base address defines
Add defines for all the SEC job rings base addresses.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Chuanhua Han
71a2da3fa9 armv8: kconfig: Fix some platforms incorrect I2C clock divider
By default, i2c input clock is platform clk / 2, but some of the
platform of i2c clock divider does not meet this kind of circumstance,
so alone to set default values for these platforms.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Pankaj Bansal
a02a9421f4 armv8: ls1028aqds: define ARCH_MISC_INIT to handle mux
Define ARCH_MISC_INIT for LS1028AQDS platform to handle board
related mux.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Chuanhua Han
67d3a815cb configs: ls1088a: Enable DM support for pcf2127 rtc
Enable related configs on all ls1088aqds boards to support pcf2127
rtc DM function.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Chuanhua Han
f3b6a711a4 armv8: dts: ls1088aqds : Add pcf2127 node
Add the pcf2127-rtc node under the i2c0->i2c-mux@77->i2c@3 for ls1088aqds boards.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Chuanhua Han
96d3fb4146 armv8: dts: ls1088ardb: Add slave nodes under the i2c0 controller
This patch adds some slave nodes to support the i2c dm on the device
side under the i2c0 controller.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Chuanhua Han
c2eda95a5b armv8: dts: ls1088a: add I2C node support
One ls1088a, there are four I2C controllers. So add all I2C node
for ls1088a in device tree.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Chuanhua Han
bd9eab46c8 gpio: do not include <asm/arch/gpio.h> on ARCH_LS1088A
As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include <asm/arch/gpio.h> for
arch ls1088a.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Chuanhua Han
292370df1c configs: ls2088a: Enable DM support for ds3231 rtc
Enable related configs on all ls2088aqds boards to support ds3231
rtc DM function.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Chuanhua Han
1703aaff8b armv8: dts: ls2088aqds : Add ds3232 node
Add the ds3232-rtc node under the i2c0->i2c-mux@77->i2c@0 for ls2088aqds
boards.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Chuanhua Han
6672ab1628 armv8: dts: ls2088ardb: Add slave nodes under the i2c0
Add some slave nodes to support the i2c dm on the device side under the i2c0.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
chuanhua han
407916f5d7 armv8: dts: fsl-ls2088a: add i2c node support
One ls2088a, there are four I2C controllers. So add I2C nodes in dts
for ls2088a.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Chuanhua Han
b547dd9584 gpio: do not include <asm/arch/gpio.h> on ARCH_LS2080A
As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include <asm/arch/gpio.h> for
arch ls2080a.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Chuanhua Han
bd9b0745f7 armv8: dts: ls1028aqds: Add pcf2127 node under i2c1
Add the pcf2127-rtc node under the i2c1 in dts for ls1028aqds boards.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:35 +05:30
Chuanhua Han
25d9467c16 armv8: dts: ls1028aqds: Add pca9547 node under the i2c0 controller
Add pca9547 node to support i2c multiplexer under the i2c0 controller
in dts for ls1028aqds boards.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:35 +05:30
Chuanhua Han
21d5e964da configs: ls1028a: Enable DM support for pcf2127 rtc
Enable related configs on all ls1028aqds boards to support pcf2127
rtc DM function.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Alex Marginean <alexm.osslist@gmail.com>
Tested-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:35 +05:30
Chuanhua Han
e120d1277d armv8: dts: ls1028ardb: Add slave nodes under the i2c0 controller
Add some slave nodes to support the i2c dm on the device side under the i2c0.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:35 +05:30
Chuanhua Han
dcfb8f516d gpio: do not include <asm/arch/gpio.h> on ARCH_LS1028A
As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include <asm/arch/gpio.h> for
arch ls1028a.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:35 +05:30
Chuanhua Han
7abf9c16aa configs: lx2160: enable DM support for pcf2127 rtc
Enable related configs on all lx2160ardb boards to support pcf2127
rtc DM feature.

Also remove SYS_I2C_MXC_I2Cx, where x is from 1 to 8 from
Kconfig.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:35 +05:30
Chuanhua Han
07cb35fb71 armv8: dts: lx2160aqds : Add pcf2127 node
Add the pcf2127-rtc node under the i2c0->i2c-mux@77->i2c@3 in dts for
lx2160aqds boards.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:35 +05:30
Chuanhua Han
29b9e66683 armv8: dts: lx2160ardb : Add the "u-boot, dm-pre-reloc" for i2c0
Lx2160ardb need to use i2c0 before relocation, so we also need to set
u-boot, dm-pre-reloc to initialize node before relocation.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:35 +05:30
Chuanhua Han
16c22fb39d armv8: dts: Add pcf2127 node for lx2160ardb
Adds the pcf2127-rtc node under the i2c4 node dts of lx2160ardb boards.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:35 +05:30
Chuanhua Han
d1edea248a armv8: dts: fsl-lx2160a: add i2c controller and gpio DT nodes
In lx2160a soc, there are eight i2c controllers, this patch adds i2c
nodes for lx2160a, and the gpio2 nodes on which the i2c4 controller
depends.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:35 +05:30
Chuanhua Han
db717629ff gpio: do not include <asm/arch/gpio.h> on ARCH_LX2160A
As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include <asm/arch/gpio.h> for
arch ls2160a.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:35 +05:30
Chuanhua Han
068cabe8f6 drivers: i2c: mxc: Fix compiler error when using i2c dm mode
I2C dm mode enablemenet causes below compilation errors:

In file included from include/config.h:8:0,
                 from include/common.h:20:
include/config_fallbacks.h:51:4: error: #error "Cannot define
CONFIG_SYS_I2C when CONFIG_DM_I2C is used"
 #  error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used"
    ^~~~~
In file included from include/config.h:8:0,
                 from include/common.h:20:
include/config_fallbacks.h:51:4: error: #error "Cannot define
CONFIG_SYS_I2C when CONFIG_DM_I2C is used"
 #  error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used"
    ^~~~~

board/freescale/lx2160a/lx2160a.c: In function 'board_early_init_f':
board/freescale/lx2160a/lx2160a.c:108:2: warning: implicit declaration
of function 'i2c_early_init_f'; did you mean 'arch_early_init_r'?
[-Wimplicit-function-declaration]
  i2c_early_init_f();
  ^~~~~~~~~~~~~~~~
  arch_early_init_r

 drivers/i2c/mxc_i2c.c: In function 'mxc_i2c_probe':
  drivers/i2c/mxc_i2c.c:824:8: warning: implicit declaration of function
'enable_i2c_clk';
  did you mean 'enable_irq_wake'? [-Wimplicit-function-declaration]
  ret = enable_i2c_clk(1, bus->seq);
        ^~~~~~~~~~~~~~
        enable_irq_wake

So fix these compilation errors.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:35 +05:30
Yuantian Tang
acf40f50b8 armv8: ls1028a: select BOARD_LATE_INIT config
Select BOARD_LATE_INIT for ls1028ardb and ls1028aqds targets
so that late init work can be done.

Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:35 +05:30
Suniel Mahesh
c8e8de138e arm: dts: Makefile: clean *dtb_HS
TI HS platforms generate *dtb_HS binary blobs and there is no
rule for cleanup. Added entry for cleanup in clean-files target.

Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-08-20 11:46:38 -04:00
Suman Anna
a517c1f62f ARM: DRA7: Fixup DPLL clock rate fixup logic for newer kernels
The commit 1b42ab3eda ("ARM: DRA7: Fixup DSPEVE, IVA and GPU clock
frequencies based on OPP") updates the kernel device-tree blob to adjust
the DSP, IVA and GPU DPLL clocks based on a one-time OPP choice selected
in U-Boot. All these DPLL clocks are children of the cm_core_aon clocks
DT node.

The hierarchy of this clocks DT node has changed in newer Linux kernels
starting from v5.0, and this results in a failure in ft_fixup_clocks()
function to update the clock rates on these newer kernels. Fix this by
updating the lookup logic to look through both the newer and older
DT hierarchy paths for the cm_core_aon clocks node.

Signed-off-by: Suman Anna <s-anna@ti.com>
2019-08-20 11:46:38 -04:00
Tom Rini
a2ca54ff52 Merge tag 'u-boot-rockchip-20190819' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Add ROC-RK3399-PC board support
- Move CONFIG_SPI_FLASH_GIGADEVICE and CONFIG_CMD_USB_MASS_STORAGE to
  Kconfig
- using SYSRESET_POWER_OFF for poweroff
  (Note that patch for rk8xx pmic is droped for it can not pass Travis
  build)
- fix ofnode_get_name() assert
2019-08-19 09:22:57 -04:00
Urja Rannikko
b8050511c6 sysreset: move stm32mp sysreset poweroff implementation to sysreset uclass
This is a generic implementation. Add CONFIG_SYSRESET_CMD_POWEROFF
to signal when we need it. Enable it from the STPMIC1 config and in
sandbox.

The config flag is transitionary, that is it can be removed after all
poweroff implementations use sysreset, and just have CMD_POWEROFF depend
on sysreset.

Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-19 12:43:26 +08:00
Urja Rannikko
857f39d7b0 sysreset: switch to using SYSRESET_POWER_OFF for poweroff
It seems that SYSRESET_POWER_OFF was added recently, and all previous code
used SYSRESET_POWER for poweroff. SYSRESET_POWER is supposed to be a
PMIC-level power cycle, not a poweroff.

(Comment by Simon Glass)
SYSRESET_POWER means to do a power reset (removing and reinstating all power)
SYSRESET_POWER_OFF means to turn the device off and leave it off

Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
(Update comment to help understand the patch)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-19 12:43:26 +08:00
Levin Du
8a681f4c5a rockchip: rk3399: Add ROC-RK3399-PC support
Add initial support for ROC-RK3399-PC board.

Specification
- Rockchip RK3399
- LPDDR4 4GiB
- eMMC slot
- SD card slot
- RTL8211E 1Gbps
- HDMI Out, DP, MIPI DSI/CSI, EDP
- PCIe M.2
- USB 2.0, USB-3.0
- USB C Type

Commit details of rk3399-roc-pc.dts sync from Linux v5.2:
"arm64: dts: rockchip: add support for ROC-RK3399-PC board"
(sha1: 8bb878cf20ae10809c36db96993bfce7026d062b)

Signed-off-by: Levin Du <djw@t-chip.com.cn>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-19 12:43:26 +08:00
Stefan Roese
8ad01ce36f x86: Remove x86 specific GD flags as they are not referenced at all
This patch removes the x86 architecture specific GD flags
(GD_FLG_COLD_BOOT & GD_FLG_WARM_BOOT), as they are not used. Only
GD_FLG_COLD_BOOT is referenced in coreboot.c but assigned in start16.S.
But the coreboot target does not use start16.S at all and boots directly
from the 32-bit start code.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-08-18 21:54:10 +08:00
Tom Rini
8c650a9fed Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- Misc gen5 fixes
2019-08-17 10:30:56 -04:00
Simon Goldschmidt
a89441a74f arm: socfpga: gen5: don't zero bss in board_init_f()
The socfpga gen5 SPL manually zeroed bss in board_init_f(). Now that the
DDR driver does not use bss any more, bss is not used before board_init_r()
and we can remove this hack.

bss is normally zeroed by crt0.S, but after board_init_f(), before
board_init_r(). socfpga just had this double-zeroing because it invalidly
used bss in board_init_f() already (during DDR initialization).

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-08-15 08:50:02 +02:00
Ley Foon Tan
63b312d882 arm: socfpga: Fix SYSRESET_SOCFPGA_S10 config name
The CONFIG name should be SYSRESET_SOCFPGA_S10 instead of
SYSRESET_SOCFPGA_STRATIX10.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-08-15 08:50:00 +02:00
Bin Meng
4d2583dba1 riscv: Access CSRs using CSR numbers
We should prefer accessing CSRs using their CSR numbers
because:
1. It compiles fine with older toolchains.
2. We can use latest CSR names in #define macro names of CSR
   numbers as-per RISC-V spec.
3. We can access newly added CSRs even if toolchain does not
   recognize newly added CSRs by name.

This commit is inspired from Linux kernel commit a3182c91ef4e
("RISC-V: Access CSRs using CSR numbers").

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-08-15 13:42:28 +08:00
Bin Meng
268753f8e6 riscv: Sync csr.h with Linux kernel v5.2
This syncs csr.h with Linux kernel 5.2, and imports asm.h that
is required by csr.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-08-15 13:42:28 +08:00
Tom Rini
88c7a0a8c2 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Various improvements to Keymile boards - mostly DT conversation
  (Pascal & Holger)
- Removal of now unsupported Keymile boards (Pascal & Holger)
- Small MVEBU PCI fix (Marek)
- Turris Omnia defconfig update (Marek)
- Misc Allied Telesis defconfig updates (Chris)
2019-08-12 23:03:44 -04:00
Tom Rini
60f38d82c4 - amlogic: add support for the SEI Robotic SEI510
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Merge tag 'u-boot-amlogic-20190812' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- amlogic: add support for the SEI Robotic SEI510
2019-08-12 23:03:35 -04:00
Tom Rini
9c6115822e Merge branch '2019-08-11-ti-imports'
- More DaVinci updates and fixes
- PCIe support on am65x
- Watchdog converted to DM
- Assorted other bugfixes
2019-08-12 18:47:53 -04:00
Andreas Dannenberg
0805fe151d arm: K3: sysfw-loader: Do not require full printf() for version info
A previous commit...

commit 2a51e16bd5 ("configs: Make USE_TINY_PRINTF depend on SPL||TPL and be default")

...causes the System Firmware version string during SPL boot to no longer
getting printed to the console as expected. To fix this issue rework the
handling of that string to only use basic printf() syntax rather than
for example disabling CONFIG_USE_TINY_PRINTF on affected devices, this
way maintaining most of the memory size benefit the initial patch brings
when it comes to SPL.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-08-12 13:33:43 -04:00
Sekhar Nori
476e991452 arm: dts: k3-am65: add support for PCIe and SERDES
Add needed device-tree nodes to support PCIe 0
and SERDES on AM65x SoC. The nodes are kept
disabled by default.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-12 13:33:40 -04:00
Hannes Schmelzer
60df809f62 board/BuR/brsmarc1: initial commit
This commit adds support for the B&R brsmarc1 SoM.

The SoM is based on TI's AM335x SoC.
Mainly vxWorks 6.9.4.x is running on the board,
doing some PLC stuff on various carrier boards.

Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2019-08-12 13:33:37 -04:00
Suniel Mahesh
6912f2a8ae watchdog: omap_wdt: Disable DM watchdog support in SPL
This patch disables DM watchdog support for SPL builds and uses
the legacy omap watchdog driver on TI AM335x chipsets.

The following build error is reported if DM watchdog support was
enabled in SPL:

  CC      spl/drivers/usb/gadget/rndis.o
  LD      spl/drivers/usb/gadget/built-in.o
  LD      spl/drivers/usb/musb-new/built-in.o
  LD      spl/drivers/built-in.o
  LD      spl/u-boot-spl
arm-linux-ld.bfd: u-boot-spl section .u_boot_list will not fit in region .sram
arm-linux-ld.bfd: region .sram overflowed by 440 bytes
make[1]: *** [spl/u-boot-spl] Error 1
make: *** [spl/u-boot-spl] Error 2

Adjusted WATCHDOG_RESET macro accordingly. Earlier it was pointing
to hw_watchdog_reset. Since CONFIG_WATCHDOG replaces CONFIG_HW_WATCHDOG,
now WATCHDOG_RESET macro points to watchdog_reset. This watchdog_reset
is not defined anywhere for am33xx/omap2 and needs to be defined. Fixed
this by simply calling hw_watchdog_reset in watchdog_reset.

Built and tested on AM335x device (BeagleboneBlack), compile tested for
all other AM33xx/omap2 based boards.

Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
[trini: Fix watchdog.h logic]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-08-12 13:27:55 -04:00
Suniel Mahesh
7659ea32a6 watchdog: omap_wdt: Convert watchdog driver to use DT and DM
This patch adds device tree and driver model watchdog support,
converts the legacy omap watchdog driver to driver model for
TI AM335x chipsets. The following compile warning is removed:

===================== WARNING ======================
This board does not use CONFIG_WDT (DM watchdog support).
Please update the board to use CONFIG_WDT before the
v2019.10 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.
====================================================

CONFIG_HW_WATCHDOG is no more a default option for AM33XX devices
after DT/DM conversion, adjusted kconfig accordingly.

DM watchdog support is enabled by default in SPL. The SPL image
doesn't fit into SRAM because of size constraints and build breaks
with an overflow. For this reason DM watchdog support should be
disabled in SPL, driver code should be adjusted accordingly to serve
this purpose.
Built and tested on AM335x device (BeagleboneBlack), compile tested
for all other AM33xx based boards.

Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
2019-08-12 07:25:22 -04:00
Neil Armstrong
9a34dedfae ARM: meson: Add support for fastboot_set_reboot_flag()
Add support for fastboot_set_reboot_flag() by storing the reboot
flag in the common code to be used by the custom PSCI reboot handler.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-08-12 10:05:10 +02:00
Neil Armstrong
b1dd7debea arm: meson: add sm command to retrieve the reboot reason
The Secure Monitor offers multiple services, like returning the
SoC unique serial number, and can provide the "reboot reason" as
set by the previous booted system.

This extends the Amlogic specific "sm" cmd with a "reboot_reason" subcommand
to print or set a specified environment variable with the reboot reason in
human readable format.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-08-12 10:02:30 +02:00
Neil Armstrong
559e6256f8 arm: meson: add sm cmd to retrieve SoC serial
The Secure Monitor offers multiple services, like returning the
SoC unique serial number, already used to generate an unique MAC
address.

This adds a new, Amlogic specific, "sm" cmd with a "serial" subcommand
to write the SoC unique serial to memory.

This "cm" command will be extended in further patches.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-08-12 10:02:30 +02:00
Neil Armstrong
cddca4b4ca ARM: dts: Import Amlogic G12A SEI510 DT from Linux 5.3-rc1
Import Linux 5.2-rc1 sei510 DT from 5f9e832c1370 ("Linus 5.3-rc1") for the
meson-g12a-sei510 board.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-08-12 10:02:30 +02:00
Holger Brunck
7b472733d8 powerpc/km: remove unmaintained target KMVECT1
Signed-off-by: Valentin Longchamp <valentin.longchamp@ch.abb.com>
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-08-12 09:12:38 +02:00
Pascal Linder
b75e9e3fce km/uart: port UART interface of KM Kirkwood boards to driver model
Activate the driver model for the serial interface in the KM Kirkwood
Kconfig file. The associated preprocessor definitions could be removed
from the header file. However, the clock of 200 MHz needs to be declared
in the device tree.

Signed-off-by: Pascal Linder <pascal.linder@edu.hefr.ch>
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-08-12 09:12:38 +02:00
Simon Glass
f3998fdc4d env: Rename environment.h to env_internal.h
This file contains lots of internal details about the environment. Most
code can include env.h instead, calling the functions there as needed.

Rename this file and add a comment at the top to indicate its internal
nature.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
[trini: Fixup apalis-tk1.c]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-08-11 19:27:31 -04:00
Simon Glass
e7dcf5645f env: Drop environment.h header file where not needed
This header file is now only used by files that access internal
environment features. Drop it from various places where it is not needed.

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11 16:43:41 -04:00
Simon Glass
f030b7b260 env: Move TOTAL_MALLOC_LEN to environment.h
This declaration is only used in three files. Although it relates to
malloc() it is actually only used during malloc() init. It uses CONFIG
options including CONFIG_ENV_ADDR which are defined only in environment.h
so this header must be included anyway, for TOTAL_MALLOC_LEN to be
correct.

Nove it to environment.h to simplify the common file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-08-11 16:43:41 -04:00
Simon Glass
0ac7d722ed env: Move get/set_default_env() to env.h
Move these functions to the new header file and rename set_default_env()
to env_set_default() so that it has a consistent env_ prefix.

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11 16:43:41 -04:00
Simon Glass
7b51b576d6 env: Move env_get() to env.h
Move env_get() over to the new header file.

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11 16:43:41 -04:00
Simon Glass
9fb625ce05 env: Move env_set() to env.h
Move env_set() over to the new header file.

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11 16:43:41 -04:00
Simon Glass
cdbff9fc40 env: Move env_get_hex() to env.h
Move env_get_hex() over to the new header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
Simon Glass
6bf6dbee01 env: Move env_get_yesno() to env.h
Move env_get_yesno() over to the new header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
Simon Glass
168068fb3d env: Move env_set_ulong() to env.h
Move env_set_ulong() over to the new header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
Simon Glass
c7694dd483 env: Move env_set_hex() to env.h
Move env_set_hex() over to the new header file along with env_set_addr()
which uses it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
Simon Glass
4bfd1f5d62 env: Move env_init() to env.h
Move env_init() over to the new header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
Simon Glass
3a7d55716d env: Move env_get_f() to env.h
Move this function over to the new header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
Manivannan Sadhasivam
c62c7ef779 board: hisilicon: Add support for Hikey960 board
This commit adds board support for Hikey960 board from Hisilicon. This
board is one of the Consumer Edition boards of the 96Boards family
powered by Kirin960 SoC.

More information about this board can be found in 96Boards website:
https://www.96boards.org/product/hikey960/

The initial supported/tested devices include:
 - Debug serial
 - SD

With these support, it's good enough for loading Linux Kernel from SD.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-08-11 16:43:41 -04:00
Manivannan Sadhasivam
881b6324f0 arm: dts: Add devicetree for Hikey960 board
This commit adds devicetree for Hikey960 board. Most of the contents are
copied from Linux kernel with some modifications for u-boot. To be
more precise, SD card's speed related properties are removed due to a
bug in u-boot clock implementation. Hence forcing the SD controller to
work in standard speed.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-08-11 16:43:41 -04:00
Manivannan Sadhasivam
af8a735ed0 arm: dts: Import HI3660 devicetree from Linux
This commit imports HI3660 SoC devicetree from Linux

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-08-11 16:43:41 -04:00
Tom Rini
feb5a02f86 Merge branch 'master' of git://git.denx.de/u-boot-sh
- R8A77980 V3H support
2019-08-10 17:57:58 -04:00
Tom Rini
9fd8b2c8c7 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- Enable SD slot on Intel Edison
- Populate CSRT ACPI table for shared DMA controller on Intel Tangier
- Convert Intel ICH-SPI driver to use new spi-mem ops
- Enable config_distro_bootcmd for QEMU x86
- Support U-Boot as a payload for Intel Slim Bootloader
- Avoid writing temporary asl files into the source tree which fixes the
  parallel build issue occasionally seen
2019-08-09 23:27:15 -04:00
Marek Vasut
3ebb91914f ARM: renesas: Add R8A77980 V3H Condor board code
Add board code for the R8A77980 V3H Condor board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-08-09 23:15:01 +02:00
Marek Vasut
57ede1a3d4 ARM: renesas: Add R8A77980 V3H platform code
Add a few bits of platform code to support R8A77980 V3H SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-08-09 23:15:01 +02:00
Marek Vasut
a811e19b91 ARM: dts: renesas: Add R8A77980 V3H DTs and headers
Import R8A77980 V3H DTs and headers from Linux 5.2.7 , commit 5697a9d3d55f.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-08-09 23:15:01 +02:00
Marcel Ziswiler
4c63a601b9 apalis-tk1: support v1.2 hardware revision
Support the V1.2 hardware revision with the following pin muxing
changes:

Ddc_scl_pv4 and ddc_sda_pv5 previously used as Apalis GPIO3 and GPIO4
are now used as DDC pins.

Gen2_i2c_scl_pt5 and gen2_i2c_sda_pt6 previously used as DDC pins are
now used as USB power enable signals.

Usb_vbus_en0_pn4 and usb_vbus_en1_pn5 previously used as USB power
enable signals are now used as GPIO3 and GPIO4.

Additionally a new device tree file tegra124-apalis-v1.2-eval.dtb is
loaded on V1.2 and later modules and resp. USB power enable signals
activated.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-08-09 10:01:35 -07:00
Dominik Sliwa
5a20adf446 apalis-tk1: remove non-essential power rails on boot
When mainline kernels reboot TK1 they use SW_RESET,
that reset mode does not reset PMIC. Some rails
need to be off for RAM Re-repair to work correctly.

Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Dominik Sliwa <dominik.sliwa@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-08-09 10:01:35 -07:00
Dominik Sliwa
fbcb925654 apalis-tk1/t30: colibri_t30: display reset reason
Display proper reset reason after the SoC info.

Signed-off-by: Dominik Sliwa <dominik.sliwa@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-08-09 10:01:35 -07:00
Park, Aiden
dbaec46767 x86: Skip setting up MTRRs in slimbootloader
The setting up MTRRs have already been done in previous
Slim Bootloader stages.

Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Park, Aiden
19cad267d9 x86: slimbootloader: Add a slimbootloader device tree
Add a new device tree which has very minimum nodes
- x86 reset
- x86 tsc_timer
- x86 pci
- Slim Bootloader serial

Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Park, Aiden
14360bf059 x86: slimbootloader: Set TSC information for tsc_timer
Slim Bootloader already calibrated TSC and provides it to U-Boot.
Therefore, U-Boot does not have to re-calibrate TSC.
Configuring tsc_base and clock_rate makes x86 tsc_timer driver bypass
TSC calibration and use the provided TSC frequency.
- Get TSC frequency from performance info hob
- Set tsc_base and clock_rate for tsc_timer driver

Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Park, Aiden
2869c3b3de x86: slimbootloader: Add serial driver
Slim Bootloader provides serial port info thru its HOB list pointer.
All these HOBs are eligible for Slim Bootloader based board only.
- Get serial port information from the serial port info HOB
- Leverage ns16550 driver with slimbootloader specific platform data

Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Park, Aiden
1fb17ea548 x86: slimbootloader: Add memory configuration
Slim Bootloader provides memory map info thru its HOB list pointer.
Configure memory size and relocation memory from the HOB data, and
provide e820 entries as well.
- Get memory size from the memory map info HOB
- Set available top memory lower than 4GB for U-Boot relocation
- Provide e820 entries from the memory map info HOB

Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Park, Aiden
7165fd584f x86: Add a common HOB library
FSP (CONFIG_HAVE_FSP) and Slim Bootloader (CONFIG_SYS_SLIMBOOTLOADER)
consume HOB (CONFIG_USE_HOB) data from the each HOB list pointer.
Add a common HOB library in lib/hob.c and include/asm/hob.h.

Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Park, Aiden
5b931a5080 x86: lib: fsp: Use EFI_GUID and efi_guid_t
Use existing EFI_GUID and efi_guid_t instead of struct efi_guid.
This is pre-work before making a common HOB library.
- Change 'struct efi_guid' to efi_guit_t
- Remove 'struct efi_guid'
- Define GUIDs with EFI_GUID() macro
- Use guidcmp() instead of compare_guid()
- Remove compare_guid()

Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Tested on MinnowMax
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Park, Aiden
544293f878 x86: Add new slimbootloader CPU type
This slimbootloader CPU type is to enable U-Boot as a payload which
runs on top of Slim Bootloader (https://github.com/slimbootloader).
The Slim Bootloader is designed with multi-stage architecture for
the execution from reset vector to OS booting, and supports QEMU,
Apollolake, Whiskeylake and Coffeelake platforms consuming Intel
FSP (https://github.com/IntelFsp) for silicon initialization
including CAR and memory initialization.
The Slim Bootloader generates new HOB (Hand Off Block) which are
serial port info, memory map info, performance data info and so on,
and passes it to a Payload. U-Boot as a payload will use these HOB
information for basic initialization such as serial console.

As an initial commit,
- Add CONFIG_SYS_SLIMBOOTLOADER to enable slimbootloader CPU type
- Add new arch/x86/cpu/slimbootloader directory with minimum codes
- Get hob_list pointer from Slim Bootloader

Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Andy Shevchenko
5e99fde34a x86: tangier: Populate CSRT for shared DMA controller
Intel Tangier has a shared DMA controller that, according to Microsoft spec,
has to be presented in CSRT table.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Andy Shevchenko
e3be52ceac x86: acpi: Enable ACPI companion for Intel iDMA 32-bit
ACPI has a capability to specify DMA parameters for DMA channel consumers.
To enable this for Intel Edison, describe GP DMA device in ACPI table
in order to get an ACPI handle to it in OS.

This works in conjunction with CSRT, which must be in align with DSDT.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Andy Shevchenko
ddd2a4244c x86: acpi: Introduce a stub to generate CSRT
Here is a stub function that generates an empty CSRT. If the target platform
provides acpi_fill_csrt() function, it will be used to populate the table.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Andy Shevchenko
eef3007945 x86: acpi: Add CSRT description
Add CSRT [1] description as it provided in Linux kernel.

[1]: http://www.uefi.org/sites/default/files/resources/CSRT%20v2.pdf

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Andy Shevchenko
42ef707922 x86: edison: Enable SD slot
Enable SD slot on Intel Edison platform.

By default firmware doesn't put device on active state. Thus,
we have to do this explicitly.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Tom Rini
21bc1935b1 Merge tag 'u-boot-rockchip-20190809' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Add rk3399 boards Khadas Edge/-V/-Captain
- Add fully souce code support for rk3328 including TPL/DRAM init
- Enable boot from eMMC for rk3399 rock960/ficus boards
- turn on the IO supply for dw_mmc
2019-08-09 07:29:20 -04:00
Tom Rini
fef408679b Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Remove unused bcm2835 watchdog driver (still non-DM)
- Cosmetic fixup of mtk_wdt.c
2019-08-08 09:19:08 -04:00
Ryder Lee
4f3ee271eb ARM: dts: add hifsys reset for MediaTek SoCs
This adds missing hifsys reset parts in header files.

Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
2019-08-07 15:31:03 -04:00
Weijie Gao
102b0b1119 arm: dts: change MT7629 to use spi-mem rather than qspi
The original mtk_qspi driver has been removed. We change MT7629 to use
newly added mtk-spimem driver.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-08-07 12:44:12 -04:00
Kever Yang
3f47db0275 rockchip: Kconfig: enable TPL support for rk3328
Enable TPL support and some related option in Kconfig.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[cherry picked from commit 430b01462b with minor modifications]
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:16:52 +08:00
Kever Yang
ec552bf036 rockchip: dts: rk3328: update dmc node for driver
Update dmc node for full feature driver.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[cherry picked from commit 1e14956365 with minor modifications]
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:14:53 +08:00
Kever Yang
85a38742e0 rockchip: ram: add full feature rk3328 DRAM driver
This driver supports DDR3/LPDDR3/DDR4 SDRAM initialization.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[cherry picked from commit 9fb0777ec3 with minor modifications]
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:14:45 +08:00
Matwey V. Kornilov
86e999f1a5 rockchip: dts: rk3328: Add rk3328-evb-u-boot.dtsi
Split u-boot specific dts configuration to separate
rk3328-evb-u-boot.dtsi

Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:14:30 +08:00
Manivannan Sadhasivam
b06def3572 arm: dts: ficus: Enable booting from eMMC when using SPL
This commits enables booting from eMMC when using SPL on 96Boards
Ficus board by adding SDHCI to boot order. Since the SDHCI driver
already has the reloc flag, this works straightaway. While we are at it,
let's also include the common u-boot dtsi for rk3399.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:14:13 +08:00
Manivannan Sadhasivam
0b5130fa3e arm: dts: rock960: Enable booting from eMMC when using SPL
This commits enables booting from eMMC when using SPL on 96Boards
Rock960 board by adding SDHCI to boot order. Since the SDHCI driver
already has the reloc flag, this works straightaway. While we are at it,
let's also include the common u-boot dtsi for rk3399.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:14:04 +08:00
Nick Xie
a5f1249bd3 arm64: dts: rockchip: Add support for Khadas Edge-Captain
Add devicetree support for Khadas Edge-Captain.
Khadas Captain is the carrier board for Khadas Edge.

Specification
- Rockchip RK3399
- Dual-Channel 2GB/4GB LPDDR4
- SD card slot
- Onboard 16GB/32GB/128GB eMMC
- RTL8211FD 1Gbps
- AP6356S/AP6398S WiFI/BT
- HDMI Out, DP, MIPI DSI/CSI, eDP
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- Full 4 Lane M.2 Socket
- 16MB SPI Flash
- IR
- Programmable MCU

Commit details of rk3399-khadas-edge-*.dts sync from Linux 5.3-rc2:
"arm64: dts: rockchip: Add support for Khadas Edge/Edge-V/Captain boards"
(sha1: c2aacceedc86af87428d998e23a1aca24fd8aa2e)

Signed-off-by: Nick Xie <nick@khadas.com>
Tested-by: Chris Webb <chris@arachsys.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:12:23 +08:00
Nick Xie
6ce9ba02b1 arm64: dts: rockchip: Add support for Khadas Edge-V
Add devicetree support for Khadas Edge-V.
Khadas Edge-V is a Khadas VIM form factor Rockchip RK3399 board.

Specification
- Rockchip RK3399
- Dual-Channel 2GB/4GB LPDDR4
- SD card slot
- Onboard 16GB/32GB/128GB eMMC
- RTL8211FD 1Gbps
- AP6356S/AP6398S WiFI/BT
- HDMI Out, DP, MIPI DSI/CSI, eDP
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- Full 4 Lane M.2 Socket
- 16MB SPI Flash
- IR
- Programmable MCU

Commit details of rk3399-khadas-edge-*.dts sync from Linux 5.3-rc2:
"arm64: dts: rockchip: Add support for Khadas Edge/Edge-V/Captain boards"
(sha1: c2aacceedc86af87428d998e23a1aca24fd8aa2e)

Signed-off-by: Nick Xie <nick@khadas.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:05:56 +08:00
Nick Xie
a839828fa1 arm64: dts: rockchip: Add support for Khadas Edge
Add devicetree support for Khadas Edge.
Khadas Edge is an expandable Rockchip RK3399 board with goldfinger.

Specification
- Rockchip RK3399
- Dual-Channel 2GB/4GB LPDDR4
- Onboard 16GB/32GB/128GB eMMC
- RTL8211FD 1Gbps
- AP6356S/AP6398S WiFI/BT
- HDMI Out, DP
- USB 3.0, 2.0
- USB Type C power and data
- 16MB SPI Flash
- Programmable MCU

Commit details of rk3399-khadas-edge-*.dts sync from Linux 5.3-rc2:
"arm64: dts: rockchip: Add support for Khadas Edge/Edge-V/Captain boards"
(sha1: c2aacceedc86af87428d998e23a1aca24fd8aa2e)

Signed-off-by: Nick Xie <nick@khadas.com>
Tested-by: Chris Webb <chris@arachsys.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:05:29 +08:00
Matwey V. Kornilov
16593ccd07 rockchip: rk3328: enable DMA for MMCs at Rock64
DMA for MMCs can be enabled, since the previous patch fixes
the following issue in SPL:

    Trying to boot from MMC1
    spl: mmc init failed with error: -110
    SPL: failed to boot from all boot devices
    ### ERROR ### Please RESET the board ###

Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:05:16 +08:00
Kever Yang
a9775a82a5 rockchip: rk3328: set DDR as non-secure in SPL
Set DDR as non-secure so that MMC DMA can access.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[cherry picked from bfe741ab9e and 73d952acc8 with minor modifications]
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:05:02 +08:00
Stefan Roese
c7adc0b5f9 watchdog: bcm2835_wdt: Remove unused BCM283x watchdog driver and its references
The BCM2835/2836 watchdog is not used in mainline U-Boot at all. This
patch removes the driver and its references (CONFIG_BCM2835_WDT)
completely.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Paolo Pisati <p.pisati@gmail.com>
2019-08-05 11:50:06 +02:00
Tom Rini
bbaf56eda0 - sync Amlogic G12A DT with linux 5.3-rc1
- add support for 4GiB DRAM memory
 - add support for Amlogic G12B based Odroid-N2
 - small duplicate logic fix for gxbb clock driver
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Merge tag 'u-boot-amlogic-20190731' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- sync Amlogic G12A DT with linux 5.3-rc1
- add support for 4GiB DRAM memory
- add support for Amlogic G12B based Odroid-N2
- small duplicate logic fix for gxbb clock driver
2019-07-31 16:06:24 -04:00
Adam Ford
2fd156b307 ARM: dts: da850-evm: Fix MDIO pinmux
In attempts to speed up SPL and reduce size, the MDIO pin muxing
was inadvertently affected.  Since the ethernet driver will setup
the pin muxing when ethernet is loaded, this patch will also
pinmux the MDIO pins at the same time.  Once an DM compatible
MDIO driver is available, this  can be removed.

Fixes: 877ab2423b ("ARM: davinci: da850: Manual pinmux only
when PINCTRL not available")

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-07-31 13:08:07 -04:00
Suman Anna
dcddf0fd83 arm: dts: k3-am654-base-board: Fix cpsw_nuss power-domains property
The commit 355be915ed ("arm: dts: k3-am654: Update power-domains
property for each node") has updated the power-domain cells value
and updated power-domains property in various existing dts nodes but
missed updating the cpsw_nuss node. This results in the following
build warning, fix this.

arch/arm/dts/k3-am654-base-board.dtb: Warning (power_domains_property): /interconnect@100000/interconnect@28380000/cpsw_nuss@046000000:power-domains: property size (8) too small for cell size 2
arch/arm/dts/k3-am654-r5-base-board.dtb: Warning (power_domains_property): /interconnect@100000/interconnect@28380000/cpsw_nuss@046000000:power-domains: property size (8) too small for cell size 2

Fixes: 355be915ed ("arm: dts: k3-am654: Update power-domains property for each node")
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-31 13:08:07 -04:00
Sam Protsenko
4347b0b0b2 omap: Correct the fastboot product var
"fastboot flashall" expects "fastboot getvar product" value to be one of
values provided in android-info.txt file (in AOSP), from "require
board=" list. Before this patch, "am57xx" is returned for all AM57xx
based boards, as it's set in $board env var from SYS_BOARD in
board/ti/am57xx/Kconfig file, which is used for default implementation
of "fastboot getvar product".

In order to fix that inconsistency, let's do next:
  1. In U-Boot: override fastboot.product, reusing the value from
     $board_name
  2. In AOSP: provide values for all AM57xx boards we can use to
     device/ti/beagle_x15/board-info.txt file

This way requirements check in "fastboot flashall" will work as
expected, verifying that user tries to flash images to the board which
those images were built for.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Acked-by: Andrew F. Davis <afd@ti.com>
2019-07-31 13:08:07 -04:00
Neil Armstrong
5e5db096a3 ARM: meson-g12a: Handle 4GiB DRAM size
When configured with 4GiB DRAM size, only 3.8GiB is available, the
I/O beeing mapped in the last 256MiB of the first 4GiB physical memory/

First fixup the mm_region to handle the first 3.8GiB as memory and the
last 256MiB as I/O.

Then limit the real memory reported by the firmware to the available
physical space, 3.8GiB aligned with the mm_region memory zone size.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
2019-07-31 12:10:54 +02:00
Neil Armstrong
0d84acb00a ARM: dts: add support for Odroid-N2
Import HardKernel Odroid-N2 DT from Linux 5.3-rc1, commit 5f9e832c1370
("Linus 5.3-rc1") based on an Amlogic G12B S922X SoC.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
2019-07-31 12:10:50 +02:00
Neil Armstrong
d93757f2f6 ARM: dts: Sync Amlogic G12A with Linux 5.3-rc1
Sync the Amlogic Meson G12A DT and Bindings file with the Linux 5.3-rc1
from the commit 5f9e832c1370 ("Linus 5.3-rc1").

Also remove the meson-g12a-u-boot.dtsi and meson-g12a-u200-u-boot.dtsi,
now conflicting with the main DT content.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
2019-07-31 12:10:42 +02:00
Tom Rini
476a3143d7 Xilinx/FPGA changes for v2019.10
fpga:
 - Xilinx virtex2 cleanup
 - Altera cyclon2 cleanup
 
 zynq:
 - Minor Kconfig cleanup
 - Add psu_init configuration for Z-turn board
 
 zynqmp:
 - Add support for pmufw config passing to PMU
 - script for psu_init conversion
 - zcu1275 renaming
 
 xilinx:
 - Add support for UltraZed-EV SoM
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Merge tag 'xilinx-for-v2019.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx/FPGA changes for v2019.10

fpga:
- Xilinx virtex2 cleanup
- Altera cyclon2 cleanup

zynq:
- Minor Kconfig cleanup
- Add psu_init configuration for Z-turn board

zynqmp:
- Add support for pmufw config passing to PMU
- script for psu_init conversion
- zcu1275 renaming

xilinx:
- Add support for UltraZed-EV SoM
2019-07-30 19:19:34 -04:00
Tom Rini
dcf722ece6 Merge branch 'master' of git://git.denx.de/u-boot-sh 2019-07-30 19:19:04 -04:00
Luca Ceresoli
ac80ac09c8 arm64: zynqmp: add support for Avnet UltraZed-EV Starter Kit
Avnet UltraZed-EV Starter Kit is composed by the UltraZed-EV SoM and the
only publicly-available compatible carrier card. The SoM is based on the EV
version of the Xilinx ZynqMP SoC+FPGA.

The psu_init_gpl.c file has been generated from the board definition files
at [0] using Vivado 2018.3 and then minimized by
tools/zynqmp_psu_init_minimize.sh. Manually removed serdes init code since
it is not mentioned in device tree and fixed a checkpatch error.

[0] 3686c9ff7d/ultrazed_7ev_cc/1.1

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30 10:20:06 +02:00
Luca Ceresoli
c28a9cfa40 arm64: zynqmp: spl: install a PMU firmware config object at runtime
Optionally allow U-Boot to load a configuration object into the Power
Management Unit (PMU) firmware on Xilinx ZynqMP.

The configuration object is required by the PMU FW to enable most SoC
peripherals. So far the only way to boot using U-Boot SPL was to hard-code
the configuration object in the PMU firmware. Allow a different boot
process, where the PMU FW is equal for any ZynqMP chip and its
configuration is passed at runtime by U-Boot SPL.

All the code for Inter-processor communication with the PMU is isolated in
a new file (pmu_ipc.c). The code is inspired by the same feature as
implemented in the Xilinx First Stage Bootloader (FSBL) and Arm Trusted
Firmware:

 * fb647e6b4c/lib/sw_apps/zynqmp_fsbl/src/xfsbl_misc_drivers.c (L295)
 * c48d02bade/plat/xilinx/zynqmp/pm_service/pm_api_sys.c (L357)

SPL logs on the console before loading the configuration object:

  U-Boot SPL 2019.07-rc1-00511-gaec224515c87 (May 15 2019 - 08:43:41 +0200)
  Loading PMUFW cfg obj (2008 bytes)
  EL Level:	EL3
  ...

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30 10:20:06 +02:00
Michal Simek
420d446781 arm64: zynqmp: Rename zc1275 to zcu1275
Name of this platform has changed and released to customers that's why
name has also changed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Series-to: uboot
2019-07-30 10:20:06 +02:00
Tom Rini
333755ef7b Merge branch '2019-07-29-ti-imports'
- More DaVinci DM migration, drop am18xx EVM platform
- Keystone bug fix
2019-07-29 17:59:15 -04:00
Andrew F. Davis
c1c564af52 arm: mach-keystone: Use appended original image size in image processing
When an image is signed/encrypted on K2 devices the image may get padded
to meet alignment requirements for the signature/encryption type. The
original size is appended as 4 bytes little-endian to the end of the
final image.

Normally the trailing extra bytes are ignored and so restoring the
exact original size is not important. In the case of initrd the
original size is important as the kernel uses it to look for
additional filesystem data and can do the wrong thing when the
size is not correct.

Read off the original size and report it back from the image post
processing stage.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-29 17:58:52 -04:00
Bartosz Golaszewski
95cffd9906 davinci: da850-evm: enable driver model for NAND
Enable the driver-model on da850-evm. We need to add a dummy nand node
to the device tree, as the real nand node is a sub-node of the aemif
device.

On linux the aemif driver populates all its child nodes, but we can't do
it in u-boot currently.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Tested-by: Adam Ford <aford173@gmail.com> #da850-evm
2019-07-29 17:58:52 -04:00
Bartosz Golaszewski
f5a47554e0 davinci: omapl138-lcdk: enable driver model for NAND
Enable the driver-model on da850-lcdk. We need to add a dummy nand node
to the device tree, as the real nand node is a sub-node of the aemif
device.

On linux the aemif driver populates all its child nodes, but we can't do
it in u-boot currently.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-07-29 17:58:52 -04:00
Bartosz Golaszewski
7bf9972643 nand: davinci: make davinci_nand_init() static
This function is only used within the driver itself. No need
to export it.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-07-29 17:58:52 -04:00
Tom Rini
2d64a0f7e9 Merge branch '2019-07-29-master-imports'
- Assorted bug fixes
2019-07-29 11:51:17 -04:00
Fabien Parent
bb4c5d6055 board: mediatek: Add pumpkin board support
The pumpkin board is made by Gossamer Engineering and is using
a MediaTek SoC. The board currently comes in two available version:
MT8516 SoC and MT8167 SoC.
The board provides the following IOs: eMMC, NAND, SD card, USB type-A,
Ethernet, Wi-Fi, Bluetooth, Audio (jack out, 2 PDM port, 1 analog in),
serial over USB, and an expansion header.

Additionally there is a HDMI port, DSI port, and camera port only
on the MT8167 version of the board.

The board can be powered by battery and/or via a USB Type-C port and
is using a PMIC MT6392.

The eMMC and NAND are sharing pins and cannot be used together.

This commit is adding the basic boot support for the Pumpkin MT8516
board on the eMMC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
2019-07-29 09:32:11 -04:00
Keerthy
5917d0b877 doc: arch: sandbox: Replace all the instances of README.sandbox
commit 49116e6d23 ("doc: arch: Convert README.sandbox to reST")
Moves README.sandbox to doc/arch.
Replace all the existing instances to point to the right documentation
file.

Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-07-29 09:32:09 -04:00
Tom Rini
92430b8fc8 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-socfpga
- Various gen5 fixes
2019-07-29 09:03:11 -04:00
Tom Rini
ad4a699cfe - dcu and imx7 DM_VIDEO conversion
- lb070wv8 compatible in simple_panel driver
 - bmp_logo improvements for DM_VIDEO
 - EDID updates to filter supported modes
 - meson_dw_hdmi: support EDID mode filtering
 - dw_hdmi: support ddc-i2c-bus phandle for external I2C masters
 - fix rpi crash when firmware doesn't report connected display
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Merge tag 'video-for-2019.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-video

- dcu and imx7 DM_VIDEO conversion
- lb070wv8 compatible in simple_panel driver
- bmp_logo improvements for DM_VIDEO
- EDID updates to filter supported modes
- meson_dw_hdmi: support EDID mode filtering
- dw_hdmi: support ddc-i2c-bus phandle for external I2C masters
- fix rpi crash when firmware doesn't report connected display
2019-07-29 09:02:46 -04:00
Tom Rini
c957be9ba0 Merge tag 'u-boot-rockchip-20190729' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Clean up and migrate to use common rockchip spl board file
- Clean up and migrate to use common rockchip board file
- Increase rk3288 CONFIG_SYS_BOOTM_LEN to 16MB
2019-07-29 09:02:15 -04:00
Kever Yang
26008cd42b rockchip: rv1108: Migrate to use common board file
Use common board file for board_init() and board_late_init(),
for Rockchip SoCs have very similar process.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:27:48 +08:00
Kever Yang
920b01388e rockchip: rk3399: Migrate to use common board file
Use common board file for board_init() and board_late_init(),
for Rockchip SoCs have very similar process.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:27:48 +08:00
Kever Yang
edaf8db866 rockchip: rk3368: Migrate to use common board file
Use common board file for board_init() and board_late_init(),
for Rockchip SoCs have very similar process.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:27:48 +08:00
Kever Yang
38ed26777f rockchip: rk3328: Migrate to use common board file
Use common board file for board_init() and board_late_init(),
for Rockchip SoCs have very similar process.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
2019-07-29 10:27:48 +08:00
Kever Yang
de57a9fd4a rockchip: rk3288: Migrate to use common board file
Use common board file for board_init() and board_late_init(),
for Rockchip SoCs have very similar process.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:27:48 +08:00
Kever Yang
271318a660 rockchip: rk3288: Move rk3288_detect_reset_reason to soc file
The rk3288_detect_reset_reason() is per-SoC operation, move
it to rk3288.c, and extend the rk_board_late_init() with
rk3288_board_late_init() to make all the board works fine
as before.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:27:45 +08:00
Kever Yang
88a87bcbb3 rockchip: rk3288: Move clock CMD to SoC file
Move the do_clock CMD to rk3288.c so that we can re-use
the common board file later.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:27:11 +08:00
Kever Yang
b678f2790c rockchip: rk3288: Move veyron_init() back to veyron.c
The veyron_init() should go to its board file veyron.c,
and the board_early_init_f() could be the right place.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:26:41 +08:00
Kever Yang
0221910042 rockchip: rk3288: move board_early_init_f() back to veyron
The board_early_init_f() is only used by veyron board now,
move it into the board file veyron.c

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:26:41 +08:00
Kever Yang
1e7d2be011 rockchip: rk3288: move SOC setting into arch_cpu_init()
Qos setting and emmc relate SoC setting should go to arch_cpu_init().

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:26:41 +08:00
Kever Yang
a97b65a7a0 rockchip: rk3188: Migrate to use common board file
Use common board file for board_init() and board_late_init(),
for Rockchip SoCs have very similar process.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:26:41 +08:00
Kever Yang
c14fe2a8e1 rockchip: rk3188: Move SoC one time setting into arch_cpu_init()
The setting for noc remap should goto arch_cpu_init().

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:26:41 +08:00
Kever Yang
cca3b09147 rockchip: rk322x: Migrate to use common board file
Use common board file for board_init() and board_late_init(),
for Rockchip SoCs have very similar process.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:26:41 +08:00
Kever Yang
55cdcebc99 rockchip: rk322x: move SoC setting into arch_cpu_init()
The SoC one time setting should go to arch_cpu_init() in
rk322x.c

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:26:41 +08:00
Kever Yang
7e719d94a5 rockchip: rk3128: Migrate to use common board file
Use common board file for board_init() and board_late_init(),
for Rockchip SoCs have very similar process.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:26:41 +08:00
Kever Yang
c0c2a2e4a5 rockchip: rk3036: Migrate to use common board file
Use common board file for board_init() and board_late_init(),
for Rockchip SoCs have very similar process.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:26:41 +08:00
Kever Yang
7559f6e9f0 rockchip: rk3036: move dram_init() into soc file
Move dram_init() into rk3036.c so that we can use to common board
file later.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:26:41 +08:00
Kever Yang
5eb9a78fcd rockchip: sdram_common: add common dram_init_banksize
dram_init_banksize() can be common used by all SoCs, move it into
sdram_common.c

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:26:28 +08:00
Kever Yang
54f17fa05d rockchip: add common board file for U-Boot proper
Add common board file for Rockchip SoCs to avoid too much
copy-paste work for different SoCs.
This board file in charge for common board_init() and board_late_init()
in U-Boot proper.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
6c9a9df9f5 rockchip: clean up board_usb_init() for all SoCs
Use "snps,dwc2" for compatible name and and common variable
names so that we can share the common code for all SoCs.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
283e61a661 rockchip: convert to use ROCKCHIP_BOOT_MODE_REG for fastboot tag
The fastboot_set_reboot_flag() update a TAG into a register
for next boot, use the common macro for the register so that
we can re-use the function for different SoCs.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
604814c8dc rockchip: rk3328: add board_debug_uart_init()
Add board_debug_uart_init() to make the debug UART work with
correct setting.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
b7abef2ecb rockchip: rk3399: Migrate to use common spl board file
rk3399 has similar boot flow in SPL with other Rockchip SoCs,
migrate to use common spl board file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
faa98c7c5a rockchip: rk3399: move chromebook bob specific flow to its board file
Add a board_early_init_f() in board_init_f() and move the board
specific init code into its own board file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
4e1aeb89af rockchip: rk3399: move boot_devices into soc file
Move boot_devices definition into rk3399.c, so that we can
share the common code for board_spl_was_booted_from().

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
47b0ead21a rockchip: rk3399; move spl_board_init() into soc file
Move spl_board_init() into rk3399.c so that we can re-use the
common SPL board file later.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
bd06a7c88e rockchip: rk3399: move SoC setting into arch_cpu_init()
SoC setting like DDR secure region and EMMC clock setting
should go to arch_cpu_init().

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
08f7905bc6 rockchip: rk3399: show SPL BANNER earlier in board_init_f()
Show the SPL BANNER earlier so that we know already get into SPL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
4238e526fa rockchip: rk3399: move spl_perform_fixups() into soc file
Move the spl_perform_fixups() into rk3399.c so that we can
use common spl board file later.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
4a395788c4 rockchip: rk3368: add boot_devices mapping to support 'same-as-spl'
The driver need a mapping to get the dts node by boot srouce ID.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
30d7109757 rockchip: rk3368: migrate to use common spl board file
rk3368 has similar boot flow in SPL with other Rockchip SoCs,
migrate to use common spl board file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
612fd9e5e0 rockchip: rk3328: add boot_devices mapping to support 'same-as-spl'
The driver need a mapping to get the dts node by boot srouce ID.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
9cc67049c2 rockchip: rk3328: migrate to use common spl board file
rk3328 has similar boot flow in SPL with other Rockchip SoCs,
migrate to use common spl board file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
8af6cafc89 rockchip: rk3288: add boot_devices mapping to support 'same-as-spl'
The driver need a mapping to get the dts node by boot srouce ID.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
68907a0a58 rockchip: rk3288-veyron: Migrate "u-boot, boot0" to "u-boot, spl-boot-order"
"u-boot,spl-boot-order" is more flexible and other rockchip SoCs
has convert to use it, migrate to use the new dts property.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
65ea919bf7 rockchip: phycore: remove no use "u-boot, boot0" in dts
We are using "u-boot,spl-boot-order" now and re-use the
definition from rk3288-u-boot.dtsi, so remove it directly here.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
60b13c8b4a rockchip: rk3288: Migrate to use common spl board file
rk3288 has similar boot flow in SPL with other Rockchip SoCs,
migrate to use common spl board file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
f35c417c9b rockchip: rk3288: move dram_init_banksize() into soc file
Mov edram_init_banksize() into rk3288.c so that we can re-use
the common SPL board file later.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
8f5b5aac76 rockchip: rk3288-phycore: move phycore_init() to its own board file
phycore_init() is use for phycore board only, it should be move back
to phycore-rk3288.c

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
57d55db603 rockchip: rk3288: move setup_led() to firefly-rk3288
Only firefly-rk3288 has the dts node "u-boot,boot-led",
while CONFIG_SPL_LED is not enable, move code to firefly-rk3288
now in case someone need this code.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
4f0b061444 rockchip: rk3288: show SPL BANNER earlier in board_init_f()
Show the SPL BANNER earlier so that we know already get into SPL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
66a503c700 rockchip: fit_spl_optee: rockchip: fix warning unit_address_vs_reg
Update to fix warning:
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/uboot@1
has a unit name, but no reg property
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/optee@1
has a unit name, but no reg property
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/fdt@1
has a unit name, but no reg property
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /configurations/conf@1
has a unit name, but no reg property

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
a49660b658 rockchip: rk322x: add boot_devices mapping to support 'same-as-spl'
The driver need a mapping to get the dts node by boot srouce ID.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
0cd65e4b9a rockchip: rk322x: migrate to use common spl board file
rk322x has similar boot flow in SPL with other Rockchip SoCs,
migrate to use common spl board file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
7dc79f8af0 rockchip: rk322x: introduce arch_cpu_init() for SoC setting init
Use arch_cpu_init() to init SoC secure region and move it to
rk322x.c

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
4eb506322e rockchip: rk3188: migrate to use common spl board file
rk3188 has similar boot flow in SPL with other Rockchip SoCs,
migrate to use common spl board file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
3b3c623e61 rockchip: rk3188: add boot_devices mapping to support 'same-as-spl'
The driver need a mapping to get the dts node by boot srouce ID.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
9323ffafc9 rockchip: rk3188: move spl_board_init() into rk3188.c
Clean up the rk3188.c so that we can re-use the common spl board file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
bf1133b1e9 rockchip: Migrate to use BOOTROM_SUPPORT driver
SPL bootrom support is a boot device just like mmc and etc,
use formal boot device instead of jump to bootrom directly.
Enable the Kconfig by default if ROCKCHIP_BACK_TO_BROM is enabled.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
4dd4fc32db rockchip: rk3188: move usb uart init into arch_cpu_init()
The SoC feature init will be better to use arch_cpu_init() and
goes to soc file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
84a6a27ae3 rockchip: rk3188: init CPU freq in clock driver
Init CPU frquency in clock driver instead of in SPL board file,
this will help for use common board file later.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
49105fb7ed rockchip: add common spl board file
The common spl board file handles board_init_f() in SPL,
and with board_early_init_f() and arch_cpu_init() callback,
other operateion after board_init_f() should go to board specific
spl_board_init().

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Igor Opaniuk
1c7bade847 ARM: dts: colibri-imx6ull: extend lcdif node
Provide proper display timings for lcdif node, used by mxsfb DM_VIDEO
enabled framebuffer driver.

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-07-29 00:12:02 +02:00
Igor Opaniuk
9de5eb23dc colibri-imx6ull: support building with DM_VIDEO=y
1. This fixes linking issues when building with DM_VIDEO enabled mxsfb
driver.
2. Provide proper defines for both VIDEO=y and DM_VIDEO=y.

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-07-29 00:11:54 +02:00
Igor Opaniuk
34b773d507 ARM: dts: colibri_imx7: Fix lcdif node definition
Fix lcdif DT node and make it conform to the structure defined in the
Linux devicetree bindings [1]. Currently there is support only for
old style lcdif node definitions.

[1] https://www.kernel.org/doc/Documentation/devicetree/bindings/display/mxsfb.txt

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-07-29 00:11:29 +02:00
Igor Opaniuk
750c68a7a7 ARM: dts: colibri_vf: Add dcu0 node
Add dumb node for NXP Display Control Unit0(DCU), which permits DM_ENABLED
converted driver to be probed. Currently no display timings are provided
in this node.

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-07-29 00:09:19 +02:00
Tom Rini
75551c8bfc Merge branch '2019-07-26-ti-imports'
- Bring in the rest of the J271E platform
- Various OMAP3/AM3517, DA850 fixes
2019-07-27 19:50:52 -04:00
Adam Ford
f3996aef8c ARM: dts: Logic PD SOM-LV and Torpedo Boards: Resync DTS
Re-sync all Logic PD OMAP35 and AM/DM37 boards with Kernel
5.2.1

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-07-27 13:36:53 -04:00
Tom Rini
df9a7a195b u-boot-imx-20190719
- CCF for i.MX6
 - nandbcb command to write SPL into NAND
 - Switch to DM (i.MX28)
 - Boards: Toradex, engicam, DH
 - Fixes for i.MX8
 - Fixes for i.MX7ULP
 
 Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/561147504
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Merge tag 'u-boot-imx-20190719' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20190719

- CCF for i.MX6
- nandbcb command to write SPL into NAND
- Switch to DM (i.MX28)
- Boards: Toradex, engicam, DH
- Fixes for i.MX8
- Fixes for i.MX7ULP

Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/561147504
2019-07-27 09:35:05 -04:00
Adam Ford
9eed1ca15b ARM: am3517-evm: Migrate to SPL_OF_CONTROL
Like the other Logic PD OMAP35/DM37 boards, this board has device
tree enabled for U-Boot.  This patch converts the board to enable
SPL_OF_CONTROL and further shrinks the device tree in SPL to limit
it to UART3 (console), MMC1, i2c1, and GPIO4 (for mmc1 CD and WP).

There appears to be a bug in minicom so users may need to
switch the minicom terminal emulation to ANSI from VT102 due
to the junk that gets pushed out of the UART on startup.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-07-26 22:24:12 -04:00
Faiz Abbas
637fc2c991 ARM: dts: dra76x: Update MMC2_HS200_MANUAL1 iodelay values
Update the MMC2_HS200_MANUAL1 iodelay values to match with the latest
dra76x data manual[1].

Also this particular pinctrl-array is using spaces instead of tabs for
spacing between the values and the comments. Fix this as well.

[1] http://www.ti.com/lit/ds/symlink/dra76p.pdf

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-07-26 22:24:11 -04:00
Faiz Abbas
6b66d2ee47 ARM: dts: am57xx: Disable voltage switching for SD card
If UHS speed modes are enabled, a compatible SD card switches down to 1.8V
during enumeration. If after this a software reboot/crash takes place and
on-chip ROM tries to enumerate the SD card, the difference in
IO voltages (host @ 3.3V and card @ 1.8V) may end up damaging the card.

The fix for this is to have support for power cycling the card in
hardware (with a PORz/soft-reset line causing a power cycle of the card).
Because the beaglebone X15 (rev A,B and C), am57xx-evms and am57xx-idks don't
have this capability, disable voltage switching for these boards.

The major effect of this is that the maximum supported speed mode is now
high speed(50 MHz) down from SDR104(200 MHz).

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-07-26 22:24:11 -04:00
Faiz Abbas
684af0be94 ARM: dts: am574x-idk: Add pinmuxes for mmc1 and mmc2
Sync with kernel dts by adding pinmuxes for mmc1 and mmc2. This fixes an
issue where mmc2 (eMMC) was coming up in HS52 mode instead of the
highest DDR52 mode.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-07-26 22:24:10 -04:00
Faiz Abbas
461918d7df ARM: dts: dra7-mmc-iodelay: Add a new pinctrl group for clk line without pullup
During a short period when the bus voltage is switched from 3.3v to 1.8v,
(to enumerate UHS mode), the mmc module is disabled and the mmc IO lines
are kept in a state according to the programmed pad mux pull type.

According to 4.2.4.2 Timing to Switch Signal Voltage in "SD Specifications
Part 1 Physical Layer Specification Version 5.00 February 22, 2016", the
host should hold CLK low for at least 5ms.

In order to keep the card line low during voltage switch, the pad mux of
mmc1_clk line should be configured to pull down.

Add a new pinctrl group for clock line without pullup to be used in boards
where mmc1_clk line is not connected to an external pullup.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-07-26 22:24:10 -04:00
Lokesh Vutla
aebb2a499e arm: dts: k3-j721e: Add r5 specific dt support
Add initial support for dt that runs on r5.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2019-07-26 21:49:29 -04:00
Lokesh Vutla
9a5e553cb4 arm: dts: k3-j721e: Add initial support for common processor board
Common Processor board is the baseboard that has most of the actual connectors,
power supply etc. A SOM (System on Module) is plugged on to the common
processor board and this contains the SoC, PMIC, DDR and basic highspeed
components necessary for functionality. Add initial dt support for this
common processor board.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:29 -04:00
Lokesh Vutla
eeb2e8b6eb arm: dts: ti: Add Support for J721E SoC
Add initial SoC definition for J721E SoC.
Kernel dts posted here:
https://lore.kernel.org/lkml/20190522161921.20750-1-nm@ti.com/

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:28 -04:00
Lokesh Vutla
f81850322a board: ti: j721e: Add board support for j721e evm
Add board specific initialization for j721e evm

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2019-07-26 21:49:27 -04:00
Suman Anna
5bc22e3277 armv8: K3: j721e: Add custom MMU support
The A72 U-Boot code loads and boots a number of remote processors
including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various
Main R5FSS Cores. Change the memory attributes for the DDR regions used
by the remote processors so that the cores can see and execute the
proper code.

A separate table based on the current AM65x table is added for J721E SoCs,
since the number of remote processors and their DDR usage will be different
between the two SoC families.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:27 -04:00
Andreas Dannenberg
9d1303b38b armv7R: K3: j721e: Load SYSFW binary and config from boot media
Use the System Firmware (SYSFW) loader framework to load and start
the SYSFW as part of the J721E early initialization sequence. While
at it also initialize the MCU_UART0 pinmux as it is used by SYSFW
to print diagnostic messages.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:27 -04:00
Lokesh Vutla
9c0ff866b3 armv7R: K3: j721e: Shut down R5 core after ATF startup on A72
Populate the release_resources_for_core_shutdown() api with
shutting down r5 cores so that it will by called just after
jumping to ATF.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:26 -04:00
Andreas Dannenberg
f94a07c8a1 armv7R: K3: j721e: Store boot index from ROM
Obtain the boot index as left behind by the device boot ROM and store
it in scratch pad SRAM for later use before it may get overwritten.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2019-07-26 21:49:26 -04:00
Andreas Dannenberg
b73fcbced9 armv7R: K3: j721e: Unlock all applicable control MMR registers
To access various control MMR functionality the registers need to
be unlocked. Do that for all control MMR regions in the MCU and MAIN
domains. We may want to go back later and limit the unlocking that's
being done.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2019-07-26 21:49:26 -04:00
Lokesh Vutla
0a704924f3 armv7R: K3: j721e: Add support for boot device detection
J721E allows for booting from primary or backup boot media.
Both media can be chosen individually based on switch settings.
ROM looks for a valid image in primary boot media, if not found
then looks in backup boot media. In order to pass this boot media
information to boot loader, ROM stores a value at a particular
address. Add support for reading this information and determining
the boot media correctly.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-07-26 21:49:26 -04:00
Lokesh Vutla
c2562d7c9e arm: K3: j721e: Add basic support for J721E SoC definition
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.

Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
  capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
  C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
  and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
  PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
  up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
  addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
  capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
  16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
  I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
  management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
  capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
  Management (DMSC)

See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1

Add base support for J721E SoC

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2019-07-26 21:49:25 -04:00
Lokesh Vutla
355be915ed arm: dts: k3-am654: Update power-domains property for each node
Update the power-domain-cells to 2 and add the permissions
to each node. Mark the following nodes accessed by r5 as shared:
- DDR node
- main uart 0

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:23 -04:00
Lokesh Vutla
c0669d28ee armv7R: k3: Release all the exclusive devices
Release all the exclusive devices held by SPL.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:22 -04:00
Andreas Dannenberg
f9380a730d armv7R: K3: am654: Shut down R5 core after ATF startup on A53
Rather than simply parking the R5 core in WFE after starting up ATF
on A53 instead use SYSFW API to properly shut down the R5 CPU cores
as well as associated timer resources that were pre-allocated. This
allows software further downstream to properly and gracefully bring
the R5 cores back online if desired.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:22 -04:00
Kever Yang
bfcf15aad2 rockchip: declear boot_devices in bootrom.h
boot_devices may defined in soc file, and used in board file,
we need to delear it in header file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-26 17:30:26 +08:00
Kever Yang
cd59501f21 rockchip: intruduce common BROM_BOOTSOURCE_ID_ADDR
The boot source from BootRom is store at a fix offset of IRAM,
update to use the common macro instead of rk3399 specific one.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-26 17:30:26 +08:00
Bartosz Golaszewski
e809285d49 net: davinci_emac: convert to using the driver model
Now that we removed all legacy boards selecting TI_EMAC we can
completely convert the driver code to using the driver model.
This patch also updates all remaining users of davinci_emac.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Tested-by: Adam Ford <aford173@gmail.com> #am3517-evm & da850-evm
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2019-07-25 13:36:13 -05:00
Jianchao Wang
8782122052 Add support for the NXP LS1021A-TSN board
The LS1021A-TSN is a development board built by VVDN/Argonboards in
partnership with NXP.

It features the LS1021A SoC and the first-generation SJA1105T Ethernet
switch for prototyping implementations of a subset of IEEE 802.1 TSN
standards.

Supported boot media: microSD card (via SPL), QSPI flash.

Rev. A of the board uses a Spansion S25FL512S_256K serial flash, which
is 64 MB in size and has an erase sector size of 256KB (therefore,
flashing the RCW would erase part of U-Boot).

Rev. B and C of the board use a Spansion S25FL256S1 serial flash, which
is only 32 MB in size but has an erase sector size of 64KB (therefore
the RCW image can be flashed without erasing U-Boot).

To avoid the problems above, the U-Boot base address has been selected
at 0x100000 (the start of the 5th 256KB erase sector), which works for
all board revisions. Actually 0x40000 would have been enough, but
0x100000 is common for all Layerscape devices.

eTSEC3 is connecting directly to SJA1105 via an RGMII fixed-link, but
SJA1105 is currently not supported by uboot. Therefore, eTSEC3 is
disabled.

Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Jianchao Wang <jianchao.wang@nxp.com>
Signed-off-by: Changming Huang <jerry.huang@nxp.com>
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>

[Vladimir] Code taken from https://github.com/openil/u-boot (which
itself is mostly copied from ls1021a-iot) and adapted with the following
changes:

- Add a008850 errata workaround
- Converted eTSEC, MMC to DM to avoid all build warnings
- Plugged in distro boot feature, including support for extlinux.conf
- Added defconfig for QSPI boot
- Added the board/freescale/ls1021atsn/README.rst for initial setup
- Increased CONFIG_SYS_MONITOR_LEN so that the SPL malloc pool does not
  get overwritten during copying of the u-boot.bin payload from MMC to
  DDR.
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-25 13:13:31 -05:00
Bin Meng
f588b4d205 arm: ls1021atwr: Convert to use driver model TSEC driver
Now that we have added driver model support to the TSEC driver,
convert ls1021atwr board to use it.

This depends on previous DM series for ls1021atwr:
http://patchwork.ozlabs.org/patch/561855/

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

[Vladimir] Made the following changes:
- Added 'status = "disabled";' for all Ethernet ports in ls1021a.dtsi
- Fixed the confusion between the SGMII/TBI PCS for enet0 and enet1 -
  a mistake ported over from Linux. Each SGMII PCS lies on the private
  MDIO bus of the interface (and the RGMII enet2 has no SGMII PCS).
- Added CONFIG_DM_ETH to all ls1021atwr_* defconfigs
- Completely removed non-DM_ETH support from ls1021atwr
- Changed "compatible" string from "fsl,tsec-mdio" to "fsl,etsec2-mdio"
  and from "fsl,tsec" to "fsl,etsec2" to match Linux
2019-07-25 13:13:31 -05:00
Alex Marginean
b32e9a7578 arm: dts: ls1028a updates for network interfaces
Defines LS1028A RDB SGMII port, QDS RGMII port.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25 13:13:30 -05:00
Patrick Delaunay
e21e3ffdd1 psci: Fix warnings when compiling with W=1
This patch solves the following warnings:
arch/arm/mach-stm32mp/psci.c:

warning: no previous prototype for ‘psci_set_state’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_arch_cpu_entry’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_features’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_version’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_affinity_info’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_migrate_info_type’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_cpu_on’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_cpu_off’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_system_reset’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_system_off’ [-Wmissing-prototypes]

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-24 14:15:38 -04:00
Tom Rini
fe4243870d Pull request for UEFI sub-system for v2019.10-rc1 (2)
* Implement the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event.
 * Address errors of type -Werror=address-of-packed-member when building
   with GCC9.1
 * Fix an error when adding memory add addres 0x00000000.
 * Rework some code comments for Sphinx compliance.
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Merge tag 'efi-2019-10-rc1-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

Pull request for UEFI sub-system for v2019.10-rc1 (2)

* Implement the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event.
* Address errors of type -Werror=address-of-packed-member when building
  with GCC9.1
* Fix an error when adding memory add addres 0x00000000.
* Rework some code comments for Sphinx compliance.
2019-07-23 22:29:53 -04:00
Tom Rini
ff8c23e784 - add rtc driver for stm32mp1
- add remoteproc driver for stm32mp1
 - use kernel qspi compatible string for stm32
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Merge tag 'u-boot-stm32-20190723' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- add rtc driver for stm32mp1
- add remoteproc driver for stm32mp1
- use kernel qspi compatible string for stm32
2019-07-23 14:16:21 -04:00
Tom Rini
9565bd7c6f Merge tag 'rockchip-for-v2019.07-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- rk3399 sdhci driver fixup
- TPL BANNER fixup
2019-07-23 09:48:16 -04:00
Eugeniu Rosca
89c00f009c ARM: dts: rmobile: Synchronize Gen3 DTs with Linux 5.2
Backport and squash below Linux 5.2 commits for R-Car Gen3:

Commit id       * Summary line
6fffb98645e67b5   arm64: dts: renesas: r8a77990: ebisu: Add GPIO expander
b068ed6efe6244d   arm64: dts: renesas: r8a77990: Fix SPDX license identifier style
96c25882252704d ! arm64: dts: renesas: r8a7796: remove unneeded sound #address/size-cells
71ac75dffdae2f8   arm64: dts: renesas: r8a77990: ebisu: Enable LVDS1 encoder
9a0ff5c727b60a3   arm64: dts: renesas: r8a77995: draak: Enable LVDS1 encoder
9130c15829846fa   arm64: dts: renesas: ebisu: Fix adv7482 hexadecimal register address
191f7dcd1f5ea1f   arm64: dts: renesas: r8a77965: add SSIU support for sound
a8f6110e64422d5   arm64: dts: renesas: ebisu: Enable VIN5
4162aa9db3d4469   arm64: dts: renesas: r8a77995: draak: Enable CAN0, CAN1
af965ba3248edde   arm64: dts: renesas: r8a77990: Remove invalid compatible value for CSI40
1f4c123a98098cc   arm64: dts: renesas: r8a77990-ebisu: Add BD9571 PMIC
474706117c2baa6   arm64: dts: renesas: ebisu: Add PMIC DDR0 Backup Power config
e2fa79de7ecbef4   arm64: dts: renesas: Update Ebisu and Draak bootargs
de8e8daaf7190ef   arm64: dts: renesas: salvator-common: Sort node label
05f1d882d28b871   arm64: dts: renesas: r8a77995: draak: Fix EthernetAVB phy mode to rgmii
7a516e49d975311   arm64: dts: renesas: use extended audio dmac register
e3414b8c45afa5c   arm64: dts: renesas: salvator-common: Add GPIO keys support
720066d17c973fd   arm64: dts: renesas: r8a7795: Add CMT device nodes
99cb95103e2d058   arm64: dts: renesas: r8a77965: Add CMT device nodes
28a5c61b5136d58   arm64: dts: renesas: r8a77990: Add CMT device nodes
32d622f3290b2a1   arm64: dts: renesas: r8a77965: Remove reg-names of display node

(*) Patch id mismatch between Linux and U-Boot commit.
[!] Dropped changes in arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts,
    since the file doesn't exist in the U-Boot tree.

Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-07-23 13:38:23 +02:00
Marek Vasut
b3db7be4e3 ARM: renesas: Update Gen3 PCIe dma-ranges before boot
Update "dma-ranges" DT property of all PCIe controllers in the system
with the up-to-date DRAM layout. This allows the PCIe controller take
full advantage of all the available DRAM.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-07-23 13:38:17 +02:00