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board/BuR/brsmarc1: initial commit

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This commit adds support for the B&R brsmarc1 SoM.

The SoM is based on TI's AM335x SoC.
Mainly vxWorks 6.9.4.x is running on the board,
doing some PLC stuff on various carrier boards.

Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
This commit is contained in:
Hannes Schmelzer 2019-08-01 07:04:46 +02:00 committed by Tom Rini
parent 6912f2a8ae
commit 60df809f62
12 changed files with 1112 additions and 0 deletions
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1
arch/arm/dts/Makefile
View file

@ -281,6 +281,7 @@ dtb-$(CONFIG_AM33XX) += \
am335x-brppt1-nand.dtb \
am335x-brppt1-spi.dtb \
am335x-brxre1.dtb \
am335x-brsmarc1.dtb \
am335x-draco.dtb \
am335x-evm.dtb \
am335x-evmsk.dtb \

416
arch/arm/dts/am335x-brsmarc1.dts Normal file
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@ -0,0 +1,416 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 B&R Industrial Automation GmbH
* http://www.br-automation.com
*
*/
/dts-v1/;
#include "am33xx.dtsi"
#include "dt-bindings/thermal/thermal.h"
/ {
model = "BRSMARC1 SoM";
compatible = "ti,am33xx";
fset: factory-settings {
bl-version = " ";
order-no = " ";
cpu-order-no = " ";
hw-revision = " ";
serial-no = <0>;
device-id = <0x0>;
parent-id = <0x0>;
hw-variant = <0x0>;
hw-platform = <0x7>;
fram-offset = <0x100>;
fram-size = <0x1F00>;
cache-disable = <0x0>;
cpu-clock = <0x0>;
};
chosen {
bootargs = "console=ttyO0,115200 earlyprintk";
stdout-path = &uart0;
};
aliases {
fset = &fset;
mmc = &mmc2;
spi0 = &spi0;
spi1 = &spi1;
touch0 = &burtouch0;
screen0 = &lcdscreen0;
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
vmmcsd_fixed: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
lcdscreen0: lcdscreen@0 {
/*backlight = <&tps_bl>; */
compatible = "ti,tilcdc,panel";
status = "okay";
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <32>;
fdd = <0x80>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
rotation = <0>;
pupdelay = <0>;
pondelay = <0>;
pwrpin = <0x000000B1>;
brightdrv = <0>;
brightfdim = <100>;
brightdef = <50>;
};
display-timings {
default {
clock-frequency = <0>;
hactive = <0>;
vactive = <0>;
hfront-porch = <0>;
hback-porch = <0>;
hsync-len = <0>;
vfront-porch = <0>;
vback-porch = <0>;
vsync-len = <0>;
hsync-active = <0>;
vsync-active = <0>;
pupdelay = <10>;
pondelay = <10>;
};
};
};
board_thermal: board-thermal {
polling-delay-passive = <1000>; /* milliseconds */
polling-delay = <2500>; /* milliseconds */
thermal-sensors = <&cputemp>;
trips {
crit_trip: crit-trip {
temperature = <95000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&crit_trip>;
cooling-device =
<&resetc THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
&uart0 { /* console uart */
u-boot,dm-spl;
status = "okay";
};
&uart2 { /* X2X - P2P */
status = "okay";
};
&uart3 { /* RS485 */
status = "okay";
};
&uart4 { /* RS232 */
status = "okay";
};
&i2c0 {
u-boot,dm-spl;
status = "okay";
clock-frequency = <100000>;
tps: tps@24 { /* PMIC controller */
u-boot,dm-spl;
reg = <0x24>;
compatible = "ti,tps65217";
};
cputemp: temperature-sensor@48 { /* cpu temperature */
#thermal-sensor-cells = <0>;
compatible = "nxp,pct2075";
reg = <0x48>;
};
basetemp: temperature-sensor@49 { /* baseboard temperature */
#thermal-sensor-cells = <0>;
compatible = "nxp,pct2075";
reg = <0x49>;
};
extrtc: rtc@51 { /* realtime clock */
compatible = "epson,rx8571";
reg = <0x51>;
};
resetc: reset-controller@60 {
compatible = "bur,rststm";
reg = <0x60>;
cooling-min-state = <0>;
cooling-max-state = <1>; /* reset gets fired */
#cooling-cells = <2>; /* min followed by max */
};
};
&i2c1 {
u-boot,dm-spl;
status = "okay";
};
&spi0 {
u-boot,dm-spl;
status = "okay";
cs-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>,
<&gpio0 6 GPIO_ACTIVE_HIGH>,
<0>,
<0>;
spi-max-frequency = <24000000>;
spi_flash: spiflash@0 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
compatible = "spidev", "spi-flash";
spi-max-frequency = <24000000>;
reg = <0>;
};
};
&spi1 {
u-boot,dm-spl;
status = "okay";
cs-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>,
<&gpio0 19 GPIO_ACTIVE_HIGH>,
<0>,
<0>;
spi-max-frequency = <24000000>;
};
&edma {
status = "okay";
};
&cppi41dma {
status = "okay";
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&davinci_mdio {
status = "okay";
};
&mac {
status = "okay";
};
&phy_sel {
rmii-clock-ext;
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "rmii";
ti,ledcr = <0x0480>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <3>;
phy-mode = "rmii";
ti,ledcr = <0x0480>;
};
&mmc1 {
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <0x4>;
ti,non-removable;
ti,needs-special-hs-handling;
ti,vcc-aux-disable-is-sleep;
status = "okay";
};
&mmc2 {
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <0x8>;
ti,non-removable;
ti,needs-special-hs-handling;
ti,vcc-aux-disable-is-sleep;
status = "okay";
};
&lcdc {
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&elm {
status = "okay";
};
&sham {
status = "okay";
};
&aes {
status = "okay";
};
&gpio0 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&gpio1 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&gpio2 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&gpio3 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&timer1 { /* today unused */
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&timer2 { /* used for vxworks primary timer device */
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&timer3 { /* used sysdelay and hal tsc counter*/
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&timer4 { /* used for PWM beeper */
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&timer5 { /* used for PWM backlight */
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&timer6 { /* used for cpsw end device */
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&timer7 { /* used for cpsw end device */
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&wdt2 {
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&epwmss0 {
status = "okay";
};
&tscadc {
status = "okay";
tsc {
burtouch0: burtouch@0 {
status = "okay";
compatible = "bur,DdVxSfTouchXXX";
bur,hwtree = "IF7";
bur,KX0 = <0x0>;
bur,KX1 = <0x0>;
bur,KX2 = <0x0>;
bur,KY0 = <0x0>;
bur,KY1 = <0x0>;
bur,KY2 = <0x0>;
};
};
};
&dcan0 {
status = "okay";
};
&dcan1 {
status = "okay";
};
&sham {
status = "disabled";
};
&aes {
status = "disabled";
};
&rng {
status = "disabled";
};

1
arch/arm/mach-omap2/Kconfig
View file

@ -176,6 +176,7 @@ source "arch/arm/mach-omap2/omap5/Kconfig"
source "arch/arm/mach-omap2/am33xx/Kconfig"
source "board/BuR/brxre1/Kconfig"
source "board/BuR/brsmarc1/Kconfig"
source "board/BuR/brppt1/Kconfig"
source "board/siemens/draco/Kconfig"
source "board/siemens/pxm2/Kconfig"

4
arch/arm/mach-omap2/am33xx/Kconfig
View file

@ -121,6 +121,10 @@ config TARGET_BRXRE1
bool "Support BRXRE1"
select BOARD_LATE_INIT
config TARGET_BRSMARC1
bool "Support BRSMARC1"
select BOARD_LATE_INIT
config TARGET_BRPPT1
bool "Support BRPPT1"
select BOARD_LATE_INIT

15
board/BuR/brsmarc1/Kconfig Normal file
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@ -0,0 +1,15 @@
if TARGET_BRSMARC1
config SYS_BOARD
default "brsmarc1"
config SYS_VENDOR
default "BuR"
config SYS_SOC
default "am33xx"
config SYS_CONFIG_NAME
default "brsmarc1"
endif

6
board/BuR/brsmarc1/MAINTAINERS Normal file
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@ -0,0 +1,6 @@
BRSMARC1 BOARD
M: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
S: Maintained
F: board/BuR/brsmarc1/
F: include/configs/brsmarc1.h
F: configs/brsmarc1_defconfig

10
board/BuR/brsmarc1/Makefile Normal file
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@ -0,0 +1,10 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
# B&R Industrial Automation GmbH - http://www.br-automation.com/
#
obj-$(CONFIG_SPL_BUILD) += mux.o
obj-y += ../common/br_resetc.o
obj-y += ../common/common.o
obj-y += board.o

168
board/BuR/brsmarc1/board.c Normal file
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@ -0,0 +1,168 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* board.c
*
* Board functions for B&R BRSMARC1 Board
*
* Copyright (C) 2017 Hannes Schmelzer <oe5hpm@oevsv.at>
* B&R Industrial Automation GmbH - http://www.br-automation.com
*
*/
#include <common.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/emif.h>
#include <power/tps65217.h>
#include "../common/bur_common.h"
#include "../common/br_resetc.h"
/* -------------------------------------------------------------------------*/
/* -- defines for used GPIO Hardware -- */
#define PER_RESET (2 * 32 + 0)
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_SPL_BUILD)
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
};
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41K256M16HA125E_RATIO,
.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd1csratio = MT41K256M16HA125E_RATIO,
.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd2csratio = MT41K256M16HA125E_RATIO,
.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
};
static struct emif_regs ddr3_emif_reg_data = {
.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
.zq_config = MT41K256M16HA125E_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
};
static const struct ctrl_ioregs ddr3_ioregs = {
.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
};
#define OSC (V_OSCK / 1000000)
const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
void am33xx_spl_board_init(void)
{
struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
int rc;
/*
* enable additional clocks of modules which are accessed later from
* VxWorks OS
*/
u32 *const clk_domains[] = { 0 };
u32 *const clk_modules_specific[] = {
&cmwkup->wkup_adctscctrl,
&cmper->spi1clkctrl,
&cmper->dcan0clkctrl,
&cmper->dcan1clkctrl,
&cmper->timer4clkctrl,
&cmper->timer5clkctrl,
&cmper->lcdclkctrl,
&cmper->lcdcclkstctrl,
0
};
do_enable_clocks(clk_domains, clk_modules_specific, 1);
/* setup I2C */
enable_i2c_pin_mux();
/* peripheral reset */
rc = gpio_request(PER_RESET, "PER_RESET");
if (rc != 0)
printf("cannot request PER_RESET GPIO!\n");
rc = gpio_direction_output(PER_RESET, 0);
if (rc != 0)
printf("cannot set PER_RESET GPIO!\n");
/* setup pmic */
pmicsetup(0, 0);
}
const struct dpll_params *get_dpll_ddr_params(void)
{
return &dpll_ddr3;
}
void sdram_init(void)
{
config_ddr(400, &ddr3_ioregs,
&ddr3_data,
&ddr3_cmd_ctrl_data,
&ddr3_emif_reg_data, 0);
}
#endif /* CONFIG_SPL_BUILD */
#if !defined(CONFIG_SPL_BUILD)
/* decision if backlight is switched on or not on powerup */
int board_backlightstate(void)
{
u8 bklmask, rstcause;
int rc = 0;
rc |= br_resetc_regget(RSTCTRL_SCRATCHREG1, &bklmask);
rc |= br_resetc_regget(RSTCTRL_ERSTCAUSE, &rstcause);
if (rc != 0) {
printf("%s: read rstctrl failed!\n", __func__);
return 1;
}
if ((rstcause & bklmask) != 0)
return 0;
return 1;
}
/* Basic board specific setup. run quite after relocation */
int board_init(void)
{
if (power_tps65217_init(0))
printf("WARN: cannot setup PMIC 0x24 @ bus #0, not found!.\n");
return 0;
}
#if defined(CONFIG_BOARD_LATE_INIT)
int board_late_init(void)
{
br_resetc_bmode();
return 0;
}
#endif /* CONFIG_BOARD_LATE_INIT */
#endif /* !CONFIG_SPL_BUILD */

33
board/BuR/brsmarc1/config.mk Normal file
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@ -0,0 +1,33 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
# B&R Industrial Automation GmbH - http://www.br-automation.com
#
hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/am335x-//')
payload_off :=$(shell printf "%d" $(CONFIG_SYS_SPI_U_BOOT_OFFS))
quiet_cmd_prodbin = PRODBIN $@ $(payload_off)
cmd_prodbin = \
dd if=/dev/zero ibs=1M count=2 2>/dev/null | tr "\000" "\377" >$@ && \
dd conv=notrunc bs=1 if=MLO.byteswap of=$@ seek=0 2>/dev/null && \
dd bs=1 if=u-boot-dtb.img of=$@ seek=$(payload_off) 2>/dev/null
quiet_cmd_prodzip = SAPZIP $@
cmd_prodzip = \
test -d misc && rm -r misc; \
mkdir misc && \
cp MLO.byteswap misc/ && \
cp spl/u-boot-spl.bin misc/ && \
cp u-boot-dtb.img misc/ && \
zip -9 -r $@ misc/* >/dev/null $<
ALL-y += $(hw-platform-y)_prog.bin
ALL-y += $(hw-platform-y)_prod.zip
$(hw-platform-y)_prog.bin: u-boot-dtb.img spl/u-boot-spl.bin
$(call if_changed,prodbin)
$(hw-platform-y)_prod.zip: $(hw-platform-y)_prog.bin
$(call if_changed,prodzip)

266
board/BuR/brsmarc1/mux.c Normal file
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@ -0,0 +1,266 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* mux.c
*
* Pinmux Setting for B&R BRSMARC1 Board (HW-Rev. 1)
*
* Copyright (C) 2017 Hannes Schmelzer <hannes.schmelzer@br-automation.com>
* B&R Industrial Automation GmbH - http://www.br-automation.com
*
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
#include <i2c.h>
static struct module_pin_mux spi0_pin_mux[] = {
/* SPI0_SCLK */
{OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
/* SPI0_D0 */
{OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
/* SPI0_D1 */
{OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
/* SPI0_CS0 */
{OFFSET(spi0_cs0), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
/* SPI0_CS1 */
{OFFSET(spi0_cs1), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
{-1},
};
static struct module_pin_mux spi1_pin_mux[] = {
/* SPI1_SCLK */
{OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE},
/* SPI1_D0 */
{OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE},
/* SPI1_D1 */
{OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE},
/* SPI1_CS0 */
{OFFSET(mcasp0_ahclkr), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
/* SPI1_CS1 */
{OFFSET(xdma_event_intr0), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
{-1},
};
static struct module_pin_mux dcan0_pin_mux[] = {
/* DCAN0 TX */
{OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
/* DCAN0 RX */
{OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
{-1},
};
static struct module_pin_mux dcan1_pin_mux[] = {
/* DCAN1 TX */
{OFFSET(uart0_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
/* DCAN1 RX */
{OFFSET(uart0_rtsn), MODE(2) | RXACTIVE},
{-1},
};
static struct module_pin_mux gpios[] = {
/* GPIO0_7 - LVDS_EN */
{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
/* GPIO0_20 - BKLT_PWM (timer7) */
{OFFSET(xdma_event_intr1), (MODE(4) | PULLUDDIS | PULLDOWN_EN)},
/* GPIO2_4 - DISON */
{OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
/* GPIO1_24 - RGB_EN */
{OFFSET(gpmc_a8), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
/* GPIO1_28 - nPD */
{OFFSET(gpmc_be1n), (MODE(7) | PULLUDEN | PULLUP_EN)},
/* GPIO2_5 - Watchdog */
{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
/* GPIO2_0 - ResetOut */
{OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN | PULLUP_EN)},
/* GPIO2_2 - BKLT_EN */
{OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
/* GPIO1_17 - GPIO0 */
{OFFSET(gpmc_a1), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO1_18 - GPIO1 */
{OFFSET(gpmc_a2), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO1_19 - GPIO2 */
{OFFSET(gpmc_a3), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO1_22 - GPIO3 */
{OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO1_23 - GPIO4 */
{OFFSET(gpmc_a7), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO1_25 - GPIO5 */
{OFFSET(gpmc_a9), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO3_7 - GPIO6 */
{OFFSET(emu0), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO3_8 - GPIO7 */
{OFFSET(emu1), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO3_18 - GPIO8 */
{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO3_19 - GPIO9 */
{OFFSET(mcasp0_fsr), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO3_20 - GPIO10 */
{OFFSET(mcasp0_axr1), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO3_21 - GPIO11 */
{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO2_28 - DRAM-strapping */
{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | PULLUP_EN)},
/* GPIO2_4 - not routed (Pin U6) */
{OFFSET(gpmc_wen), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* GPIO2_5 - not routed (Pin T6) */
{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* GPIO2_28 - not routed (Pin G15) */
{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* GPIO3_18 - not routed (Pin B12) */
{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
{-1},
};
static struct module_pin_mux uart0_pin_mux[] = {
/* UART0_RXD */
{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* UART0_TXD */
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
{-1},
};
static struct module_pin_mux uart234_pin_mux[] = {
/* UART2_RXD */
{OFFSET(mii1_txclk), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* UART2_TXD */
{OFFSET(mii1_rxclk), (MODE(1) | PULLUDEN)},
/* UART3_RXD */
{OFFSET(mii1_rxd3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* UART3_TXD */
{OFFSET(mmc0_dat0), (MODE(3) | PULLUDEN)},
/* UART3_RTS */
{OFFSET(mmc0_cmd), (MODE(2) | PULLUDEN)},
/* UART3_CTS */
{OFFSET(mmc0_clk), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* UART4_RXD */
{OFFSET(mii1_txd3), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* UART4_TXD */
{OFFSET(mii1_txd2), (MODE(3) | PULLUDEN)},
/* UART4_RTS */
{OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN)},
/* UART4_CTS */
{OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
{-1},
};
static struct module_pin_mux i2c_pin_mux[] = {
/* I2C0_DATA */
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
/* I2C0_SCLK */
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
/* I2C1_DATA */
{OFFSET(uart1_rxd), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)},
/* I2C1_SCLK */
{OFFSET(uart1_txd), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)},
{-1},
};
static struct module_pin_mux eth_pin_mux[] = {
/* ETH1 */
{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* ETH1_REFCLK */
{OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRSDV */
{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXER */
{OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
{OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
{OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
/* ETH2 */
{OFFSET(mii1_col), MODE(1) | RXACTIVE}, /* ETH2_REFCLK */
{OFFSET(gpmc_wait0), MODE(3) | RXACTIVE}, /* RMII2_CRSDV */
{OFFSET(gpmc_wpn), MODE(3) | RXACTIVE}, /* RMII2_RXER */
{OFFSET(gpmc_a0), MODE(3)}, /* RMII2_TXEN */
{OFFSET(gpmc_a11), MODE(3) | RXACTIVE}, /* RMII2_RXD0 */
{OFFSET(gpmc_a10), MODE(3) | RXACTIVE}, /* RMII2_RXD1 */
{OFFSET(gpmc_a5), MODE(3)}, /* RMII2_TXD0 */
{OFFSET(gpmc_a4), MODE(3)}, /* RMII2_TXD1 */
/* gpio2_19, gpio 3_4, not connected on board */
{OFFSET(mii1_rxd2), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
{OFFSET(mii1_rxdv), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
/* ETH Management */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{-1},
};
static struct module_pin_mux mmc1_pin_mux[] = {
{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
{-1},
};
static struct module_pin_mux lcd_pin_mux[] = {
{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
{-1},
};
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
}
void enable_i2c_pin_mux(void)
{
configure_module_pin_mux(i2c_pin_mux);
}
void enable_board_pin_mux(void)
{
configure_module_pin_mux(eth_pin_mux);
configure_module_pin_mux(spi0_pin_mux);
configure_module_pin_mux(spi1_pin_mux);
configure_module_pin_mux(dcan0_pin_mux);
configure_module_pin_mux(dcan1_pin_mux);
configure_module_pin_mux(uart234_pin_mux);
configure_module_pin_mux(mmc1_pin_mux);
configure_module_pin_mux(lcd_pin_mux);
configure_module_pin_mux(gpios);
}

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CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=600
CONFIG_TARGET_BRSMARC1=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x20000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x0
# CONFIG_EXPERT is not set
# CONFIG_FIT is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=0
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run b_default"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_CLK=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_ITEST is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-brsmarc1"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_OF_TRANSLATE is not set
# CONFIG_SPL_BLK is not set
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHY_NATSEMI=y
CONFIG_DM_ETH=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
# CONFIG_OMAP_WATCHDOG is not set
CONFIG_SPL_TINY_MEMSET=y
CONFIG_SHA1=y
CONFIG_SHA256=y
# CONFIG_EFI_LOADER is not set

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include/configs/brsmarc1.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* brsmarc1.h
*
* specific parts for B&R BRSMARC1 Motherboard
*
* Copyright (C) 2017 Hannes Schmelzer <oe5hpm@oevsv.at> -
* B&R Industrial Automation GmbH - http://www.br-automation.com
*
*/
#ifndef __CONFIG_BRSMARC1_H__
#define __CONFIG_BRSMARC1_H__
#include <configs/bur_cfg_common.h>
#include <configs/bur_am335x_common.h>
/* ------------------------------------------------------------------------- */
#define CONFIG_BOARD_TYPES
/* memory */
#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024)
#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024)
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
#define CONFIG_MACH_TYPE 3589
#ifndef CONFIG_SPL_BUILD
/* Default environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
BUR_COMMON_ENV \
"autoload=0\0" \
"scradr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"cfgscr=mw ${dtbaddr} 0;" \
" sf probe && sf read ${scradr} 0xC0000 0x10000 && source ${scradr};" \
" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" \
"dtbaddr=0x84000000\0" \
"loadaddr=0x82000000\0" \
"b_break=0\0" \
"b_tgts_std=mmc0 mmc1 def net usb0\0" \
"b_tgts_rcy=def net usb0\0" \
"b_tgts_pme=net usb0 mmc0 mmc1\0" \
"b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \
" elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \
" else setenv b_tgts ${b_tgts_std}; fi\0" \
"b_mmc0=load mmc 1 ${scradr} bootscr.img && source ${scradr}\0" \
"b_mmc1=load mmc 1 ${loadaddr} arimg.ugz && run startsys\0" \
"b_def=sf read ${loadaddr} 100000 700000; run startsys\0" \
"b_net=tftp ${scradr} netscript.img && source ${scradr}\0" \
"b_usb0=usb start && load usb 0 ${scradr} bootscr.img && source ${scradr}\0" \
"b_default=run b_deftgts; for target in ${b_tgts};"\
" do run b_${target}; if test ${b_break} = 1; then; exit; fi; done\0" \
"vxargs=setenv bootargs cpsw(0,0)host:vxWorks h=${serverip}" \
" e=${ipaddr}:${netmask} g=${gatewayip} u=vxWorksFTP pw=vxWorks\0" \
"vxfdt=fdt addr ${dtbaddr}; fdt resize 0x8000;" \
" fdt boardsetup\0" \
"startsys=run vxargs && mw 0x80001100 0 && run vxfdt &&" \
" bootm ${loadaddr} - ${dtbaddr}\0"
#endif /* !CONFIG_SPL_BUILD*/
/* undefine command which we not need here */
#undef CONFIG_BOOTM_NETBSD
#undef CONFIG_BOOTM_PLAN9
#undef CONFIG_BOOTM_RTEMS
/* Support both device trees and ATAGs. */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
/* SPI Flash */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
/* Environment */
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
CONFIG_ENV_SECT_SIZE)
#define CONFIG_CONS_INDEX 1
#endif /* __CONFIG_BRSMARC1_H__ */