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P4080: dts: Added PCIe DT nodes

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P4080 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Hou Zhiqiang 2019-08-27 11:04:56 +00:00 committed by Prabhakar Kushwaha
parent 7b7e4e1b7e
commit 936339a500
1 changed files with 36 additions and 0 deletions
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36
arch/powerpc/dts/p4080.dtsi
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@ -80,4 +80,40 @@
clock-frequency = <0x0>;
};
};
pcie@ffe200000 {
compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
law_trgt_if = <0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pcie@ffe201000 {
compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
law_trgt_if = <1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pcie@ffe202000 {
compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
law_trgt_if = <2>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
};
};