Commit graph

1381 commits

Author SHA1 Message Date
Shengzhou Liu
2ffa96d815 powerpc/t208x: fix macro CONFIG_SYS_FSL_NUM_USB_CTRLS
CONFIG_SYS_FSL_NUM_USB_CTRLS is no longer used,
update it to new CONFIG_USB_MAX_CONTROLLER_COUNT.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2014-01-02 14:10:13 -08:00
Priyanka Jain
b135991a3c powerpc/mpc85xx: Add support for single source clocking
Single-source clocking is new feature introduced in T1040.
In this mode, a single differential clock is supplied to the
DIFF_SYSCLK_P/N inputs to the processor, which in turn is
used to supply clocks to the sysclock, ddrclock and usbclock.

So, both ddrclock and syclock are driven by same differential
sysclock in single-source clocking mode whereas in normal clocking
mode, generally separate DDRCLK and SYSCLK pins provides
reference clock for sysclock and ddrclock

DDR_REFCLK_SEL rcw bit is used to determine DDR clock source
-If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in
 normal clocking mode by DDR_Reference clock

-If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in
 single source clocking mode by DIFF_SYSCLK

Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
2014-01-02 14:10:13 -08:00
Masahiro Yamada
e8a8b8246a Makefile: Select objects by CONFIG_ rather than $(ARCH) or $(CPU)
Convert like follows:

 CPU mpc83xx  -> CONFIG_MPC83xx
 CPU mpc85xx  -> CONFIG_MPC85xx
 CPU mpc86xx  -> CONFIG_MPC86xx
 CPU mpc5xxx  -> CONFIG_MPC5xxx
 CPU mpc8xx   -> CONFIG_8xx
 CPU mpc8260  -> CONFIG_8260
 CPU ppc4xx   -> CONFIG_4xx
 CPU x86      -> CONFIG_X86
 ARCH x86     -> CONFIG_X86
 ARCH powerpc -> CONFIG_PPC

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-12-16 08:59:42 -05:00
Miao Yan
871a57bb81 common/cmd_bootm: extend do_bootm_vxworks to support the new VxWorks boot interface.
The next version VxWorks adopts device tree (for PowerPC and ARM) as its hardware
description mechanism. For PowerPC, the boot interface conforms to
the ePAPR standard, which is:

   void (*kernel_entry)(ulong fdt_addr,
          ulong r4 /* 0 */,
          ulong r5 /* 0 */,
          ulong r6 /* EPAPR_MAGIC */, ulong r7 /* IMA size */,
          ulong r8 /* 0 */, ulong r9 /* 0 */)

For ARM, the boot interface is:

   void (*kernel_entry)(void *fdt_addr)

Signed-off-by: Miao Yan <miao.yan@windriver.com>
[trini: Fix build error when !CONFIG_OF_FDT is set, typo on PowerPC,
missing extern ft_fixup_num_cores]
Signed-off-by: Tom Rini <trini@ti.com>
2013-12-16 08:59:05 -05:00
Masahiro Yamada
de04d64eda PowerPC: merge commonly-defined flags
PLATFORM_RELFLAGS += -meabi
PLATFORM_CPPFLAGS += -ffixed-r2
were defined in all arch/powerpc/${CPU}/config.mk.

This commit moves them to arch/powerpc/config.mk.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-12-13 09:17:32 -05:00
Prabhakar Kushwaha
e03c76c303 powerpc/mpc85xx: Update CONFIG_SYS_FSL_TBCLK_DIV for T1040
The default value of CONFIG_SYS_FSL_TBCLK_DIV is 16.

So, update its value as default.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-12-11 11:12:54 -08:00
Shaohui Xie
c1015c67f4 powerpc/t4240: Add a frequency setting case for fman1
A new valid setting case added for fman1, it uses platform frequency.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-12-11 11:12:04 -08:00
York Sun
1df99080cb powerpc/mpc8349: Use generic mpc85xx DDR driver
MPC8349 has been using mpc85xx DDR driver through a symbolic link to
mpc85xx_ddr_gen2.c. After consolidating the drivers to a single set
under driver/ddr/fsl/, the link is replaced by referring driver
directly. We now can simply enable the macro and use the driver.
Other mpc83xx SoCs still use their own driver.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-12-04 14:55:05 -08:00
Zang Roy-R61911
e88f421e7a T4240: Address T4240/T4160 Rev2.0 DDR clock change
MEM_PLL_RAT on T4240/T4160 Rev2.0 uses a value which is half of Rev1.0.
It's 12 in Rev1.0, for Rev2.0 it uses 6.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-12-04 14:54:42 -08:00
Dave Liu
24936ed1c9 powerpc/corenet: CPC1 speculation disable
In PBL RAMBOOT(SPI/SD/NAND boot) mode, CPC1 used as SRAM, should disable
CPC1 speculation and keep it till relocation. Otherwise, speculation
transactions will go to DDR controller, it will cause problem.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-12-04 14:54:10 -08:00
Shengzhou Liu
629d6b32d6 powerpc/mpc85xx: Add T2080/T2081 SoC support
Add support for Freescale T2080/T2081 SoC.

T2080 includes the following functions and features:
- Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs)
- High-speed peripheral interfaces
  - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
  - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
  - Two serial ATA (SATA 2.0) controllers
  - Two high-speed USB 2.0 controllers with integrated PHY
  - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
  - Enhanced serial peripheral interface (eSPI)
  - Four I2C controllers
  - Four 2-pin UARTs or two 4-pin UARTs
  - Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0

Differences between T2080 and T2081:
  Feature               T2080 T2081
  1G Ethernet numbers:  8     6
  10G Ethernet numbers: 4     2
  SerDes lanes:         16    8
  Serial RapidIO,RMan:  2     no
  SATA Controller:      2     no
  Aurora:               yes   no
  SoC Package:          896-pins 780-pins

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-11-25 11:44:25 -08:00
Shengzhou Liu
82a55c1ef8 net/fman: Add support for 10GEC3 and 10GEC4
There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080).
This patch adds support for 10GEC3 and 10GEC4.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2013-11-25 11:43:47 -08:00
York Sun
0b66513b27 Driver/IFC: Move Freescale IFC driver to a common driver
Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/misc
and fix the header file includes.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:47 -08:00
York Sun
9a17eb5b7e Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx
Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3
structure for 83xx, 85xx and 86xx.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:46 -08:00
York Sun
5614e71b49 Driver/DDR: Moving Freescale DDR driver to a common driver
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:43 -08:00
Tang Yuantian
f40fcfd911 mpc85xx: Fix the offset of register address error
The offset of register address within GPIO module is just
CONFIG_SYS_MPC85xx_GPIO_ADDR. So, fix it. The following platforms
are confirmed: MPC8572, P1023, P1020, P1022, P2020, P4080,
P5020, P5040, T4240, B4860.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
2013-11-25 11:40:05 -08:00
Masahiro Yamada
0a3656a42e powerpc: mpc824x: Do not create a symbolic link to bedbug_603e.c
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-17 14:11:33 -05:00
Masahiro Yamada
5cdee2d41a powerpc: mpc83xx: Do not create a symbolic link to ddr-gen2.c
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-17 14:11:33 -05:00
Masahiro Yamada
c64c5aa56a powerpc: mpc83xx: delete unused rules
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-17 14:11:33 -05:00
Masahiro Yamada
c54ecaa965 powerpc: move mpc8xxx entry under arch/powerpc/cpu/
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-17 14:11:31 -05:00
Masahiro Yamada
e5c5301f14 Makefile: make directories by Makefile.build
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-17 14:11:31 -05:00
Laurentiu TUDOR
51abee64ee powerpc/85xx: fix broken cpu "clock-frequency" property
When indexing freqProcessor[] we use the first
value in the cpu's "reg" property, which on
new e6500 cores IDs the threads.
But freqProcessor[] should be indexed with a
core index so, when fixing "the clock-frequency"
cpu node property, access the freqProcessor[]
with the core index derived from the "reg' property.
If we don't do this, last half of the "cpu" nodes
will have broken "clock-frequency" values.

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Cc: York Sun <yorksun@freescale.com>
2013-11-13 12:41:28 -08:00
Laurentiu TUDOR
8f9fe660fc powerpc/t4240: fix per pci endpoint liodn offsets
Update the code that builds the pci endpoint liodn
offset list so that it doesn't overlap with other
liodns and doesn't generate negative offsets like:

  fsl,liodn-offset-list = <0 0xffffffcd 0xffffffcf
                             0xffffffd1 0xffffffd3
                             0xffffffd5 0xffffffd7
                             0xffffffd9 0xffffffdb>;

The update consists in adding a parameter to the
function that builds the list to specify the base
liodn.
On PCI v2.4 use the old base = 256 and, on PCI 3.0
where some of the PCIE liodns are larger than 256,
use a base = 1024. The version check is based on
the PCI controller's version register.

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: York Sun <yorksun@freescale.com>
2013-11-13 12:41:28 -08:00
Laurentiu TUDOR
b4125a235e powerpc/t4240: set pcie liodn in the correct register
The liodn for the T4240's PCIE controller is no longer set
through a register in the guts register block but with one
in the PCIE register block itself.
Use the already existing SET_PCI_LIODN_BASE macro that puts
the liodn in the correct register.

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: York Sun <yorksun@freescale.com>
2013-11-13 12:41:28 -08:00
ramneek mehresh
4e2e0df94d powerpc/83xx: Define USB1 and USB2 base addr for MPC834x
Define base addresse for both MPH(USB1) and DR(USB2) controllers
for MPC834x socs

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2013-11-13 12:41:28 -08:00
Priyanka Jain
2967af6816 powerpc/t1040: Update defines to support T1040SoC personalities
T1040 Soc has four personalities:
-T1040 (4 cores with L2 switch)
-T1042:Reduced personality of T1040 without L2 switch
-T1020:Reduced personality of T1040 with less cores(2 cores)
-T1022:Reduced personality of T1040 with 2 cores and without L2 switch

Update defines in arch/powerpc header files, Makefiles and in
driver/net/fm/Makefile to support all T1040 personalities

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: fixed Makefiles]
Acked-by: York Sun <yorksun@freescale.com>
2013-11-13 12:41:08 -08:00
Wolfgang Denk
649acfe149 MPC824x: remove obsolete "PN62" board
The MPC824x processors have long reached EOL, and the PN62 board has
not seen any board-specific updates for more than a decade.  It is now
causing build issues.  Instead of wasting time on things nobody is
interested in any more, we rather drop this board.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Wolfgang Grandegger <wg@grandegger.com>
cc: Tom Rini <trini@ti.com>
2013-11-11 14:46:24 -05:00
Masahiro Yamada
643aae1406 include: delete include/linux/config.h
Linux Kernel abolished include/linux/config.h long time ago.
(around version v2.6.18..v2.6.19)

We don't need to provide Linux copatibility any more.

This commit deletes include/linux/config.h
and fixes source files not to include this.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-08 15:25:13 -05:00
Masahiro Yamada
0f0f75774e cosmetic: remove empty lines at the top of file
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-08 09:41:37 -05:00
Masahiro Yamada
06c14117c4 powerpc: convert makefiles to Kbuild style
Note:
arch/powerpc/cpu/mpc8260/Makefile is originally like follows:

    ---<snip>---
    START   = start.o kgdb.o
    COBJS   = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \
    ---<snip>---
    COBJS-$(CONFIG_ETHER_ON_SCC) = ether_scc.o
    ---<snip>---
    $(LIB): $(OBJS)
            $(call cmd_link_o_target, $(OBJS) $(obj)kgdb.o)

The link rule `$(call cmd_link_o_target, $(OBJS) $(obj)kgdb.o)'
is weird.
kbdg.o is not included in $(OBJS) but linked into $(LIB)
and $(LIB) is not dependent on kgdb.o.
(Broken dependency tracking)

So,
    START   = start.o kgdb.o
shoud have been
    START   = start.o
    SOBJS   = kgdb.o

That is why this commit adds kgdb.o to obj-y, not to extra-y.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
2013-10-31 13:26:44 -04:00
Valentin Longchamp
935b402eae fsl/mpc85xx: define common serdes_clock_to_string function
This allows to share some common code for the boards that use a corenet
base SoC.

Two different versions of the function are available in
fsl_corenet_serdes.c and fsl_corenet2_serdes.c files.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[York Sun: fix t1040qds.c]
Acked-by: York Sun <yorksun@freescale.com>
2013-10-24 09:36:18 -07:00
Valentin Longchamp
7e157b0ade mpc8xxx: set x2 DDR3 refresh rate if SPD config requires it
If the DDR3 module supports industrial temperature range and requires
the x2 refresh rate for that temp range, the refresh period must be
3.9us instead of 7.8 us.

This was successfuly tested on kmp204x board with some MT41K128M16 DDR3
RAM chips (no module used, chips directly soldered on board with an SPD
EEPROM).

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[York Sun: fix minor conflicts in fsl_ddr_dimm_params.h,
	   lc_common_dimm_params.c, common_timing_params.h]
Acked-by: York Sun <yorksun@freescale.com>
2013-10-24 09:35:52 -07:00
Valentin Longchamp
0778bbe2d4 mpc8xxx: call i2c_set_bus_num in __get_spd
This is necessary with the new I2C subystem that was introduced lately.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
2013-10-24 09:35:46 -07:00
Valentin Longchamp
13287e3d47 powerpc: cast bi_memsize to ulong for %ld usage
When exporting the new memsize without reserved PRAM area, the -Wformat
option produces a warning since %ld is used for snprintf and bi_memsize
is phys_size_t.

This patch removes this warning for all PRAM PowerPC boards.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
2013-10-24 09:35:15 -07:00
ramneek mehresh
77354e9d50 powerpc/usb:Differentiate USB controller base address
Introduce different macros for storing addresses of multiple
USB controllers. This is required for successful initialization
and usage of multiple USB controllers inside u-boot

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2013-10-24 09:35:09 -07:00
ramneek mehresh
f1810d851c powerpc/usb:Define CONFIG_USB_MAX_CONTROLLER_COUNT for all 85xx socs
CONFIG_USB_MAX_CONTROLLER_COUNT macro recently defined for
initializing all USB controllers on a given platform. This
macro is defined for all 85xx socs

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2013-10-24 09:35:03 -07:00
Tom Rini
748bde608a Merge branch 'master' of git://git.denx.de/u-boot-usb 2013-10-21 08:10:36 -04:00
Troy Kisky
06d513ecb6 usb: add enum usb_init_type parameter to usb_lowlevel_init
This parameter will later be used to verify OTG ports.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-10-20 23:45:26 +02:00
Zhao Qiang
287df01e6a PCIe:change the method to get the address of a requested capability in configuration space.
Previously, the address of a requested capability is define like that
	"#define PCI_DCR	0x78"
But, the addresses of capabilities is different with regard to PCIe revs.
So this method is not flexible.

Now a function to get the address of a requested capability is added and used.
It can get the address dynamically by capability ID.
The step of this function:
	1. Read Status register in PCIe configuration space to confirm that
	   Capabilities List is valid.
	2. Find the address of Capabilities Pointer Register.
	3. Find the address of requested capability from the first capability.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-16 16:15:17 -07:00
York Sun
133fbfa9e6 powerpc/mpc85xx: Add workaround for erratum A006379
Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default
value after POR. The workaround is to set this field before enabling
CPC to 0x1e.

Erratum A006379 applies to
	T4240 rev 1.0
	B4860 rev 1.0, 2.0

Signed-off-by: York Sun <yorksun@freescale.com>
2013-10-16 16:15:17 -07:00
Priyanka Jain
0dd38a35f4 powerpc: Fix CamelCase warnings in DDR related code
Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h
has various parameters with embedded acronyms capitalized that trigger the CamelCase
warning in checkpatch.pl

Convert those variable names to smallcase naming convention and modify all files
which are using these structures with modified structures.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
2013-10-16 16:15:16 -07:00
Prabhakar Kushwaha
ce746fe03e powerpc/mpc85xx:Avoid fix clk groups for Cluster & HW accelerator
CHASSIS2 architecture never fix clock groups for Cluster and hardware
  accelerator like PME, FMA. These are SoC defined. SoC defines :-
    - NUM of PLLs present in the system
    - Clusters and their Clock group
    - hardware accelerator and their clock group
      if no clock group, then platform clock divider for FMAN, PME

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2013-10-16 16:13:11 -07:00
Prabhakar Kushwaha
1d384eca61 powerpc/mpc85xx:Update processor defines for T1040
T1040 SoC has
    - DDR controller ver 5.0
    - 2 PLLs
    - 8 IFC Chip select
    - FMAN Muram 192K
    - No Srio
    - Sec controller ver 5.0
    - Max CPU update for its personalities

So, update the defines accordingly.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2013-10-16 16:13:11 -07:00
Prabhakar Kushwaha
e982746844 powerpc/mpc85xx:Make L2 cache type independent of CHASSIS2
CHASSIS2 architecture never defines type of L2 cache present in SoC.
 it is dependent upon the core present in the SoC.
 for example,
    - e6500 core has L2 cluster (Kibo)
    - e5500 core has Backside L2 Cache

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2013-10-16 16:13:11 -07:00
Po Liu
0d2cff2d9e powerpc: add CONFIG_SECURE_BOOT condition into fsl_secure_boot.h
This patch is for board config file not to add CONFIG_SECURE_BOOT
condition for include the asm/fsl_secure_boot.h.

Signed-off-by: Po Liu <Po.Liu@freescale.com>
2013-10-16 16:13:10 -07:00
Wolfgang Denk
93e1459641 Coding Style cleanup: replace leading SPACEs by TABs
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Drop changes for PEP 4 following python tools]
Signed-off-by: Tom Rini <trini@ti.com>
2013-10-14 16:06:54 -04:00
Wolfgang Denk
3765b3e7bd Coding Style cleanup: remove trailing white space
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14 16:06:53 -04:00
Wolfgang Denk
1b387ef55c SPDX: fix IBM-pibs license identifier
The SPDX License List version 1.19 now contains an official entry for
the IBM-pibs license.  However, instead of our suggestion "ibm-pibs",
the SPDX License List uses "IBM-pibs", with the following rationale:
"The reason being that all other SPDX License List short identifiers
tend towards using capital letters unless spelling a word.  I'd prefer
to be consistent to this end".

Change the license IDs to use the official name.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-09-20 10:30:54 -04:00
York Sun
954a1a4776 powerpc/mpc85xx: Add workaround for erratum A-005125
In a very rare condition, a system hang is possible when the e500 core
initiates a guarded load to PCI / PCIe /SRIO performs a coherent write
to memory. Please refer to errata document for more details. This erratum
applies to the following SoCs and their variants, if any.

BSC9132
BSC9131
MPC8536
MPC8544
MPC8548
MPC8569
MPC8572
P1010
P1020
P1021
P1022
P1023
P2020
C29x

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
2013-09-10 14:31:47 -07:00
Tang Yuantian
f62b123813 powerpc/mpc85xx: Fix the I2C bus speed error on p1022
The source clock frequency of I2C bus on p1022 is the platform(CCB)
clock, not CCB/2. The wrong source clock frequency leads to wrong
I2C bus speed setting. so, fixed it.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
2013-09-09 07:44:27 +02:00
Ying Zhang
81b867aa44 SPL: P1022DS: switch to new multibus/multiadapter support
- Added section "u_boot_list" in arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
- Use the function i2c_init_all instead of i2c_init

Signed-off-by: Ying Zhang <b40530@freescale.com>
2013-09-09 07:43:43 +02:00
Tom Rini
6612ab3395 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2013-08-21 16:27:47 -04:00
Николай Пузанов
e6394e9e8f Fix for incorrect conversion hex string to number (FMAN firmware address).
Signed-off-by: Николай Пузанов <punzik@gmail.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 11:51:26 -07:00
Shengzhou Liu
424bf94273 powerpc/sec: Add workaround for SEC A-003571
Multiple read/write transactions initiated by security
engine may cause system to hang.
Workaround: set MCFGR[AXIPIPE] to 0 to avoid hang.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 10:47:07 -07:00
Shaohui Xie
1c68d01eea powerpc/t4240: add QSGMII interface support
Also some fix for QSGMII.
1. fix QSGMII configure of Serdes2.
2. fix PHY address of QSGMII MAC9 & MAC10 for each FMAN.
3. fix dtb for QSGMII interface.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 10:46:48 -07:00
Shruti Kanetkar
6b44d9e5b7 powerpcv2: Print hardcoded size like print_size() does
Makes the startup output more consistent

Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 10:38:12 -07:00
Shruti Kanetkar
2f848f97d7 powerpc: Use print_size() where appropriate
Makes the startup output more consistent

Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 10:37:58 -07:00
Prabhakar Kushwaha
997399fa42 powerpc: Fix CamelCase checkpatch warnings
85xx, 86xx PowerPC folders have code variables with CamelCase naming conventions.
because of this code checkpatch script generates "WARNING: Avoid CamelCase".

Convert variables name to normal naming convention and modify board, driver
files with updated the new structure.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 09:57:51 -07:00
Ying Zhang
bb0dc1084f powerpc: mpc85xx: Support booting from SD Card with SPL
The code from the internal on-chip ROM. It loads the final uboot image
into DDR, then jump to it to begin execution.

The SPL's size is sizeable, the maximum size must not exceed the size of L2
SRAM. It initializes the DDR through SPD code, and copys final uboot image
to DDR. So there are two stage uboot images:
	* spl_boot, 96KB size. The env variables are copied to L2 SRAM, so that
	ddr spd code can get the interleaving mode setting in env. It loads
	final uboot image from offset 96KB.
	* final uboot image, size is variable depends on the functions enabled.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 09:47:26 -07:00
Ying Zhang
0151d99d74 powerpc: deleted unused symbol CONFIG_SPL_NAND_MINIMAL and enabled some functionality for common SPL
1. The symbol CONFIG_SPL_NAND_MINIMAL is unused, so deleted it.
2. Some functions were unused in the minimal SPL, but it is useful
in the common SPL. So, enabled some functionality for common SPL.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 09:47:15 -07:00
Matthias Fuchs
3fb8588912 ppc4xx: Remove support for PPC405CR CPUs
This patch removes support for the APM 405CR CPU.
This CPU is EOL and no board uses this chip.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2013-08-20 11:35:24 -04:00
Chunhe Lan
9c3f77eb3b fsl_i2c: add workaround for the erratum I2C A004447
This workaround is for the erratum I2C A004447. Device reference
manual provides a scheme that allows the I2C master controller
to generate nine SCL pulses, which enable an I2C slave device
that held SDA low to release SDA. However, due to this erratum,
this scheme no longer works. In addition, when I2C is used as
a source of the PBL, the state machine is not able to recover.

At the same time, delete the reduplicative definition of SVR_VER
and SVR_REV. The SVR_REV is the low 8 bits rather than the low 16
bits of svr. And we use the CONFIG_SYS_FSL_A004447_SVR_REV macro
instead of hard-code value 0x10, 0x11 and 0x20.

The CONFIG_SYS_FSL_A004447_SVR_REV = 0x00 represents that one
version of platform has this I2C errata. So enable this errata
by IS_SVR_REV(svr, maj, min) function.

Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
2013-08-20 11:15:31 +02:00
Wolfgang Denk
46263f2de4 SPDX-License-Identifier: convert PIBS licensed files
This commit adapts the files that were derived from PIBS (PowerPC
Initialization and Boot Software) codeto using SPDX License
Identifiers.

So far, SPDX has not assigned an official License ID for the PIBS
license yet, so this should be considered preliminary.

Note that the following files contained incorrect license information:

	arch/powerpc/cpu/ppc4xx/4xx_uart.c
	arch/powerpc/cpu/ppc4xx/start.S
	arch/powerpc/include/asm/ppc440.h

These files included, in addition to the GPL-2.0 / ibm-pibs dual
license as inherited from PIBS, a GPL-2.0+ license header which was
obviously incorrect.  This has been removed.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>

Conflicts:
	Licenses/README
Acked-by: Stefan Roese <sr@denx.de>
2013-08-19 15:34:14 -04:00
ramneek mehresh
61033367a0 powerpc/usb: Depricate usb_phy_type and usb_dr_mode uboot env variables
Remove getting values of usb mode and phy_type from "usb_dr_mode"
and "usb_phy_type" uboot env variables. Now, these are determined
only from hwconfig string

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-14 10:58:21 -07:00
ramneek mehresh
9dee205d78 fsl/usb: Move USB internal phy definitions to fsl_usb.h
fsl_usb.h file created to share data bewteen usb platform code
and usb ip driver. Internal phy structure definitions moved to
this file

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-14 10:58:01 -07:00
Prabhakar Kushwaha
a4c955bc3b powerpc/mpc85xx:Avoid hardcoded init for serdes block 1 & 2
It is not necessary for all processor to have serdes block 1 & 2.
They may have only one serdes block.

So, put serdes block 1 & 2 related code under defines

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-14 10:57:49 -07:00
Tom Rini
b98d934128 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2013-08-13 09:14:02 -04:00
York Sun
3aab0cd852 powerpc/mpc85xx: Cleanup license header in source files
Fix the license header introduced by the following patches

Add TWR-P10xx board support
Add T4240EMU target
IDT8T49N222A configuration code
Add C29x SoC support
Add support for C29XPCIE board

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-12 15:04:24 -07:00
Marek Vasut
ac8ba84c56 video: Encapsulate font in video_font_data.h
This patch moves all the font configuration values into video_font_data.h
so they are all in the right place with the font. The video_font.h now only
includes video_font_data.h and will allow us to select and include different
font once more fonts are added.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
[agust: fixed build warning for mcc200]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-08-12 22:28:41 +02:00
Roy Zang
ce24f87b7b 83xx/pcie: fix build error for 83xx pcie
Fix the following build error caused by patch "powerpc/pcie: add PCIe
version 3.x support":

pcie.c:302:34: error: 'PCI_LTSSM' undeclared (first use in this function)
pcie.c:303:15: error: 'PCI_LTSSM_L0' undeclared (first use in this function)

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:50:56 -07:00
James Yang
c45f5c08b7 powerpc/mpc8xxx: Fix TIMING_CFG_3[EXT_ACTTOPRE]
The TIMING_CFG_3[EXT_ACTTOPRE] register field is 2 bits wide, but
the mask omitted the LSB.  This patch provides a 2-bit wide mask.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:43:32 -07:00
Mingkai Hu
3b75e98273 powerpc/85xx: Add C29x SoC support
The Freescale C29x family is a high performance crypto co-processor.
It combines a single e500v2 core with necessary SEC engine. There're
three SoC types(C291, C292, C293) with the following features:

 - 512K L2 Cache/SRAM and 512 KB platform SRAM
 - DDR3/DDR3L 32bit DDR controller
 - One PCI express (x1, x2, x4) Gen 2.0 Controller
 - Trust Architecture 2.0
 - SEC6.0 engine

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Po Liu <Po.Liu@freescale.com>
2013-08-09 12:41:42 -07:00
Zang Roy-R61911
1218f7eb11 powerpc/pcie: remove PCIe version 3.x define for B4860 and B4420
B4860 and B4420 has PCIe version 2.4 IP instead of 3.x

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
2013-08-09 12:41:42 -07:00
Zang Roy-R61911
7b4e58440f powerpc/pcie: add PCIe version 3.x support
T4240 PCIe IP is version 3.0 and has some update comparing previous
QorIQ products.

1.  Move Freescale specific register define
to
arch/powerpc/include/asm/fsl_pci.h
and update the register offset define for T4240.

2. add the status/control register define
use status/control register to judge the link status

3. The original code uses 'Programming Interface' field to judge if PCIE is
EP or RC mode, however, T4240 does not support this functionality.
According to PCIE specification, 'Header Type' offset 0x0e is used to
indicate header type, so for PCIE controller, the patch changes code to
use 'Header Type' field to identify if the PCIE is RC or EP mode.

This patch fixes  the PCIe card link up issue on T4240QDS.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:41 -07:00
Minghuan Lian
0795eff34c powerpc/rman: fix RMan support for t4240 and b4860
1. Add CONFIG_SYS_DPAA_RMAN macro to t4240 and b4860.
2. Decrease RMan liodn offset number.
SET_RMAN_LIODN() is used to set liodn offset of RMan blocks 0-3.
For t4240 and b4860, RMan liodn base is assigned to 922, the original
offset number is too large that the liodn (base+offset 922+678 = 1600)
is greater than 0x500 the maximum liodn number.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:41 -07:00
Shaveta Leekha
40f398a42b powerpc/asm: Move function declaration of 'serdes_get_prtcl' to fsl_serdes.h
It allows files not in the same path to use this function
as required by B4 board file

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
2013-08-09 12:41:41 -07:00
Shaveta Leekha
6fbe988901 powerpc/mpc85xx: Add defines for serdes RSTCTL register
Also change the define name SRDS_RSTCTL_SDPD to
SRDS_RSTCTL_SDEN, which stands for SerDes enable
as mentioned in SerDes module guide

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
2013-08-09 12:41:41 -07:00
Priyanka Jain
f9d379a707 board/bsc9132qds: Configure DSP DDR controller
BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side
DDR. They are mapped to PowerPC and DSP CCSR space respectively.
BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC
and other to DSP side controller.

Configure DSP DDR controller similar to PowerPC side DDR controller as
memories are exactly similar.

Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:40 -07:00
Priyanka Jain
64501c6698 board/bsc9132qds: Add DSP side tlb and laws
BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a
integrated device that contains two powerpc e500v2 cores and two DSP
starcores.

To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 and M3 memory
-Creating LAW for 1GB DDR which is connected exclusively to DSP-cores

Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:40 -07:00
Liu Gang
17b8614754 powerpc/srio-pcie-boot: Avoid the NOR_BOOT macro when boot from SRIO/PCIE
When a board (slave) boots from SRIO/PCIE, it would get the instructions
from a remote board (master) by SRIO/PCIE interface, and the slave's
u-boot image should be built with the

	SYS_TEXT_BASE=0xFFF80000;

So the u-boot of the slave should avoid the NOR_BOOT branch at the
booting stage.

For example, when a P2041RDB boots from SRIO/PCIE, it will set TLB
entry 15 from base address "CONFIG_SYS_MONITOR_BASE & 0xffc00000",
and with the 4M size as the boot window in NOR_BOOT branch. Because
the CONFIG_SYS_MONITOR_BASE = CONFIG_SYS_TEXT_BASE = 0xFFF80000, so
the TLB entry will be from base address 0xffc00000 and with 4M size.

Then the u-boot will set TLB entry 14 from base address
"CONFIG_SYS_INIT_RAM_ADDR", and with the 16K size as the initial
stack window. For the P2041RDB platform, the CONFIG_SYS_INIT_RAM_ADDR
= 0xffd00000. So the TLB entry 14 and 15 will be in confliction.

There will be right TLB entries configurations when avoid the
NOR_BOOT branch and set the boot window from 0xfff00000 with 1M
size space.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
2013-08-09 12:41:40 -07:00
York Sun
d217a9ad01 powerpc/mpc85xx: Workaround for A-005812
Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can
result in invalid atomic operations. For u-boot, this erratum only impacts
SoCs running in write shadow mode.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:40 -07:00
York Sun
c63e137014 powerpc/mpc8xxx: Add memory reset control
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:39 -07:00
York Sun
b61e061566 powerpc/mpc8xxx: Add x4 DDR device support
On selected platforms, x4 DDR devices can be supported. Using x4 devices may
lower the performance, but generally they are available for higher density.

Tested on MT36JSF2G72PZ-1G9E1 RDIMM.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:39 -07:00
York Sun
d8556db1d4 powerpc/mpc8xxx: Set inactive csn_bnds to 0xffffffff
When chip select interleaving is enabled, cs0_bnds is used for address
binding. Other csn_bnds are not used. When two controllers interleaving is
enabled, cs0_bnds of both controllers are used, other csn_bnds are not.
However, the unused csn_bnds may be used internally for calculating
addresses for calibration. Setting those registers to 0 may confuse
controllers in some cases. Instead, setting them to 0xffffffff together
with normal LAWs will guarantee the address is not mapped to DDR.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:39 -07:00
York Sun
f165bc3528 powerpc/corenet: Move RCW print to cpu.c
The RCW print is common for all corenet platforms. Not necessary to ducplicate
in each board file.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:38 -07:00
York Sun
cb93071bb6 mpc85xx: Base emulator support
Prepare for emulator support for mpc85xx parts.
Disable DDR training and skip wrlvl_cntl_2 and wrlvl_cntl_3 registers.
These two registers improve stability but not supported by emulator.
Add CONFIG_FSL_TBCLK_EXTRA_DIV for possible adjustment to time base.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:38 -07:00
York Sun
d2ab4bbc7b powerpc/corenet: Move CONFIG_FSL_CORENET out of board header file
Move CONFIG_FSL_CORENET define to config_mpc85xx.h. It is not board
specific feature and belongs to SoC header.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:38 -07:00
Liu Gang
08047937b4 powerpc/t4: Correct LIODN assignment for SRIO
For T4 platform, the SRIO LIODN registers are in SRIO address space
and not in GUTs.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
2013-08-09 12:41:38 -07:00
Liu Gang
32f38ee3ed powerpc/b4860: Correct LIODN assignment for SRIO
For B4, the SRIO LIODN registers are in SRIO address space and not
in GUTs.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
2013-08-09 12:41:37 -07:00
Liu Gang
b383102040 powerpc/srio: Update the SRIO LIODN registers and ID table macro
For some PowerPC platforms, LIODN registers for SRIO ports are
in SRIO register address space. So the ccsr_rio structure should
be updated for those LIODN registers.

In addition, add a new macro "SET_SRIO_LIODN_BASE" to create
the SRIO LIODN ID table based on the SRIO LIODN register address.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:37 -07:00
Tom Rini
c2120fbfbc Merge branch 'master' of git://git.denx.de/u-boot-i2c
The sandburst-specific i2c drivers have been deleted, conflict was just
over the SPDX conversion.

Conflicts:
	board/sandburst/common/ppc440gx_i2c.c
	board/sandburst/common/ppc440gx_i2c.h

Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:50:24 -04:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Dirk Eibach
880540decf i2c, ppc4xx_i2c: switch to new multibus/multiadapter support
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2013-07-23 08:34:56 +02:00
Heiko Schocher
9a2accb44f i2c, multibus: get rid of CONFIG_I2C_MUX
CONFIG_I2C_MUX is replaced through the new i2c multibus/multiadapter
framework, configured through CONFIG_SYS_I2C. As CONFIG_I2C_MUX
is only used on the keymile boards, and they are now completely
moved to the new framework, remove CONFIG_I2C_MUX.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Holger Brunck <holger.brunck@keymile.com>
Tested-By: Holger Brunck <holger.brunck@keymile.com>
2013-07-23 08:34:53 +02:00
Heiko Schocher
ea818dbbcd i2c, soft-i2c: switch to new multibus/multiadapter support
- added to soft_i2c driver new multibus/multiadpater support
- adapted all config files, which uses this driver

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
2013-07-23 05:54:29 +02:00
Heiko Schocher
3f4978c713 i2c: common changes for multibus/multiadapter support
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Cc: Henrik Nordström <henrik@henriknordstrom.net>
2013-07-23 05:54:28 +02:00
Prabhakar Kushwaha
2a6936059a powerpc/mpc85xx:Disable Debug TLB entry for non-minimal SPL
CONFIG_SPL_BUILD creates debug TLB entry, so disable it before init_tlbs.

CONFIG_SPL_INIT_MINIMAL never creates any debug TLB entry, so no need
of disable_tlb().

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-07-16 17:44:30 -05:00
Dirk Eibach
b8eee4354f Build arch/$ARCH/lib/bootm.o depending on CONFIG_CMD_BOOTM
MAKEALL is fine for ppc4xx and mpc85xx.
Run checks were done on our controlcenterd hardware.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-07-16 17:44:30 -05:00
Stefan Roese
ed12b5b9da Fix bootm to work on powerpc again (compressed uImage)
Patch 35fc84fa1 [Refactor the bootm command to reduce code duplication]
breaks booting Linux (compressed uImage with fdt) on powerpc.

boot_jump_linux() mustn't be called before boot_prep_linux() and
boot_body_linux() have been called. So remove the superfluous call
to boot_jump_linux() in arch/powerpc/lib/bootm.c as its called later on
in this function.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@ti.com>
2013-06-28 16:26:52 -04:00
Chunhe Lan
5707233880 powerpc/85xx: Add P1023RDB board support
P1023RDB Specification:
-----------------------
Memory subsystem:
   512MB DDR3 (Fixed DDR on board)
   64MB NOR flash
   128MB NAND flash

Ethernet:
   eTSEC1: Connected to Atheros AR8035 GETH PHY
   eTSEC2: Connected to Atheros AR8035 GETH PHY

PCIe:
   Three mini-PCIe slots

USB:
   Two USB2.0 Type A ports

I2C:
   AT24C08 8K Board EEPROM (8 bit address)

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:53 -05:00
Prabhakar Kushwaha
bd7c023e48 powerpc/mpc85xx:Disable Debug TLB entry before init_tlbs
init_tlbs() initialize all the TLB entries required for the system.

So disable DEBUG TLB entry before TLB entries initialization.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:53 -05:00
Axel Lin
e51e47d38e powerpc: mpc85xx/mpc86xx: Fix off-by-one boundary checking with ARRAY_SIZE
If a variable is used as array subscript, it's valid value range is
0 ... ARRAY_SIZE -1.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:51 -05:00
Ying Zhang
67ad0d52df powerpc/mpc85xx: modify the functionality clear_bss and aligning the end address of the BSS
There will clear the BSS in the function clear_bss(), the reset address of
the BSS started from the __bss_start, and increased by four-byte increments,
finally stoped depending on the address is equal to the _bss_end. If the end
address __bss_end is not alignment to 4byte, it will be an infinite loop.

1. The reset action stoped depending on the reset address is greater
than or equal the end address of the BSS.
2. The end address of the BSS should be 4byte aligned. Because the reset unit
is 4 Bytes.

This patch is on top of the patch "powerpc/mpc85xx: support application
without resetvec segment in the linker script".

Signed-off-by: Ying Zhang <b40530@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:50 -05:00
Ying Zhang
5df572f013 powerpc/mpc85xx: support application without resetvec segment in the linker script
For SD/SPI 2-stage bootloader, the On-Chip Rom code loads the SPL into L2 SRAM,
then jump to it to begin execution. After that, the SPL loads the final uboot
image into DDR, then jump to it to begin execution. The segment .resetvec in
the SPL and in final U-boot is useless.

So, add new symbols CONFIG_SYS_MPC85XX_NO_RESETVEC for this application.
If CONFIG_SYS_MPC85XX_NO_RESETVEC is set, the segment .resetvec is excluded
and the segment .bootpg is placed in the previous 4K of the segment .text.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:50 -05:00
Scott Wood
8212519254 powerpc/mpc85xx: work around erratum A-006593
Erratum A-006593 is "Atomic store may report failure but still allow
the store data to be visible".

The workaround is: "Set CoreNet Platform Cache register CPCHDBCR0 bit
21 to 1'b1.  This may have a small impact on synthetic write bandwidth
benchmarks but should have a negligible impact on real code."

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:49 -05:00
Mingkai Hu
362ee04b79 fsl_ifc: add support for different IFC bank count
Calculate reserved fields according to IFC bank count

1. Move csor_ext register behind csor register and fix res offset
2. Move ifc bank count to config_mpc85xx.h to support 8 bank count
3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile
   error on some devices that does not have IFC controller.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:49 -05:00
Liu Gang
69fdf90010 powerpc/t4qds: Slave module for boot from SRIO and PCIE
When a T4 board boots from SRIO or PCIE, it needs to finish these processes:
	1. Set all the cores in holdoff status.
	2. Set the boot location to one PCIE or SRIO interface by RCW.
	3. Set a specific TLB entry for the boot process.
	4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
	5. Set a specific TLB entry in order to fetch ucode and ENV from
	   master.
	6. Set a LAW entry with the TargetID one of the PCIE ports for
	   ucode and ENV.
	7. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIO_PCIE_BOOT_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:49 -05:00
Liu Gang
5870fe44b2 powerpc/b4860qds: Slave module for boot from SRIO and PCIE
When a b4860qds board boots from SRIO or PCIE, it needs to finish these
processes:
	1. Set all the cores in holdoff status.
	2. Set the boot location to one PCIE or SRIO interface by RCW.
	3. Set a specific TLB entry for the boot process.
	4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
	5. Set a specific TLB entry in order to fetch ucode and ENV from
	   master.
	6. Set a LAW entry with the TargetID one of the PCIE ports for
	   ucode and ENV.
	7. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIO_PCIE_BOOT_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:48 -05:00
Liu Gang
c8b281524b powerpc/boot: Change the macro of Boot from SRIO and PCIE master module
Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable
the master module of Boot from SRIO and PCIE on a platform. But this
is not a silicon feature, it's just a specific booting mode based on
the SRIO and PCIE interfaces. So it's inappropriate to put the macro
into the file arch/powerpc/include/asm/config_mpc85xx.h.

Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to
"CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from
arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros
in configuration header file of each board which can support the
master module of Boot from SRIO and PCIE.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:48 -05:00
Andy Fleming
8bd00c9494 85xx: Change case of MPC85XX_PORBMSR_ROMLOC_SHIFT
All the other constants use lowercase 'x' in "MPC85xx", so we
duplicate that here.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 16:09:09 -05:00
Fabio Estevam
6770c5e2e8 powerpc: Use lower case for the core names
Freescale documentation presents the PowerPC core names in lower case, such as
"e300", "e500", "e600", etc.

Change the upper case occurrences into lower case so that the core names
reported in U-boot can match the ones from the documentation.

While at it also fix a checkpatch error:

ERROR: space prohibited before that close parenthesis ')'
#53: FILE: arch/powerpc/cpu/mpc86xx/cpu.c:81:
+	printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0 );

Reported-by: Heinz Wrobel <heinz.wrobel@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 16:09:09 -05:00
York Sun
061ffedaaf powerpc/BSC9132: Add IFC bank count
BSC9132 has 3 IFC banks.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 16:09:09 -05:00
Priyanka Jain
765b0bdb89 board/bsc9131rdb: Add DSP side tlb and laws
BSC9131RDB is a Freescale Reference Design Board for
BSC9131 SoC which is a integrated device that contains
one powerpc e500v2 core and one DSP starcore.

To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 memory

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 16:09:08 -05:00
Prabhakar Kushwaha
3a88179d03 powerpc/mpc85xx: new SPL support for IFC NAND
Linker script is not able find start.o binary. So add its absolute path in
u-boot-spl.lds. This change is similar to u-boot-nand.lds

common/Makefile: Avoid compiling unnecssary files

fsl_ifc_spl.c : It is is responsible for reading u-boot binary from
NAND flash and copying into DDR. It also transfer control from NAND SPL
to u-boot image present in DDR.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 16:08:58 -05:00
Prabhakar Kushwaha
74fa22ed73 powerpc/mpc85xx:No NOR boot, do not compile IFC errata A003399
IFC errata A003399 is valid for IFC NOR boot i.e.if no on-board NOR flash or
no NOR boot, do not compile its workaround.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 13:51:24 -05:00
Mingkai Hu
76d354f411 powerpc/mpc85xx: explicit cast the SDRAM size to type phys_size_t
To avoid sign extension problem, use explicit casting to cast
the SDRAM size to type phys_size_t, or else, if the SDRAM size
is 2G(0x80000000), it will be extended to 0xffffffff80000000
when phys_size_t is type 'unsigned long long'.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 13:51:24 -05:00
Andy Fleming
7dd09b546d 85xx: Change clock-frequency compatible to 2.0
Accidentally applied an earlier version of the patch, which set
the compatible to "fsl,qoriq-clockgen-2", lacking the final
".0".

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
2013-06-20 13:51:04 -05:00
Scott Wood
a166fbca20 powerpc: fix 8xx and 82xx type-punning warnings with GCC 4.7
C99's strict aliasing rules are insane to use in low-level code such as a
bootloader, but as Wolfgang has rejected -fno-strict-aliasing in the
past, add a union so that 16-bit accesses can be performed.

Compile-tested only.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Wolfgang Denk <wd@denx.de>
2013-06-11 22:01:45 +02:00
Albert ARIBAUD
a19b0dd62d Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	common/cmd_fpga.c
	drivers/usb/host/ohci-at91.c
2013-05-30 14:45:06 +02:00
York Sun
a71d45d706 powerpc/mpc85xx: Clear L1 D-cache lock
dcbi instruction has been used to clear D-cache lock. However, the cache
lock is persistent for e6500 core. Use dcblc to clear the lock explicitly.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:14 -05:00
Ruchika Gupta
39bdaff4f4 SECURE BOOT - Removed deletion of TLB entries code
Boot ROM code creates TLB entries for 3.5G space before entering
the u-boot. Earlier we were deleting these entries after early
initialization of CPU. In recent past, code has been added
to invalidate all these entries before relocation of u-boot code.
So this code to delete TLB entries after CPU initialization
is no longer required.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Acked-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:14 -05:00
Shaveta Leekha
6eaeba23dd powerpc/b4860qds: Add LAW Target ID and Create LAW entry for Maple
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:14 -05:00
Poonam Aggrwal
8fa0102bcf powerpc/B4: Merge B4420 and B4860 in config_mpc85xx.h
B4420 is a subset of B4860. Merge them in config_mpc85xx.h to simplify
the defines.
- Removed #define CONFIG_SYS_FSL_NUM_CLUSTERS as this is used nowhere.
- defined CONFIG_SYS_NUM_FM1_10GEC to 0 for B4420 as it does not have 10G.

Also move CONFIG_E6500 out of B4860QDSds.h into config_mpc85xx.h.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:14 -05:00
York Sun
1b294b7a93 powerpc/mpc8xxx: Allow DDR overclock
Allow DDR clock runs faster than SPD specifes. This may cause memory
failure, but the user should know what is going to happen when using
higher than expected DDR clock.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:11 -05:00
York Sun
f69814397e powerpc/chassis2: Change core numbering scheme
To align with chassis generation 2 spec, all cores are numbered in sequence.
The cores may reside across multiple clusters. Each cluster has zero to four
cores. The first available core is numbered as core 0. The second available
core is numbered as core 1 and so on.

Core clocks are generated by each clusters. To identify the cluster of each
core, topology registers are examined.

Cluster clock registers are reorganized to be easily indexed.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:11 -05:00
York Sun
5f208d118a powerpc/mpc8xxx: Add T1040 and variant SoCs
T1040 and variants have e5500 cores and are compliant to QorIQ Chassis
Generation 2. The major difference between T1040 and its variants is the
number of cores and the number of L2 switch ports.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:11 -05:00
York Sun
3d2972feac powerpc/T4160: Merge T4160 and T4240 in config_mpc85xx.h
T4160 is a subset of T4240. Merge them in config_mpc85xx.h to simplify
the defines. Also move CONFIG_E6500 out of t4qds.h into config_mpc85xx.h.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:11 -05:00
James Yang
9cd95ac74a Add e6500 L2 replacement policy selection
This is compile-time config.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:10 -05:00
York Sun
0c9ab437de powerpc/mpc85xx: check if core is disabled for showing status
"cpu <num> status" should check if core is disabled before printing
the spin table location.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:09 -05:00
James Yang
c416faf84f Enable L2 cache parity/ECC error checking
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:09 -05:00
Tom Rini
fb651b10d4 Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx 2013-05-15 08:41:04 -04:00
Wolfgang Denk
d6ed322222 Power: remove support for Freescale MPC8220
The Freescale MPC8220 Power Architecture processors have long reached
EOL; Freescale does not even list these any more on their web site.

Remove the code to avoid wasting maitaining efforts on dead stuff.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Andy Fleming <afleming@gmail.com>
2013-05-15 08:41:03 -04:00
York Sun
ef00227551 powerpc/mpc8xxx: Allow board file to override DDR address assignment
This gives boards flexibility to assign other than default addresses to each
DDR controller. For example, DDR controler 2 can have 0 as the base and DDR
controller 1 has higher memory.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:13:25 -05:00
York Sun
8444b536c9 powerpc/mpc85xx: Update workaround for DDR erratum A-004934
The workaround has been updated to use a slightly different magic number.
Change from 0x00003000 to 0x30003000.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:13:25 -05:00
Roy Zang
3fa75c875c T4/usb: move usb 2.0 utmi dual phy init code to cpu_init.c
This is what we have done for the UTMI PHY on P3041/P5020. Then the PHY
initialization can be reused in kernel without  “usb start” command.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:13:25 -05:00
Shengzhou Liu
fbe27ce7ba powerpc/85xx: fix build error introduced by serdes_get_prtcl
Removed unused declare serdes_get_prtcl() which was no longer needed.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:13:24 -05:00
Shengzhou Liu
959278083d t4240qds/eth: fixup ethernet for t4240qds
1, Implemented board_ft_fman_fixup_port() to fix port for kernel.
2, Implemented fdt_fixup_board_enet() to fix node status of different
   slots and interfaces.
3, Adding detection of slot present for XGMII interface.
4, There is no PHY for XFI, so removed related phy address settings.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:13:24 -05:00
Shaohui Xie
3e83fc9b4d powerpc/85xx: add missing QMAN frequency calculation
When CONFIG_SYS_FSL_QORIQ_CHASSIS2 is not defined, QMAN frequency will not
be initialized, and QMAN will have a wrong frequency display.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:13:24 -05:00
York Sun
b62408464b powerpc/mpc85xx: Add T4160 SoC
T4160 SoC is low power version of T4240. The T4160 combines eight dual
threaded Power Architecture e6500 cores and two memory complexes (CoreNet
platform cache and DDR3 memory controller) with the same high-performance
datapath acceleration, networking, and peripheral bus interfaces.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:29 -05:00
York Sun
924859ac23 powerpc/t4240: Fix SerDes protocol arrays with const prefix
Protocols are constants. Fix arrays with const prefix.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:29 -05:00
York Sun
615f0cba58 powerpc/mpc85xx: Fix PIR parsing for chassis2
The PIR parsing algorithm we used is not only for E6500. It applies to all
SoCs with chassis 2.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:29 -05:00
York Sun
eb80880eb2 powerpc/corenet2: Print SerDes protocol in decimal
Use decimal and hexadecimal for protocol numbers. It helps to match with
SoC user manual.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:28 -05:00
Roy Zang
1e501f9136 T4/USB: Add USB 2.0 UTMI dual phy support
T4240 internal UTMI phy is different comparing to previous UTMI PHY
in P3041.
This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for
T4240.
The phy timing is very sensitive and moving the phy enable code to
cpu_init.c will not work.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:28 -05:00
York Sun
e1d5a2773f powerpc/mpc85xx: Fix portal setup
Missing nodes of crypto, pme, etc in device tree is not a fatal error.
Setting up the qman portal should skip the missing node and continue
to finish the rest.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:27 -05:00
York Sun
0a7c5353a4 powerpc/mpc8xxx: Fix DDR 3-way interleaving
Should check if interleaving is enabled before using interleaving mode.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:27 -05:00
Roy Zang
f9772444a0 T4/SerDes: correct the SATA index
Lane H on SerDes4 should be SATA2 instead of SATA1

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:26 -05:00
Andy Fleming
3e4c3137d6 e6500: Move L1 enablement after L2 enablement
The L1 D-cache on e6500 is write-through. This means that it's not
considered a good idea to have the L1 up and running if the L2 is
disabled. We don't actually *use* the L1 until after the L2 is
brought up on e6500, so go ahead and move the L1 enablement after
that code is done.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:25 -05:00
York Sun
45c18853d8 powerpc/mpc85xx: Update corenet global utility block registers
Fix ccsr_gur for corenet platform. Remove non-exist registers. Add fuse
status register.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:24 -05:00
Andy Fleming
cd7ad62996 powerpc/mpc85xx: Add definitions for HDBCR registers
Makes it a bit easier to see if we've properly set them. While
we're in there, modify the accesses to HDBCR0 and HDBCR1  to actually
use those definitions.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:24 -05:00
Sandeep Singh
0cb3325cd3 powerpc/B4860: Corrected FMAN1 operating frequency print at u-boot
The bit positions for FMAN1 freq in RCW is different for B4860.
Also addded a case when FMAN1 frewuency is equal to systembus.

Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:24 -05:00
Simon Glass
3e51266a4e powerpc: Use image_setup_linux() instead of local code
Rather than having similar code in powerpc, use image_setup_linux() which
should be common across all architectures that use the FDT.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-14 15:37:25 -04:00
Albert ARIBAUD
ec7023db8d Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Conflicts:
	drivers/mtd/nand/mxc_nand_spl.c
	include/configs/m28evk.h
2013-05-11 09:25:36 +02:00
Tom Rini
3fe0128540 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2013-05-02 19:54:32 -04:00
Cristian Sovaiala
1f06c9af31 powerpc/mpc85xx: Changed LIODN offset values
Extending LIODN offset range from 1-5 to 1-10
While using a qman portal with a higher index the LIODN offset
is incorrectly set, thus extending the range of offsets covers
all 10 qman portals

Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com>
Acked-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:57:34 -05:00
York Sun
e22be77a4a powerpc/mpc85xx: Extend workaround for erratum DDR_A003 to other SoCs
Erratum DDR_A003 applies to P5020, P3041, P4080, P3060, P2041, P5040.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:57:33 -05:00
Timur Tabi
ca9131c056 powerpc/85xx: add SerDes bank 4 lanes
Only some chips have four SerDes banks, so don't define lanes for a bank
that doesn't exist.

Signed-off-by: Timur Tabi <timur@tabi.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:56:45 -05:00
Prabhakar Kushwaha
f153b682b3 powerpc/mpc85xx:IFC Errata A003399 is not valid for BSC913x
As per Errata list of BSC9131 and BSC9132, IFC Errata A003399 is no more
valid. So donot compile its workaround.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:56:44 -05:00
Horst Kronstorfer
df616cae64 mpc85xx: Fix a compiler warning when CONFIG_WATCHDOG is turned on
cpu.c:288:2:
warning: implicit declaration of function 'reset_85xx_watchdog'
[-Wimplicit-function-declaration]

Signed-off-by: Horst Kronstorfer <hkronsto@frequentis.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:56:44 -05:00
Xulei
99d7b0a43d powerpc/85xx: Add workaround for errata USB-14 (enable on P204x/P3041/P50x0)
On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal
multi-bit ECC errors, which has impact on performance, so software should
disable all ECC reporting from USB1 and USB2.

In formal release document, the errata number should be USB14 instead of USB138.

Signed-off-by: xulei <Lei.Xu@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: xulei <B33228@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:56:44 -05:00
Zang Roy-R61911
c5729f0b1f fman/mEMAC: set SETSP bit in IF_MODE regisgter for RGMII speed
Some legacy RGMII phys don't have in band signaling for the
speed information. so set the RGMII MAC mode according to
the speed got from PHY.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Reported-by: John Traill <john.traill@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:56:44 -05:00
Tang Yuantian
7b700d2125 powerpc/mpc85xx: set clock-frequency for T4/B4 clockgen node
For T4/B4, the clockgen node compatible string is updated to version 2.
Add clock-frequency setting for this new version.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:56:43 -05:00
Shengzhou Liu
04feb57f89 powerpc/b4860: Adding workaround errata A-005871
Per the latest errata updated, B4860/B4420 Rev 1.0 has also
errata A-005871, so adding define A-005871 for B4 SoCs.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:56:43 -05:00
Liu Gang
ada961e2fc powerpc/b4: Fix the wrong register offset of B4 PCIE module
B4420/B4860 PCIE can not work because of the wrong definition of
the PCIE register offset in the file:
	arch/powerpc/include/asm/immap_85xx.h

Add the judgement of B4420/B4860 to make the register offset to:
	#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET         0x200000

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:56:43 -05:00
Dongsheng.wang@freescale.com
f5c2623d80 powerpc/mpc85xx: add setting of clock-frequency for mpic node
Set the device tree property associated with the mpic source
frequency. The frequency is used for mpic timer.

Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:56:42 -05:00
Jeffrey Ladouceur
3c1bfc04c6 powerpc/mpc85xx: Add revision properties in portal device tree node 'pme'
The 'fsl,pme-rev1' and 'fsl-pme-rev2' properties have been added to the
pme portal node. This is required for software to determine which version
of PME hardware is present and take appropriate actions.
These properties are a direct reflection of the corresponding ccsr pme
register value.

Also removed unnecessary static global variables.

Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:56:42 -05:00
Tom Rini
e3288e1d15 Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxx 2013-05-02 16:21:20 -04:00
Anatolij Gustschin
b91363cd34 mpc512x: remove dead code
The prt_mpc512x_clks() function isn't referenced
anywhere and its prototype is wrong. Remove it.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-05-02 20:43:38 +02:00
Andreas Bießmann
d2eae43ba8 lib: consolidate hang()
Delete all occurrences of hang() and provide a generic function.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
[trini: Modify check around puts() in hang.c slightly]
Signed-off-by: Tom Rini <trini@ti.com>
2013-05-01 16:41:08 -04:00
Benoît Thébaudeau
83306927de mpc: iim: Switch to common fsl_iim
Make all mpc512x code point to the new common fsl_iim driver, and remove the
former mpc512x-specific iim driver.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28 11:07:41 +02:00
Benoît Thébaudeau
0f67e09e9e Add fsl_iim driver
Add a fsl_iim driver common to i.MX and MPC.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28 11:07:41 +02:00
Stefan Roese
98f99e9f16 ppc4xx: Add SPL support
This patch adds SPL booting support (NOR flash) for the
PPC4xx platforms.

This SPL booting (Falcon mode) will be used by the upcoming
lcd4_lwmon5 board port (lwmon5 variant).

Signed-off-by: Stefan Roese <sr@denx.de>
2013-04-22 09:53:53 +02:00
Tom Rini
980464a4fc Merge branch 'master' of git://git.denx.de/u-boot-usb 2013-04-11 14:31:50 -04:00
Mats Kärrman
fac150e83f powerpc/lib: fix unsafe register handling in wait_ticks
If watchdog is enabled, the arch/powerpc/lib/ticks.S::wait_ticks() function
calls the function specified by the WATCHDOG_RESET macro.
The wait_ticks function depends on the registers r0, r6 and r7 being
preserved however that is not guaranteed, e.g. if the reset function is a
C function this will probably overwrite r0 and cause an endless loop.

The following patch changes to using r14+r15 instead of r6+r7 (to resemble
what would have been generated by a C compiler) and saves all necessary
registers on the stack.

The patch has been tested on a custom MPC5125 based machine using the 512x
powerpc architecture.

Signed-off-by: Mats Karrman <mats.karrman@tritech.se>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Joakim Tjernlund <joakim.tjernlund@transmode.se>
Tested-by: Stefan Roese <sr@denx.de>
2013-04-10 10:31:02 -04:00
ramneek mehresh
dda48e8eff powerpc/usb: Fix usb device-tree fix-up
Fix USB device-tree fixup to properly handle device-tree fixup and
print appropriate message when wrong/junk "dr_mode" or "phy_type"
are mentioned in hwconfig string

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2013-04-10 15:22:25 +02:00
York Sun
472d546054 Consolidate bool type
'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.

All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.

Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-04-01 16:33:52 -04:00
Jeroen Hofstee
59155f4c50 lcd, mpc8xx: move the mpc8xx driver to drivers/video
Since the lcd code was compiled unconditionally in arch also
add CONFIG_MPC8XX_LCD to the boards using this driver.

cc: Anatolij Gustschin <agust@denx.de>
cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2013-03-21 09:17:39 +01:00
Wolfgang Denk
46d1d5dd43 common/lcd.c: cleanup use of global variables
lcd_color_fg and lcd_color_bg had to be declared in board specific
code, but were not actually used there; in addition, we have getter /
setter functions for these, which were not used either.

Get rid of the global variables, and use the getter function where
needed (so far no setter calls are needed).

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Alessandro Rubini <rubini@unipv.it>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stelian Pop <stelian@popies.net>
Cc: Tom Warren <twarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Jeroen Hofstee <jeroen@myspectrum.nl>
[agust: also fixed cm_t35 board while rebasing]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-03-21 09:05:08 +01:00
Tom Rini
0ce033d258 Merge branch 'master' of git://git.denx.de/u-boot-arm
Albert's rework of the linker scripts conflicted with Simon's making
everyone use __bss_end.  We also had a minor conflict over
README.scrapyard being added to in mainline and enhanced in
u-boot-arm/master with proper formatting.

Conflicts:
	arch/arm/cpu/ixp/u-boot.lds
	arch/arm/cpu/u-boot.lds
	arch/arm/lib/Makefile
	board/actux1/u-boot.lds
	board/actux2/u-boot.lds
	board/actux3/u-boot.lds
	board/dvlhost/u-boot.lds
	board/freescale/mx31ads/u-boot.lds
	doc/README.scrapyard
	include/configs/tegra-common.h

Build tested for all of ARM and run-time tested on am335x_evm.

Signed-off-by: Tom Rini <trini@ti.com>
2013-03-18 14:37:18 -04:00
Simon Glass
660c60c4e7 ppc: Enable generic board support
This enables generic board support so that ppc boards can define
CONFIG_SYS_GENERIC_BOARD.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:14:00 -04:00
Simon Glass
6f6430d72b Introduce generic post-relocation board_r.c
This file handles common post-relocation init for boards which use
the generic framework.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:13:59 -04:00
Simon Glass
a6741bce50 Declare watchdog functions in watchdog.h
These functions are only available for powerpc and are not declared in a
header file. We want to use the rest function in two places (board_f and
board_r), so declare the functions in watchdog.h.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:13:59 -04:00
Simon Glass
1865286466 Introduce generic link section.h symbol files
We create a separate header file for link symbols defined by the link
scripts. It is helpful to have these all in one place and try to
make them common across architectures. Since Linux already has a similar
file, we bring this in even though many of the symbols there are not
relevant to us.

Each architecture has its own asm/sections.h where symbols specifc to
that architecture can be added. For now everything except AVR32 just
includes the generic header.

One change is needed in arch/avr32/lib/board.c to make this conversion
work.

Reviewed-by: Tom Rini <trini@ti.com> (version 5)
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:13:58 -04:00
Simon Glass
3929fb0a14 Replace __bss_end__ with __bss_end
Note this is a tree-wide change affecting multiple architectures.

At present we use __bss_start, but mostly __bss_end__. This seems
inconsistent and in a number of places __bss_end is used instead.

Change to use __bss_end for the BSS end symbol throughout U-Boot. This
makes it possible to use the asm-generic/sections.h file on all
archs.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:13:54 -04:00
Albert ARIBAUD
ef123c5253 Refactor linker-generated arrays
Refactor linker-generated array code so that symbols
which were previously linker-generated are now compiler-
generated. This causes relocation records of type
R_ARM_ABS32 to become R_ARM_RELATIVE, which makes
code which uses LGA able to run before relocation as
well as after.

Note: this affects more than ARM targets, as linker-
lists span possibly all target architectures, notably
PowerPC.

Conflicts:
	arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
	arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
	arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
	board/ait/cam_enc_4xx/u-boot-spl.lds
	board/davinci/da8xxevm/u-boot-spl-da850evm.lds
	board/davinci/da8xxevm/u-boot-spl-hawk.lds
	board/vpac270/u-boot-spl.lds

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-03-12 23:28:40 +01:00
Stefan Roese
7c9e89bd1f ppc: Remove PCIPPC2 and PCIPPC6 boards
These boards seem to be unmaintained for quite some time. So lets
remove support for them completely. This also cleans up some
common drivers/files.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Guillaume Alexandre <guillaume.alexandre@gespac.ch>
Acked-by: Wolfgang Denk <wd@denx.de>
2013-03-11 17:00:28 -04:00
Anatolij Gustschin
a615dfda8c mpc512x: Adjust the DRAM init sequence to the datasheet spec
Do maintain a 200 usecs period of stable power and clock before
asserting the CKE signal and sending commands, have at least 200
DRAM clock cycles pass after initialization before data access.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-03-09 08:23:02 +01:00
Anatolij Gustschin
fcc7fe4251 mpc512x: add ifm ac14xx board
Add new mpc5121e based ac14xx board and a new pinmux config
function for setting individual pinmux bit groups. This
function is used in ac14xx board code.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-03-09 08:22:57 +01:00
Anatolij Gustschin
5643709ede mpc512x: allow configuring board specific IPS divider
Boards may define own IPS divider in the config file if
the default IPS divider doesn't fit their needs.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-03-09 08:22:50 +01:00
Anatolij Gustschin
1d63b8ffdb mpc512x: optionally configure DIU, LPC and NFC deviders
If a board config file defines DIU, LPC and NFC deviders,
configure them in the SCFR1 register.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-03-09 08:22:45 +01:00
Anatolij Gustschin
e5f538649c mpc512x: use common code for clock setting for all mpc512x boards
Only define enabled clocks in the config file and enable
the clocks in common code.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Cc: Wolfgang Denk <wd@denx.de>
2013-03-09 08:22:23 +01:00
Anatolij Gustschin
b84d6d27fc mpc512x: add common LAW and Chip Select configuration
Currently each mpc512x board has its own LAW and CS config code,
we should avoid this code duplication. Allow all boards to use
common code by only defining LAW and CS config macros like
CONFIG_SYS_CSx_START, CONFIG_SYS_CSx_SIZE and CONFIG_SYS_CSx_CFG.

Also allow common configuration of additional CS parameters by
CONFIG_SYS_CS_ALETIMING, CONFIG_SYS_CS_BURST, CONFIG_SYS_CS_DEADCYCLE
and CONFIG_SYS_CS_HOLDCYCLE options.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-03-09 08:20:54 +01:00
Stefan Roese
b4dc0bddbf mpc5200: spl_boot.c: Change init oder to first enable printf
On MPC5200, the initial RAM (and gd) is located in the internal
SRAM. So we can actually call the preloader console init code
before calling initdram(). This makes serial output (printf)
available very early, even before SDRAM init, which has been
an U-Boot priciple from day 1.

Signed-off-by: Stefan Roese <sr@denx.de>
2013-03-09 08:14:24 +01:00
Gerald Van Baren
58864ddc72 Clean up libfdt.h includes
The libfdt.h file is the definition file for libfdt.  It is unnecessary
to include other fdt header files (the necessary ones are pulled in
by libfdt.h).

Signed-off-by: Gerald Van Baren <gvb@unssw.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefan Roese <sr@denx.de>
2013-02-08 22:32:38 -05:00
Kim Phillips
8aa5ec6e16 common/fdt_support.c: sparse fixes
trivial:

fdt_support.c:89:64: warning: Using plain integer as NULL pointer
fdt_support.c:325:65: warning: Using plain integer as NULL pointer
fdt_support.c:352:65: warning: Using plain integer as NULL pointer

For the following bad constant expression, We hardcode the max. number of
memory banks to four for the foreseeable future, and add an error with
instructions on what to do once it's exceeded:

fdt_support.c:397:22: error: bad constant expression

For the rest below, sparse found a couple of wrong endian conversions
in of_bus_default_translate() and fdt_get_base_address(), but
otherwise the rest is mostly annotation fixes:

fdt_support.c:64:24: warning: cast to restricted __be32
fdt_support.c:192:21: warning: incorrect type in assignment (different base types)
fdt_support.c:192:21:    expected unsigned int [unsigned] [usertype] tmp
fdt_support.c:192:21:    got restricted __be32 [usertype] <noident>
fdt_support.c:201:21: warning: incorrect type in assignment (different base types)
fdt_support.c:201:21:    expected unsigned int [unsigned] [addressable] [usertype] tmp
fdt_support.c:201:21:    got restricted __be32 [usertype] <noident>
fdt_support.c:304:13: warning: incorrect type in assignment (different base types)
fdt_support.c:304:13:    expected unsigned int [unsigned] [usertype] val
fdt_support.c:304:13:    got restricted __be32 [usertype] <noident>
fdt_support.c:333:13: warning: incorrect type in assignment (different base types)
fdt_support.c:333:13:    expected unsigned int [unsigned] [usertype] val
fdt_support.c:333:13:    got restricted __be32 [usertype] <noident>
fdt_support.c:359:13: warning: incorrect type in assignment (different base types)
fdt_support.c:359:13:    expected unsigned int [unsigned] [usertype] val
fdt_support.c:359:13:    got restricted __be32 [usertype] <noident>
fdt_support.c:373:21: warning: cast to restricted __be32
fdt_support.c:963:48: warning: incorrect type in argument 1 (different base types)
fdt_support.c:963:48:    expected restricted __be32 const [usertype] *p
fdt_support.c:963:48:    got unsigned int [usertype] *<noident>
fdt_support.c:971:48: warning: incorrect type in argument 1 (different base types)
fdt_support.c:971:48:    expected restricted __be32 const [usertype] *p
fdt_support.c:971:48:    got unsigned int [usertype] *<noident>
fdt_support.c:984:29: warning: incorrect type in argument 1 (different base types)
fdt_support.c:984:29:    expected restricted __be32 const [usertype] *cell
fdt_support.c:984:29:    got unsigned int [usertype] *addr
fdt_support.c:996:32: warning: incorrect type in argument 1 (different base types)
fdt_support.c:996:32:    expected restricted __be32 const [usertype] *cell
fdt_support.c:996:32:    got unsigned int [usertype] *addr
fdt_support.c:1041:41: warning: incorrect type in argument 1 (different base types)
fdt_support.c:1041:41:    expected restricted __be32 const [usertype] *cell
fdt_support.c:1041:41:    got unsigned int [usertype] *addr
fdt_support.c:1053:41: warning: incorrect type in argument 2 (different base types)
fdt_support.c:1053:41:    expected restricted __be32 const [usertype] *range
fdt_support.c:1053:41:    got unsigned int const [usertype] *[assigned] ranges
fdt_support.c:1064:53: warning: incorrect type in argument 2 (different base types)
fdt_support.c:1064:53:    expected restricted __be32 const [usertype] *addr
fdt_support.c:1064:53:    got unsigned int [usertype] *addr
fdt_support.c:1110:50: warning: incorrect type in argument 2 (different base types)
fdt_support.c:1110:50:    expected restricted __be32 const [usertype] *addr
fdt_support.c:1110:50:    got unsigned int *<noident>
fdt_support.c:1121:49: warning: incorrect type in argument 1 (different base types)
fdt_support.c:1121:49:    expected restricted __be32 const [usertype] *cell
fdt_support.c:1121:49:    got unsigned int *<noident>
fdt_support.c:1147:60: warning: incorrect type in argument 2 (different base types)
fdt_support.c:1147:60:    expected restricted __be32 const [usertype] *addr
fdt_support.c:1147:60:    got unsigned int *<noident>
fdt_support.c:1081:5: warning: symbol '__of_translate_address' was not declared. Should it be static?
fdt_support.c:1154:5: error: symbol 'fdt_translate_address' redeclared with different type (originally declared at include/fdt_support.h:95) - incompatible argument 3 (different base types)
fdt_support.c: In function 'fdt_node_offset_by_compat_reg':
fdt_support.c:1173:17: warning: initialization discards 'const' qualifier from pointer target type [enabled by default]

See also linux kernel commit 0131d897 "of/address: use proper
endianess in get_flags".

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Jerry Van Baren <gvb.uboot@gmail.com>
2013-02-07 20:38:55 -05:00
Kim Phillips
12e06fe03f treewide: include libfdt_env.h before fdt.h
and, if including libfdt.h which includes libfdt_env.h in
the correct order, don't include fdt.h before libfdt.h.

this is needed to get the fdt type definitions set from
the project environment before fdt.h uses them.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Jerry Van Baren <gvb.uboot@gmail.com>
2013-02-07 20:38:55 -05:00
Simon Glass
2ab575e05d powerpc: Use generic global_data
Move powerpc over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:46 -05:00
Simon Glass
e9adeca3fc ppc: arm: Move sdhc_clk into arch_global_data
This is used by both powerpc and arm, but I think it still qualifies as
architecture-specific.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
225ca83dfe ppc: Move kbd_status to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
a0d3c820c4 ppc: Move wdt_last to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
923a662f2f ppc: Move fpga_state to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
7273ccec61 ppc: Remove console_addr from global data
This does not appear to be used, so punt it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
7e15d6dbf3 ppc: Move mirror_hack to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
3a1dc8f125 arm: Move uart_clk to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
6bb9ba7260 ppc: Move dp_alloc_base, dp_alloc_top to arch_global_data
Move these fields into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
43e60814b3 ppc: Move arbiter fields to arch_global_data
Move arbiter_event_attributes and arbiter_event_address into
arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
3c4c308c00 ppc: Move reset_status to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
1c356135fa ppc: Move mpc8220 clocks to arch_global_data
Move these fields into arch_global_data and tidy up. The bExtUart field
does not appear to be used, so punt it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
fefb098b18 ppc: Move mpc512x clocks to arch_global_data
Move ips_clk and csb_clk into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
b28774966c ppc: Move mpc5xxx clocks to arch_global_data
Move ipb_clk and pci_clk into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
7c80c6c51a ppc: Move used_tlb_cams to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
8670dbc953 ppc: Move used_laws to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
45bae2e3cf ppc: Move CONFIG_QE to arch_global_data
Move the quantative easing fields into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:42 -05:00
Simon Glass
609e6ec3f6 ppc: m68k: Move i2c1_clk, i2c2_clk to arch_global_data
Move these fields into arch_global_data and tidy up. This is needed for
both ppc and m68k since they share the i2c driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:42 -05:00
Simon Glass
67ac13b1b9 ppc: Move lbc_clk and cpu to arch_global_data
Move these fields into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Update for bsc9132qds.c, b4860qds.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-02-04 09:04:57 -05:00
Simon Glass
c6731fe22a ppc: Move mpc83xx clock fields to arch_global_data
Move al mpc83xx fields into arch_global_data and tidy up. Also indent
the nested #ifdef for clarity.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:42:45 -05:00
Simon Glass
748cd0591a ppc: Move clock fields to arch_global_data
Move vco_out, cpm_clk, scc_clk, brg_clk into arch_global_data and tidy
up. Leave pci_clk on its own since this should really depend only on
CONFIG_PCI and not any particular chip type.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:42:45 -05:00
Simon Glass
9fb23624a6 ppc: Remove extra pci_clk fields from global_data
PPC has several of these fields, selected by chip type, although only one
is ever compiled in.

Instead, use a single field. It would be nice if this could be selected
by CONFIG_PCI, but some chips (e.g. mpc5xxx) use pci_clk even when
CONFIG_PCI is not enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:42:45 -05:00
Simon Glass
1206c18403 ppc: Move brg_clk to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:42:45 -05:00
Simon Glass
5cb48582ac Add architecture-specific global data
We plan to move architecture-specific data into a separate structure so
that we can make the rest of it common.

As a first step, create struct arch_global_data to hold these fields.
Initially it is empty.

This patch applies to all archs at once. I can split it if this is really
a pain.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:49 -05:00
Shengzhou Liu
72bd83cd0a powerpc/t4240: Adding workaround errata A-005871
When CoreNet Fabric (CCF) internal resources are consumed by the cores,
inbound SRIO messaging traffic through RMan can put the device into a
deadlock condition.

This errata workaround forces internal resources to be reserved for
upstream transactions. This ensures resources exist on the device for
upstream transactions and removes the deadlock condition.

The Workaround is for the T4240 silicon rev 1.0.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:15 -06:00
Vakul Garg
5e95e2d84b powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto'
If property 'fsl,sec-era' is already present, it is updated.
This property is required so that applications can ascertain which
descriptor commands are supported on a particular CAAM version.

Signed-off-by: Vakul Garg <vakul@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:15 -06:00
Anatolij Gustschin
5b93394318 mpc8xxx: fix DDR init value to use CONFIG_MEM_INIT_VALUE
Configuring custom memory init value using CONFIG_MEM_INIT_VALUE in
the board config file doesn't work and memory is always initialized
to the value 0xdeadbeef. Only use this default value if a board doesn't
define CONFIG_MEM_INIT_VALUE.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:15 -06:00
Scott Wood
31d084ddda powerpc/mpc85xx: add support for MMUv2 page sizes
e6500 implements MMUv2 and supports power-of-2 page sizes rather than
power-of-4.  Add support for such pages.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:15 -06:00
Prabhakar Kushwaha
35fe948e3b powerpc/mpc85xx: Add BSC9132/BSC9232 processor support
The BSC9132 is a highly integrated device that targets the evolving
 Microcell, Picocell, and Enterprise-Femto base station market subsegments.

 The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
 core technologies with MAPLE-B2P baseband acceleration processing elements
 to address the need for a high performance, low cost, integrated solution
 that handles all required processing layers without the need for an
 external device except for an RF transceiver or, in a Micro base station
 configuration, a host device that handles the L3/L4 and handover between
 sectors.

 The BSC9132 SoC includes the following function and features:
    - Power Architecture subsystem including two e500 processors with
	512-Kbyte shared L2 cache
    - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
	cache
    - 32 Kbyte of shared M3 memory
    - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
      Processing (MAPLE-B2P)
    - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
      ECC), up to 1333 MHz data rate
    - Dedicated security engine featuring trusted boot
    - Two DMA controllers
         - OCNDMA with four bidirectional channels
         - SysDMA with sixteen bidirectional channels
    - Interfaces
        - Four-lane SerDes PHY
	    - PCI Express controller complies with the PEX Specification-Rev 2.0
        - Two Common Public Radio Interface (CPRI) controller lanes
	    - High-speed USB 2.0 host and device controller with ULPI interface
        - Enhanced secure digital (SD/MMC) host controller (eSDHC)
	    - Antenna interface controller (AIC), supporting four industry
		standard JESD207/four custom ADI RF interfaces
       - ADI lanes support both full duplex FDD support & half duplex TDD
       - Universal Subscriber Identity Module (USIM) interface that
	   facilitates communication to SIM cards or Eurochip pre-paid phone
	   cards
       - Two DUART, two eSPI, and two I2C controllers
       - Integrated Flash memory controller (IFC)
       - GPIO
     - Sixteen 32-bit timers

Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:14 -06:00
James Yang
e8ba6c503f powerpc/mpc8xxxx: FSL DDR debugger auto run of stored commands
This patch adds the ability for the FSL DDR interactive debugger to
automatically run the sequence of commands stored in the ddr_interactive
environment variable.  Commands are separated using ';'.

ddr_interactive=compute; edit c0 d0 dimmparms caslat_X 0x3FC0; go

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:14 -06:00
James Yang
5926ee3800 Add copy command to FSL DDR interactive
Add copy command which allows copying of DIMM/controller settings.
This saves tedious retyping of parameters for each identical DIMM
or controller.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:13 -06:00
James Yang
992f2fb28c Fix data stage name matching issue
This fix allows the name of the stage to be specifed after the
controler and DIMM is specified.  Prior to this fix, if the
data stage name is not the first entry on the command line,
the operation is applied to all controller and DIMMs.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:13 -06:00
James Yang
bf4189307f Move DDR command parsing to separate function
Move the FSL DDR prompt command parsing to a separate function
so that it can be reused.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:13 -06:00
York Sun
e750cfaa01 powerpc/mpc8xxx: Enable entering DDR debugging by key press
Using environmental variable "ddr_interactive" to activate interactive DDR
debugging seomtiems is not enough. For example, after updating SPD with a
valid but wrong image, u-boot won't come up due to wrong DDR configuration.
By enabling key press method, we can enter debug mode to have a chance to
boot without using other tools to recover the board.

CONFIG_FSL_DDR_INTERACTIVE needs to be defined in header file. To enter the
debug mode by key press, press key 'd' shortly after reset, like one would
do to abort auto booting. It is fixed to lower case 'd' at this moment.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:12 -06:00
Prabhakar Kushwaha
db9a807054 powerpc/mpc85xx:Fix Core cluster configuration loop
Different personalities/derivatives of SoC may have reduced cluster. But it is
not necessary for last valid DCFG_CCSR_TP_CLUSTER register to have
DCFG_CCSR_TP_CLUSTER[EOC] bit set to represent "End of Clusters".

EOC bit can still be set in last DCFG_CCSR_TP_CLUSTER register of orignal SoC
which may not be valid for the personality.
So add initiator type check to find valid cluster.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:10 -06:00
Poonam Aggrwal
e1dbdd8152 powerpc/mpc85xx:Add support of B4420 SoC
B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900
and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and
reduced target frequencies.

Key differences between B4860 and B4420
----------------------------------------
B4420 has:
1. Fewer e6500 cores: 1 cluster with 2 e6500 cores
2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster.
3. Single DDRC
4. 2X 4 lane serdes
5. 3 SGMII interfaces
6. no sRIO
7. no 10G

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:10 -06:00
Poonam Aggrwal
e394ceb17f powerpc/mpc85xx: Few updates for B4860 cpu changes
- Added some more serdes1 and serdes2 combinations
  serdes1= 0x2c, 0x2d, 0x2e
  serdes2= 0x7a, 0x8d, 0x98
- Updated Number of DDR controllers to 2.
- Added FMAN file for B4860, drivers/net/fm/b4860.c

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:10 -06:00
York Sun
2d9f26b693 powerpc/mpc85xx: Reserve default boot page
The boot page in memory is already reserved so OS won't overwrite.
As long as the boot page translation is active, the default boot page
also needs to be reserved in case the memory is 4GB or more.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:08 -06:00
Scott Wood
06f60ae3e4 powerpc/mpc83xx: add support for new SPL
This adds arch support for PPC mpc83xx to boot "minimal" (4K) SPLs
using the new infrastructure.

Existing nand_spl targets are updated to deal with the name change
from nand_init.c to spl_minimal.c (as in theory this isn't limited
to NAND anymore).

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-12-19 17:45:44 -06:00
Joe Hershberger
ec8a252cd4 env: Use getenv_yesno() more generally
Move the getenv_yesno() to env_common.c and change most checks for
'y' or 'n' to use this helper.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-12-13 11:46:55 -07:00
Simon Glass
b1f17bf5ff Add strcasecmp() and strncasecmp()
strncasecmp() is present as strnicmp() but disabled. Make it available
and define strcasecmp() also. There is a only a small performance penalty
to having strcasecmp() call strncasecmp(), so do this instead of a
standalone function, to save code space.

Update the prototype in arch-specific headers as needed to avoid warnings.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-11 13:17:34 -07:00
Stefan Roese
083f2e08d2 mpc5200: Add SPL support
This patch adds SPL booting support (NOR flash) for the
MPC5200 platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05 17:30:51 +01:00
Stefan Roese
ea8256f072 SPL: Port SPL framework to powerpc
This patch enables the SPL framework to be used on powerpc platforms
and not only ARM.

timer_init() does not exist on PPC systems. The timer (decrementer) is
initialized and enabled in interrupt_init() here. And currently
interrupt_init() is called after relocation to SDRAM. Since the only
powerpc SPL implementation (a3m071) doesn't need a timer, let's remove
this timer_init() call for PPC systems.

Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05 17:30:22 +01:00
Stefan Roese
966b11c749 powerpc: Extract EPAPR_MAGIC constants into processor.h
By extracting these defines into a header, they can be re-used by other
C sources as well. This will be done by the SPL framework OS boot
support.

Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05 17:27:02 +01:00
York Sun
afbfdf5450 powerpc/mpc85xx: Fix a bug introduced by CONFIG_PPC_SPINTABLE_COMPATIBLE
Fix a bug introduced by this patch
powerpc/mpc85xx: Temporary fix for spin table backward compatibility

Should have checked both CONFIG_PPC_SPINTABLE_COMPATIBLE and CONFIG_MP in
cpu_init.c.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:08 -06:00
Timur Tabi
b25f6de7c0 powerpc/85xx: update the work-around for P4080 erratum SERDES-9
The documented work-around for P4080 erratum SERDES-9 has been updated.
It is now compatible with the work-around for erratum A-4580.

This requires adding a few bitfield macros for the BnTTLCRy0 register.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:07 -06:00
Yuanquan Chen
c0a4e6b889 powerpc/p4080ds: fix PCI-e x8 link training down failure
Due to SerDes configuration error, if we set the PCI-e controller link width
as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to
PCI-e slot, it fails to train down to the PCI-e device's link width. According
to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in
u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between
RC and EP.

Signed-off-by: Yuanquan Chen <B41889@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:07 -06:00
Zang Roy-R61911
9760b274df powerpc/corenet_ds: move SATA config to board configuration
board configuration file is included before asm/config_mpc85xx.h.
however, CONFIG_FSL_SATA_V2 is defined in asm/config_mpc85xx.h.
it will never take effective in the board configuration file for
this kind of code :

 #ifdef CONFIG_FSL_SATA_V2
 ...
 #endif

To solve this problem, move CONFIG_FSL_SATA_V2 to board
configuration header file.

This patch reverts Timur's
commit:3e0529f742e893653848494ffb9f7cd0d91304bf

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:07 -06:00
Timur Tabi
d607b9684b powerpc/85xx: implement check for erratum A-004580 work-around
The work-around for erratum A-004580 ("Internal tracking loop can falsely
lock causing unrecoverable bit errors") is implemented via the PBI
(pre-boot initialization code, typically attached to the RCW binary).
This is because the work-around is easier to implement in PBI than in
U-Boot itself.

It is still useful, however, for the 'errata' command to tell us whether
the work-around has been applied.  For A-004580, we can do this by verifying
that the values in the specific registers that the work-around says to
update.

This change requires access to the SerDes lane sub-structure in
serdes_corenet_t, so we make it a named struct.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:07 -06:00
Kim Phillips
345d6efdc7 powerpc/mpc8xxx: take fdt_fixup_crypto_node() off the checkstack list
by moving compat_strlist into the .bss section.

0xfe004d80 fdt_fixup_crypto_node [u-boot]:		264

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:07 -06:00
York Sun
2a5fcb835f powerpc/mpc85xx: Temporary fix for spin table backward compatibility
Once u-boot sets the spin table to cache-enabled memory, old kernel which
uses cache-inhibit mapping without coherence will not work properly. We
use this temporary fix until kernel has updated its spin table code.
For now this fix is activated by default. To disable this fix for new
kernel, set environmental variable "spin_table_compat=no". After kernel
has updated spin table code, this default shall be changed.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:06 -06:00
Timur Tabi
0118033b67 powerpc/85xx: implement check for erratum A-004849 work-around
The work-around for erratum A-004849 ("CoreNet fabric (CCF) can exhibit a
deadlock under certain traffic patterns causing the system to hang") is
implemented via the PBI (pre-boot initialization code, typically attached
to the RCW binary).  This is because the work-around is easier to implement
in PBI than in U-Boot itself.

It is still useful, however, for the 'errata' command to tell us whether
the work-around has been applied.  For A-004849, we can do this by verifying
that the values in the specific registers that the work-around says to
update.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:06 -06:00
Timur Tabi
1956e431f8 powerpc/85xx/p5040: add CONFIG_SYS_PPC64, del CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
The P5040 has an e5500 core, so CONFIG_SYS_PPC64 should be defined in
config_mpc85xx.h.  This macro was absent in the initial P5040 patch because
it crossed paths with the patch that introduced the macro.

Also delete CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC, since it's not used in the
upstream U-Boot.  It's a holdover from the SDK.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:05 -06:00
Andy Fleming
e76cd5d4cf 8xxx: Change all 8*xx_DDR addresses to 8xxx
There were a number of shared files that were using
CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and
several variants (DDR2, DDR3). A recent patchset added
85xx-specific ones to code which was used by 86xx systems.
After reviewing places where these constants were used, and
noting that the type definitions of the pointers assigned to
point to those addresses were the same, the cleanest approach
to fixing this problem was to unify the namespace for the
85xx, 83xx, and 86xx DDR address definitions.

This patch does:

s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g

All 85xx, 86xx, and 83xx have been built with this change.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Andy Fleming <afleming@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-27 17:45:17 -06:00
Tom Rini
dfe161032d Merge branch 'master' of git://git.denx.de/u-boot-nand-flash 2012-11-26 14:53:33 -07:00
Scott Wood
c97cd1ba48 spl/85xx: new SPL support
Update CONFIG_RAMBOOT and CONFIG_NAND_SPL references to accept CONFIG_SPL
and CONFIG_SPL_BUILD, respectively.  CONFIG_NAND_SPL can be removed once
the last mpc85xx nand_spl target is gone.

CONFIG_RAMBOOT will need to remain for other use cases, but it doesn't
seem right to overload it for meaning SPL as well as nand_spl does.  Even
if it's somewhat appropriate for the main u-boot, the SPL itself isn't
(necessarily) ramboot, and we don't have separate configs for SPL and
main u-boot.  It was also inconsistent, as other platforms such as
mpc83xx didn't use CONFIG_RAMBOOT in this way.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:25 -06:00
Scott Wood
4b919725b6 spl/powerpc: introduce CONFIG_SPL_INIT_MINIMAL
cpu_init_nand.c is renamed to spl_minimal.c as it is not really NAND-specific.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
v2: factor out START, and change cpu_init_nand.c to spl_minimal.c
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:24 -06:00
Scott Wood
a179eb0a4b powerpc/mpc85xx: consistently use COBJS-y
A subsequent patch will conditionalize some of the files that are
currently unconditional.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:24 -06:00
Scott Wood
b9735cbaeb spl/mpc85xx: rename cpu_init_nand.c to spl_minimal.c
There is nothing really NAND-specific about this file.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:24 -06:00
Scott Wood
59629c2897 spl/mpc85xx: move udelay to cpu code
It applies to non-Freescale 85xx boards as well as Freescale boards,
so it doesn't belong in board/freescale.  Plus, it needs to come out
of nand_spl if it's to be used by the new SPL.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:23 -06:00
Scott Wood
8bc50f0b6d powerpc/mpc8xxx: move LAW code into arch/powerpc/cpu/mpc8xxx
It's arch code and not a driver, so move it where it belongs.  When it
originally went into drivers/misc there was no 8xxx CPU directory.

This will make new-SPL support a little easier since we can keep the CPU
stuff together and not need to pull stuff in from drivers/misc.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:22 -06:00
Scott Wood
7f0a22ff25 powerpc/mpc85xx: fix TLB alignment
In the RAMBOOT/SPL case we were creating a TLB entry starting at
CONFIG_SYS_MONITOR_BASE, and just hoping that the base was properly
aligned for the TLB entry size.  This turned out to not be the case
with NAND SPL because the main U-Boot starts at an offset into the image
in order to skip the SPL itself.

Fix the TLB entry to always start at a proper alignment.  We still assume that
CONFIG_SYS_MONITOR_BASE doesn't start immediately before a large-page boundary
thus requiring multiple TLB entries.

Signed-off-by: Scott Wood <scottwood@frescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:22 -06:00
Scott Wood
6ec63f411e powerpc: change .fixup test to a GCC version test
This was introduced by commit 2446151974, but it
fails in a minimal SPL build where the only thing in arch/powerpc/lib is
cache.c, which apparently doesn't generate any fixup records.

The problem is reported to occur with GCC 3.x, so insist on GCC 4.0 or newer.
Patterned after checkthumb as suggested by Tom Rini.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Tom Rini <trini@ti.com>
--
v2: test gcc version instead of testing nothing
2012-11-26 15:41:22 -06:00
Scott Wood
9a511bd6a3 powerpc/mpc85xx: add comma before "already enabled"
Now outputs like this:

L2:    512 KB already enabled, moving to 0xf8f80000

rather than this:

L2:    512 KB already enabledmoving to 0xf8f80000

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
2012-11-26 15:41:20 -06:00
Scott Wood
f545d300b0 powerpc/mpc85xx: move debug tlb entry after TLB is in known state
Previously, in many if not all configs we were creating overlapping TLB entries
which is illegal.  This caused a crash during boot when moving p2020rdb NAND SPL
into L2 SRAM.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Prabhakar Kushwaha <prabhakar@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
--
Prabhakar, please test that debug still works.
2012-11-26 15:41:20 -06:00
Ilya Yanok
c60795f41d usb: use linux/usb/ch9.h instead of usbdescriptors.h
Linux usb/ch9.h seems to have all the same information (and more)
as usbdescriptors.h so use the former instead of the later one.

As a consequense of this change USB_SPEED_* values don't correspond
directly to EHCI speed encoding anymore, I've added necessary
recoding in EHCI driver. Also there is no point to put speed into
pipe anymore so it's removed and a bunch of host drivers fixed to
look at usb_device->speed instead.

Old usbdescriptors.h included is not removed as it seems to be
used by old USB device code.

This makes usb.h and usbdevice.h incompatible. Fortunately the
only place that tries to include both are the old MUSB code and
it needs usb.h only for USB_DMA_MINALIGN used in aligned attribute
on musb_regs structure but this attribute seems to be unneeded
(old MUSB code doesn't support any DMA at all).

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-11-20 00:16:06 +01:00
Kim Phillips
a2873bde4c powerpc/mpc83xx: sparse fixes
fdt.c:91:78: warning: Using plain integer as NULL pointer
fdt.c:103:78: warning: Using plain integer as NULL pointer
speed.c:55:11: warning: symbol 'corecnf_tab' was not declared. Should it be static?
speed.c:519:5: warning: symbol 'do_clocks' was not declared. Should it be static?
mpc8313erdb.c:73:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:74:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:75:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:76:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:79:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:80:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:81:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:82:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:85:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:86:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:87:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:88:17: warning: obsolete struct initializer, use C99 syntax

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04 11:00:37 -07:00
Kim Phillips
e56143e54f powerpc/mpc85xx: sparse fixes
fsl_corenet_serdes.c:485:6: warning: symbol '__soc_serdes_init' was not declared. Should it be static?
cpu_init.c:185:6: warning: symbol 'invalidate_cpc' was not declared. Should it be static?
bcsr.c:28:27: warning: non-ANSI function declaration of function 'enable_8568mds_duart'
bcsr.c:39:33: warning: non-ANSI function declaration of function 'enable_8568mds_flash_write'
bcsr.c:46:34: warning: non-ANSI function declaration of function 'disable_8568mds_flash_write'
bcsr.c:53:29: warning: non-ANSI function declaration of function 'enable_8568mds_qe_mdio'
bcsr.c:28:33: warning: non-ANSI function declaration of function 'enable_8569mds_flash_write'
bcsr.c:33:34: warning: non-ANSI function declaration of function 'disable_8569mds_flash_write'
bcsr.c:38:28: warning: non-ANSI function declaration of function 'enable_8569mds_qe_uec'
bcsr.c:63:47: warning: non-ANSI function declaration of function 'disable_8569mds_brd_eeprom_write_protect'
ngpixis.c:245:1: error: directive in argument list
ngpixis.c:247:1: error: directive in argument list

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04 11:00:36 -07:00
Kim Phillips
2ed2e9121f arch/powerpc/cpu/mpc8xxx/: sparse fixes
ctrl_regs.c:31:5: warning: symbol 'fsl_ddr_get_version' was not declared. Should it be static?
cpu.c:135:14: warning: non-ANSI function declaration of function 'cpu_mask'
cpu.c:154:18: warning: non-ANSI function declaration of function 'cpu_numcores'
cpu.c:37:17: warning: symbol 'cpu_type_list' was not declared. Should it be static?
cpu.c:117:17: warning: symbol 'cpu_type_unknown' was not declared. Should it be static?
fsl_lbc.c:14:6: warning: symbol '__lbc_sdram_init' was not declared. Should it be static?

and:

lc_common_dimm_params.c:15:1: warning: symbol 'compute_cas_latency_ddr3' was not declared. Should it be static?

making it static produces the following compiler warning:

lc_common_dimm_params.c:15:1: warning: 'compute_cas_latency_ddr3' defined but not used [-Wunused-function]

so we protect it with the preprocessor.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04 11:00:36 -07:00
Kim Phillips
20051f2ab2 arch/powerpc/lib/board.c, *traps.c: sparse fixes
traps.c:*:1: warning: symbol 'print_backtrace' was not declared. Should it be static?
traps.c:93:1: warning: symbol '_exception' was not declared. Should it be static?
board.c:166:6: warning: symbol '__board_add_ram_info' was not declared. Should it be static?
board.c:174:5: warning: symbol '__board_flash_wp_on' was not declared. Should it be static?
board.c:187:6: warning: symbol '__cpu_secondary_init_r' was not declared. Should it be static?
board.c:265:12: warning: symbol 'init_sequence' was not declared. Should it be static?
board.c:348:5: warning: symbol '__fixup_cpu' was not declared. Should it be static?
board.c:405:53: warning: Using plain integer as NULL pointer

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04 11:00:35 -07:00
Kim Phillips
fe44f452db arch/powerpc/lib/extable.c: sparse fix
extable.c:66:9: warning: symbol 'ex_tab_message' was not declared. Should it be static?

making it static can produce a new build warning on some boards:

extable.c:66:12: warning: 'ex_tab_message' defined but not used [-Wunused-variable]

but ex_tab_message doesn't do much even when used, so just remove it.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04 11:00:35 -07:00
Kim Phillips
cdfdb8d7f3 arch/powerpc/include/asm/io.h: fix warning: preprocessor token __iomem redefined
a fixup __iomem definition in arch code appears to be placed there as a cover
up from a code import from linux when u-boot didn't yet have a compiler.h,
introduced by commit 812711ce6b "Implement
__raw_{read,write}[bwl] on all architectures".

git show 812711ce6b3a386125dcf0d6a59588e461abbb87:include/linux/compiler.h
fatal: Path 'include/linux/compiler.h' exists on disk, but not in '812711ce6b3a386125dcf0d6a59588e461abbb87'.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04 11:00:35 -07:00
Kim Phillips
eef1cf2d5c include/linux/byteorder: import latest endian definitions from linux
u-boot's byteorder headers did not contain endianness attributions
for use with sparse, causing a lot of false positives.  Import the
kernel's latest definitions, and enable them by including compiler.h
and types.h.  They come with 'const' added for some swab functions, so
fix those up, too:

include/linux/byteorder/big_endian.h:46:2: warning: passing argument 1 of '__swab64p' discards 'const' qualifier from pointer target type [enabled by default]

Also, note: u-boot's historic __BYTE_ORDER definition has been
preserved (for the time being at least).

We also remove ad-hoc barrier() definitions, since we're including
compiler.h in files that hadn't in the past:

macb.c:54:0: warning: "barrier" redefined [enabled by default]

In addition, including compiler.h in byteorder changes the 'noinline'
definition to expand to __attribute__((noinline)).  This fixes
arch/powerpc/lib/bootm.c:

bootm.c:329:16: error: attribute '__attribute__': unknown attribute
bootm.c:329:16: error: expected ')' before '__attribute__'
bootm.c:329:25: error: expected identifier or '(' before ')' token

powerpc sparse builds yield:

include/common.h:356:22: error: marked inline, but without a definition

the unknown-reason inlining without a definition is considered obsolete
given it was part of the 2002 initial commit, and no arm version was
'fixed.'

also fixed:
ydirectenv.h:60:0: warning: "inline" redefined [enabled by default]

and:

Configuring for devconcenter - Board: intip, Options: DEVCONCENTER
make[1]: *** [4xx_ibm_ddr2_autocalib.o] Error 1
make: *** [arch/powerpc/cpu/ppc4xx/libppc4xx.o] Error 2
powerpc-fsl-linux-size: './u-boot': No such file
4xx_ibm_ddr2_autocalib.c: In function 'DQS_autocalibration':
include/asm/ppc4xx-sdram.h:1407:13: sorry, unimplemented: inlining failed in call to 'ppc4xx_ibm_ddr2_register_dump': function body not available
4xx_ibm_ddr2_autocalib.c:1243:32: sorry, unimplemented: called from here

and:

In file included from crc32.c:50:0:
crc32table.h:4:1: warning: implicit declaration of function '___constant_swab32' [-Wimplicit-function-declaration]
crc32table.h:4:1: error: initializer element is not constant
crc32table.h:4:1: error: (near initialization for 'crc32table_le[0]')

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
[trini: Remove '#endif' in include/common.h around setenv portion]
Signed-off-by: Tom Rini <trini@ti.com>
2012-11-04 11:00:34 -07:00
Wolfgang Denk
1b0757eced PPC: remove dead boards (AMX860, c2mon, ETX094, IAD210, LANTEC, SCM)
These boards have long reached EOL, and there has been no indication
of any active users of such hardware for years.  Get rid of the dead
weight.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Wolfgang Grandegger <wg@denx.de>
2012-10-28 20:17:25 +01:00
Gerlando Falauto
a88731a6c2 mpc83xx: add support for mpc8309
This processor, though very similar to other members of the
PowerQUICC II Pro family (namely 8308, 8360 and 832x), provides
yet another feature set than any supported sibling.

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-10-23 15:23:26 -05:00
Gerlando Falauto
8afad91f15 cleanup: introduce CONFIG_MPC830x
Introduce a new configuration token CONFIG_MPC830x to be shared among
mpc8308 and mpc8309. Define it for existing 8308 boards, and refactor
existing common code so to make future introduction of 8309 simpler.

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-10-23 15:23:25 -05:00
Gerlando Falauto
4b5282de99 cleanup: use CONFIG_QE instead of CONFIG_MPC8360 || CONFIG_MPC832x
simplify #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
for qe variables
with #if defined(CONFIG_QE)

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-10-23 15:23:25 -05:00
Tom Rini
c7656bab41 Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx 2012-10-22 16:54:38 -07:00
Andy Fleming
23028d69e9 85xx: Protect timeout_save variable with ifdefs
The timeout_save variable was only used by the DDR111_134
erratum code. It was being set, but never used. Newer compilers
will actually complain about this.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 17:28:18 -05:00
Liu Gang
19e4a00965 powerpc/boot: Change the compile macro for SRIO & PCIE boot master module
Currently, the SRIO and PCIE boot master module will be compiled into the
u-boot image if the macro "CONFIG_FSL_CORENET" has been defined. And this
macro has been included by all the corenet architecture platform boards.
But in fact, it's uncertain whether all corenet platform boards support
this feature.

So it may be better to get rid of the macro "CONFIG_FSL_CORENET", and add
a special macro for every board which can support the feature. This
special macro will be defined in the header file
"arch/powerpc/include/asm/config_mpc85xx.h". It will decide if the SRIO
and PCIE boot master module should be compiled into the board u-boot image.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 15:52:46 -05:00
Haiying Wang
990e1a8ce1 poweprc/85xx: add QMan frequency info and fdt fixup.
Starting from QMan3.0, the QMan clock cycle needs be exposed so that the kernel
driver can use it to calculate the shaper prescaler and rate.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 15:52:46 -05:00
Haiying Wang
b0e8115741 mpc85xx/portals: Add qman and bman ip_cfg field into portal info
Because QMan3.0 and BMan2.1 used ip_cfg in ip_rev_2 register to differ the
total portal number, buffer pool number etc, we can use this info to limit
those resources in kernel driver.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 15:52:46 -05:00
York Sun
98ffa19053 powerpc/mpc85xx: Add CONFIG_DDR_CLK_FREQ for corenet platform
New corenet platforms with chassis2 have separated DDR clock inputs. Use
CONFIG_DDR_CLK_FREQ for DDR clock. This patch also cleans up the logic of
detecting and displaying synchronous vs asynchronous mode.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:33 -05:00
York Sun
ffd06e0231 powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.

'M' bit is set for DDR TLB to maintain cache coherence.

See details in doc/README.mpc85xx-spin-table.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:32 -05:00
York Sun
3f0997b325 powerpc/mpc85xx: Remove R6 from spin table
R6 was in ePAPR draft version but was dropped in official spec.
Removing it to comply.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:31 -05:00
York Sun
82968a7ab5 powerpc/mpc8xxx: Fix DDR SPD failed message
Since empty DIMM slot is allowed on other than the first slot, remove the
error message if SPD is not found in this case.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:31 -05:00
York Sun
89b7809568 powerpc/mpc8xxx: Add auto select bank interleaving mode
Based on populated DIMMs, automatically select from cs0_cs1_cs2_cs3 or
cs0_cs1 interleaving, or non-interleaving if not available.

Fix the message of interleaving disabled if controller interleaving
is enabled but DIMMs don't support it.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:30 -05:00
York Sun
a1d558a20f powerpc/mpc85xx: Add workaround for DDR erratum A004934
After DDR controller is enabled, it performs a calibration for the
transmit data vs DQS paths. During this calibration, the DDR controller
may make an inaccurate calculation, resulting in a non-optimal tap point.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:29 -05:00
York Sun
eb53941206 powerpc/mpc85xx: software workaround for DDR erratum A-004468
Boot space translation utilizes the pre-translation address to select
the DDR controller target. However, the post-translation address will be
presented to the selected DDR controller. It is possible that the pre-
translation address selects one DDR controller but the post-translation
address exists in a different DDR controller when using certain DDR
controller interleaving modes. The device may fail to boot under these
circumstances. Note that a DDR MSE error will not be detected since DDR
controller bounds registers are programmed to be the same when configured
for DDR controller interleaving.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:28 -05:00
York Sun
f31cfd1925 powerpc/mpc8xxx: Fix DDR initialization waiting for D_INIT
When ECC is enabled, DDR controller needs to initialize the data and ecc.
The wait time can be calcuated with total memory size, bus width, bus speed
and interleaving mode. If it went wrong, it is bettert to timeout than
waiting for D_INIT to clear, where it probably hangs.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:27 -05:00
York Sun
123922b1e5 powerpc/mpc8xxx: Fix DDR driver handling quad-rank DIMMs and address calculation
Fix handling quad-rank DIMMs in a system with two DIMM slots and first
slot supports both dual-rank DIMM and quad-rank DIMM.

For systems with quad-rank DIMM and double dual-rank DIMMs, cs_config
registers need to be enabled to maintain proper ODT operation. The
inactive CS should have bnds registers cleared.

Fix the turnaround timing for systems with all chip-selects enabled. This
wasn't an issue before because DDR was running lower than 1600MT/s with
this interleaving mode.

Fix DDR address calculation. It wasn't an issue until we have multiple
controllers with each more than 4GB and interleaving is disabled.

It also fixes the message of DDR: 2 GiB (DDR3, 64-bit, CL=0.5, ECC off)
when debugging DDR and first DDR controller is disabled. With the fix,
the first enabled controller information will be displayed.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:26 -05:00
York Sun
57495e4e5e powerpc/mpc8xxx: Update DDR registers
DDRC ver 4.7 adds DDR_SLOW bit in sdram_cfg_2 register. This bit needs to be
set for speed lower than 1250MT/s.

CDR1 and CDR2 are control driver registers. ODT termination valueis for
IOs are defined. Starting from DDRC 4.7, the decoding of ODT for IOs is
	000 -> Termsel off
	001 -> 120 Ohm
	010 -> 180 Ohm
	011 -> 75 Ohm
	100 -> 110 Ohm
	101 -> 60 Ohm
	110 -> 70 Ohm
	111 -> 47 Ohm

Add two write leveling registers. Each QDS now has its own write leveling
start value. In case of zero value, the value of QDS0 will be used. These
values are board-specific and are set in board files.

Extend DDR register timing_cfg_1 to have 4 bits for each field.

DDR control driver registers and write leveling registers are added to
interactive debugging for easy access.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:26 -05:00
Roy Zang
111fd19e3b fm/mEMAC: add mEMAC frame work
The multirate ethernet media access controller (mEMAC) interfaces to
10Gbps and below Ethernet/IEEE 802.3 networks via either RGMII/RMII
interfaces or XAUI/XFI/SGMII/QSGMII using the high-speed SerDes interface.

Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:25 -05:00
York Sun
d2404141f9 powerpc/mpc85xx: Add B4860 and variant SoCs
Add support for Freescale B4860 and variant SoCs. Features of B4860 are
(incomplete list):

Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
    clusters-each core runs up to 1.2 GHz, with an architecture highly
    optimized for wireless base station applications
Four dual-thread e6500 Power Architecture processors organized in one
    cluster-each core runs up to 1.8 GHz
Two DDR3/3L controllers for high-speed, industry-standard memory interface
    each runs at up to 1866.67 MHz
MAPLE-B3 hardware acceleration-for forward error correction schemes
    including Turbo or Viterbi decoding, Turbo encoding and rate matching,
    MIMO MMSE equalization scheme, matrix operations, CRC insertion and
    check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration,
    and UMTS chip rate acceleration
CoreNet fabric that fully supports coherency using MESI protocol between
    the e6500 cores, SC3900 FVP cores, memories and external interfaces.
    CoreNet fabric interconnect runs at 667 MHz and supports coherent and
    non-coherent out of order transactions with prioritization and
    bandwidth allocation amongst CoreNet endpoints.
Data Path Acceleration Architecture, which includes the following:
  Frame Manager (FMan), which supports in-line packet parsing and general
    classification to enable policing and QoS-based packet distribution
  Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
    of queue management, task management, load distribution, flow ordering,
    buffer management, and allocation tasks from the cores
  Security engine (SEC 5.3)-crypto-acceleration for protocols such as
    IPsec, SSL, and 802.16
  RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
    outbound). Supports types 5, 6 (outbound only)
Large internal cache memory with snooping and stashing capabilities for
    bandwidth saving and high utilization of processor elements. The
    9856-Kbyte internal memory space includes the following:
  32 Kbyte L1 ICache per e6500/SC3900 core
  32 Kbyte L1 DCache per e6500/SC3900 core
  2048 Kbyte unified L2 cache for each SC3900 FVP cluster
  2048 Kbyte unified L2 cache for the e6500 cluster
  Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
Sixteen 10-GHz SerDes lanes serving:
  Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total
    of up to 8 lanes
  Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-
    less antenna connection
  Two 10-Gbit Ethernet controllers (10GEC)
  Six 1G/2.5-Gbit Ethernet controllers for network communications
  PCI Express controller
  Debug (Aurora)
Two OCeaN DMAs
Various system peripherals
182 32-bit timers

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:24 -05:00
York Sun
9e75875849 powerpc/mpc85xx: Add T4240 SoC
Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):

12 dual-threaded e6500 cores built on Power Architecture® technology
  Arranged as clusters of four cores sharing a 2 MB L2 cache.
  Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
    v2.06-compliant)
  Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
  CoreNet fabric supporting coherent and non-coherent transactions with
    prioritization and bandwidth allocation amongst CoreNet end-points
  1.6 Tbps coherent read bandwidth
  Queue Manager (QMan) fabric supporting packet-level queue management and
    quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
    support
  Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
    the following functions:
  Packet parsing, classification, and distribution (Frame Manager 1.1)
  Queue management for scheduling, packet sequencing, and congestion
    management (Queue Manager 1.1)
  Hardware buffer management for buffer allocation and de-allocation
    (BMan 1.1)
  Cryptography acceleration (SEC 5.0) at up to 40 Gbps
  RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
  Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
  DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
  Up to four 10 Gbps Ethernet MACs
  Up to sixteen 1 Gbps Ethernet MACs
  Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
  Four PCI Express 2.0/3.0 controllers
  Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
    Type 11 messaging and Type 9 data streaming support
  Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
  Two serial ATA (SATA 2.0) controllers
  Two high-speed USB 2.0 controllers with integrated PHY
  Enhanced secure digital host controller (SD/MMC/eMMC)
  Enhanced serial peripheral interface (eSPI)
  Four I2C controllers
  Four 2-pin or two 4-pin UARTs
  Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:23 -05:00
Andy Fleming
f311838ded powerpc/mpc85xx: Add T4 device definitions
The T4 has added devices to previous corenet implementations:

* SEC has 3 more DECO units
* New PMAN device
* New DCE device

This doesn't add full support for the new devices. Just some
preliminary support.

Move PMAN LIODN to upper half of register

Despite having only one LIODN, the PMAN LIODN is stored in the
upper half of the register. Re-use the 2-LIODN code and just
set the LIODN as if the second one is 0. This results in the
actual LIODN being written to the upper half of the register.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:22 -05:00
York Sun
379c5145ef powerpc/corenet2: fix mismatch DDR sync bit from RCW
Corenet 2nd generation Chassis doesn't have ddr_sync bit in RCW. Only
async mode is supported.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:20 -05:00
York Sun
d1001e3f0c powerpc/corenet2: Add SerDes for corenet2
Create new files to handle 2nd generation Chassis as the registers are
organized differently.

 - Add SerDes protocol parsing and detection
 - Add support of 4 SerDes
 - Add CPRI protocol in fsl_serdes.h
	The Common Public Radio Interface (CPRI) is publicly available
	specification that standardizes the protocol interface between the
	radio equipment control (REC) and the radio equipment (RE) in wireless
	basestations. This allows interoperability of equipment from different
	vendors,and preserves the software investment made by wireless service
	providers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:19 -05:00
York Sun
fd3cebd020 powerpc/mpc85xx: Add RCW bits and registers for SerDes for corenet2
Corenet 2nd generation Chassis has different RCW and registers for SerDes.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:18 -05:00
York Sun
92230d49da powerpc/e6500: Move QCSP registers for QMan v3
The QCSP registers are expanded and moved from offset 0 to offset 0x1000
for SoCs with QMan v3.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:18 -05:00
York Sun
f8f85b049c powerpc/mpc85xx: expand SERDES reference clock select bit
Expand the reference clock select to three bits
000: 100 MHz
001: 125 MHz
010: 156.25MHz
011: 150 MHz
100: 161.1328125 MHz
All others reserved

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:17 -05:00
York Sun
9a653a9810 powerpc/mpc85xx: Fix core cluster PLL calculation for Chassis generation 2
Corenet based SoCs have different core clocks starting from Chassis
generation 2. Cores are organized into clusters. Each cluster has up to
4 cores sharing same clock, which can be chosen from one of three PLLs in
the cluster group with one of the devisors /1, /2 or /4. Two clusters are
put together as a cluster group. These two clusters share the PLLs but may
have different divisor. For example, core 0~3 are in cluster 1. Core 4~7
are in cluster 2. Core 8~11 are in cluster 3 and so on. Cluster 1 and 2
are cluster group A. Cluster 3 and 4 are in cluster group B. Cluster group
A has PLL1, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have
PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1.

PME and FMan blocks can take different PLLs, configured by RCW.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:16 -05:00
York Sun
2f1712b275 powerpc/mpc85xx: check number of cores
Panic if the number of cores is more than CONFIG_MAX_CPUS because it will
surely overflow gd structure.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:15 -05:00
York Sun
f77329cfcf powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2
Chassis generation 2 has different mask and shift. Use macro instead of
magic numbers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:15 -05:00
York Sun
6d2b9da19c powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500
Using E6500 L1 cache as initram requires L2 cache enabled.
Add l2-cache cluster enabling.

Setup stash id for L1 cache as (coreID) * 2 + 32 + 0
Setup stash id for L2 cache as (cluster) * 2 + 32 + 1
Stash id for L2 is only set for Chassis 2.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:15 -05:00
York Sun
69c7826759 powerpc/mpc85xx: Introduce new macros to add and delete TLB entries
These assembly macros simplify codes to add and delete temporary TLB entries.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:15 -05:00
Kumar Gala
800c73c410 powerpc/85xx: Add determining and report IFC frequency
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:14 -05:00
York Sun
553ae6f8f2 powerpc/DPAA: Fix compiling error
FSL_HW_PORTAL_PME is used even when CONFIG_SYS_DPAA_PME is not defined.
Remove the #ifdef.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:14 -05:00
Timur Tabi
4905443f1c powerpc/85xx: Add P5040 processor support
Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:

Four P5040 single-threaded e5500 cores built
    Up to 2.4 GHz with 64-bit ISA support
    Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
    2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
        support Up to 1600MT/s
    Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
    Packet parsing, classification, and distribution (FMAN)
    Queue management for scheduling, packet sequencing and
    congestion management (QMAN)
    Hardware buffer management for buffer allocation and
    de-allocation (BMAN)
    Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes
    20 lanes at up to 5 Gbps
    Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
    Two 10 Gbps Ethernet MACs
    Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
    Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
    Two serial ATA (SATA 2.0) controllers
    Two high-speed USB 2.0 controllers with integrated PHY
    Enhanced secure digital host controller (SD/MMC/eMMC)
    Enhanced serial peripheral interface (eSPI)
    Two I2C controllers
    Four UARTs
    Integrated flash controller supporting NAND and NOR flash
DMA
    Dual four channel
Support for hardware virtualization and partitioning enforcement
    Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
    Secure boot, secure debug, tamper detection, volatile key storage

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:13 -05:00
Laurentiu Tudor
71cfcef649 powerpc/p5040ds: add per pci endpoint liodn offset list
Add a new device tree property named "fsl,liodn-offset-list"
holding a list of per pci endpoint permitted liodn offsets.
This property is useful in virtualization scenarios
that implement per pci endpoint partitioning.
The final liodn of a partitioned pci endpoint is
calculated by the hardware, by adding these offsets
to pci controller's base liodn, stored in the
"fsl,liodn" property of its node.
The liodn offsets are interleaved to get better cache
utilization. As an example, given 3 pci controllers,
the following liodns are generated for the pci endpoints:
    pci0: 193 256 259 262 265 268 271 274 277
    pci1: 194 257 260 263 266 269 272 275 278
    pci2: 195 258 261 264 267 270 273 276 279

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:13 -05:00
Timur Tabi
fd946040f1 powerpc/85xx: define SRIO LIODN functions only if SRIO is defined
The P5040 does not have SRIO support, so there are no SRIO LIODNs.
Therefore, the functions that set the SRIO LIODNs should not be compiled.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:13 -05:00
Laurentiu Tudor
e389a377ee powerpc/85xx: introduce SET_PCI_LIODN_BASE, for setting PCI LIODNs
The liodn for the new PCIE controller included in P5040DS is no longer set
through a register in the guts register block but with one in the PCIE
register block itself.  Update the PCIE CCSR structure to add the new liodn
register and add a new dedicated SET_PCI_LIODN_BASE macro that puts
the liodn in the correct register.

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:12 -05:00
Timur Tabi
0c7e65f3d6 powerpc/mpc85xx: fix Unicode characters in release.S
Commit 709389b6 unintentionally used the Unicode version of the
apostrophy.  Replace it with the normal ASCII version.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:12 -05:00
Liu Gang
d59c557049 powerpc/srio: Workaround for srio erratrm a004034
Erratum: A-004034
Affects: SRIO

Description: During port initialization, the SRIO port performs
lane synchronization (detecting valid symbols on a lane) and
lane alignment (coordinating multiple lanes to receive valid data
across lanes). Internal errors in lane synchronization and lane
alignment may cause failure to achieve link initialization at
the configured port width.

An SRIO port configured as a 4x port may see one of these scenarios:

1.	One or more lanes fails to achieve lane synchronization.
	Depending on which lanes fail, this may result in downtraining
	from 4x to 1x on lane 0, 4x to 1x on lane R (redundant lane).

2.	The link may fail to achieve lane alignment as a 4x, even
	though all 4 lanes achieve lane synchronization, and downtrain
	to a 1x. An SRIO port configured as a 1x port may fail to complete
	port initialization (PnESCSR[PU] never deasserts) because of
	scenario 1.

Impact: SRIO port may downtrain to 1x, or may fail to complete
link initialization. Once a port completes link initialization
successfully, it will operate normally.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:12 -05:00
ramneek mehresh
9c889ece32 powerpc/mpc8xxx: Fix USB device-tree fixup
Fix usb device-tree fixup:
	- wrong modification of dr_mode and phy_type when
	  "usb1" is not mentioned inside hwconfig string;
	   now allows hwconfig strings like:
		"usb2:dr_mode=host,phy_type=ulpi"
	- add warning message for using usb_dr_mode
	  and usb_phy_type env variables (if either is used)

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:12 -05:00
Marek Vasut
8b493a5236 common: Discard the __u_boot_cmd section
The command declaration now uses the new LG-array method to generate
list of commands. Thus the __u_boot_cmd section is now superseded and
redundant and therefore can be removed. Also, remove externed symbols
associated with this section from include/command.h .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
2012-10-22 08:29:42 -07:00
Marek Vasut
556751427b common: Add .u_boot_list into all linker files
Add section for the linker-generated lists into all possible linker
files, so that everyone can easily use these lists. This is mostly
a mechanical adjustment.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
2012-10-22 08:29:42 -07:00
Zang Roy-R61911
4e0be34a85 P4080/esdhc: make the P4080 ESDHC13 errata workaround conditional
P4080 Rev3.0 fixes ESDHC13 errata, so update the code to make the
workaround conditional.
In formal release document, the errata number should be ESDHC13 instead
of ESDHC136.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 03:04:28 -05:00
Mark Marshall
320d53da60 powerpc mpc85xx: Only clear TSR:WIS in watchdog_reset.
We should only write TSR_WIS to the SPRN_TSR register in
reset_85xx_watchdog.

The old code would cause the timer interrupt to be acknowledged when the
watchdog was reset, and we would then get no more timer interrupts.
This bug would affect all mpc85xx boards that have the watchdog enabled.

Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 03:04:27 -05:00
Chris Packham
168e5bc409 mpc85xx: make gpio_direction_output respect value
Users of familiar with the Linux gpiolib API expect that value parameter
to gpio_direction_output reflects the initial state of the output pin.
gpio_direction_output was always driving the output low, now it drives
it high or low according to the value provided.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 03:03:16 -05:00
Simon Glass
a7e5ee9ebb powerpc: Change bi_baudrate and global data baudrate to int
These don't need to be longs, so change them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-19 15:25:45 -07:00
Pavel Herrmann
8d1165e11a split mpc8xx hooks from cmd_ide.c
move most of mpc8xx hooks from cmd_ide.c into ide_preinit() and newly created
ide_init_postreset() (invoked after calling ide_reset after ide_preinit),
some cleanup to make checkpatch happy, enable IDE init hooks in configs of
affected boards.
confusingly, these hooks are used by more than just mpc8xx-based boards, and
therefore are placed in arch/ppc/lib/

note: checkpatch still emits warnings about using volatile

Signed-off-by: Pavel Herrmann <morpheus.ibis@gmail.com>
2012-10-17 07:59:08 -07:00
Marek Vasut
ec3fd68952 serial: Use default_serial_puts() in drivers
Replace the in-place ad-hoc implementation of serial_puts() within
the drivers with default_serial_puts() call. This cuts down on the
code duplication quite a bit.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
2012-10-17 07:55:50 -07:00
Stefan Roese
bfa5b71408 mpc82xx: Remove BMW board port
As the board seems to be unmaintained for some time, lets remove
the support in mainline completely.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: James F. Dougherty <jfd@broadcom.com>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
2012-10-17 07:55:50 -07:00
Lucas Stach
c7e3b2b586 usb: lowlevel interface change to support multiple controllers
Carry an index in the lowlevel usb functions to make specify the
respective usb controller.

Also pass through an controller struct from lowlevel_init to the
creation of the root usb device of this controller.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2012-10-15 11:54:00 -07:00
Stefan Roese
a821d08dca ppc4xx: Remove AP1000 board support
As the board seems to be unmaintained for some time, lets remove
the support in mainline completely.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: James MacAulay <james.macaulay@amirix.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-10-15 11:53:59 -07:00
Stefan Roese
dee9c534db ppc4xx: Remove ML2 board support
As the board seems to be unmaintained for some time, lets remove
the support in mainline completely.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Peter De Schrijver <p2@mind.be>
Acked-by: Marek Vasut <marex@denx.de>
2012-10-15 11:53:59 -07:00
Stefan Roese
99bcad1809 ppc4xx: Remove IOP480 support
Since the IOP480 (PPC401/3 variant from PLX) is only used on 2
boards that are not actively maintained, lets remove support
for it completely. This way the ppc4xx code will get a bit cleaner.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Acked-by: Marek Vasut <marex@denx.de>
2012-10-15 11:53:59 -07:00
Marek Vasut
036036d79c serial: Remove CONFIG_SERIAL_MULTI from remaining sources
Remove the parts depending either on disabled CONFIG_SERIAL_MULTI
or ifdefs around CONFIG_SERIAL_MULTI parts since CONFIG_SERIAL_MULTI
is now enabled by default.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
2012-10-15 11:53:59 -07:00
Marek Vasut
a382725060 serial: Remove CONFIG_SERIAL_MULTI from serial drivers
Remove the support for not-CONFIG_SERIAL_MULTI part from serial
port drivers and some board files. Since CONFIG_SERIAL_MULTI is
now enabled by default, that part is a dead code. Remove it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-15 11:53:58 -07:00
Marek Vasut
fcc2074d57 serial: powerpc: Implement CONFIG_SERIAL_MULTI into iop480 serial driver
Implement support for CONFIG_SERIAL_MULTI into iop480 serial driver.
This driver was so far only usable directly, but this patch also adds
support for the multi method. This allows using more than one serial
driver alongside the iop480 driver. Also, add a weak implementation
of default_serial_console() returning this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
2012-10-15 11:53:52 -07:00
Marek Vasut
7a31154627 serial: powerpc: Implement CONFIG_SERIAL_MULTI into mpc85xx serial driver
Implement support for CONFIG_SERIAL_MULTI into mpc85xx serial driver.
This driver was so far only usable directly, but this patch also adds
support for the multi method. This allows using more than one serial
driver alongside the mpc85xx driver. Also, add a weak implementation
of default_serial_console() returning this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
2012-10-15 11:53:52 -07:00
Marek Vasut
d68f4da2fa serial: powerpc: Implement CONFIG_SERIAL_MULTI into mpc8260 serial drivers
Implement support for CONFIG_SERIAL_MULTI into both SCC and SMC mpc8260
serial drivers. These drivers were so far only usable directly, but this
patch also adds support for the multi method. This allows using more than
one serial driver alongside the mpc8260 drivers. Also, add a weak
implementation of default_serial_console() returning this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
2012-10-15 11:53:51 -07:00
Marek Vasut
2063a54e14 serial: powerpc: Implement CONFIG_SERIAL_MULTI into mpc8220 serial driver
Implement support for CONFIG_SERIAL_MULTI into mpc8220 serial driver.
This driver was so far only usable directly, but this patch also adds
support for the multi method. This allows using more than one serial
driver alongside the mpc8220 driver. Also, add a weak implementation
of default_serial_console() returning this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
2012-10-15 11:53:51 -07:00
Marek Vasut
b57c652802 serial: powerpc: Implement CONFIG_SERIAL_MULTI into mpc5xx serial driver
Implement support for CONFIG_SERIAL_MULTI into mpc5xx serial driver.
This driver was so far only usable directly, but this patch also adds
support for the multi method. This allows using more than one serial
driver alongside the mpc5xx driver. Also, add a weak implementation
of default_serial_console() returning this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
2012-10-15 11:53:51 -07:00
Marek Vasut
918327c8f0 serial: mpc512x: Move serial registration from serial_initialize()
Move the registration of serialN_device ports from default
serial_initialize() into driver specific function called from
serial_initialize(). This slims down the serial_initialize() call
to a bare tracker of all possible serial port registration routines
in U-Boot.

The newly implemented mpc512x_serial_initialize() function, which is
implemented inside of the mpc512x serial driver allows encapsulation
of serialN_device within the mpc512x serial driver itself.

Also, remove the exports of serialN_device from include/serial.h
as they are no longer needed. This is simply because the implementation of
default_serial_console() is wrapped into the mpx512x serial driver and
the default console is picked by CONFIG_SERIAL<N> macro in config file.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
2012-10-15 11:53:50 -07:00
Marek Vasut
f0eb1f61b0 serial: mpc8xx: Move serial registration from serial_initialize()
Move the registration of serial_smc and serial_scc ports from
default serial_initialize() into CPU specific function called from
serial_initialize(). This slims down the serial_initialize() call
to a bare tracker of all possible serial port registration routines
in U-Boot.

The exports of both serial_scc_device and serial_smc_device can
not yet be removed as they are still used in default_serial_console()
calls.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
2012-10-15 11:53:49 -07:00
Marek Vasut
90bad891e1 serial: Properly spell out the structure member names of serial_driver
Properly spell out the whole structure member names when an initialized
varible is instantiated from the struct serial_driver. In case the
structure definition for struct serial_driver undergoes reordering,
there will be no impact on variables defined based on this structure.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: C Nauman <cnauman@diagraph.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Michal Simek <monstr@monstr.eu>
2012-10-15 11:53:48 -07:00
Tom Rini
5675b50916 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2012-09-25 12:23:55 -07:00
Anatolij Gustschin
e5ab702a6c powerpc: re-add bi_ip_addr to bd_t struct
Since commit 50a47d0523
(net: punt bd->bi_ip_addr) booting old 2.4.x ppc kernels
is broken due to changed offsets of the fields in struct bd_t.
Offsets of the fields after removed bi_ip_addr are wrong,
causing wrong bus clocks and console baudrate configurations
and various other issues. Re-add the bi_ip_addr field to preserve
backward compatibility with older ppc kernels. Setting bi_ip_addr
in board.c is not really needed, grepping in the 2.4 linux tree
shows that bi_ip_addr is not accessed there. Adding bi_ip_addr
to struct bd_t for other arches isn't needed it seems. bd_t is
not used by other arches in the 2.4 linux tree.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
2012-09-02 22:55:59 +02:00
Joakim Tjernlund
83f83d1935 ppc: Create a stack frame for wait_ticks()
wait_ticks() calls get_ticks() without building a back chain which
makes gdb unhappy when doing back trace. This can also cause
improper memory accesses.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2012-09-02 17:10:21 +02:00
Stefan Roese
0044c42e94 Consolidate bootcount code into drivers/bootcount
This patch moves all bootcount implementations into a common
directory: drivers/bootcount. The generic bootcount driver
is now usable not only by powerpc platforms, but others as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Cc: Christian Riesch <christian.riesch@omicron.at>
Cc: Manfred Rudigier <manfred.rudigier@omicron.at>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
Tested-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-09-01 14:26:02 +02:00
Anatolij Gustschin
d7903ae159 mpc5xxx: add GPIO port configuration
Add posibility for board specifig GPIO configurations using
various CONFIG_SYS_ macros.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2012-09-01 14:19:52 +02:00
Andy Fleming
98ae9ac434 Revert "powerpc: Fix declaration type for I/O functions"
This reverts commit 20959471b5.
2012-08-23 12:16:57 -05:00
Scott Wood
3ea21536d7 powerpc/85xx: clear out TLB on boot
Instead of just shooting down the entry that covers CCSR, clear out
every TLB entry that isn't the one that we're executing out of.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:57 -05:00
York Sun
7ac3cc20e0 powerpc/mpc8xxx: Move HWCONFIG_BUFFER_SIZE into config.h
Before proper environment is setup, we extract hwconfig and put it into a
buffer with size HWCONFIG_BUFFER_SIZE. We need to enlarge the buffer to
accommodate longer string. Since this macro is used in multiple files, we
move it into arch/powerpc/include/asm/config.h.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:56 -05:00
York Sun
1d083ff2c4 powerpc/mpc8xxx DDR: Fix interactive DDR debugging
Add one more argument to call function readline_into_buffer().
Fix print SPD format for negative values.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:56 -05:00
York Sun
62f739fe46 powerpc/mpc8xxx DDR: Fall back to raw timing for first controller only
Only the first DIMM of first controller should fall back to raw timing
parameters if SPD is missing or corrupted.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:56 -05:00
York Sun
7e4db27ffd powerpc/mpc8xxx DDR: Fix CAS latency calculation
Empty slot should be skipped when calculating CAS latency.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:56 -05:00
York Sun
45064adcae powerpc/mpc8xxx: Fix bug for extended DDR timing
Faster DDR3 timing requires parameters exceeding previously defined
range. Extended parameters are fixed. Added some debug messages.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
York Sun
a4c66509f1 powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving
Restructure DDR interleaving option to support 3 and 4 DDR controllers
for 2-, 3- and 4-way interleaving.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
York Sun
fcea30688f powerpc/mpc8xxx: Add support for cas latency 12 and above
Required by JEDEC 79-3E for high speed DDR3.
Also change "CSn disabled" message to debug.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
York Sun
73b5396b25 powerpc/mpc8xxx: Add fine timing support for DDR3
When the DDR3 speed goes higher, we need to utilize fine offset
from SPD.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
York Sun
744713a6a3 powerpc/mpc85xx: Skip zero values for DDR debug registers
Some debug registers have non-zero default out of reset. If software is
not setting debug registers, skip writing to them to avoid unnecessary
overriding.

Also add debug messages for workarounds and debug registers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
York Sun
709389b654 powerpc/mpc8xxx: fix core id for multicore booting
For the cores with multiple threads, we need to figure out which physical
core a thread belongs. To match the core ids, update PIR registers and
spin tables.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
Kumar Gala
ffdf8890ae Added new ext fields to IFC
In case more than 32 bit address is used, the EXT bit should be set.
Need to fix up address map for IFC #CS for 4, also need to move # of IFC
banks into config_mpc85xx.h

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
Kumar Gala
50d96e95b4 Add IFC offset for DPAA/Corenet platforms
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
Kumar Gala
5b6b85ae63 Add e6500 processor detection
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
York Sun
123bd96d53 powerpc/mpc8xxx: use topology registers to calculate number of cores
We have actual topology infomation to find out exactly which core is present.
Calculate the number of cores if not specified.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
York Sun
1ca8690d27 powerpc/mpc8xxx: Add immap for topology and rcpm registers
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
Prabhakar Kushwaha
3854173aa8 powerpc/mpc85xx: Add IFC LAW target ID for FSL High-End SoC
Freescale's High-End SoC are going to have Integrated Flash controller
(IFC)'s support.

So add IFC LAW target ID support for High-End SoC or corenet SoC.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
Prabhakar Kushwaha
e4879afba3 powerpc/mpc85xx:Enable debugger support to missed e500v2 SoC
Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some
restrictions on external debugging (JTAG). Need to define define
CONFIG_SYS_PPC_E500_DEBUG_TLB to enable a temporary TLB entry to be
used during boot to work around the limitations.

Enable missed e500v2 SoC i.e. MPC8536, MPC8544, MPC8548 and MPC8572 for
debug support.

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Cc: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
Scott Wood
33eee330cc powerpc/fsl-corenet: work around erratum A004510
Erratum A004510 says that under certain load conditions, modified
cache lines can be discarded, causing data corruption.

To work around this, several CCSR and DCSR register updates need to be
made in a careful manner, so that there is no other transaction in
corenet when the update is made.

The update is made from a locked cacheline, with a delay before to flush
any previous activity, and a delay after to flush the CCSR/DCSR update.
We can't use a readback because that would be another corenet
transaction, which is not allowed.

We lock the subsequent cacheline to prevent it from being fetched while
we're executing the previous cacheline.  It is filled with nops so that a
branch doesn't cause us to fetch another cacheline.

Ordinarily we are running in a cache-inhibited mapping at this point, so
we temporarily change that.  We make it guarded so that we should never
see a speculative load, and we never do an explicit load.  Thus, only the
I-cache should ever fill from this mapping, and we flush/unlock it
afterward.  Thus we should avoid problems from any potential cache
aliasing between inhibited and non-inhibited mappings.

NOTE that if PAMU is used with this patch, it will need to use a
dedicated LAW as described in the erratum.  This is the responsibility
of the OS that sets up PAMU.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
Scott Wood
3e978f5dc8 powerpc/fsl-corenet: remove dead variant symbols
These are not supported as individual build targets, but instead
are supported by another target.

The dead p4040 defines in particular had bitrotted significantly.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
Timur Tabi
055ce08004 powerpc/85xx: remove support for the Freescale P3060
The P3060 was cancelled before it went into production, so there's no point
in supporting it.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:53 -05:00
Timur Tabi
99abf7ded3 powerpc/85xx: add support for FM2 DTSEC5
Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second
Fman, so add the Fman and SerDes macros for that DTSEC.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:18 -05:00
Matthew McClintock
9c6b47d53e p1014rdb: set ddr bus width properly depending on SVR
Currently, for NAND boot for the P1010/4RDB we hard code the DDR
configuration. We can still dynamically set the DDR bus width in
the nand spl so the P1010/4RDB boards can boot from the same
u-boot image

Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:16 -05:00
York Sun
be7bebeac2 powerpc/mpc8xxx: Remove P1015 and P1016 from CPU list
P1015 is the same as P1011 and P1016 is the same as P1012 from software
point of view. They have different packages but share SVRs.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:16 -05:00
Liu Gang
b5f7c8732a powerpc/corenet_ds: Master module for boot from PCIE
For the powerpc processors with PCIE interface, boot location can be
configured from one PCIE interface by RCW. The processor booting from PCIE
can do without flash for u-boot image. The image can be fetched from another
processor's memory space by PCIE link connected between them.

The processor booting from PCIE is slave, the processor booting from normal
flash memory space is master, and it can help slave to boot from master's
memory space.

When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.

Environment and requirement:

master:
    1. NOR flash for its own u-boot image, ucode and ENV space.
    2. Slave's u-boot image is in master NOR flash.
    3. Normally boot from local NOR flash.
    4. Configure PCIE system if needed.
slave:
    1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
    2. Boot location should be set to one PCIE interface by RCW.
    3. RCW should configure the SerDes, PCIE interfaces correctly.
	4. Must set all the cores in holdoff by RCW.
	5. Must be powered on before master's boot.

For the master module, need to finish these processes:
    1. Initialize the PCIE port and address space.
    2. Set inbound PCIE windows covered slave's u-boot image stored in
       master's NOR flash.
	3. Set outbound windows in order to configure slave's registers
	   for the core's releasing.
    4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2"
	   or "PCIE3" using the following command:

			setenv bootmaster PCIE1
			saveenv

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:15 -05:00
Liu Gang
81fa73bab0 powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro
When compile the slave image for boot from SRIO, no longer need to
specify which SRIO port it will boot from. The code will get this
information from RCW and then finishes corresponding configurations.

This has the following advantages:
	1. No longer need to rebuild an image when change the SRIO port for
	   boot from SRIO, just rewrite the new RCW with selected port,
	   then the code will get the port information by reading new RCW.
	2. It will be easier to support other boot location options, for
	   example, boot from PCIE.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:14 -05:00
Liu Gang
ff65f12699 powerpc/corenet_ds: Get rid of the SRIOBOOT_MASTER build target
Get rid of the SRIOBOOT_MASTER build target, and to support for serving as
a SRIO boot master via environment variable. Set the environment variable
"bootmaster" to "SRIO1" or "SRIO2" using the following command:

		setenv bootmaster SRIO1
		saveenv

The "bootmaster" will enable the function of the SRIO boot master, and
this has the following advantages compared with SRIOBOOT_MASTER build
configuration:
	1. Reduce a build configuration item in boards.cfg file.
	   No longer need to build a special image for master, just use a
	   normal target image and set the "bootmaster" variable.
	2. No longer need to rebuild an image when change the SRIO port for
	   boot from SRIO, just set the corresponding value to "bootmaster"
	   based on the using SRIO port.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:14 -05:00
York Sun
57125f222e powerpc/mpc85xx: Make NMG_CPU_A011 workaround conditional
This erratum applies to the following SoCs:
P4080 rev 1.0, 2.0, fixed in rev 3.0
P2041 rev 1.0, 1.1, fixed in rev 2.0
P3041 rev 1.0, 1.1, fixed in rev 2.0.

Workaround for erratum NMG_CPU_A011 is enabled by default. This workaround
may degrade performance. P4080 erratum CPU22 shares the same workaround.
So it is always enabled for P4080. For other SoCs, it can be disabled by
hwconfig with syntax:

fsl_cpu_a011:disable

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:13 -05:00
Joakim Tjernlund
7de8a7169e powerpc: Stack Pointer not properly aligned
The code first aligns the SP to 16 then subtract 8, making it
8 bytes aligned. Furthermore the initial stack frame not
quite correct either.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-22 16:07:42 -05:00
Joakim Tjernlund
89f4289958 mpc85xx: Initial SP alignment is wrong.
PowerPC mandates SP to be 16 bytes aligned.
Furthermore, a stack frame is added, pointing to the reset vector
which may in the way when gdb is walking the stack because
the reset vector may not accessible depending on emulator settings.
Also use a temp register so gdb doesn't pick up intermediate values.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-22 16:07:42 -05:00
Prabhakar Kushwaha
20959471b5 powerpc: Fix declaration type for I/O functions
Prototype declaration of I/O operation functions are not correct. as both
'extern' and function definition are at same place.

Chage protoype declaration as static.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-08-09 22:24:31 +02:00
Prabhakar Kushwaha
a16a5cccfb powerpc:Fix return type & parameter passed for I/O functions
Return type of in_8, in_be16 and in_le16 should not be'int'. Update it to type
u8/u16/u32.
Although 'unsigned' for in_be32 and in_le32 is correct. But to make return type
uniform across the file changed to u32

Similarly, parameter passed to out_8, out_be16, out_le16 ,out_be32 & out_le32
should not be 'int'.Change it to type u8/u16/u32.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-08-09 22:23:14 +02:00
Mike Frysinger
47fde91f0c global_data: unify global flag defines
All the global flag defines are the same across all arches.  So unify them
in one place, and add a simple way for arches to extend for their needs.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-08-09 21:46:32 +02:00
Timur Tabi
5c5befda58 powerpc/85xx: use CONFIG_SYS_FSL_PCIE_COMPAT macro when setting the PCI LIODNs
The SET_PCI_LIODN() macro takes a compatible property string as a parameter, so that it knows
which PCI device tree node to look for.  The calls to these macros are using a hard-coded string,
but we already have the CONFIG_SYS_FSL_PCIE_COMPAT macro which contains the same string, so we
should use that.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 18:32:16 -05:00
York Sun
718f2b3187 powerpc/mpc85xx: Ignore E bit for BSC9130/1
Commit 48f6a5c34 removed E bit. BSC9130/1 were left out due to patch apply
timing. Remove them now.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 18:32:16 -05:00
Timur Tabi
7ee411071f powerpc/85xx: improve definition of BR_PHYS_ADDR macro
The BR_PHYS_ADDR(x) macro was missing parentheses around "x" in the macro
definition, so callers had to supply their own parenthesis.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 18:32:15 -05:00
Shaohui Xie
98de369b1c powerpc/ddr: fix fsl_ddr_get_dimm_params compile error
fsl_ddr_get_dimm_params() should be wrapped by
CONFIG_SYS_DDR_RAW_TIMING, otherwise, when using fixed_sdram() instead of
using SPD, it will cause compile error.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 17:13:38 -05:00
York Sun
535a159ab6 powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134 for DDR over 4GB
The fix for errata workaround is to avoid covering physical address
0xff000000 to 0xffffffff during the implementation. Early commit eb672e92
works until DDR size exceeds 4GB. This fix works for DDR size up to 64GB.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 17:13:38 -05:00
Wolfgang Denk
b98b611502 Merge branch 'next' of git://git.denx.de/u-boot
* 'next' of git://git.denx.de/u-boot:
  MPC8xx: Fixup warning in arch/powerpc/cpu/mpc8xx/cpu.c
  doc: cleanup - move board READMEs into respective board directories
  net: sh_eth: add support for SH7757's GETHER
  net: sh_eth: modify the definitions of regsiter
  net: sh_eth: add SH_ETH_TYPE_ condition
  net: sh_eth: clean up for the SH7757's code
  net: fec_mxc: Fix MDC for xMII
  net: fec_mxc: Fix setting of RCR for xMII
  net: nfs: make NFS_TIMEOUT configurable
  net: Inline the new eth_setenv_enetaddr_by_index function
  net: allow setting env enetaddr from net device setting
  net/designware: Consecutive writes to the same register to be avoided
  CACHE: net: asix: Fix asix driver to work with data cache on
  net: phy: micrel: make ksz9021 phy accessible
  net: abort network initialization if the PHY driver fails
  phylib: phy_startup() should return an error code on failure
  net: tftp: fix type of block arg to store_block

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-30 20:39:52 +02:00
Marek Vasut
15ae8a31ca MPC8xx: Fixup warning in arch/powerpc/cpu/mpc8xx/cpu.c
cpu.c: In function ‘check_CPU’:
cpu.c:256:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Subject slightly changed.
Signed-off-by: Wolfgang Denk <wd@denx.de>

Tested on TQM855MDCBAB7-T66.102 (MPC855T at 66 MHz) and
TQM860LDB0A3-T50.202 (MPC860T at 50MHz).

Tested-by: Wolfgang Denk <wd@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
2012-07-30 09:58:02 +02:00
Stefano Babic
569fadcd74 MPC83xx, MPC85xx: compile stub cache function
An empty flush_dcache_range() was added into MPC83xx and MPC85xx to
work with drivers shared with other architecture.  However, it is
compiled only if USB is set, but it is required for other drivers
(FSL_ESDHC), too.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Andy Fleming <afleming@gmail.com>
CC: Dirk Behme <dirk.behme@de.bosch.com>
CC: Marek Vasut <marex@denx.de>
CC: Wolfgang Denk <wd@denx.de>

Added MPC83xx version.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-21 23:37:48 +02:00
Wolfgang Denk
8246ff864d Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
  powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040E
  powerpc/mpc85xx: Workaround for erratum CPU_A011
  powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()
  powerpc/P4080: Check SVR for CPU22 workaround
  lib/powerpc: addrmap_phys_to_virt() should return a pointer
  powerpc/85xx: clean up P1022DS board configuration header file
  powerpc/85xx: fdt_set_phy_handle() should return an error code
  powerpc/85xx: minor clean-ups to the P2020DS board header file
  powerpc/p1010rdb: add readme document for p1010rdb
  powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address setting
  powerpc/mpc85xx:Add debugger support for e500v2 SoC
  powerpc/85xx:Fix NAND code base to support debugger
  powerpc/85xx:Make debug exception vector accessible
  powerpc/85xx:Fix MSR[DE] bit in MSR to support debugger
  PATCH 1/4][v4] doc:Add documentation for e500 external debugger support
  powerpc/p1010rdb: update mux config of p1010rdb board
  powerpc/mpc85xx:Add BSC9131 RDB Support
  powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support
  powerpc/85xx: Add USB device-tree fixup for various platforms

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-08 19:16:14 +02:00
York Sun
feae34243f powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040E
Fix SVR checking for commit acf3f8da.

Signed-off-by: York Sun <yorksun@freescale.com>
2012-07-06 17:30:33 -05:00
York Sun
5e23ab0a31 powerpc/mpc85xx: Workaround for erratum CPU_A011
Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0.
It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the
same workaround as erratum CPU22. Rearrange registers usage in assembly
code to avoid accidental overwriting.

Signed-off-by: York Sun <yorksun@freescale.com>
2012-07-06 17:30:33 -05:00
York Sun
48f6a5c348 powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()
We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.

Signed-off-by: York Sun <yorksun@freescale.com>
2012-07-06 17:30:33 -05:00
York Sun
1e9ea85f7d powerpc/P4080: Check SVR for CPU22 workaround
Workaround for erratum CPU22 applies to P4080 rev 1 and rev 2 only.

Signed-off-by: York Sun <yorksun@freescale.com>
2012-07-06 17:30:33 -05:00
Timur Tabi
7b6e80538b lib/powerpc: addrmap_phys_to_virt() should return a pointer
addrmap_phys_to_virt() converts a physical address (phys_addr_t) to a
virtual address, so it should return a pointer instead of an unsigned long.
Its counterpart, addrmap_virt_to_phys(), takes a pointer, so now they're
orthogonal.

The only caller of addrmap_phys_to_virt() converts the return value to
a pointer anyway.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-07-06 17:30:32 -05:00
Prabhakar Kushwaha
e87dc41fc1 powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address setting
During NAND_SPL boot, base address and different register are programmed
default by corresponding NAND controllers(eLBC/IFC). These settings are
sufficient enough for NAND SPL.

Avoid updating these register.They will be programmed during NAND RAMBOOT.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-07-06 17:30:31 -05:00
Prabhakar Kushwaha
ad75d44239 powerpc/mpc85xx:Add debugger support for e500v2 SoC
Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some
restrictions on external debugging (JTAG).

So define CONFIG_SYS_PPC_E500_DEBUG_TLB to enable a temporary TLB entry to be
used during boot to work around the limitations.

Please refer doc/README.mpc85xx for more information

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-07-06 17:30:31 -05:00
Prabhakar Kushwaha
d16a37b864 powerpc/85xx:Fix NAND code base to support debugger
Update NAND code base to ovecome e500 and e500v2's second limitation i.e. IVPR
+ IVOR15 should be valid fetchable OP code address.

As NAND SPL does not compile vector table so making sure IVOR + IVOR15 points to
any fetchable valid data

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-07-06 17:30:30 -05:00
Prabhakar Kushwaha
689f00fc7e powerpc/85xx:Make debug exception vector accessible
Debugging of e500 and e500v1 processer requires debug exception vecter (IVPR +
IVOR15) to have valid and fetchable OP code.

1) While executing in translated space (AS=1), whenever a debug exception is
generated, the MSR[DS/IS] gets cleared i.e. AS=0 and the processor tries to
fetch an instruction from the debug exception vector (IVPR + IVOR15); since now
we are in AS=0, the application needs to ensure the proper TLB configuration to
have (IVOR + IVOR15) accessible from AS=0 also.
Create a temporary TLB in AS0 to make sure debug exception verctor is
accessible on debug exception.

2) Just after relocation in DDR, Make sure IVPR + IVOR15 points to valid opcode

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-07-06 17:30:30 -05:00
Prabhakar Kushwaha
5344f7a258 powerpc/85xx:Fix MSR[DE] bit in MSR to support debugger
Debugging of e500 and e500v1 processer requires MSR[DE] bit to be set always.
Where MSR = Machine State register

Make sure of MSR[DE] bit is set uniformaly across the different execution
address space i.e. AS0 and AS1.

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Catalin Udma <catalin.udma@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-07-06 17:30:30 -05:00
Prabhakar Kushwaha
19a8dbdc45 powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support
- BSC9131 is integrated device that targets Femto base station market.
   It combines Power Architecture e500v2 and DSP StarCore SC3850 core
   technologies with MAPLE-B2F baseband acceleration processing elements.
 - BSC9130 is exactly same as BSC9131 except that the max e500v2
   core and DSP core frequencies are 800M(these are 1G in case of 9131).
 - BSC9231 is similar to BSC9131 except no MAPLE

The BSC9131 SoC includes the following function and features:
    . Power Architecture subsystem including a e500 processor with 256-Kbyte shared
      L2 cache
    . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
    . The Multi Accelerator Platform Engine for Femto BaseStation Baseband
      Processing (MAPLE-B2F)
    . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
     Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
     and CRC algorithms
    . Consists of accelerators for Convolution, Filtering, Turbo Encoding,
     Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
     operations
    . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
     ECC, up to 400-MHz clock/800 MHz data rate
    . Dedicated security engine featuring trusted boot
    . DMA controller
    . OCNDMA with four bidirectional channels
    . Interfaces
    . Two triple-speed Gigabit Ethernet controllers featuring network acceleration
      including IEEE 1588. v2 hardware support and virtualization (eTSEC)
    . eTSEC 1 supports RGMII/RMII
    . eTSEC 2 supports RGMII
    . High-speed USB 2.0 host and device controller with ULPI interface
    . Enhanced secure digital (SD/MMC) host controller (eSDHC)
    . Antenna interface controller (AIC), supporting three industry standard
      JESD207/three custom ADI RF interfaces (two dual port and one single port)
      and three MAXIM's MaxPHY serial interfaces
    . ADI lanes support both full duplex FDD support and half duplex TDD support
    . Universal Subscriber Identity Module (USIM) interface that facilitates
      communication to SIM cards or Eurochip pre-paid phone cards
    . TDM with one TDM port
    . Two DUART, four eSPI, and two I2C controllers
    . Integrated Flash memory controller (IFC)
    . TDM with 256 channels
    . GPIO
    . Sixteen 32-bit timers

The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.

This patch takes care of code pertaining to power side functionality only.

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-07-06 17:03:25 -05:00
Timur Tabi
a6cdaa0cd1 powerpc/mpc83xx: fix copyright string in serdes.c
The misspelling of "semiconductor" causes some internal copyright analysis
tools to complain.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-07-03 11:07:21 -05:00
Marek Vasut
25315683fd MPC8xxx: Define cache ops for USB
This patch conditionally defines flush_dcache_range() and
invalidate_dcache_range() on MPC8xxx, to avoid EHCI complaining,
resulting in the following output:

$ ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnu- ./MAKEALL MPC8572DS
Configuring for MPC8572DS board...
make: *** [u-boot] Error 1
powerpc-linux-gnu-size: './u-boot': No such file
e1000.c: In function ‘e1000_initialize’:
e1000.c:5264:13: warning: assignment from incompatible pointer type [enabled by default]
tsec.c: In function ‘tsec_initialize’:
tsec.c:638:12: warning: assignment from incompatible pointer type [enabled by default]
drivers/usb/host/libusb_host.o: In function `ehci_td_buffer':
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:186: undefined reference to `flush_dcache_range'
drivers/usb/host/libusb_host.o: In function `ehci_submit_async':
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:346: undefined reference to `flush_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:348: undefined reference to `flush_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:349: undefined reference to `flush_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:372: undefined reference to `invalidate_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:374: undefined reference to `invalidate_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:376: undefined reference to `invalidate_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:386: undefined reference to `invalidate_dcache_range'
make: *** [u-boot] Error 1

--------------------- SUMMARY ----------------------------
Boards compiled: 1
Boards with errors: 1 ( MPC8572DS )
----------------------------------------------------------

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
2012-06-07 23:29:19 +02:00
Joe Hershberger
cb487f5664 net: cosmetic: Un-typedef Ethernet_t
Separate the Ethernet header from the 802 header.
Base the size constants on the structs.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-23 17:46:14 -05:00
Joe Hershberger
1735188329 net: Encapsulate CDP packet identification
Checking for CDP packets should be encapsulated, not copied code.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-23 14:19:23 -05:00
Joe Hershberger
7a10692a9c arch/powerpc/cpu/mpc8260/ether_scc.c: Fix compile warning
Fix this:
ether_scc.c: In function 'mpc82xx_scc_enet_initialize':
ether_scc.c:377:14: warning: assignment from incompatible pointer type

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-22 23:17:52 -05:00
Joe Hershberger
412411cb2e arch/powerpc/cpu/mpc85xx/ether_fcc.c: Fix compile warning
Fix this:
ether_fcc.c: In function 'fec_initialize':
ether_fcc.c:453:15: warning: assignment from incompatible pointer type

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-22 13:41:46 -05:00
Joe Hershberger
888fc6158e arch/powerpc/cpu/mpc8260/ether_fcc.c: Fix compile warning
Fix this:
ether_fcc.c: In function 'fec_initialize':
ether_fcc.c:390:15: warning: assignment from incompatible pointer type

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-22 13:41:46 -05:00
Joe Hershberger
3573c327a6 arch/powerpc/cpu/mpc8220/fec.c: Fix compile warning
Fix this:
fec.c: In function 'mpc8220_fec_recv':
fec.c:791:9: warning: passing argument 1 of 'NetReceive' discards qualifiers from pointer target type
include/net.h:438:13: note: expected 'uchar *' but argument is of type 'volatile uchar *'
fec.c: In function 'mpc8220_fec_initialize':
fec.c:839:12: warning: assignment from incompatible pointer type

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-22 13:41:46 -05:00
Wolfgang Denk
1b10d0717a MPC8xx: fix "Remove volatile from net API" aftermath
Commit db288a9 "net: Remove volatile from net API" caused a number of
build warnings:
fec.c: In function 'fec_initialize':
fec.c:183:13: warning: assignment from incompatible pointer type [enabled by default]
fec.c: In function 'fec_recv':
fec.c:284:5: warning: passing argument 1 of 'NetReceive' discards 'volatile' qualifier from pointer target type [enabled by default]
/home/wd/git/u-boot/work/include/net.h:433:13: note: expected 'uchar *' but argument is of type 'volatile uchar *'
scc.c: In function 'scc_initialize':
scc.c:85:14: warning: assignment from incompatible pointer type [enabled by default]

Fix these.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2012-05-22 10:18:14 -05:00
Wolfgang Denk
8fa3d2b816 Merge branch 'master' of git://git.denx.de/u-boot-nand-flash
* 'master' of git://git.denx.de/u-boot-nand-flash:
  NAND: Remove ONFI detection message to from bootup log
  driver/mtd:IFC: Fix possible memory leak
  driver/mtd: IFC NAND: Add support of ONFI NAND flash
  mtd, nand: move some printfs to debug output.
  nand_util: correct YAFFS image write function
  powerpc/85xx: fix NAND boot linker scripts for -fpic
  nand: extend .raw accesses to work on multiple pages
2012-05-20 22:47:40 +02:00
Scott Wood
d2a97daf62 powerpc/85xx: fix NAND boot linker scripts for -fpic
GOT is now handled the way the main u-boot.lds does it.  Without this,
the boot hangs when built with newer GCC (since 4.6).  Older toolchains
hid the issue by converting -fpic to -fPIC.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2012-05-18 17:34:39 -05:00
Mike Frysinger
de30122bb5 net: move bootfile init into eth_initialize
All arches init this the same way, so move the logic into the core
net code to avoid duplicating it everywhere else.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-15 17:32:33 -05:00
Mike Frysinger
50a47d0523 net: punt bd->bi_ip_addr
This field gets read in one place (by "bdinfo"), and we can replace
that with getenv("ipaddr").  After all, the bi_ip_addr field is kept
up-to-date implicitly with the value of the ipaddr env var.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-15 17:32:05 -05:00
Timur Tabi
822ad60f1c powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSR
The CCSR relocation code in start.S writes to MAS7 on all e500 parts, but
that register does not exist on e500v1.

Signed-off-by: Timur Tabi <timur@freescale.com>
2012-04-24 23:58:34 -05:00
Liu Gang
5056c8e068 powerpc/corenet_ds: Slave core in holdoff when boot from SRIO
When boot from SRIO, slave's core can be in holdoff after powered on for
some specific requirements. Master can release the slave's core at the
right time by SRIO interface.

Master needs to:
	1. Set outbound SRIO windows in order to configure slave's registers
	   for the core's releasing.
	2. Check the SRIO port status when release slave core, if no errors,
	   will implement the process of the slave core's releasing.
Slave needs to:
	1. Set all the cores in holdoff by RCW.
	2. Be powered on before master's boot.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2012-04-24 23:58:33 -05:00
Liu Gang
0a85a9e705 powerpc/corenet_ds: Slave reads ENV from master when boot from SRIO
When boot from SRIO, slave's ENV can be stored in master's memory space,
then slave can fetch the ENV through SRIO interface.

NOTE: Because the slave can not erase, write master's NOR flash by SRIO
	  interface, so it can not modify the ENV parameters stored in
	  master's NOR flash using "saveenv" or other commands.

Master needs to:
	1. Put the slave's ENV into it's own memory space.
	2. Set an inbound SRIO window covered slave's ENV stored in master's
	   memory space.
Slave needs to:
	1. Set a specific TLB entry in order to fetch ucode and ENV from master.
	2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode and ENV.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2012-04-24 23:58:33 -05:00
Liu Gang
3f1af81b80 powerpc/corenet_ds: Slave uploads ucode when boot from SRIO
When boot from SRIO, slave's ucode can be stored in master's memory space,
then slave can fetch the ucode image through SRIO interface. For the
corenet platform, ucode is for Fman.

Master needs to:
	1. Put the slave's ucode image into it's own memory space.
	2. Set an inbound SRIO window covered slave's ucode stored in master's
	   memory space.
Slave needs to:
	1. Set a specific TLB entry in order to fetch ucode from master.
	2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2012-04-24 23:58:33 -05:00
Liu Gang
5ffa88eca7 powerpc/corenet_ds: Master module for boot from SRIO
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.

The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:

master:
	1. NOR flash for its own u-boot image, ucode and ENV space.
	2. Slave's u-boot image in master NOR flash.
	3. Normally boot from local NOR flash.
	4. Configure SRIO switch system if needed.
slave:
	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
	2. Boot location should be set to SRIO1 or SRIO2 by RCW.
	3. RCW should configure the SerDes, SRIO interfaces correctly.
	4. Slave must be powered on after master's boot.

For the master module, need to finish these processes:
	1. Initialize the SRIO port and address space.
	2. Set inbound SRIO windows covered slave's u-boot image stored in
	   master's NOR flash.
	3. Master's u-boot image should be generated specifically by
	   make xxxx_SRIOBOOT_MASTER_config
	4. Master must boot first, and then slave can be powered on.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2012-04-24 23:58:32 -05:00
Liu Gang
7d67ed58a2 powerpc/srio: Rewrite the struct ccsr_rio
Rewrite this struct for the support of two ports and two message
units registers.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
2012-04-24 23:58:32 -05:00
Prabhakar Kushwaha
5113ee706d powerpc/85xx:Fix lds for nand boot debug info
Currently "u-boot", the elf file generated via u-boot-nand.lds does not
contain required debug information i.e. .debug_{line, info, abbrev, aranges,
ranges} into their respective _global_ sections.

The original ld script line arch/powerpc/cpu/mpc85xx/start.o
KEEP(*(.bootpg)) is not entirely correct because the start.o file is already
processed by the linker,therefore the file wildcard in "KEEP(*(.bootpg))" will
not process start.o again for bootpg.

So Fix u-boot-nand.lds to generate these debug information.

Signed-off-by: Anmol Paralkar <b07584@freescale.com>
Signed-off-by: John Russo <John.Russo@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-04-24 23:58:31 -05:00
Prabhakar Kushwaha
119a55f9cf powerpc/85xx:Avoid vector table compilation for nand_spl
NAND SPL code never compile the vector table.
So no need to setup interrupt vector table for NAND SPL.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-04-24 23:58:30 -05:00
Prabhakar Kushwaha
64829baf04 powerpc/85xx:Fix IVORs addr after vector table relocation
After relocation of vector table in SDRAM's lower address, IVORs value should
be updated with new handler addresses.

As vector tables are relocated to 0x100,0x200... 0xf00 address in DDR.IVORs
are updated with 0x100, 0x200,....f00  hard-coded values.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-04-24 23:58:30 -05:00
Prabhakar Kushwaha
a4107f8617 powerpc/85xx:Avoid hardcoded vector address for IVORs
For e500 and e500v2 architecturees processor IVPR address should be alinged on
64K boundary.

in start.S, CONFIG_SYS_MONITOR_BASE is stored blindly in IVPR assuming it to be
64K aligned. It may not be true always. If it is not aligned, IVPR + IVORs may
not point to an exception handler.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-04-24 23:58:30 -05:00
Mike Frysinger
5b84dd67cf usb: replace wait_ms() with mdelay()
Common code has a mdelay() func, so use that instead of the usb-specific
wait_ms() func.  This also fixes the build errors:

ohci-hcd.c: In function 'submit_common_msg':
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1519:9: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1816:10: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1827:10: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1844:10: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1563:11: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1583:9: sorry, unimplemented: called from here
make[1]: *** [ohci-hcd.o] Error 1

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Marek Vasut <marex@denx.de>
2012-03-19 00:08:16 +01:00
Simon Glass
770605e4f9 bootstage: Replace show_boot_progress/error() with bootstage_...()
These calls should not be made directly any more, since bootstage
will call the show_boot_...() functions as needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-03-18 21:41:39 +01:00
Simon Glass
8ade950638 bootstage: Convert progress numbers 20-41 to enums
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-03-18 21:16:22 +01:00
Simon Glass
5ddb118da4 bootstage: Use show_boot_error() for -ve progress numbers
Rather than the caller negating our progress numbers to indicate an
error has occurred, which seems hacky, add a function to indicate this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-03-18 20:56:00 +01:00
Simon Glass
578ac1e9ba bootstage: Make use of BOOTSTAGE_ID_RUN_OS in show_boot_progress()
This changes the number 15 as used in boot_stage_progress() to use the
new name provided for it. This is a separate patch because it touches
so many files.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-03-18 20:45:57 +01:00
Simon Glass
d01b17611b ppc: Change memsz variable to signed char
This seems to be unsigned char for no good reason. Tidy this up and
remove the casts.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-03-03 16:56:51 +01:00
ramneek mehresh
79f49120ba powerpc/8xxx:Add MPH controller support in USB device-tree fixup
Add support for fixing usb mode and phy type for
MPH(Multi Port Host) USB controllers in device-tree nodes.
Required for socs like P3060, P5020, etc having MPH USB controller

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2012-02-15 16:50:14 -06:00
ramneek mehresh
5a52977f28 powerpc/8xxx: Cleanup USB device-tree fixup
Some code cleanup done for USB device-tree fixup:
	- handling error value returned from fdt_fixup_usb_mode_phy_type()
	- using ARRAY_SIZE macro
	- using snprintf instead of sprintf

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2012-02-15 16:50:14 -06:00
Wolfgang Denk
670c24f6f3 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
  fsl_lbc: add printout of LCRR and LBCR to local bus regs
  sbc8548: Fix up local bus init to be frequency aware
  sbc8548: enable support for hardware SPD errata workaround
  sbc8548: relocate fixed ddr init code to ddr.c file
  sbc8548: Make enabling SPD RAM configuration work
  sbc8548: Fix LBC SDRAM initialization settings
  sbc8548: enable ability to boot from alternate flash
  sbc8548: relocate 64MB user flash to sane boundary
  Revert "SBC8548: fix address mask to allow 64M flash"
  MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC
  eXMeritus HWW-1U-1A: Add support for the AT24C128N I2C EEPROM
  eXMeritus HWW-1U-1A: Minor environment variable tweaks
2012-01-13 20:38:49 +01:00
Paul Gortmaker
3dc23c7c30 fsl_lbc: add printout of LCRR and LBCR to local bus regs
It can be handy to have these in the output when trying to
debug odd behaviour.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-13 12:56:06 -06:00
Joe Hershberger
4b56579388 mpc83xx: Add a GPIO driver for the MPC83XX family
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-01-09 20:10:33 -06:00
Jerry Huang
509adc8b77 powerpc/mpc83xx: set TXEQA/TXEQE value for mpc837XE sata
In the current u-boot code, the value of these fields are the reserved
value (0b100), through the signal integrity measurement on freescale's
board with these reserved setting, the signal eye is out of the recommended
spec for non-transition amplitude at 500mV nominal.
According to the errata for MPC8379E, we should make a change to the
recommended setting from essentially nothing at this time to 0b001 for SATA.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-12-12 18:33:39 -06:00
Kumar Gala
3b2001105f powerpc/bootm: Flush ramdisk and device tree image when booting on MP
We already flush the kernel image after we've loaded it to ensure
visiblity to the other cores.  We need to do the same thing for the
ramdisk and device tree images.  In AMP boot scenarios we might not be
HW cache coherent with the secondary core that we are loading and
setting the ramdisk and device tree up for.  Thus we need to ensure
we've flushed the regions of memory utilized by ramdisk and device tree
so the loadding and any modifications (from decompression or fdt updates)
are made visible to the secondary cores.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-12-12 08:17:52 +01:00
Kyle Moffett
01baa05643 powerpc: Minimal private libgcc to build on Debian
Standard Debian powerpc and powerpcspe systems only include hard-float
libgcc in their native compilers, which causes scary build warnings when
building U-Boot.

Debian and other PowerPC-supporting distributions used to provide libgcc
and other libraries in a "nof" (soft-float) form in the "multilib"
packages.  As they were completely unused by the distribution and
therefore tended to be very buggy it was decided to save some time on
the part of the maintainers and build-servers by removing them.

Admittedly, right now the linker warnings do not indicate any problems,
as the included routines do not use any floating point at all.

The concern is that if floating-point code were ever added it might
cause hard-float code to be unexpectedly included in U-Boot without
generating a hard error.  This would cause unexplained crashes or
indeterminate results at runtime.

The easiest way to resolve this is to borrow the routines that U-Boot
needs from the Linux kernel, which has the same issue.

Specifically, the routines are: _ashldi3(), _ashrdi3(), and _lshrdi3().
They were borrowed from arch/powerpc/kernel/misc_32.S as of v2.6.38-rc5,
commit 85e2efbb1db9a18d218006706d6e4fbeb0216213, and are GPLv2+.

The Makefile framework was copied from the U-Boot ARM port.

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kumar Gala <kumar.gala@freescale.com>
Cc: Stefan Roese <sr@denx.de>
2011-12-07 23:04:32 +01:00
Wolfgang Denk
1086c5d6f8 Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
* 'master' of git://git.denx.de/u-boot-mpc83xx:
  powerpc/83xx: fix sdram initialization for keymile boards
  powerpc/mpc83xx: cleanup makefile for mpc83xx
2011-12-07 23:01:26 +01:00
Stefan Roese
ce2acd371c ppc4xx: Remove usbdev.c
As this "driver" doesn't seem to be really used, let's remove
it completely.

Signed-off-by: Stefan Roese <sr@denx.de>
2011-12-07 20:00:40 +01:00
Wolfgang Denk
ad37ef1a85 arch/powerpc/cpu/mpc86xx/cpu.c: Fix GCC 4.6 build warning
Fix:
cpu.c: In function 'checkcpu':
cpu.c:51:7: warning: variable 'ver' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
2011-12-02 00:16:46 +01:00
Ira W. Snyder
9839709ea3 mpc85xx: support for Freescale COM Express P2020
This adds support for the Freescale COM Express P2020 board. This board
is similar to the P1_P2_RDB, but has some extra (as well as missing)
peripherals.

Unlike all other mpc85xx boards, it uses a watchdog timeout to reset.
Using the HRESET_REQ register does not work.

This board has no NOR flash, and can only be booted via SD or SPI. This
procedure is documented in Freescale Document Number AN3659 "Booting
from On-Chip ROM (eSDHC or eSPI)." Some alternative documentation is
provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated
Processor Reference Manual" (section 4.5).

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 09:07:51 -06:00
Kumar Gala
411e150375 arch/powerpc/cpu/mpc8xxx/ddr/interactive.c: Fix GCC 4.6 build warning
Fix:

interactive.c: In function 'fsl_ddr_interactive':
interactive.c:1357:15: warning: variable 'len' set but not used [-Wunused-but-set-variable]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
Ira W. Snyder
c18de0d7ae mpc85xx: support board-specific reset function
This is useful for boards which cannot be reset in the usual way for the
85xx CPU. An example is a board which can only be reset by a hardware
watchdog.

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
Timur Tabi
cc15df57b1 powerpc/85xx: verify the localbus device tree address before booting the OS
The localbus controller node in the device tree is typically a root node,
even though the controller is part of CCSR.  If we were to put the lbc
node under the SOC node, then the 'ranges' property in the lbc node would
translate through the 'ranges' property of the parent SOC node, and we
don't want that.

Since the lbc is a separate node, it's possible for the 'reg' property to
be wrong.  This happened with the original version of p1022ds.dts, which
used a 32-bit value in the 'reg' address, instead of a 36-bit address.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
Ira W. Snyder
2f3a71f235 mpc8xxx: update module_type values from JEDEC DDR3 SPD Specification
Newer JEDEC DDR3 SPD Specifications define several additional values for
the DDR3 module_type field which were undefined when this code was
written. Update the code to handle the newer module types.

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
Timur Tabi
f2717b47ea powerpc/85xx: clean up and document the QE/FMAN microcode macros
Several macros are used to identify and locate the microcode binary image
that U-boot needs to upload to the QE or Fman.  Both the QE and the Fman
use the QE Firmware binary format to package their respective microcode data,
which is why the same macros are used for both.  A given SOC will only have
a QE or an Fman, so this is safe.

Unfortunately, the current macro definition and usage has inconsistencies.
For example, CONFIG_SYS_FMAN_FW_ADDR was used to define the address of Fman
firmware in NOR flash, but CONFIG_SYS_QE_FW_IN_NAND contains the address
of NAND.  There's no way to know by looking at a variable how it's supposed
to be used.

In the future, the code which uploads QE firmware and Fman firmware will
be merged.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
Timur Tabi
fbc20aab11 powerpc/85xx: always implement the work-around for Erratum SATA_A001
On the P1022/P1013, the work-around for erratum SATA_A001 was implemented
only if U-Boot initializes SATA, but SATA is not initialized by default.  So
move the work-around to the CPU initialization function, so that it's always
executed on the SOCs that need it.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
Timur Tabi
3e0529f742 powerpc/85xx: CONFIG_FSL_SATA_V2 should be defined in config_mpc85xx.h
Macro CONFIG_FSL_SATA_V2 is defined if the SOC has a V2 Freescale SATA
controller, so it should be defined in config_mpc85xx.h instead of the various
board header files.  So now CONFIG_FSL_SATA_V2 is always defined on the P1013,
P1022, P2041, P3041, P5010, and P5020.  It was already defined for the
P1010 and P1014.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
York Sun
4108508a96 powerpc/85xx: Add workaround for erratum A-003474
Erratum A-003474: Internal DDR calibration circuit is not supported

Impact:
Experience shows no significant benefit to device operation with
auto-calibration enabled versus it disabled. To ensure consistent timing
results, Freescale recommends this feature be disabled in future customer
products. There should be no impact to parts that are already operating
in the field.

Workaround:
Prior to setting DDR_SDRAM_CFG[MEM_EN]=1, do the following:
1. Write a value of 0x0000_0015 to the register at offset
	CCSRBAR + DDR OFFSET + 0xf30
2. Write a value of 0x2400_0000 to the register at offset
	CCSRBAR + DDR OFFSET + 0xf54

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
Jia Hongtao
33c875366e powerpc/85xx: fixup flexcan device tree clock-frequency
Make the fixup matchable with dts and kernel.  Update the compatible from
"fsl,flexcan-v1.0" to "fsl,p1010-flexcan" and Change the "clock-freq"
property to "clock-frequency".  We also change flexcan frequency from
CCB-clock to CCB-clock/2 according to P1010 spec.

We now keep the old interfaces to make previous kernel work. They should
be removed in the future.

Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:05 -06:00
Kumar Gala
43f082bb7f powerpc/85xx: Add workaround for erratum CPU-A003999
Erratum A-003999: Running Floating Point instructions requires special
initialization.

Impact:
Floating point arithmetic operations may result in an incorrect value.

Workaround:
Perform a read modify write to set bit 7 to a 1 in SPR 977 before
executing any floating point arithmetic operation. This bit can be set
when setting MSR[FP], and can be cleared when clearing MSR[FP].
Alternatively, the bit can be set once at boot time, and never cleared.
There will be no performance degradation due to setting this bit.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:05 -06:00
Kim Phillips
9da752e97f mpc83xx: spd_sdram - fix gcc 4.6 compiler warning
Configuring for sbc8349 board...
spd_sdram.c: In function 'spd_sdram':
spd_sdram.c:152:41: warning: variable 'trfc_high' set but not used [-Wunused-but-set-variable]

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-11-16 21:40:26 +01:00
Stefan Roese
bddf144cb6 iop480_uart.c: Fix GCC 4.6 build warnings
Fix:
iop480_uart.c: In function 'serial_init':
iop480_uart.c:137:16: warning: variable 'val' set but not used [-Wunused-but-set-variable]

Signed-off-by: Stefan Roese <sr@denx.de>
2011-11-16 21:17:36 +01:00
Stefan Roese
4a1272662a 40x_spd_sdram.c: Fix GCC 4.6 build warnings
Fix:
40x_spd_sdram.c: In function 'spd_sdram':
40x_spd_sdram.c:137:6: warning: variable 'sdram0_b3cr' set but not used [-Wunused-but-set-variable]
40x_spd_sdram.c:136:6: warning: variable 'sdram0_b2cr' set but not used [-Wunused-but-set-variable]
40x_spd_sdram.c:129:6: warning: variable 'sdram0_ecccfg' set but not used [-Wunused-but-set-variable]

Signed-off-by: Stefan Roese <sr@denx.de>
2011-11-16 21:15:59 +01:00
Stefan Roese
deeecb7c7e 44x_spd_ddr2.c: Fix GCC 4.6 build warnings
44x_spd_ddr2.c: In function 'initdram':
44x_spd_ddr2.c:450:17: warning: variable 'dimm_spd' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c: In function 'program_copt1':
44x_spd_ddr2.c:1003:16: warning: variable 'ddrtype' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c: In function 'DQS_calibration_process':
44x_spd_ddr2.c:2498:7: warning: variable 'window_found' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c:2497:16: warning: variable 'end_rffd' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c:2496:16: warning: variable 'end_rqfd' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c:2495:16: warning: variable 'begin_rffd' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c:2494:16: warning: variable 'begin_rqfd' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c:2493:7: warning: variable 'min_end' set but not used [-Wunused-but-set-variable]

Signed-off-by: Stefan Roese <sr@denx.de>
2011-11-16 21:15:51 +01:00
Stefan Roese
6cd71d0f17 44x_spd_ddr.c: Fix GCC 4.6 build warnings
Fix:
44x_spd_ddr.c: In function 'program_cfg0':
44x_spd_ddr.c:384:16: warning: variable 'dimm_64bit' set but not used [-Wunused-but-set-variable]
44x_spd_ddr.c:383:16: warning: variable 'dimm_32bit' set but not used [-Wunused-but-set-variable]

Signed-off-by: Stefan Roese <sr@denx.de>
2011-11-16 21:15:36 +01:00
Stefan Roese
a6370da13e cmd_ecctest.c: Fix GCC 4.6 build warnings
Fix:
cmd_ecctest.c: In function 'inject_ecc_error':
cmd_ecctest.c:116:6: warning: variable 'val' set but not used [-Wunused-but-set-variable]
cmd_ecctest.c: In function 'rewrite_ecc_parity':
cmd_ecctest.c:154:6: warning: variable 'val' set but not used [-Wunused-but-set-variable]

Signed-off-by: Stefan Roese <sr@denx.de>
2011-11-16 21:15:20 +01:00
Stefan Roese
8f6db4b7ab 4xx_ibm_ddr2_autocalib.c: Fix GCC 4.6 build warnings
Fix:
4xx_ibm_ddr2_autocalib.c: In function 'get_membase':
4xx_ibm_ddr2_autocalib.c:157:8: warning: variable 'bxcf' set but not used [-Wunused-but-set-variable]
4xx_ibm_ddr2_autocalib.c: In function 'DQS_calibration_methodB':
4xx_ibm_ddr2_autocalib.c:722:8: warning: variable 'rffd' set but not used [-Wunused-but-set-variable]

Signed-off-by: Stefan Roese <sr@denx.de>
2011-11-16 21:15:07 +01:00