Commit graph

23815 commits

Author SHA1 Message Date
Andre Przywara
7f0938eac5 sunxi: fel: drop redundant "control register" save/restore
For some reasons shrouded in mystery, the code saving the FEL state was
saving the SCTLR register twice, with the second copy trying to justify
itself by using its ancient "control register" alias name.

Drop the redundant second copy, both from the fel_stash data structure,
and also the code saving and restoring it.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
2023-01-21 01:32:23 +00:00
Andre Przywara
4871650c95 sunxi: armv8: fel: load only 32-bit values
Both the values and the MMIO addresses that we need during the 64-bit FEL
restore are smaller than 2^32, so we don't need to do any 64-bit loads.

Change the loads to only load 32 bits worth of data, that saves us some
bytes for storing the values.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
2023-01-21 01:32:23 +00:00
Andre Przywara
3baa0fbe6b sunxi: f1c100s: Drop no-MMC hack
When support for the Allwinner F1C100s SoC was originally introduced,
its DT lacked any MMC nodes, which upset our sunxi-u-boot.dtsi overlay,
when it tried to add an alias to the SD card.  To quickly fix this back
then, we guarded that alias with a preprocessor macro.

Now the F1C100s family has gained MMC nodes, so we don't need the
special treatment anymore. Just remove this guard.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
2023-01-21 01:32:23 +00:00
Tom Rini
6e7df1d151 global: Finish CONFIG -> CFG migration
At this point, the remaining places where we have a symbol that is
defined as CONFIG_... are in fairly odd locations. While as much dead
code has been removed as possible, some of these locations are simply
less obvious at first. In other cases, this code is used, but was
defined in such a way as to have been missed by earlier checks.  Perform
a rename of all such remaining symbols to be CFG_... rather than
CONFIG_...

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-20 12:27:24 -05:00
Tom Rini
a84fa1bef4 nxp: Finish migration of SYS_FSL_SRDS_[12] to Kconfig
As this is used on both ARM and PowerPC platforms, this needs to be
listed in arch/Kconfig.nxp and match how they're currently used by
select'ing them under the required PowerPC ARCH_xxx options.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-01-20 12:27:23 -05:00
Tom Rini
89c90cadf3 nxp: Finish migration of SYS_FSL_IFC_BANK_COUNT to Kconfig
As this is used on both ARM and PowerPC platforms, this needs to be
asked in arch/Kconfig.nxp.  Set the PowerPC defaults based on
arch/powerpc/include/asm/config_mpc85xx.h and remove the default set in
drivers/mtd/nand/raw/fsl_ifc_nand.c

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-01-20 12:27:06 -05:00
Tom Rini
80c75ce00d fsl-layerscape: Rework usage of CONFIG_CLUSTER_CLK_FREQ
In the case where CONFIG_CLUSTER_CLK_FREQ is not defined, simply set
cluster_clk to get_board_sys_clk().

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-01-20 12:27:06 -05:00
Tom Rini
1c88640fc8 arm: lib1funcs.S: Update compatibility with Linux comment slightly
At this point, the Linux code for "lib1funcs" has changed rather
dramatically. While a resync would be beneficial, it's outside the scope
of what we need here.  Simply remove the define for CONFIG_AEABI and
tests for it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-01-20 12:27:06 -05:00
Tom Rini
ae8a922bd2 arm: Rework usage of CONFIG_ARMV[78]_SECURE_BASE in linker scripts
In order to avoid defining CONFIG_ARMV[78_]SECURE_BASE as empty in the
linker scripts, if not already defined, add and use
__ARMV[78_]SECURE_BASE for when the base is not defined and we want the
linker scripts to continue.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-01-20 12:27:06 -05:00
Tom Rini
409163a46e arc: Migrate ARC_MMU_VER to Kconfig
Move this value to Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-01-20 12:27:06 -05:00
Tom Rini
a3fda0d30a global: Remove unused CONFIG defines
Remove some CONFIG symbols and related comments, etc, that are unused
within the code itself at this point.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-01-20 12:27:06 -05:00
Neil Armstrong
640192d04f ARM: meson: add support for Odroid Go Ultra
This adds initial support for the Hardkernel Odroid Go Ultra.

The Odroid Go Ultra is a portable gaming device with the following
characteristics:
- Amlogic S922X SoC
- RK817 & RK818 PMICs
- 2GiB LPDDR4
- On board 16GiB eMMC
- Micro SD Card slot
- 5inch 854×480 MIPI-DSI TFT LCD
- Earphone stereo jack, 0.5Watt 8Ω Mono speaker
- Li-Polymer 3.7V/4000mAh Battery
- USB-A 2.0 Host Connector
- x16 GPIO Input Buttons
- 2x ADC Analog Joysticks
- USB-C Port for USB2 Device and Charging

The following are not yet handled:
- Battery RK818 Gauge and Charging
- 5inch 854×480 MIPI-DSI TFT LCD

Link: https://lore.kernel.org/r/20230119-u-boot-odroid-go-ultra-v1-2-f96bab9db396@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-01-20 16:27:40 +01:00
Neil Armstrong
2acbc33b3d ARM: dts: sync Amlogic ARM64 DT from v6.2-rc1
This syncs the Amlogic G12A, G12B & SM1 base DT + the
Odroid Go Ultra DT from Linux v6.2-rc1 from commmit [1].

[1] 1b929c02afd3 ("Linux 6.2-rc1")

Link: https://lore.kernel.org/r/20230119-u-boot-odroid-go-ultra-v1-1-f96bab9db396@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-01-20 16:27:40 +01:00
Neil Armstrong
e327e2affd ARM: meson: switch AXG & GX dwc2 otg to DM
With CONFIG_DM_USB_GADGET=y, we no longer need any board_usb_*() logic
because:
* the dwc2 driver is DM compatible, and handles its own clock enabling
* the dwc3-meson-gxl glue drivers handles "force mode switching"

Remove all mach-meson gx & axg usb code and enable CONFIG_DM_USB_GADGET.

Note: Only configs having both CONFIG_USB_DWC3_MESON_GXL=y *and*
      USB_GADGET_DWC2_OTG=y have been updated.

Thanks for the original work from Mattijs at [1]

[1] https://lore.kernel.org/all/20221024-meson-dm-usb-v1-2-2ab077a503b9@baylibre.com/

Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20230117-u-boot-usb-gxl-otg-dm-v1-2-2853f6d75b06@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-01-20 16:21:31 +01:00
Tom Rini
53c47c59e6 convert rockchip to use binman
patman fix for checkpatch
 binman optional entries, improved support for ELF symbols
 trace improvements
 minor fdt refactoring
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Merge tag 'dm-pull-18jan23' of https://source.denx.de/u-boot/custodians/u-boot-dm

convert rockchip to use binman
patman fix for checkpatch
binman optional entries, improved support for ELF symbols
trace improvements
minor fdt refactoring
2023-01-19 09:46:57 -05:00
Simon Glass
12c3e948ee rockchip: Drop the FIT generator script
This is not used anymore. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-18 14:55:40 -07:00
Simon Glass
e0c0efff2a rockchip: Support building the all output files in binman
Add the required binman images to replace the Makefile rules which are
currently used. This includes subsuming:

   - tpl/u-boot-tpl-rockchip.bin if TPL is enabled
   - idbloader.img if either or both of SPL and TPL are enabled
   - u-boot.itb if SPL_FIT is enabled
   - u-boot-rockchip.bin if SPL is used, either using u-boot.itb when
     SPL_FIT is enabled or u-boot.img when it isn't

Note that the intermediate files are dropped with binman, since it
producing everything in one pass. This means that
tpl/u-boot-tpl-rockchip.bin is not created, for example.

Note that for some 32-bit rk3288 boards, rockchip-optee.dtsi is included.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-18 14:55:39 -07:00
Simon Glass
4170dd9ec0 rockchip: Use multiple-images for rk3399
Enable multiple-images so we can generate more than one image. Also
add a comment for the end of the #if block.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-18 11:50:01 -07:00
Simon Glass
b2412dd5de rockchip: Enable bootstage on rockpro64
This board is useful for benchmarking overall U-Boot performance. Enable
the bootstage feature so we get a report.

Since this returns to the boot rom before finishing executing
board_init_r() in SPL, add a few bootstage calls so that we can collect
timing from TPL.

For the stash region, use a portion of SRAM, 64KB below the stack top.
This allows the TPL image to be up to nearly 120KB (it is typically about
64KB). SPL normally runs from SDRAM at 0, so can use the same stash
region.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-18 11:49:13 -07:00
Simon Glass
d81d17637a arm: Support trace on armv8
Use the notrace attribute so that timer functions can be used when
tracing. This is required to avoid infinite loops when recording a trace.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-18 11:49:13 -07:00
Simon Glass
33c60a38bb trace: Use notrace for short
The attribute syntax is quite verbose. Use the macro provided for this
purpose.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-18 11:49:12 -07:00
Tom Rini
448e2b6327 event: Correct dependencies on the EVENT framework
The event framework is just that, a framework. Enabling it by itself
does nothing, so we shouldn't ask the user about it. Reword (and correct
typos) around this the option and help text. This also applies to
DM_EVENT and EVENT_DYNAMIC. Only EVENT_DEBUG and CMD_EVENT should be
visible to the user to select, when EVENT is selected.

With this, it's time to address the larger problems. When functionality
uses events, typically via EVENT_SPY, the appropriate framework then
must be select'd and NOT imply'd. As the functionality will cease to
work (and so, platforms will fail to boot) this is non-optional and
where select is appropriate. Audit the current users of EVENT_SPY to
have a more fine-grained approach to select'ing the framework where
used. Also ensure the current users of event_register and also select
EVENT_DYNAMIC.

Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reported-by: Oliver Graute <Oliver.Graute@kococonnector.com>
Reported-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Fixes: 7fe32b3442 ("event: Convert arch_cpu_init_dm() to use events")
Fixes: 42fdcebf85 ("event: Convert misc_init_f() to use events")
Fixes: c5ef202557 ("dm: fix DM_EVENT dependencies")
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-01-18 12:46:13 -05:00
Tom Rini
e8272cbd59 x86: Fix saying arch_cpu_init_dm in debug/docs
The function arch_cpu_init_dm was renamed to fsp_setup_pinctrl in these
cases, so rename debug / docs to match.

Cc: Simon Glass <sjg@chromium.org>
Fixes: 7fe32b3442 ("event: Convert arch_cpu_init_dm() to use events")
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-18 12:46:13 -05:00
Tom Rini
5b958dea5c Merge branch '2022-01-16-bootstd-updates'
To quote the author:
So far standard boot lacks a boot menu, although it is possible to create
a rudimentary one using the existing 'bootmenu' command.

Even then, this text-based menu offer only basic functionality and does
not take full advantage of the displays which are common on many devices.

This series provides a 'bootflow menu' command which allows the user to
select from the available bootflows. An attempt is made to show the name
of the available operating systems, by reading more information into the
bootflow. A logo can be read also, where supported, so that this can be
presented to the user when an option is highlighted.

Full use is made of TrueType fonts, if enabled. For cases where only a
serial console is available, it falls back to a simple text-based menu.

All of this is implementing using a new 'expo' construct, a collection of
scenes (like menu screens) which can be navigated by the user to view
information and select options. This is fairly general and should be able
to cope with a wider array of use cases, with less hacking of the menu
code, such as is currently needed for CMD_BOOTEFI_BOOTMGR.

Of course it would be possible to enhance the existing menu rather than
creating a new setup. Instead it seems better to make the existing menu
use expo, if code space permits. It avoids the event-loop problem and
should be more extensible, given its loosely coupled components and use of
IDs instead of pointers. Further motivation is provided in the
documentation.

For now the CLI keypress-decoding code is split out to be used by the new
menu. The key codes defined by menu.h are reused also.

This is of course just a starting point. Some ideas for future work are
included in the documentation.
2023-01-17 08:55:40 -05:00
Tom Rini
6d03688e75 Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- kirkwood: Convert to DM Serial for various Kirkwood boards (Tony)
- orion-timer: Fix problem in early_init_done() (Stefan)
2023-01-17 08:10:56 -05:00
Mattijs Korpershoek
b96640cbfb ARM: meson: g12a: switch dwc2 otg to DM
With CONFIG_DM_USB_GADGET=y, we no longer need any board_usb_*() logic
because:
* the dwc2 driver is DM compatible, and handles its own clock enabling
* the dwc3-meson-g12a glue drivers handles "force mode switching"

Remove all mach-meson/g12a usb code and enable CONFIG_DM_USB_GADGET.

Note: Only configs having both CONFIG_USB_DWC3_MESON_G12A=y *and*
      USB_GADGET_DWC2_OTG=y have been updated.

Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20221024-meson-dm-usb-v1-2-2ab077a503b9@baylibre.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-01-17 09:27:17 +01:00
Tony Dinh
bee23537ba arm: kirkwood: Convert to DM Serial for various Kirkwood boards
For Kirkwood boards, it is necessary to have early malloc in DRAM area
when Driver Model for Serial is enabled. Please see Michael's patch here:
https://lore.kernel.org/u-boot/20220817193809.1059688-20-michael@walle.cc/

This patch enables the early malloc in DRAM for all Kirkwood boards.
Note that this will work for boards that have either non-DM serial
and DM_SERIAL. Also, add the CONFIG_KIRKWOOD_COMMON option to enable
DM_SERIAL as a common option for boards that have been tested.

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
2023-01-17 07:08:42 +01:00
Simon Glass
d985f1dbdd bootstd: Add a test for the bootstd menu
Add a test which checks that two operating systems can be displayed in a
menu, allowing one to be selected.

Enable a few things on snow so that the unit tests build.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-16 18:26:51 -05:00
Simon Glass
30f3333d88 image: Move common image code to image_board and command
We should use the cmd/ directory for commands rather than for common code
used elsewhere in U-Boot. Move the common 'source' code into
image-board.c to achieve this.

The image_source_script() function needs to call run_command_list()  so
seems to belong better in the command library. Move and rename it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-16 18:26:50 -05:00
Ashok Reddy Soma
724379d9af xilinx: versal-net: Add support for timer and start it
Add support for starting timer by setting up time stamp generator
registers. This is done only for EL3 i.e. mini U-Boot case.
For other cases, it will be done TF-A.

Add COUNTER_FREQUENCY and IOU_SWITCH_DIVISOR0 to Kconfig so that they
can be tuned as required.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fcd8b0dc4b45a11f5e753afff42f84738ac813da.1673336645.git.michal.simek@amd.com
2023-01-16 15:34:37 +01:00
Quentin Schulz
c925be73a0 rockchip: add support for PX30 Ringneck SoM on Haikou Devkit
The PX30-µQ7 (Ringneck) is a system-on-module featuring the Rockchip
PX30 in a micro Qseven-compatible form-factor.

PX30-µQ7 features:
        * CPU: quad-core Cortex-A35
        * DRAM: 2GB dual-channel
        * eMMC: onboard eMMC
        * SD/MMC
        * TI DP83825I 10/100Mbps PHY
        * USB:
                * USB2.0 dual role port
                * 3x USB2.0 host via onboard USB2.0 hub
        * Display: MIPI-DSI
        * Camera: MIPI-CSI
        * onboard 2.4GHz WiFi + Bluetooth module
        * Companion Controller: on-board additional microcontroller
	  (STM32 Cortex-M0 or ATtiny):
                * RTC
                * fan controller
                * CAN (only STM32)

The non-U-Boot DTS files are imported from Linux v6.2-rc2.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2023-01-16 18:01:11 +08:00
Quentin Schulz
2c9f077064 arm64: dts: rockchip: sync px30 DTSI with Linux kernel v6.1
Sync the px30 dtsi from Linux kernel v6.1.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2023-01-16 18:01:11 +08:00
Quentin Schulz
600e0177e7 rockchip: px30: insert u-boot, spl-boot-device into U-Boot device tree
It is possible to boot U-Boot proper from a different storage medium
than the one used by the BOOTROM to load the SPL. This information is
stored in the u-boot,spl-boot-device Device Tree property and is
accessible from U-Boot proper so that it has knowledge at runtime where
it was loaded from.

Let's add support for this feature for px30.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2023-01-16 18:01:11 +08:00
Quentin Schulz
3898237384 rockchip: px30: list possible SPL boot devices
BOOTROM sets a bit in a CPU register so that the software can know from
where the first stage bootloader was booted. One use case for this is to
specify the default loading medium for U-Boot proper to match the one
used by the BOOTROM to load the SPL (same-as-spl in
u-boot,spl-boot-order).

Let's create the mapping between BOOTROM value and Device Tree node
names for MMC devices.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2023-01-16 18:01:11 +08:00
Quentin Schulz
e53856aaf4 rockchip: px30: fix possibly unused grf and cru variables
The grf and cru are only used when no UART base is provided by the user
(defaults to UART2) or for UART1, UART3 and UART5 to be used for the
debug UART. Therefore, let's surround those variable definitions with
the proper checks.

This wasn't an issue before support for UART0 was added, because all
cases were using cru and grf. UART0 only uses pmucru so there's a need
to not define those variables anymore.

Fixes: d0af506625 ("rockchip: px30: support debug uart on UART0")
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:11 +08:00
Peter Robinson
5a42fd0258 rockchip: Add initial support for the PINE64 Pinephone Pro
The Pinephone Pro is another device by PINE64. It's closely related
to the Pinebook Pro of which this initial support is derived from.

Specification:
- A variant of the Rockchip RK3399
- A 6 inch 720*1440 DSI display
- Front and rear cameras
- Type-C interface with alt mode display (DP 1.2) and PD charging
- 4GB LPDDR4 RAM
- 128GB eMMC
- mSD card slot
- An AP6255 module for 802.11ac WiFi and Bluetooth 5
- Quectel EG25-G 4G/LTE modem

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-16 18:01:11 +08:00
Peter Robinson
30a6d14a97 arm64: dts: rk3399: Add upstream Pinephone Pro dts
Initial support for the PinePhone Pro has now landed upstream in
Linux 6.1 RC1 so sync the dts from 6.2-rc1 for initial support.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
2023-01-16 18:01:11 +08:00
Jagan Teki
b8f1ca9540 board: rockchip: Add Edgeble Neu2 IO Board
Neural Compute Module 2(Neu2) IO board is an industrial form factor
IO board from Edgeble AI.

General features:
- microSD slot
- MIPI DSI connector
- 2x USB Host
- 1x USB OTG
- Ethernet
- mini PCIe
- Onboard PoE
- RS485, RS232, CAN
- Micro Phone array
- Speaker
- RTC battery slot
- 40-pin expansion

Neu2 needs to mount on top of this IO board in order to create complete
Edgeble Neural Compute Module 2(Neu2) IO platform.

Add support for it.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2023-01-16 18:01:11 +08:00
Jagan Teki
43e89241f3 ARM: dts: rockchip: Add rv1126-u-boot.dtsi
Add u-boot,dm-spl and u-boot,dm-pre-reloc related properties
for Rockchip RV1126 SoC.

Both eMMC and SD boot are tested in Edgeble Neu2 SoM.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:11 +08:00
Jagan Teki
0736dad4ed ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2) IO
Neural Compute Module 2(Neu2) IO board is an industrial form factor
evaluation board from Edgeble AI.

General features:
- microSD slot
- MIPI DSI connector
- 2x USB Host
- 1x USB OTG
- Ethernet
- mini PCIe
- Onboard PoE
- RS485, RS232, CAN
- Micro Phone array
- Speaker
- RTC battery slot
- 40-pin expansion

Neu2 needs to mount on top of this IO board in order to create complete
Edgeble Neural Compute Module 2(Neu2) IO platform.

Add support for it.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2023-01-16 18:01:11 +08:00
Jagan Teki
d12471c7be ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2)
Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module
based on Rockchip RV1126 from Edgeble AI.

General features:
- Rockchip RV1126
- 2/4GB LPDDR4
- 8/16/32GB eMMC
- 2x MIPI CSI2 FPC connector
- Fn-link 8223A-SR WiFi/BT

Industrial grade (-40 °C to +85 °C) version of the same class of module
called Neu2k powered with Rockchip RV1126K.

Neu2 needs to mount on top of Edgeble IO boards for creating complete
platform solutions.

Add support for it.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2023-01-16 18:01:11 +08:00
Jagan Teki
c6154677c8 arm: rockchip: rv1126: Set dram area unsecure for SPL
Unsecure the dram area so that MMC, USB, and SFC controllers
can able to read data from dram.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:11 +08:00
Jagan Teki
ffb191e458 arm: rockchip: Add RV1126 arch core support
Rockchip RV1126 is a high-performance vision processor SoC
for IPC/CVR, especially for AI related application.

Add arch core support for it.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I22fde40ec375e3c6aba39808abf252edc45d4b04
2023-01-16 18:01:11 +08:00
Jagan Teki
2204a8c90a ARM: dts: rockchip: Add Rockchip RV1126 SoC
RV1126 is a high-performance vision processor SoC for IPC/CVR,
especially for AI related application.

It is based on quad-core ARM Cortex-A7 32-bit core which integrates
NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core
and 512KB unified L2 cache. It has build-in NPU supports INT8/INT16
hybrid operation and computing power is up to 2.0TOPs.

This patch add basic core dtsi support.

Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2023-01-16 18:01:11 +08:00
Jagan Teki
3fc0dee585 ARM: dts: rockchip: Add Rockchip RV1126 pinctrl
Add pinctrl definitions for Rockchip RV1126.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:11 +08:00
Jagan Teki
43cecf7234 arm: rockchip: Add grf header for rv1126
Add GRF header for Rockchip RV1126.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:11 +08:00
Jagan Teki
f4ca986e29 arch: rockchip: Add cru header for rv1126
Add clock and reset unit header include for rv1126.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:11 +08:00
Jagan Teki
e869b3485c ram: rockchip: Add rv1126 ddr driver support
Add DDR driver for Rockchip RV1126 SoC.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:10 +08:00
Jagan Teki
5ab30c3176 ram: rockchip: Update ddr pctl regs for px30
Add full ddr pctl registers and bit masks for px30.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:10 +08:00
Jagan Teki
29c3148974 ram: rockchip: Compute ddr capacity based on grf split
DDR chip capacity is computed based on GRF split in some
Rockchip SoC's like PX30 and RV1126.

Add split argument in ddr print info so-that the respective
ddr driver will pass the grf split.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:10 +08:00
Quentin Schulz
ccaa55fb6e rockchip: puma-rk3399: sync DTS with Linux kernel next-20221114
This synchronizes the Device Trees related to Puma RK3399 SoM with Linux
kernel next-20221114 to include two important changes pertaining to
eMMC and SD card instability.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:10 +08:00
Quentin Schulz
4b56446002 rockchip: px30: make watchdog and tsadc trigger a first global reset
By default, the PX30 is configured for watchdog and tsadc to trigger a
second global reset which is a more permissive reset than first global
reset.

From TRM part 1 "2.3 System Reset Solution":
glb_srstn_1 will reset the all logic, and
glb_srstn_2 will reset the all logic except GRF, SGRF and all GPIOs.

This enforces that the watchdog and tsadc trigger glb_srstn_1 as
similarly done for RK3399 in U-Boot (in SDRAM driver for some reason?),
TF-A and Coreboot.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:10 +08:00
Hai Pham
0fe4366c9a ARM: renesas: condor: switch eMMC bus to 1V8
The eMMC card has two supplies, VCC and VCCQ. The VCC supplies the NAND
array and the VCCQ supplies the bus. On Condor, the VCC is connected to
3.3V rail, while the VCCQ is connected to 1.8V rail. Adjust the pinmux
to match the bus, which is always operating in 1.8V mode.

Based on Linux commit 69efe4bbeda50745 ("arm64: dts: renesas: condor:
Switch eMMC bus to 1V8") from Wolfram Sang

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2023-01-14 14:10:12 +01:00
Marek Vasut
3405cfa29d ARM: dts: renesas: condor: Enable SPI NOR fast-read
This board requires SPI NOR fast-read, otherwise the SPI NOR
access returns corrupted data. Enable the fast-read explicitly
in DT as it has been disabled in the MTD subsystem by commit
d008190920 ("mtd: spi-nor: Mask out fast read if not requested in DT")

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2023-01-14 14:10:12 +01:00
Tom Rini
fe4c21de4f Add driver to manage onboard hub supplies
Add calibration support for stm32-adc
 Linux kernel v6.1 DT synchronization for stm32mp151.dtsi
 stm32mp157a-dk1-scmi-u-boot.dtsi update
 Add support of OP-TEE and STM32MP13x in bsec driver
 ECDSA various fixes for stm32mp
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Merge tag 'u-boot-stm32-20230113' of https://source.denx.de/u-boot/custodians/u-boot-stm

Add driver to manage onboard hub supplies
Add calibration support for stm32-adc
Linux kernel v6.1 DT synchronization for stm32mp151.dtsi
stm32mp157a-dk1-scmi-u-boot.dtsi update
Add support of OP-TEE and STM32MP13x in bsec driver
ECDSA various fixes for stm32mp
2023-01-13 09:56:19 -05:00
Marek Vasut
0e86f813f4 ARM: stm32: Make ECDSA authentication available to U-Boot
With U-Boot having access to ROM API call table, it is possible to use
the ROM API call it authenticate e.g. signed kernel fitImages using the
BootROM ECDSA support. Make this available by pulling the ECDSA BootROM
call support from SPL-only guard.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-13 13:46:57 +01:00
Marek Vasut
6eea541514 ARM: stm32: Pass ROM API table pointer to U-Boot proper
The ROM API table pointer is no longer accessible from U-Boot, fix
this by passing the ROM API pointer through. This makes it possible
for U-Boot to call ROM API functions to authenticate payload like
signed fitImages.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-13 13:46:57 +01:00
Marek Vasut
dbeaca79b7 ARM: stm32: Factor out save_boot_params
The STM32MP15xx platform currently comes with two incompatible
implementations of save_boot_params() weak function override.
Factor the save_boot_params() implementation into common cpu.c
code and provide accessors to read out both ROM API table address
and DT address from any place in the code instead.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-13 13:46:57 +01:00
Marek Vasut
bbafbc044d ARM: stm32: Fix ECDSA authentication with Dcache enabled
In case Dcache is enabled while the ECDSA authentication function is
called via BootROM ROM API, the MMU tables are set up and the BootROM
region is not marked as executable, so an attempt to run code from it
results in a hang. Mark the BootROM region as executable as suggested
by Patrick to prevent the hang.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-13 13:46:57 +01:00
Heinrich Schuchardt
7e808fcc97 efi_loader: add .rela sections to .text on arm64
_relocate() needs the information in .rela* for self relocation
of the EFI binary.

Fixes: d7ddeb66a6 ("efi_loader: fix building aarch64 EFI binaries")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-01-13 09:09:07 +01:00
Sean Anderson
0998a20cfc misc: fs_loader: Add function to get the chosen loader
The fs_loader device is used to pull in settings via the chosen node.
However, there was no library function for this, so arria10 was doing it
explicitly. This function subsumes that, and uses ofnode_get_chosen_node
instead of navigating the device tree directly. Because fs_loader pulls
its config from the environment by default, it's fine to create a device
with nothing backing it at all. Doing this allows enabling
CONFIG_FS_LOADER without needing to modify the device tree.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-01-12 14:06:15 -05:00
Kshitiz Varshney
81ceb1695a Added dcp_rng driver initialization code
This commit initializes dcp_rng device driver inside
arch_misc_init() function.

Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
2023-01-12 11:25:46 -05:00
Patrick Delaunay
a33885ff49 stm32mp: Add support of STM32MP13x in bsec driver
Add support for "st,stm32mp13-bsec" for STM32MP13x in the
bsec driver based on OP-TEE pseudo TA STM32MP BSEC.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:37:13 +01:00
Patrick Delaunay
33a909a42a stm32mp: Add OP-TEE support in bsec driver
When OP-TEE is used, the SMC for BSEC management are not available and
the STM32MP BSEC pseudo TA must be used (it is mandatory for STM32MP13
and it is a new feature for STM32MP15x).

The BSEC driver try to open a session to this PTA BSEC at probe
and use it for OTP read or write access to fuse or to shadow.

This patch also adapts the commands stm32key and stboard to handle
the BSEC_LOCK_PERM lock value instead of 1.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:37:13 +01:00
Patrick Delaunay
27bad4e7fc stm32mp: cosmetic: Update of bsec driver
Remove unnecessary return in stm32mp_bsec_write_lock and replace tab
by space for plat_auto opts.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:37:13 +01:00
Patrick Delaunay
6e391c7d5f ARM: dts: stm32: Add timer interrupts on stm32mp15
The timer units in the stm32mp15x CPUs have interrupts, depending on the
timer flavour either one "global" or four dedicated ones. Add the irqs
to the timer units on stm32mp15x.

Sync the DT Files with linux kernel v6.1 and with commit a9b70102253ce
("ARM: dts: stm32: Add timer interrupts on stm32mp15")

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:30:52 +01:00
Patrick Delaunay
126aa470d6 ARM: dts: stm32mp15: fix typo in stm32mp15xx-dkx.dtsi
Remove unnecessary space in device tree stm32mp15xx-dkx.dtsi.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:30:52 +01:00
Patrick Delaunay
d1d56638c4 ARM: dts: stm32mp15: remove clksrc include in SCMI dtsi file
The include file stm32mp1-clksrc.h is not necessary for the SCMI STM32MP15
dtsi files as the clock tree is not defined in the U-Boot SCMI device tree;
these SCMI device tree only support TFABOOT with stm32mp15_defconfig,
SPL with the basic boot defconfig is not supported.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:30:52 +01:00
Fabrice Gasnier
214d6e7e68 ARM: dts: stm32: add support for USB2514B onboard hub on stm32mp157c-ev1
Add support for USB2514B onboard hub on stm32mp157c EV1 board. The HUB
is supplied by a 3v3 PMIC regulator.

[backport from linux ad9591b01d24]
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-01-12 16:19:53 +01:00
Fabrice Gasnier
79da4074dd ARM: dts: stm32: update vbus-supply of usbphyc_port0 on stm32mp157c-ev1
phy-stm32-usbphyc bindings uses a connector node with vbus-supply
property.

[backport from linux 43e55d778a6b]
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:08:43 +01:00
Ville Skyttä
fe482b886d Use grep -E or plain grep instead of egrep
`egrep` has been deprecated in GNU grep since 2007,
and since 3.8 it emits obsolescence warnings:
https://git.savannah.gnu.org/cgit/grep.git/commit/?id=a9515624709865d480e3142fd959bccd1c9372d1
Acked-by: Dhruva Gole <d-gole@ti.com>
2023-01-11 15:02:24 -05:00
Heinrich Schuchardt
89d47b33b5 Kconfig: move NXP specific stuff into a sub-menu
Having NXP specific items in the main menu is confusing. Especially
the comment line

   *** Other functionality shared between NXP SoCs ***

is simply misleading.

Move all NXP stuff into a separate sub-menu.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-01-11 15:02:24 -05:00
Heinrich Schuchardt
c394e8d0ee Kconfig: clean up skipping low-level initialization
Put all entries for skipping low-level initialization into a sub-menu.
Use different titles for main U-Boot, SPL, TPL.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-01-11 15:02:24 -05:00
Luca Ceresoli
66b39c1a8c arm64: zynqmp: remove Avnet UltraZed-EV Starter Kit
Nobody seems interested and able to keep this board supported, and
xilinx_zynqmp_virt_defconfig is supposed to be enough for any zynqmp board.

See the discussion at: https://lore.kernel.org/u-boot/CAPnjgZ3hHbyiFf=_Lp-Wz_XOWBkV-3vK4Q3xp=7bcERw-spNpA@mail.gmail.com/T/#m76d726f1ab3f7074c8105c9a2af2110ac7d18708

Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Link: https://lore.kernel.org/r/20230111082554.1930782-1-luca.ceresoli@bootlin.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-01-11 10:43:39 +01:00
Andrew Davis
367c9e0614 ARM: omap3: evm: Name this directory omap3evm
Before this was named just evm, which doesn't match the naming
of the other TI board file directory and makes it look like a
common directory for evms. Name this omap3evm.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Derald Woods <woods.technical@gmail.com>
2023-01-10 15:39:08 -05:00
Dzmitry Sankouski
971ccee2fb SoC: sdm845: find and save KASLR to env variables
KASLR address is needed to boot fully functional Android.
KASLR is set by primary bootloader, and since u-boot is used
as a secondary bootloader(replacing kernel) on sdm845 platform,
KASLR may be found by comparing memory chunks at relocaddr over
supposed KASLR range.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-01-10 15:39:07 -05:00
Bryan Brattlof
b672e85810 arm: mach-k3: copy bootindex to OCRAM for main domain SPL
Texas Instruments has begun enabling security settings on the SoCs it
produces to instruct ROM and TIFS to begin protecting the Security
Management Subsystem (SMS) from other binaries we load into the chip by
default.

One way ROM and TIFS do this is by enabling firewalls to protect the
OCSRAM and HSM RAM regions they're using during bootup.

The HSM RAM the wakeup SPL is in is firewalled by TIFS to protect
itself from the main domain applications. This means the 'bootindex'
value in HSM RAM, left by ROM to indicate if we're using the primary
or secondary boot-method, must be moved to OCSRAM (that TIFS has open
for us) before we make the jump to the main domain so the main domain's
bootloaders can keep access to this information.

Signed-off-by: Bryan Brattlof <bb@ti.com>
2023-01-10 15:39:07 -05:00
Martyn Welch
7c34b71a42 arm64:mach-k3 am625_init: Correct boot mode detection
The boot mode detection assumes that BOOT_DEVICE_MMC2 should always
result in MMCSD_MODE_FS, but MMCSD_MODE_RAW is also a valid option for
this port.

The current logic also avoids looking at the bootmode pin strapping,
which should be the primary means of determining whether a device is
being booted in MMCSD_MODE_EMMCBOOT mode.

Switch around the logic to check the boot mode to determine whether the
eMMC boot mode is expected or MMC/SD boot mode. From there we can look
at the boot mode config if in MMC/SD boot mode to determine whether to
attempt RAW or FS based booting.

This change allows U-Boot to also be successfully booted from RAW
offsets in addition to from a filesystem.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2023-01-10 15:39:06 -05:00
Sjoerd Simons
39248d3260 arm: dts: k3-am625-sk: Enable first ethernet port
The K3 am625 sk EVM has two ethernet ports; Enable the first one for
usage in u-boot.

Signed-off-by: Sjoerd Simons <sjoerd@collabora.com>
2023-01-10 15:39:06 -05:00
Jim Liu
7ee1c4d1d1 pinctrl: nuvoton: add NPCM7xx/NPCM8xx reset type detect
add reset type detect and persist setting.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-01-10 15:39:06 -05:00
Alexey Romanov
311106a1c6 arm/mach-meson: move smc commands in cmd/meson
It is incorrect to keep commands in the arch/ folder.

Signed-off-by: Alexey Romanov <avromanov@sberdevices.ru>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230110105650.54580-3-avromanov@sberdevices.ru
[narmstrong: moved after cmd/sound in index.rst]
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-01-10 15:27:17 +01:00
Alexey Romanov
12d7827349 asm/arch-meson: add missing meson_sm_write_efuse signature
This function can be used by other modules. Also add comments.

Signed-off-by: Alexey Romanov <avromanov@sberdevices.ru>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20230110105650.54580-2-avromanov@sberdevices.ru
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-01-10 15:25:48 +01:00
Michal Simek
67ac851488 arm64: zynqmp: Remove unused snps,refclk_fladj property
The commit c55ac51a55 ("usb: dwc3: Program GFLADJ") hopefully fixed
issues around fladj logic. This DT property was used in Xilinx stack only
that's why remove because it is not needed anymore.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9bdbd1156b19e28cdebeca29149268b0579a8b6a.1670855257.git.michal.simek@amd.com
2023-01-10 08:15:54 +01:00
Harini Katakam
fd5f2718d3 arm64: zynqmp: Enable TI phy reset via GPIO
Add DT property to support reset of TI PHY connected to GEM.
This is present in RevA DT but needs to be extended RevB/1.0/1.1
versions which are built on top.

Fixes: 2b1db7b18c ("arm64: zynqmp: Wire GEM reset gpio")
Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/7b093616ddea269043cbbb1e3806644d5a4b23be.1670854455.git.michal.simek@amd.com
2023-01-10 08:15:54 +01:00
Harini Katakam
4664a63cc7 arm64: zynqmp: Describe TI phy as ethernet phy ID on ZCU102 RevB & up
TI phy requires a reset before PHY address detection to make sure
correct strapping via MIO is detected. Facilitate the same using
ethernet-phy-id compatible string. GPIO reset entry will be added in
a separate commit.
This support is present in RevA but needs to be extended to RevB/1.0/1.1
versions which are built on top.

Fixes: 13622c7a9d ("arm64: zynqmp: Describe TI phy as ethernet-phy-id")
Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6d500a83a787316353d4b26c75d1b51d29e3730e.1670854455.git.michal.simek@amd.com
2023-01-10 08:15:54 +01:00
Michal Simek
ef440787da arm64: zynqmp: Remove unused USB DT properties
xlnx,usb-polarity, xlnx,usb-reset-mode and snps,mask_phy_reset are not
documented in dt binding and also there is no code associated with them
that's why remove them.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/369139fafa1745252ef687e31aebf6bcc2080a32.1670853972.git.michal.simek@amd.com
2023-01-10 08:15:54 +01:00
Michal Simek
a30a3ec888 arm64: zynqmp: Remove id from usb node name
There is no reason to have number in usb node name. This is also sync up
patch with upstream kernel.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/7b13db34031af88a5738d2ec2e05d2498ea8c869.1670590595.git.michal.simek@amd.com
2023-01-10 08:15:54 +01:00
Michal Simek
b1d3e7fd9a arm64: zynqmp: Align gpio-key node names with dtschema
The node names should be generic and DT schema expects certain pattern
(e.g. with key/button/switch).
It is based on kernel commit (228e8a88b1915a2b467c83d8d0976605f1272fae).

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ae23999097553acb21dfca9288a913bb8b24587a.1670590595.git.michal.simek@amd.com
2023-01-10 08:15:54 +01:00
Michal Simek
8dfdb6958b arm64: zynqmp: Fix AMS device tree node
Aligned node description with the Linux kernel. Node has been added by
kernel commit (271c1fa01c2307cf74f4656390d6299991119c3e).

Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/74188b64cf615100345d058e026cb0d2de0e089b.1670590595.git.michal.simek@amd.com
2023-01-10 08:15:54 +01:00
Michal Simek
e6a01d5102 arm64: zynqmp: Added GEM reset definitions
The Cadence GEM/MACB driver now utilizes the platform-level reset on the
ZynqMP platform. Add reset definitions to the ZynqMP platform device
tree to allow this to be used.
Linux upstream commit (e461bd6f43f4e568f7436a8b6bc21c4ce6914c36).

Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/14e3637735dbc626659e96d142f04a63398362f8.1670590595.git.michal.simek@amd.com
2023-01-10 08:15:54 +01:00
Michal Simek
2a5f7fd30c arm64: zynqmp: Sync #dma-cells property location
Sync property location with Linux kernel done by Linux commit
(1ff2d58e60c8093e9be935b1f191341c0cda957a).

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e09ad90ea610a81528ef5ecbc931bc9791b1c653.1670590595.git.michal.simek@amd.com
2023-01-10 08:15:54 +01:00
Tom Rini
cebdfc22da Merge branch 'next'
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-01-09 11:30:08 -05:00
Heinrich Schuchardt
4bba71ff83 efi_loader: make .data section of *_efi.so files RW
When building with binutils 2.39 warnings

    *_efi.so has a LOAD segment with RWX permissions

occur.

Use SHF_WRITE | SHF_ALLOC as section flags for the .data section.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-01-06 22:27:30 +01:00
Tom Rini
b82f12b642 First set of u-boot-at91 features for the 2023.04 cycle
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Merge tag 'u-boot-at91-2023.04-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next

First set of u-boot-at91 features for the 2023.04 cycle:

This feature set includes the new DM-based NAND flash driver (old non-DM
driver is still kept for backwards compatibility), and the move to DM
NAND flash driver for sam9x60ek board. Feature set also includes
devicetree alignment for sama7g5 with Linux, devicetree alignment on USB
with Linux for all boards (sama5, sam9x60), chip id for sama7g5, minor
configs and tweaks.
2023-01-06 11:53:26 -05:00
Tom Rini
9ddcdcc03c - stm32mp: Fix board_get_usable_ram_top(): workaround to avoid issue after the
commit 777aaaa706 ("common/memsize.c: Fix get_effective_memsize() to check
   for overflow") because the effective DDR effective size is reduce by 4KiB
   and sometime the board hang on boot
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Merge tag 'u-boot-stm32-20230106' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- stm32mp: Fix board_get_usable_ram_top(): workaround to avoid issue after the
  commit 777aaaa706 ("common/memsize.c: Fix get_effective_memsize() to check
  for overflow") because the effective DDR effective size is reduce by 4KiB
  and sometime the board hang on boot
2023-01-06 08:16:15 -05:00
Adam Ford
edd9c891d2 arm: dts: rz-g2-beacon-u-boot: Fix QSPI Regression
The QSPI is accessed via the RPC-IF, but the compatible flags
previously used a different name.  This compatibel name was changed
which broke the ability to access the QSPI.  Fix this by removing
the custom naming reference.

Fixes: 68083b897b ("renesas: Fix RPC-IF compatible values")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2023-01-06 08:14:19 -05:00
Fabio Estevam
f8548ce0e0 imx7d-pico: Fix the name of the u-boot.dtsi file
Since commit 2f96d4dd95 ("imx7s/d: synchronise device trees with linux")
the imx7d-pico board no longer boots.

The reason is that prior to the above commit there was an explicit
inclusion of arch/arm/dts/imx7d-pico-u-boot.dtsi inside imx7d-pico.dtsi.

After the syncing with the Linux upstream dtsi, this u-boot.dtsi inclusion
is gone and the board fails to boot.

U-Boot uses the imx7d-pico-pi.dtb file, so rename the u-boot.dtsi to
imx7d-pico-pi-u-boot.dtsi which gets included automatically by U-Boot
standard make logic and makes the board boot again.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-01-06 08:14:19 -05:00
Pali Rohár
1b697407ae powerpc/mpc85xx: socrates: Re-enable building u-boot-socrates.bin
U-Boot build system builds final U-Boot binary for socrates board in custom
file u-boot-socrates.bin (instead of standard u-boot.bin). Output target
file u-boot-socrates.bin is generated by binman as defined in board binman
config file arch/powerpc/dts/socrates-u-boot.dtsi.

But binman was disabled in commit 5af42eafd7 ("Makefile: Reduce usage of
custom mpc85xx u-boot.bin target") for all mpc85xx boards which do not use
standard powerpc binman config file arch/powerpc/dts/u-boot.dtsi and boards
which do not require binman at all.

The only such mpc85xx board is socrates. So since that commit, U-Boot does
not final binary for socrates board anymore.

Fix this issue by re-enabling binman for socrates board. And build process
starts again producing u-boot-socrates.bin binary.

Note that build process for this socrates board always produce u-boot.bin
binary which is broken and not usable for socrates board. Long term
solution should be to disable building broken binary u-boot.bin and then
renaming u-boot-socrates.bin to u-boot.bin, or switching to use common
powerpc binman config file arch/powerpc/dts/socrates-u-boot.dtsi (if it is
possible).

Fixes: 5af42eafd7 ("Makefile: Reduce usage of custom mpc85xx u-boot.bin target")
Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Heiko Schocher <hs@denx.de>
2023-01-06 08:14:19 -05:00
Marek Vasut
a2e0b041d6 arm: stm32mp: Fix board_get_usable_ram_top() again
Do not access gd->ram_size and assume this is actual valid RAM size. Since commit
777aaaa706 ("common/memsize.c: Fix get_effective_memsize() to check for overflow")
the RAM size may be less than gd->ram_size , call get_effective_memsize() to get
the limited value instead.

The aforementioned commit makes STM32MP15xx boards with 1 GiB of DRAM
at 0xc0000000 hang on boot, which is a grave defect.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-01-06 11:02:17 +01:00
Cristian Birsan
11c037ab92 ARM: at91: add sama7 SFR definitions
Special Function Registers(SFR) definitions for SAMA7 product family.

Signed-off-by: Cristian Birsan <cristian.birsan@microchip.com>
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
2023-01-05 10:06:09 +02:00
Sergiu Moga
e4ad98d67b ARM: dts: sama5d27_wlsom1_ek: Add pinctrl nodes for USB DT nodes
Add the pinctrl nodes required by the USB related DT nodes.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
2023-01-05 10:04:57 +02:00
Sergiu Moga
20bc95f8c8 ARM: dts: sama5d2_icp: Add pinctrl nodes for USB related DT nodes
Add the pinctrl subnodes required by the USB related DT nodes.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
2023-01-05 10:04:57 +02:00
Sergiu Moga
3cd06bfa96 ARM: dts: sama7g5ek: Add pinctrl, gpio and phy properties for USB
Add the required pinctrl, gpio and phy properties required by the
USB DT nodes of the sama7g5ek boards. Since these have not yet been
defined in upstream Linux, place them in the U-Boot specific DT file.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
2023-01-05 10:04:57 +02:00
Sergiu Moga
851960e591 ARM: dts: sama7g5: Add USB and UTMI DT nodes
Define the USB and UTMI DT nodes for the sama7g5 SoC's. Since these have
not yet been defined in upstream Linux, place them in the U-Boot specific
DT file.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-01-05 10:04:57 +02:00
Sergiu Moga
205ecbdccd ARM: dts: sam9x60ek: Add pinctrl and gpio properties for USB
Add the required pinctrl and gpio properties required by the USB DT
nodes of the sam9x60ek boards.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
2023-01-05 10:04:57 +02:00
Sergiu Moga
445ff8bb5a ARM: dts: sam9x60_curiosity: Add pinctrl and gpio properties for USB
Add the required pinctrl and gpio properties needed by the USB DT nodes
of the sam9x60_curiosity boards.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
2023-01-05 10:04:57 +02:00
Sergiu Moga
3631be3ed6 ARM: dts: sam9x60: Add OHCI and EHCI DT nodes
Add the OHCI and EHCI DT nodes for the sam9x60 SoC's.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-01-05 10:04:57 +02:00
Heinrich Schuchardt
d7ddeb66a6 efi_loader: fix building aarch64 EFI binaries
While our EFI binaries execute without problems on EDK II they crash on
a Lenovo X13s. Let our binaries look more like what EDK II produces:

* move all writable data to a .data section
* align sections to 4 KiB boundaries (matching EFI page size)
* remove IMAGE_SCN_LNK_NRELOC_OVFL from .reloc section flags

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-01-04 13:17:42 +01:00
Mihai Sain
ee43b1e744 ARM: dts: at91: sam9x60: add sdhci1 node and pinctrl
Add node for sdhci1 controller and its pinctrl.

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
2023-01-03 10:58:15 +02:00
Stefan Bosch
28663622cf arm: s5p4418: dm_serial: remove old code / add DEBUG_UART
Remove init of UART-clock and UART-reset in arch_cpu_init(). Add DEBUG_UART
to s5p4418_nanopi2_defconfig.

Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
2023-01-02 16:06:08 -05:00
Stefan Bosch
5745de2c9d arm: s5p4418: dm_serial: switch to DM_SERIAL
Switch the S5P4418-SOC and therefore the s5p4418_nanopi2 board to
DM_SERIAL.

Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
2023-01-02 16:06:08 -05:00
Stefan Bosch
c8ba27f760 arm: s5p4418: dm_serial: add uarts to dts
Add S5P4418 UARTs and appropriate pinctrl to dts. Add UART to
s5p4418-nanopi2.dts.

Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
2023-01-02 16:06:08 -05:00
Dai Okamura
872413bb0a arm: uniphier: use DM_TIMER of arm a9 global timer
All uniphier v7 SoCs have cortex-a9 and use cortex-a9 global timer
in a simple implementation. Now DM_TIMER of it is available
on 35751c7f3f ("timer: sti: convert sti-timer to arm a9 global timer"),
so let's switch to it.

The old driver reads the lower 32bits of counter field
and sets the prescaler as 50 with PERIPHCLK(=50MHz),
so the global timer works as a 32-bit 1MHz timer.

The DM_TIMER uses the whole 64bits with no prescaler,
so the global timer works as a 64-bit PERIPHCLK timer.

CONFIG_SYS_HZ_CLOCK is set as the default PERIPHCLK frequency,
if there is no 'clocks' property in devicetree.

Signed-off-by: Dai Okamura <okamura.dai@socionext.com>
2023-01-02 16:01:39 -05:00
Rob Herring
bd8851c5b4 dts: synquacer: Drop unused and undocumented GPIO 'base' property
The 'base' GPIO controller property is unused in u-boot and Linux. It is
also not documented in the binding. So drop it.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
2023-01-02 14:10:23 -05:00
Rob Herring
36ee37632c dts: synquacer: Drop unused and undocumented SPI properties
'active_clk_edges' and 'chipselect_num' SPI controller properties are
unused in u-boot and Linux. They are also not documented in the binding.
So drop them.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
2023-01-02 14:10:23 -05:00
Pali Rohár
499fe577c8 powerpc: dts: keymile: Deduplicate binman code
kmcent2-u-boot.dtsi file contains copy of powerpc u-boot.dtsi binman file.
So remove code duplication and replace it by including u-boot.dtsi file.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2023-01-02 14:06:31 -05:00
Rob Herring
00723684e4 dts: synquacer: Fix idle-states 'entry-method' value
The correct value for 'entry-method' in the idle-states binding is 'psci',
not 'arm,psci'. It hasn't mattered because it isn't used by the OS.

Signed-off-by: Rob Herring <robh@kernel.org>
2023-01-02 14:05:44 -05:00
Rob Herring
563f238b67 dts: synquacer: Fix "arm, armv7-timer-mem" node address sizes
The "arm,armv7-timer-mem" schema defines the address sizes for child
nodes to be 32-bit as there's no need for 64-bit offsets and sizes of
the child 'frame' nodes.

Signed-off-by: Rob Herring <robh@kernel.org>
2023-01-02 14:05:44 -05:00
Rob Herring
cc891c41f2 dts: synquacer: Use generic node names
DT node names should follow generic names defined in the DT spec. These
are also now checked by dtschema tools.

Signed-off-by: Rob Herring <robh@kernel.org>
2023-01-02 14:05:44 -05:00
Rob Herring
6136c85ed0 dts: synquacer: Drop CPU 'arm,armv8' compatibles
'arm,armv8' compatible is for software models only. so drop it from cpu
nodes.

Signed-off-by: Rob Herring <robh@kernel.org>
2023-01-02 14:05:43 -05:00
Christian Gmeiner
e93efaf9cc arm: dts: ti: k3-am64-mcu: Add pinctrl
Add the definition of the pinctrl for the MCU domain.

Same as kernel commit 500e6dfbb465531150ac6e2ff0856dd357ddc8a4

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2023-01-02 14:05:43 -05:00
Sean Anderson
bcc85b96b5 cmd: source: Support specifying config name
As discussed previously [1,2], the source command is not safe to use with
verified boot unless there is a key with required = "images" (which has its
own problems). This is because if such a key is absent, signatures are
verified but not required. It is assumed that configuration nodes will
provide the signature. Because the source command does not use
configurations to determine the image to source, effectively no
verification takes place.

To address this, allow specifying configuration nodes. We use the same
syntax as the bootm command (helpfully provided for us by fit_parse_conf).
By default, we first try the default config and then the default image. To
force using a config, # must be present in the command (e.g. `source
$loadaddr#my-conf`). For convenience, the config may be omitted, just like
the address may be (e.g. `source \#`). This also works for images
(`source :` behaves exactly like `source` currently does).

[1] https://lore.kernel.org/u-boot/7d711133-d513-5bcb-52f2-a9dbaa9eeded@prevas.dk/
[2] https://lore.kernel.org/u-boot/042dcb34-f85f-351e-1b0e-513f89005fdd@gmail.com/

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-31 13:35:19 -05:00
Sean Anderson
30fb045f2d treewide: Use NULL for script image name
Two callers of image_source_script specify an image name. However, both
use the deprecated @ syntax, indicating that they have not been updated
in a while. If CONFIG_FIT_SIGNATURE is enabled, we will reject such
names outright. Back in commit 152576a598 ("stm32mp: stm32prog: handle
U-Boot script in flashlayout alternate"), we even renamed one of the
nodes. Instead of hard-coding a script image name, just use the default
image.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-12-31 13:35:19 -05:00
Tom Rini
d36bc89be2 Pull request for efi-2023-01-rc5-2
Documentation:
 
 * Reorganize existing TI docs and add K3 generation page
 * Add texinfodocs and infodocs targets
 * Update qemu-ppce500 documentation
 * Use "changesets" not "csets" in statistics pages
 
 UEFI
 
 * Fix merging of preseeded non-volatile variables
 * Fix a return value in the  EFI_HII_DATABASE_PROTOCOL
 * Set UEFI specification version to 2.10
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Merge tag 'efi-2023-01-rc5-2' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2023-01-rc5-2

Documentation:

* Reorganize existing TI docs and add K3 generation page
* Add texinfodocs and infodocs targets
* Update qemu-ppce500 documentation
* Use "changesets" not "csets" in statistics pages

UEFI

* Fix merging of preseeded non-volatile variables
* Fix a return value in the  EFI_HII_DATABASE_PROTOCOL
* Set UEFI specification version to 2.10
2022-12-29 13:32:50 -05:00
Tom Rini
88c2e9157c PowerPC: Update dependencies on *SYS_MPC85XX_NO_RESETVEC
In 96699f097a ("powerpc: mpc85xx: Use binman to embed dtb inside
U-Boot") we introduce CONFIG_MPC85XX_HAVE_RESET_VECTOR and do so via
Kconfig. However, much later in de47ff5363 ("Convert
CONFIG_SYS_MPC85XX_NO_RESETVEC to Kconfig") I converted the symbol that
is the inverse of this to Kconfig. This should have included a
dependency on the first symbol as they are logically opposite.

The dependency being missing lead to some platforms being broken at
runtime due to discarding the require reset vector.

Fixes: de47ff5363 ("Convert CONFIG_SYS_MPC85XX_NO_RESETVEC to Kconfig")
Reported-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Pali Rohár <pali@kernel.org>
2022-12-29 13:31:30 -05:00
Heinrich Schuchardt
3ec07c99d8 efi_loader: set IMAGE_FILE_LARGE_ADDRESS_AWARE
For the 64bit EFI binaries that we create set the
IMAGE_FILE_LARGE_ADDRESS_AWARE characteristic in the PE-COFF header
to indicate that they can handle addresses above 2 GiB.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-12-29 10:51:50 +01:00
Tom Rini
e95bcfb56c bcmcygnus: Convert CONFIG_IPROC to Kconfig
Select this symbol as needed.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:13 -05:00
Tom Rini
f5dd0c5e19 configs: Remove unused or redundant CONFIG symbols
A number of CONFIG symbols have crept in that are never referenced in
code, so drop them here. Further, we have two symbols being enabled
in headers while already enabled correctly in Kconfig, so these lines
can also be removed.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:13 -05:00
Tom Rini
92a5c89998 global: Migrate CONFIG_X86_REFCODE_RUN_ADDR to CFG
Perform a simple rename of CONFIG_X86_REFCODE_RUN_ADDR to CFG_X86_REFCODE_RUN_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:13 -05:00
Tom Rini
d4143373f1 global: Migrate CONFIG_X86_REFCODE_ADDR to CFG
Perform a simple rename of CONFIG_X86_REFCODE_ADDR to CFG_X86_REFCODE_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:13 -05:00
Tom Rini
fa2fd534b5 global: Migrate CONFIG_X86_MRC_ADDR to CFG
Perform a simple rename of CONFIG_X86_MRC_ADDR to CFG_X86_MRC_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:13 -05:00
Tom Rini
bb34410509 global: Migrate CONFIG_WATCHDOG_PRESC et al to CFG
Perform simple renames of:
   CONFIG_WATCHDOG_PRESC to CFG_WATCHDOG_PRESC
   CONFIG_WATCHDOG_RC to CFG_WATCHDOG_RC

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
e660e972c4 global: Migrate CONFIG_TEGRA_BOARD_STRING to CFG
Perform a simple rename of CONFIG_TEGRA_BOARD_STRING to CFG_TEGRA_BOARD_STRING

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
3e204427c8 global: Migrate CONFIG_SMP_PEN_ADDR to CFG
Perform a simple rename of CONFIG_SMP_PEN_ADDR to CFG_SMP_PEN_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
3cdd6302a5 global: Migrate CONFIG_SC_TIMER_CLK to CFG
Perform a simple rename of CONFIG_SC_TIMER_CLK to CFG_SC_TIMER_CLK

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
9dbe356ef4 global: Migrate CONFIG_SAR_REG to CFG
Perform a simple rename of CONFIG_SAR_REG to CFG_SAR_REG

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:11 -05:00
Tom Rini
f9932d38a3 global: Migrate CONFIG_SAR2_REG to CFG
Perform a simple rename of CONFIG_SAR2_REG to CFG_SAR2_REG

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:11 -05:00
Tom Rini
3db78c830f global: Migrate CONFIG_RESET_VECTOR_ADDRESS to CFG
Perform a simple rename of CONFIG_RESET_VECTOR_ADDRESS to CFG_RESET_VECTOR_ADDRESS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:11 -05:00
Tom Rini
62350c72d4 global: Migrate CONFIG_QBMAN_CLK_DIV to CFG
Perform a simple rename of CONFIG_QBMAN_CLK_DIV to CFG_QBMAN_CLK_DIV

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:11 -05:00
Tom Rini
b33953b796 global: Migrate CONFIG_PME_PLAT_CLK_DIV to CFG
Perform a simple rename of CONFIG_PME_PLAT_CLK_DIV to CFG_PME_PLAT_CLK_DIV

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
f410d0ac8a global: Migrate CONFIG_PL011_CLOCK to CFG
Perform a simple rename of CONFIG_PL011_CLOCK to CFG_PL011_CLOCK

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
830fd095a3 global: Migrate CONFIG_PHY_IRAM_BASE to CFG
Perform a simple rename of CONFIG_PHY_IRAM_BASE to CFG_PHY_IRAM_BASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
8a897c4f97 global: Migrate CONFIG_MAX_RAM_BANK_SIZE to CFG
Perform a simple rename of CONFIG_MAX_RAM_BANK_SIZE to CFG_MAX_RAM_BANK_SIZE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
1d457dbb91 global: Migrate CONFIG_MAX_MEM_MAPPED to CFG
Perform a simple rename of CONFIG_MAX_MEM_MAPPED to CFG_MAX_MEM_MAPPED

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
dd5b58c491 global: Migrate CONFIG_MALLOC_F_ADDR to CFG
Perform a simple rename of CONFIG_MALLOC_F_ADDR to CFG_MALLOC_F_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
8000ac874c global: Migrate CONFIG_LOWPOWER_FLAG to CFG
Perform a simple rename of CONFIG_LOWPOWER_FLAG to CFG_LOWPOWER_FLAG

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
77db07ce1c global: Migrate CONFIG_LOWPOWER_ADDR to CFG
Perform a simple rename of CONFIG_LOWPOWER_ADDR to CFG_LOWPOWER_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
d4e4bc898b global: Migrate CONFIG_KSNET_NETCP_BASE to CFG
Perform a simple rename of CONFIG_KSNET_NETCP_BASE to CFG_KSNET_NETCP_BASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
f060d1885c global: Migrate CONFIG_KSNET_MAC_ID_BASE to CFG
Perform a simple rename of CONFIG_KSNET_MAC_ID_BASE to CFG_KSNET_MAC_ID_BASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
21bd204239 global: Migrate CONFIG_KSNET_CPSW_NUM_PORTS to CFG
Perform a simple rename of CONFIG_KSNET_CPSW_NUM_PORTS to CFG_KSNET_CPSW_NUM_PORTS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:49 -05:00