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global: Remove unused CONFIG defines

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Remove some CONFIG symbols and related comments, etc, that are unused
within the code itself at this point.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2023-01-10 11:19:28 -05:00
parent 8bd3c0a7e1
commit a3fda0d30a
17 changed files with 7 additions and 112 deletions
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6
arch/arm/cpu/arm1176/start.S
View file

@ -17,10 +17,6 @@
#include <config.h>
#include <linux/linkage.h>
#ifndef CONFIG_SYS_PHY_UBOOT_BASE
#define CONFIG_SYS_PHY_UBOOT_BASE CFG_SYS_UBOOT_BASE
#endif
/*
*************************************************************************
*
@ -88,7 +84,7 @@ cpu_init_crit:
/* Prepare to disable the MMU */
adr r2, mmu_disable_phys
sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_TEXT_BASE)
sub r2, r2, #(CFG_SYS_UBOOT_BASE - CONFIG_TEXT_BASE)
b mmu_disable
.align 5

2
arch/arm/mach-at91/include/mach/at91rm9200.h
View file

@ -126,6 +126,4 @@
#define ATMEL_PIO_PORTS 4 /* theese SoCs have 4 PIO */
#define ATMEL_PMC_UHP AT91RM9200_PMC_UHP
#define CONFIG_SYS_ATMEL_CPU_NAME "AT91RM9200"
#endif

16
arch/m68k/include/asm/immap.h
View file

@ -13,7 +13,6 @@
#include <asm/immap_520x.h>
#include <asm/m520x.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */
@ -36,7 +35,6 @@
#include <asm/immap_5235.h>
#include <asm/m5235.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
/* Timer */
@ -104,7 +102,6 @@
#include <asm/immap_5271.h>
#include <asm/m5271.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
/* Timer */
@ -127,7 +124,6 @@
#include <asm/immap_5272.h>
#include <asm/m5272.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
@ -150,8 +146,6 @@
#include <asm/immap_5275.h>
#include <asm/m5275.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
@ -174,7 +168,6 @@
#include <asm/immap_5282.h>
#include <asm/m5282.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
@ -221,8 +214,6 @@
#include <asm/immap_5301x.h>
#include <asm/m5301x.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */
@ -245,7 +236,6 @@
#include <asm/immap_5329.h>
#include <asm/m5329.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */
@ -268,9 +258,6 @@
#include <asm/immap_5441x.h>
#include <asm/m5441x.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
#if (CFG_SYS_UART_PORT < 4)
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
(CFG_SYS_UART_PORT * 0x4000))
@ -303,9 +290,6 @@
#include <asm/m547x_8x.h>
#ifdef CONFIG_FSLDMAFEC
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
#define FEC0_RX_TASK 0
#define FEC0_TX_TASK 1
#define FEC0_RX_PRIORITY 6

4
arch/powerpc/cpu/mpc85xx/fdt.c
View file

@ -92,7 +92,6 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
}
#if defined(T1040_TDM_QUIRK_CCSR_BASE)
#define CONFIG_MEM_HOLE_16M 0x1000000
/*
* Extract hwconfig from environment.
* Search for tdm entry in hwconfig.
@ -103,8 +102,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
/* Reserve the memory hole created by TDM LAW, so OSes dont use it */
if (tdm_hwconfig_enabled) {
off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE,
CONFIG_MEM_HOLE_16M);
off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE, SZ_16);
if (off < 0)
printf("Failed to reserve memory for tdm: %s\n",
fdt_strerror(off));

31
arch/powerpc/include/asm/processor.h
View file

@ -979,37 +979,6 @@
#define PVR_5200 0x80822011
#define PVR_5200B 0x80822014
/*
* 405EX/EXr CHIP_21 Errata
*/
#ifdef CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
#define CONFIG_SYS_4xx_CHIP_21_ERRATA
#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX1_RC
#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX1_RD
#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x0
#endif
#ifdef CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY
#define CONFIG_SYS_4xx_CHIP_21_ERRATA
#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX2_RC
#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX2_RD
#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x1
#endif
#ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY
#define CONFIG_SYS_4xx_CHIP_21_ERRATA
#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR1_RC
#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR1_RD
#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x2
#endif
#ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY
#define CONFIG_SYS_4xx_CHIP_21_ERRATA
#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR2_RC
#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR2_RD
#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x3
#endif
/*
* System Version Register
*/

1
board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c
View file

@ -13,7 +13,6 @@
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_I2C_EEPROM_ADDR_P1 0x51
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
static iomux_v3_cfg_t const eeprom_pads[] = {
IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),

12
common/spl/spl_fit.c
View file

@ -20,14 +20,6 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY_BUF_SZ
#define CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY_BUF_SZ (64 * 1024)
#endif
#ifndef CONFIG_SYS_BOOTM_LEN
#define CONFIG_SYS_BOOTM_LEN (64 << 20)
#endif
struct spl_fit_info {
const void *fit; /* Pointer to a valid FIT blob */
size_t ext_data_offset; /* Offset to FIT external data (end of FIT) */
@ -408,7 +400,7 @@ static int spl_fit_append_fdt(struct spl_image_info *spl_image,
if (CONFIG_IS_ENABLED(FIT_IMAGE_TINY))
return 0;
if (CONFIG_IS_ENABLED(LOAD_FIT_APPLY_OVERLAY)) {
#if CONFIG_IS_ENABLED(LOAD_FIT_APPLY_OVERLAY)
void *tmpbuffer = NULL;
for (; ; index++) {
@ -462,7 +454,7 @@ static int spl_fit_append_fdt(struct spl_image_info *spl_image,
free(tmpbuffer);
if (ret)
return ret;
}
#endif
/* Try to make space, so we can inject details on the loadables */
ret = fdt_shrink_to_minimum(spl_image->fdt_addr, 8192);
if (ret < 0)

10
doc/README.socfpga
View file

@ -6,16 +6,6 @@ This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore
based SOCFPGA. To know more about the hardware itself, please refer to
www.altera.com.
socfpga_dw_mmc
--------------
Here are macro and detailed configuration required to enable DesignWare SDMMC
controller support within SOCFPGA
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
-> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM
---------------------------------------------------------------------
Cyclone 5 / Arria 5 generating the handoff header files for U-Boot SPL
---------------------------------------------------------------------

7
drivers/i2c/soft_i2c.c
View file

@ -88,13 +88,6 @@ DECLARE_GLOBAL_DATA_PTR;
# define I2C_SOFT_DECLARATIONS
#endif
#if !defined(CONFIG_SYS_I2C_SOFT_SPEED)
#define CONFIG_SYS_I2C_SOFT_SPEED CONFIG_SYS_I2C_SPEED
#endif
#if !defined(CONFIG_SYS_I2C_SOFT_SLAVE)
#define CONFIG_SYS_I2C_SOFT_SLAVE CONFIG_SYS_I2C_SLAVE
#endif
/*-----------------------------------------------------------------------
* Definitions
*/

6
drivers/mtd/ubi/build.c
View file

@ -86,13 +86,7 @@ static bool fm_debug;
#endif
#else
#ifdef CONFIG_MTD_UBI_FASTMAP
#if !defined(CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT)
#define CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT 0
#endif
static bool fm_autoconvert = CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT;
#if !defined(CONFIG_MTD_UBI_FM_DEBUG)
#define CONFIG_MTD_UBI_FM_DEBUG 0
#endif
static bool fm_debug = CONFIG_MTD_UBI_FM_DEBUG;
#endif
#endif

2
drivers/net/eepro100.c
View file

@ -168,9 +168,7 @@ struct descriptor { /* A generic descriptor. */
unsigned char params[0];
};
#define CONFIG_SYS_CMD_EL 0x8000
#define CONFIG_SYS_CMD_SUSPEND 0x4000
#define CONFIG_SYS_CMD_INT 0x2000
#define CONFIG_SYS_CMD_IAS 0x0001 /* individual address setup */
#define CONFIG_SYS_CMD_CONFIGURE 0x0002 /* configure */

2
drivers/net/mvpp2.c
View file

@ -66,8 +66,6 @@ do { \
#define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
#define CONFIG_NR_CPUS 1
/* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
#define WRAP (2 + ETH_HLEN + 4 + 32)
#define MTU 1500

5
drivers/video/vidconsole-uclass.c
View file

@ -19,11 +19,6 @@
#include <video_font.h> /* Bitmap font for code page 437 */
#include <linux/ctype.h>
/* By default we scroll by a single line */
#ifndef CONFIG_CONSOLE_SCROLL_LINES
#define CONFIG_CONSOLE_SCROLL_LINES 1
#endif
int vidconsole_putc_xy(struct udevice *dev, uint x, uint y, char ch)
{
struct vidconsole_ops *ops = vidconsole_get_ops(dev);

3
drivers/video/videomodes.c
View file

@ -7,8 +7,7 @@
/************************************************************************
Get Parameters for the video mode:
The default video mode can be defined in CONFIG_SYS_DEFAULT_VIDEO_MODE.
If undefined, default video mode is set to 0x301
The default video mode is set to 0x301
Parameters can be set via the variable "videomode" in the environment.
2 diferent ways are possible:
"videomode=301" - 301 is a hexadecimal number describing the VESA

4
drivers/video/videomodes.h
View file

@ -6,10 +6,6 @@
#include <edid.h>
#ifndef CONFIG_SYS_DEFAULT_VIDEO_MODE
#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x301
#endif
/* Some mode definitions */
#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */
#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */

5
include/fsl_ddr.h
View file

@ -50,13 +50,12 @@ compute_dimm_parameters(const unsigned int ctrl_num,
*
* All data structures have to be on the stack
*/
#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
typedef struct {
generic_spd_eeprom_t
spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
struct dimm_params_s
dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];

3
include/fsl_usb.h
View file

@ -43,10 +43,8 @@ struct ccsr_usb_phy {
#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
#define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV (1 << 0)
#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
#define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13)
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK (5 << 4)
#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK (6 << 16)
@ -55,7 +53,6 @@ struct ccsr_usb_phy {
#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4)
#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
#define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0)
#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7)
#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4)