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https://github.com/AsahiLinux/u-boot
synced 2025-02-17 14:38:58 +00:00
global: Migrate CONFIG_RESET_VECTOR_ADDRESS to CFG
Perform a simple rename of CONFIG_RESET_VECTOR_ADDRESS to CFG_RESET_VECTOR_ADDRESS Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
parent
d4c8dd1e6f
commit
3db78c830f
18 changed files with 46 additions and 46 deletions
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@ -931,7 +931,7 @@ config ARCH_T4240
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imply FSL_SATA
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config MPC85XX_HAVE_RESET_VECTOR
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bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
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bool "Indicate reset vector at CFG_RESET_VECTOR_ADDRESS - 0xffc"
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depends on MPC85xx
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config BTB
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@ -5,8 +5,8 @@
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#include "config.h"
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#ifdef CONFIG_RESET_VECTOR_ADDRESS
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#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS
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#ifdef CFG_RESET_VECTOR_ADDRESS
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#define RESET_VECTOR_ADDRESS CFG_RESET_VECTOR_ADDRESS
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#else
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#define RESET_VECTOR_ADDRESS 0xfffffffc
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#endif
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@ -91,7 +91,7 @@
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align = <256>;
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};
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powerpc-mpc85xx-bootpg-resetvec {
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offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>;
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offset = <(CFG_RESET_VECTOR_ADDRESS - 0xffc)>;
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};
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};
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};
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@ -23,11 +23,11 @@
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u-boot-dtb-with-ucode {
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align = <4>;
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};
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#ifndef CFG_RESET_VECTOR_ADDRESS
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#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
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#endif
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powerpc-mpc85xx-bootpg-resetvec {
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offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>;
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offset = <(CFG_RESET_VECTOR_ADDRESS - 0xffc)>;
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};
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};
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};
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@ -57,7 +57,7 @@ enabled in relative defconfig file,
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1. CONFIG_DEFAULT_DEVICE_TREE="p1020rdb" (Change default device tree name if required)
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2. CONFIG_OF_CONTROL
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3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
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CONFIG_RESET_VECTOR_ADDRESS - 0xffc
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CFG_RESET_VECTOR_ADDRESS - 0xffc
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If device tree support is enabled in defconfig,
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1. use 'u-boot.bin' for NOR boot.
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@ -98,7 +98,7 @@ enabled in relative defconfig file,
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1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required)
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2. CONFIG_OF_CONTROL
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3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
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CONFIG_RESET_VECTOR_ADDRESS - 0xffc
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CFG_RESET_VECTOR_ADDRESS - 0xffc
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CPLD command
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============
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@ -379,7 +379,7 @@ enabled in relative defconfig file,
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1. CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" (Change default device tree name if required)
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2. CONFIG_OF_CONTROL
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3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
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CONFIG_RESET_VECTOR_ADDRESS - 0xffc
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CFG_RESET_VECTOR_ADDRESS - 0xffc
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If device tree support is enabled in defconfig,
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1. use 'u-boot.bin' for NOR boot.
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@ -285,7 +285,7 @@ enabled in relative defconfig file,
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1. CONFIG_DEFAULT_DEVICE_TREE="t2080qds" (Change default device tree name if required)
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2. CONFIG_OF_CONTROL
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3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
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CONFIG_RESET_VECTOR_ADDRESS - 0xffc
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CFG_RESET_VECTOR_ADDRESS - 0xffc
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If device tree support is enabled in defconfig,
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1. use 'u-boot.bin' for NOR boot.
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@ -281,7 +281,7 @@ enabled in relative defconfig file,
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1. CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" (Change default device tree name if required)
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2. CONFIG_OF_CONTROL
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3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
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CONFIG_RESET_VECTOR_ADDRESS - 0xffc
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CFG_RESET_VECTOR_ADDRESS - 0xffc
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If device tree support is enabled in defconfig,
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1. use 'u-boot.bin' for NOR boot.
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@ -24,7 +24,7 @@
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#ifdef CONFIG_SPIFLASH
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#ifdef CONFIG_NXP_ESBC
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#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
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#define CFG_RESET_VECTOR_ADDRESS 0x110bfffc
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#else
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#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
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#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
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@ -52,11 +52,11 @@
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#endif
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#ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
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#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
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#define CFG_RESET_VECTOR_ADDRESS 0x110bfffc
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#endif
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#ifndef CFG_RESET_VECTOR_ADDRESS
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#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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/* High Level Configuration Options */
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@ -12,7 +12,7 @@
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#define __CONFIG_H
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#ifdef CONFIG_RAMBOOT_PBL
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
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#endif
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#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
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@ -20,13 +20,13 @@
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#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
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#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
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(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
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#endif
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/* High Level Configuration Options */
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#ifndef CFG_RESET_VECTOR_ADDRESS
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#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
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@ -28,7 +28,7 @@
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#endif
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#ifdef CONFIG_SPIFLASH
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#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
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#define CFG_RESET_VECTOR_ADDRESS 0x30000FFC
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#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
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#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
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#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
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@ -36,7 +36,7 @@
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#endif
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#ifdef CONFIG_SDCARD
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#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
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#define CFG_RESET_VECTOR_ADDRESS 0x30000FFC
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#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
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#define CFG_SYS_MMC_U_BOOT_DST (0x30000000)
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#define CFG_SYS_MMC_U_BOOT_START (0x30000000)
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@ -45,8 +45,8 @@
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#endif /* CONFIG_RAMBOOT_PBL */
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#ifndef CFG_RESET_VECTOR_ADDRESS
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#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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/*
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@ -87,7 +87,7 @@
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#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
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#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
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(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
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#endif
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/*
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@ -29,7 +29,7 @@
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#endif
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#ifdef CONFIG_SPIFLASH
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#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
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#define CFG_RESET_VECTOR_ADDRESS 0x30000FFC
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#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
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#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
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#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
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#endif
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#ifdef CONFIG_SDCARD
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#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
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#define CFG_RESET_VECTOR_ADDRESS 0x30000FFC
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#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
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#define CFG_SYS_MMC_U_BOOT_DST (0x30000000)
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#define CFG_SYS_MMC_U_BOOT_START (0x30000000)
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/* High Level Configuration Options */
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#ifndef CFG_RESET_VECTOR_ADDRESS
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#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
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@ -30,7 +30,7 @@
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#endif
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#ifdef CONFIG_SPIFLASH
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#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
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#define CFG_RESET_VECTOR_ADDRESS 0x200FFC
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#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
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#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
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#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
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#endif
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#ifdef CONFIG_SDCARD
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#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
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#define CFG_RESET_VECTOR_ADDRESS 0x200FFC
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#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
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#define CFG_SYS_MMC_U_BOOT_DST (0x00200000)
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#define CFG_SYS_MMC_U_BOOT_START (0x00200000)
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#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
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#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
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(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
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#endif
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#ifndef CFG_RESET_VECTOR_ADDRESS
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#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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/*
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@ -30,7 +30,7 @@
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#endif
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#ifdef CONFIG_SPIFLASH
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#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
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#define CFG_RESET_VECTOR_ADDRESS 0x200FFC
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#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
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#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
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#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
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#endif
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#ifdef CONFIG_SDCARD
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#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
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#define CFG_RESET_VECTOR_ADDRESS 0x200FFC
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#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
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#define CFG_SYS_MMC_U_BOOT_DST (0x00200000)
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#define CFG_SYS_MMC_U_BOOT_START (0x00200000)
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#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
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#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
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(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
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#endif
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#ifndef CFG_RESET_VECTOR_ADDRESS
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#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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/*
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@ -16,13 +16,13 @@
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#ifdef CONFIG_RAMBOOT_PBL
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#ifndef CONFIG_SDCARD
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
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#else
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#define RESET_VECTOR_OFFSET 0x27FFC
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#define BOOT_PAGE_OFFSET 0x27000
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#ifdef CONFIG_SDCARD
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#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
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#define CFG_RESET_VECTOR_ADDRESS 0x200FFC
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#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
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#define CFG_SYS_MMC_U_BOOT_DST 0x00200000
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#define CFG_SYS_MMC_U_BOOT_START 0x00200000
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/* High Level Configuration Options */
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#ifndef CFG_RESET_VECTOR_ADDRESS
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#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
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/* High Level Configuration Options */
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#define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc
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#define CFG_RESET_VECTOR_ADDRESS 0xebfffffc
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#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
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#endif /* not CONFIG_TPL_BUILD */
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#endif
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#ifndef CFG_RESET_VECTOR_ADDRESS
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#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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#define CFG_SYS_CCSRBAR 0xffe00000
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