global: Migrate CONFIG_RESET_VECTOR_ADDRESS to CFG

Perform a simple rename of CONFIG_RESET_VECTOR_ADDRESS to CFG_RESET_VECTOR_ADDRESS

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-12-04 10:13:40 -05:00
parent d4c8dd1e6f
commit 3db78c830f
18 changed files with 46 additions and 46 deletions

View file

@ -931,7 +931,7 @@ config ARCH_T4240
imply FSL_SATA
config MPC85XX_HAVE_RESET_VECTOR
bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
bool "Indicate reset vector at CFG_RESET_VECTOR_ADDRESS - 0xffc"
depends on MPC85xx
config BTB

View file

@ -5,8 +5,8 @@
#include "config.h"
#ifdef CONFIG_RESET_VECTOR_ADDRESS
#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS
#ifdef CFG_RESET_VECTOR_ADDRESS
#define RESET_VECTOR_ADDRESS CFG_RESET_VECTOR_ADDRESS
#else
#define RESET_VECTOR_ADDRESS 0xfffffffc
#endif

View file

@ -91,7 +91,7 @@
align = <256>;
};
powerpc-mpc85xx-bootpg-resetvec {
offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>;
offset = <(CFG_RESET_VECTOR_ADDRESS - 0xffc)>;
};
};
};

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@ -23,11 +23,11 @@
u-boot-dtb-with-ucode {
align = <4>;
};
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#ifndef CFG_RESET_VECTOR_ADDRESS
#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
powerpc-mpc85xx-bootpg-resetvec {
offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>;
offset = <(CFG_RESET_VECTOR_ADDRESS - 0xffc)>;
};
};
};

View file

@ -57,7 +57,7 @@ enabled in relative defconfig file,
1. CONFIG_DEFAULT_DEVICE_TREE="p1020rdb" (Change default device tree name if required)
2. CONFIG_OF_CONTROL
3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
CONFIG_RESET_VECTOR_ADDRESS - 0xffc
CFG_RESET_VECTOR_ADDRESS - 0xffc
If device tree support is enabled in defconfig,
1. use 'u-boot.bin' for NOR boot.

View file

@ -98,7 +98,7 @@ enabled in relative defconfig file,
1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required)
2. CONFIG_OF_CONTROL
3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
CONFIG_RESET_VECTOR_ADDRESS - 0xffc
CFG_RESET_VECTOR_ADDRESS - 0xffc
CPLD command
============

View file

@ -379,7 +379,7 @@ enabled in relative defconfig file,
1. CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" (Change default device tree name if required)
2. CONFIG_OF_CONTROL
3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
CONFIG_RESET_VECTOR_ADDRESS - 0xffc
CFG_RESET_VECTOR_ADDRESS - 0xffc
If device tree support is enabled in defconfig,
1. use 'u-boot.bin' for NOR boot.

View file

@ -285,7 +285,7 @@ enabled in relative defconfig file,
1. CONFIG_DEFAULT_DEVICE_TREE="t2080qds" (Change default device tree name if required)
2. CONFIG_OF_CONTROL
3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
CONFIG_RESET_VECTOR_ADDRESS - 0xffc
CFG_RESET_VECTOR_ADDRESS - 0xffc
If device tree support is enabled in defconfig,
1. use 'u-boot.bin' for NOR boot.

View file

@ -281,7 +281,7 @@ enabled in relative defconfig file,
1. CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" (Change default device tree name if required)
2. CONFIG_OF_CONTROL
3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
CONFIG_RESET_VECTOR_ADDRESS - 0xffc
CFG_RESET_VECTOR_ADDRESS - 0xffc
If device tree support is enabled in defconfig,
1. use 'u-boot.bin' for NOR boot.

View file

@ -24,7 +24,7 @@
#ifdef CONFIG_SPIFLASH
#ifdef CONFIG_NXP_ESBC
#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#define CFG_RESET_VECTOR_ADDRESS 0x110bfffc
#else
#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
@ -52,11 +52,11 @@
#endif
#ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#define CFG_RESET_VECTOR_ADDRESS 0x110bfffc
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#ifndef CFG_RESET_VECTOR_ADDRESS
#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
/* High Level Configuration Options */

View file

@ -12,7 +12,7 @@
#define __CONFIG_H
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
@ -20,13 +20,13 @@
#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
/* High Level Configuration Options */
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#ifndef CFG_RESET_VECTOR_ADDRESS
#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS

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@ -28,7 +28,7 @@
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
#define CFG_RESET_VECTOR_ADDRESS 0x30000FFC
#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
@ -36,7 +36,7 @@
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
#define CFG_RESET_VECTOR_ADDRESS 0x30000FFC
#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_MMC_U_BOOT_DST (0x30000000)
#define CFG_SYS_MMC_U_BOOT_START (0x30000000)
@ -45,8 +45,8 @@
#endif /* CONFIG_RAMBOOT_PBL */
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#ifndef CFG_RESET_VECTOR_ADDRESS
#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
/*
@ -87,7 +87,7 @@
#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
/*

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@ -29,7 +29,7 @@
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
#define CFG_RESET_VECTOR_ADDRESS 0x30000FFC
#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
@ -37,7 +37,7 @@
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
#define CFG_RESET_VECTOR_ADDRESS 0x30000FFC
#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_MMC_U_BOOT_DST (0x30000000)
#define CFG_SYS_MMC_U_BOOT_START (0x30000000)
@ -48,8 +48,8 @@
/* High Level Configuration Options */
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#ifndef CFG_RESET_VECTOR_ADDRESS
#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS

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@ -30,7 +30,7 @@
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
#define CFG_RESET_VECTOR_ADDRESS 0x200FFC
#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
@ -38,7 +38,7 @@
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
#define CFG_RESET_VECTOR_ADDRESS 0x200FFC
#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_MMC_U_BOOT_DST (0x00200000)
#define CFG_SYS_MMC_U_BOOT_START (0x00200000)
@ -52,11 +52,11 @@
#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#ifndef CFG_RESET_VECTOR_ADDRESS
#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
/*

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@ -30,7 +30,7 @@
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
#define CFG_RESET_VECTOR_ADDRESS 0x200FFC
#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
@ -38,7 +38,7 @@
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
#define CFG_RESET_VECTOR_ADDRESS 0x200FFC
#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_MMC_U_BOOT_DST (0x00200000)
#define CFG_SYS_MMC_U_BOOT_START (0x00200000)
@ -52,11 +52,11 @@
#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#ifndef CFG_RESET_VECTOR_ADDRESS
#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
/*

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@ -16,13 +16,13 @@
#ifdef CONFIG_RAMBOOT_PBL
#ifndef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
#else
#define RESET_VECTOR_OFFSET 0x27FFC
#define BOOT_PAGE_OFFSET 0x27000
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
#define CFG_RESET_VECTOR_ADDRESS 0x200FFC
#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_MMC_U_BOOT_DST 0x00200000
#define CFG_SYS_MMC_U_BOOT_START 0x00200000
@ -34,8 +34,8 @@
/* High Level Configuration Options */
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#ifndef CFG_RESET_VECTOR_ADDRESS
#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS

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@ -122,7 +122,7 @@
/* High Level Configuration Options */
#define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc
#define CFG_RESET_VECTOR_ADDRESS 0xebfffffc
#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS

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@ -105,8 +105,8 @@
#endif /* not CONFIG_TPL_BUILD */
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#ifndef CFG_RESET_VECTOR_ADDRESS
#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
#define CFG_SYS_CCSRBAR 0xffe00000