The 834x rev1.x silicon has one CPU5 errata.
The issue is when the data cache locked with
HID0[DLOCK], the dcbz instruction looks like no-op inst.
The right behavior of the data cache is when the data cache
Locked with HID0[DLOCK], the dcbz instruction allocates
new tags in cache.
The 834x rev3.0 and later and 8360 have not this bug inside.
So, when 834x rev3.0/8360 are working with ECC, the dcbz
instruction will corrupt the stack in cache, the processor will
checkstop reset.
However, the 834x rev1.x can work with ECC with these code,
because the sillicon has this cache bug. The dcbz will not
corrupt the stack in cache.
Really, it is the fault code running on fault sillicon.
This patch fix the incorrect dcbz operation. Instead of
CPU FP writing to initialise the ECC.
CHANGELOG:
* Fix the incorrect dcbz operation instead of CPU FP
writing to initialise the ECC memory. Otherwise, it
will corrupt the stack in cache, The processor will checkstop
reset.
Signed-off-by: Dave Liu <daveliu@freescale.com>
add ft_pci_setup, OF_CPU, OF_SOC, OF_TBCLK, and
STDOUT_PATH configuration bits to mpc8349emds,
mpc8349itx, and mpc8360emds board code.
redo environment to use bootm with the fdtaddr
for booting ARCH=powerpc kernels by default,
and provide default fdtaddr values.
PREREQUISITE PATCHES:
* This patch can only be applied after the following patches have been applied:
1) DNX#2006092142000015 "Add support for the MPC8349E-mITX 1/2"
2) DNX#2006092142000024 "Add support for the MPC8349E-mITX 2/2"
CHANGELOG:
* For the 8349E-mITX, fix some size values in pci_init_board(), enable
the clock for the 2nd USB board (Linux kernel will hang otherwise),
and fix the CONFIG_BOOTARGS macro.
Signed-off-by: Timur Tabi <timur@freescale.com>
PREREQUISITE PATCHES:
* This patch can only be applied after the following patches have been applied:
1) DNX#2006090742000024 "Add support for multiple I2C buses"
2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x"
3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c"
4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems"
5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems"
CHANGELOG:
* Add support for the Freescale MPC8349E-mITX reference design platform.
The second TSEC (Vitesse 7385 switch) is not supported at this time.
Signed-off-by: Timur Tabi <timur@freescale.com>
Hello,
Attached is a patch implementing multiple I2C buses on the MPC834x CPU
family and the MPC8349EMDS board in particular.
This patch requires Patch 1 (Add support for multiple I2C buses).
Testing was performed on a 533MHz board.
/*** Note: This patch replaces ticket DNX#2006083042000027 ***/
Signed-off-by: Ben Warren <bwarren@qstreams.com>
CHANGELOG:
Implemented driver-level code to support two I2C buses on the
MPC834x CPU family and the MPC8349EMDS board. Available I2C bus speeds
are 50kHz, 100kHz and 400kHz on each bus.
regards,
Ben
Hello,
Attached is a patch providing support for multiple I2C buses at the
command level. The second part of the patch includes an implementation
for the MPC834x CPU and MPC8349EMDS board.
/*** Note: This patch replaces ticket DNX#2006083042000018 ***/
Signed-off-by: Ben Warren <bwarren@qstreams.com>
Overview:
1. Include new 'i2c' command (based on USB implementation) using
CONFIG_I2C_CMD_TREE.
2. Allow multiple buses by defining CONFIG_I2C_MULTI_BUS. Note that
the commands to change bus number and speed are only available under the
new 'i2c' command mentioned in the first bullet.
3. The option CFG_I2C_NOPROBES has been expanded to work in multi-bus
systems. When CONFIG_I2C_MULTI_BUS is used, this option takes the form
of an array of bus-device pairs. Otherwise, it is an array of uchar.
CHANGELOG:
Added new 'i2c' master command for all I2C interaction. This is
conditionally compiled with CONFIG_I2C_CMD_TREE. New commands added for
setting I2C bus speed as well as changing the active bus if the board
has more than one (conditionally compiled with
CONFIG_I2C_MULTI_BUS). Updated NOPROBE logic to handle multiple buses.
Updated README.
regards,
Ben
Unified TQM834x variable names with 83xx and consolidated macro
in preparation for the 8360 and other upcoming 83xx devices.
Signed-off-by: Tanya Jiang <tanya.jiang@freescale.com>
Incorporated the common unified variable names and the changes in preparation
for releasing mpc8360 patches.
Signed-off-by: Dave Liu <daveliu@freescale.com>
The Tundra Semiconductor Corporation (Tundra) Tsi108 is a host bridge for
PowerPC processors that offers numerous system interconnect options for
embedded application designers. The Tsi108 can interconnect 60x or
MPX processors to PCI/X peripherals, DDR2-400 memory, Gigabit Ethernet,
and Flash. Provided the macro define for tsi108 chip.
Signed-off-by: Alexandre Bounine <alexandreb@tundra.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
The mpc7448hpc2 board support header file.
Signed-off-by: Alexandre Bounine <alexandreb@tundra.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
1. Add 7447A and 7448 processor support.
2. Add the following flags.
CFG_CONFIG_BUS_CLK : If the 74xx bus frequency can be configured dynamically
(such as by switch on board), this flag should be set.
CFG_EXCEPTION_AFTER_RELOCATE: If an exception occurs after the u-boot
relocates to RAM, this flag should be set.
CFG_SERIAL_HANG_IN_EXCEPTION: If the print out function will cause the
system hang in exception, this flag should be set.
There is a design issue for tsi108/109 pci configure read. When pci scan
the slots, if there is no pci card, the tsi108/9 will cause a machine
check exception for mpc7448 processor.
Signed-off-by: Alexandre Bounine <alexandreb@tundra.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
MPC5XXX_WU_GPIO_DATA macro to MPC5XXX_WU_GPIO_DATA_O (per MPC5200 User's
Manual). Replace the uses of MPC5XXX_WU_GPIO_DATA with
MPC5XXX_WU_GPIO_DATA_O for affected boards.
- Add defintions for some MPC5XXX GPIO pins.
Patch by Haavard Skinnemoen, 06 Sep 2006
This patch adds support for the ATSTK1000 with the ATSTK1002 CPU
daughterboard.
ATSTK1000 is a full-featured development board for AT32AP CPUs. It
has two ethernet ports, a high quality QVGA LCD panel, a loudspeaker,
and connectors for USART, PS/2, VGA, USB, MMC/SD cards and
CompactFlash cards. For more information, please see this page:
http://www.atmel.com/dyn/products/tools.asp?family_id=682
The ATSTK1002 is a daughterboard for the ATSTK1000 supporting the
AT32AP7000 chip.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Patch by Haavard Skinnemoen, 06 Sep 2006
This patch adds support for the AT32AP CPU family and the AT32AP7000
chip, which is the first chip implementing the AVR32 architecture.
The AT32AP CPU core is a high-performance implementation featuring a
7-stage pipeline, separate instruction- and data caches, and a MMU.
For more information, please see the "AVR32 AP Technical Reference":
http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf
In addition to this, the AT32AP7000 chip comes with a large set of
integrated peripherals, many of which are shared with the AT91 series
of ARM-based microcontrollers from Atmel. Full data sheet is
available here:
http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Patch by Haavard Skinnemoen, 6 Sep 2006 16:23:02 +0200
This patch adds common infrastructure code for the Atmel AVR32
architecture. See doc/README.AVR32 for details.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Replace private IMMAP I2C structures with generic reg block
and allow 86xx to have multiple I2C device busses.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Introduced COFIG_FSL_I2C to select the common FSL I2C driver.
And removed hard i2c path from a few u-boot.lds scipts too.
Minor whitespace cleanups along the way.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
- JFFS2 related commands implemented in mtd-utils style
- Support for bad blocks
- Bad block testing commands
- NAND lock commands
Please take a look at doc/README.nand for more details
Patch by Guido Classen, 10 Oct 2006
- Map in a additional chip selects CS4 and CS5.
- Modify the port configration, configure six UARTs and no PCI,
ATA and USB.
- Add custom flash driver to handle specific byte swapping
* Added support for using eTSEC 3 and eTSEC 4 on the 8548 CDS.
This will only work on rev 1.3 boards (but doesn't break older boards)
* Cleaned up some comments to reflect the expanded role of tsec
in other systems
Both 8641 and 8641D have SVR == 0x8090, and are distinguished
by the byte in bits 16-23 instead.
Thanks to Jason Jin for noticing.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
- Add support for PPC440EPx & PPC440GRx
- Add support for PPC440EP(x)/GR(x) NAND controller
in cpu/ppc4xx directory
- Add NAND boot functionality for Sequoia board,
please see doc/README.nand-boot-ppc440 for details
- This Sequoia NAND image doesn't support environment
in NAND for now. This will be added in a short while.
Patch by Stefan Roese, 07 Sep 2006
* Added comments and a printf to warn that PCI-X won't
work at 33MHz
Patch by Andy Fleming 17-Mar-2006
Signed-off-by: Andy Fleming <afleming@freescale.com>
- make highboot configurations use environment at high end, too,
to avoid flash fragmentation
- always use redundand environment
- don't enable video code for modules without graphics controller
- provide useful (though different) mtdparts settings
- get rid of CONFIG_CS_AUTOCONF which was always set anyway
* Extend mkconfig tool to print more useful target name
Hint: the CPLD on the TQM5200 must be programmed with a software
version supporting the high boot option! The new TQM5200S is
already supporting this option. On the TQM5200 this option will be
supported in configurations with MPC5200 rev B processors.
To actually "high boot", set jumper X30 on the STK52xx.
Patch by Martin Krause, 12 Jul 2006
- Support for TQM5200S (short version without graphic controller)
- Support for modules with 'N' type S29GL128N Spansion flashes
(requires changes to flash layout)
- Support for MPC5200B cpu (mostly support for second SDRAM bank)
The PS/2 keyobard driver for the TQM85xx modules only supports the
internal DUART of the MPC85xx CPU. Since the MPC8560 doesn't
include a DUART, the TQM8560 modules can't be used with the PS/2
keyboard controller on the STK85xx board.
The PS/2 keyboard driver should work with the modules TQM8540,
TQM8541 and TQM8555, but it only has been tested on a TQM8540, yet.
Make sure the PS/2 controller on the STK85xx is programmed. Jumper
settings: X66 1-2, 9-10; X61 2-3
Patch by Martin Krause, 21 Jun 2006
- increase CFG_FLASH_ERASE_TOUT from 2 to 15 seconds
- use CFG_FLASH_WRITE_TOUT for programming instead of CFG_FLASH_ERASE_TOUT
- remove "Unlock Bypass" mode, because macronix flashes do not support
this mode officially
- fix flash reset command from 0x00FF to 0x00F0. 0x00FF is only specified
for Intel compatible flashes, not for AMD compatible.
Patch by Martin Krause, 15 Feb 2006
The TB5200 ("Tinybox") is a small baseboard for the TQM5200 module
integrated in a little aluminium case.
Patch by Martin Krause, 8 Jun 2006
Some code cleanup
Added code for reading and writing Mac addresses to/from ID EEPROM(0x57).
With attached patch, we can use command "mac/mac read/mac save/"
to read and write EEPROM under u-boot prompt.
U-boot will calculate the checksum of EEPROM while bootup,
if it is right, then u-boot will check whether the mac address
of eTSEC0/1/2/3 is availalbe (non-zero).
If there is mac address availabe in EEPROM, u-boot will use it,
otherewise, u-boot will use the mac address defined in
MPC8641HPCN.h. This matches the requirement to set unique mac address
for each TSEC port.
Signed-off-by: Haiying Wang <haiying.wang@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Notes:
- Board-dependend code for RPXLITE and RPXCLASSIC-based boards
placed to the drivers/rpx_pmcia.c file to avoid duplication.
Same for TQM8xx-based boards (drivers/tqm8xx_pmcia.c).
- drivers/i82365.c has been split into two parts located at
board/atc/ti113x.c and board/cpc45/pd67290.c (ATC and CPC45 are
the only boards using CONFIG_82365).
- Changes were tested for clean build and *very* *few* boards.
* Added comments and a printf to warn that PCI-X won't
work at 33MHz
Patch by Andy Fleming 17-Mar-2006
Signed-off-by: Andy Fleming <afleming@freescale.com>
Patch by Martin Krause, 8 Jun 2006
This patch supports two serial consoles on boards with
a MPC5xxx CPU. The console can be switched at runtime
by setting stdin, stdout and stderr to the desired serial
interface (serial0 or serial1). The PSCs to be used as
console port are definded by CONFIG_PSC_CONSOLE
and CONFIG_PSC_CONSOLE2.
See README.serial_multi for details.
Patch by Martin Krause, 07 Nov 2005
Tested on a STK85XX baseboard. Make sure the PS/2 controller
has been programmed. Jumper Settings: X66 1-2, 9-10; X61 2-3
Make the automatic CS configuration the default.
The dedicated configurations CONFIG_TQM5200_AA, CONFIG_TQM5200_AB
and CONFIG_TQM5200_AC are removed.
"TQM5200_config" is now the default for STK52XX.200 base boards.
On a STK52XX.100 base board "TQM5200_STK100_config" must be used.
Patch by Martin Krause, 07 Nov 2005
-When booting from an epcs controller, the epcs bootrom may leave the
slave select in an asserted state causing soft reset hang. This
patch ensures slave select is negated at reset.
Patch by Scott McNutt, 08 Jun 2006
-Fix asm/io.h macros
-Eliminate use of CACHE_BYPASS in cpu code
-Eliminate assembler warnings
-Fix mini-app stubs and force no small data
Patch by Scott McNutt, 08 Jun 2006
- Add IXP4xx NPE ethernet MAC support
- Add support for Intel IXDPG425 board
- Add support for Prodrive PDNB3 board
- Add IRQ support
Patch by Stefan Roese, 23 May 2006
[This patch does not include cpu/ixp/npe/IxNpeMicrocode.c which still
sufferes from licensing issues. Blame Intel.]
- Fix OMAP support that omap5912osk compiles in current source tree
- Update with code from "http://omap.spectrumdigital.com/osk5912"
to fix problems with DDR initialization
- Fix timer setup
- Use CFI flash driver and support complete 32MB of onboard flash
- Add "print_cpuinfo()" and "checkboard()" functions to display
CPU (with frequency) and Board infos
Patch by Stefan Roese, 10 May 2006
Enable the CFI driver.
Remove bogus LAWBAR7 cruft.
Use correct TEXT_BASE, Fixup load script.
Enable SPD EEPROM during DDR setup.
Use generic RFC 1918 IP addresses by default.
- Removed MPC8349ADS port
- Added PCI support to MPC8349ADS
- reworked memory map to allow mapping of all regions with BATs
Patch by Kumar Gala 20 Apr 2006
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Patch from Scott McNutt 11, Aug 2005
-When booting from an epcs controller, the epcs bootrom may leave the
slave select in an asserted state causing soft reset hang. This
patch ensures slave select is negated at reset.
Patch by Scott McNutt 11, Aug 2005
-Fix asm/io.h macros
-Eliminate use of CACHE_BYPASS in cpu code
-Eliminate assembler warnings
-Fix mini-app stubs and force no small data
relocate ichache_State to ram
u-boot can run from internal flash
Add EB+MCF-EV123 board support.
Add m68k Boards to MAKEALL
Patch from Jens Scharsig, 08 Aug 2005
- Fix dbau1x00 boards broken by dbau1550 patch
PLL:s were not set for boards other than 1550.
Flash CFI caused card to hang due to undefined CFG_FLASH_BANKS_LIST.
Default boot is now bootp for cards other than 1550.
Patch by Thomas Lange Aug 10 2005
Necessary defines and data structures were copied to DoC specific files
so that legacy NAND code could be entirely removed from u-boot tree
in the near future.
- Add Intel legacy lock/unlock support to common CFI driver
On some Intel flash's (e.g. Intel J3) legacy unlocking is
supported, meaning that unlocking of one sector will unlock
all sectors of this bank. Using this feature, unlocking
of all sectors upon startup (via env var "unlock=yes") will
get much faster.
- Fixed problem with multiple reads of envronment variable
"unlock" as pointed out by Reinhard Arlt & Anders Larsen.
- Removed unwanted linefeeds from "protect" command when
CFG_FLASH_PROTECTION is enabled.
- Changed p3p400 board to use CFG_FLASH_PROTECTION
Patch by Stefan Roese, 01 Apr 2006
* Changes/fixes for drivers/cfi_flash.c:
- Correctly handle the cases where CFG_HZ != 1000 (several
XScale-based boards)
- Fix the timeout calculation of buffered writes (off by a
factor of 1000)
Patch by Anders Larsen, 31 Mar 2006
405 SDRAM: - The SDRAM parameters can now be defined in the board
config file and the 405 SDRAM controller values will
be calculated upon bootup (see PPChameleonEVB).
When those settings are not defined in the board
config file, the register setup will be as it is now,
so this implementation should not break any current
design using this code.
Thanks to Andrea Marson from DAVE for this patch.
440 DDR: - Added function sdram_tr1_set to auto calculate the
TR1 value for the DDR.
- Added ECC support (see p3p440).
Patch by Stefan Roese, 17 Mar 2006
- add support for Analog Devices Blackfin BF533 CPU
- add support for the ADI BF533 Stamp uClinux board
- add support for the ADI BF533 EZKit board
Patches by Richard Klingler, June 11th 2005:
- Use correct flash sector size
- Use correct memory test end address
- Add support for bzip2 compression
- Various small fixes
Patch by Yuli Barcohen, 05 Jun 2005
- Fix SDRAM timing on both local bus and 60x bus
- Add support for second flash bank (SIMM)
- Change boot flash base
Patch by Yuli Barcohen, 05 Jun 2005
* For READ_STATUS and READID commands always 8 bytes need to be read from
NDDB. Otherwise they stay there and get send to flash as the first data
word when writing.
* In nand_base.c the oob variable is not reset so this->oob_buf is
overwritten what eventually screws up the bad block descriptor table.
code and in SoC code). Boards using the old way have CFG_NAND_LEGACY and
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a added. Build breakage for
NETTA.ERR and NETTA_ISDN - will go away when the new NAND support is
implemented for these boards.
* Debug message can be turned on and off.
* Waiting for events now times out.
* Implemented RESET command.
* Added appropriate nand_bbt_descriptor and nand_oobinfo.
Remaining Problems:
* Read Status still behaves weird an returns invalid stuff sometimes.
* ECC Placement does not respect our scheme in nand_oobinfo.
* Add env-variable "unlock" to handle initial state of sectors
(locked/unlocked).
Only the U-Boot image and it's environment is protected,
all other sectors are unprotected (unlocked) if flash
hardware protection is used (CFG_FLASH_PROTECTION) and
the environment variable "unlock" is set to "yes".
Patch by Stefan Roese, 28 Feb 2006
* Update drivers/cfi_flash.c:
- find_sector() called in both versions of flash_write_cfiword()
Patch by Peter Pearse, 27th Feb 2006
* CFI support for a x8/x16 AMD/Spansion flash configured in x8 mode
Patch by Jose Maria Lopez, 16 Jan 2006
* Add support for AMD/Spansion Flashes in flash_write_cfibuffer
Patch by Alex Bastos and Thomas Schaefer, 2005-08-29
* Changes/fixes for drivers/cfi_flash.c:
We *should* check if there are any error bits if the previous call
returned ERR_OK (Otherwise we will have output an error message in
flash_status_check() already.) The original code would only check for
error bits if flash_status_check() returns ERR_TIMEOUT.
Patch by Marcus Hall, 23 Aug 2005
* Changes/fixes for drivers/cfi_flash.c:
- Add CFG_FLASH_PROTECT_CLEAR on drivers/cfi_flash.c
- Prohibit buffer write when buffer_size is 1 on drivers/cfi_flash.c
Patch by Sangmoon Kim, 19 Aug 2005
* Fixes for drivers/cfi_flash.c:
- Fix wrong timeout value usage in flash_status_check()
- Round write_tout up when converting to msec in flash_get_size()
- Remove clearing flash status at the end of flash_write_cfibuffer()
which sets Intel 28F640J3 flash back to command mode on CSB472
Patch by Tolunay Orkun, 02 July 2005
As done in the linux kernel, the U-Boot version (U_BOOT_VERSION)
of all unreleased (untagged) U-Boot images will be automatically
extended upon compiletime with a part of the GIT commit ID and
possibly with "dirty" if uncommited changes are detected.
Here an example for the resulting version:
"U-Boot 1.1.4-g3457ac18-dirty"
The version is now maintained in the toplevel Makefile and the
version headers are autogenerated.
Patch by Stefan Roese, 9 Feb 2006
* lots of bugfixes in the assembler code
* reverted hardware.h back to original
* enabled hardware DRAM calibration
* GCC-4 fix: modified GLOBAL_DATA_POINTER macro
done so far:
* created zylonite board dir (based on lubbock)
* extended some - but not all pxa sources and headers for Intel
Monahans support (CONFIG_CPU_MONAHANS)
* created Makefile zylonite target + MAKEALL entry
* added some debug nonsense, remove later, grep for mk@tbd
Status: compiles (eldk-4.0), and can be started with BDI, but runs forever
and doesn't halt at breakpoints. Hmmm...
