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https://github.com/AsahiLinux/u-boot
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Add ADI Blackfin support
- add support for Analog Devices Blackfin BF533 CPU - add support for the ADI BF533 Stamp uClinux board - add support for the ADI BF533 EZKit board Patches by Richard Klingler, June 11th 2005:
This commit is contained in:
Wolfgang Denk
parent
dc013d4640
commit
0afe519a43
15 changed files with 88 additions and 7 deletions
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@ -2,6 +2,12 @@
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Changes since U-Boot 1.1.4:
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======================================================================
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* Add ADI Blackfin support
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- add support for Analog Devices Blackfin BF533 CPU
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- add support for the ADI BF533 Stamp uClinux board
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- add support for the ADI BF533 EZKit board
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Patches by Richard Klingler, 11 Jun 2005
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* Add loads of ntohl() in image header handling
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Patch by Steven Scholz, 10 Jun 2005
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21
Makefile
21
Makefile
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@ -85,6 +85,9 @@ endif
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ifeq ($(ARCH),microblaze)
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CROSS_COMPILE = mb-
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endif
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ifeq ($(ARCH),blackfin)
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CROSS_COMPILE = bfin-elf-
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endif
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endif
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endif
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@ -111,6 +114,10 @@ endif
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ifeq ($(CPU),mpc85xx)
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OBJS += cpu/$(CPU)/resetvec.o
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endif
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ifeq ($(CPU),bf533)
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OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o
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OBJS += cpu/$(CPU)/cplbhdlr.o cpu/$(CPU)/cplbmgr.o cpu/$(CPU)/flush.o
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endif
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LIBS = lib_generic/libgeneric.a
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LIBS += board/$(BOARDDIR)/lib$(BOARD).a
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@ -1859,6 +1866,19 @@ suzaku_config: unconfig
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@echo "#define CONFIG_SUZAKU 1" >> include/config.h
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@./mkconfig -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno
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#########################################################################
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## Blackfin
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#########################################################################
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ezkit533_config : unconfig
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@./mkconfig $(@:_config=) blackfin bf533 ezkit533
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stamp_config : unconfig
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@./mkconfig $(@:_config=) blackfin bf533 stamp
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dspstamp_config : unconfig
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@./mkconfig $(@:_config=) blackfin bf533 dsp_stamp
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#########################################################################
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#########################################################################
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#########################################################################
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@ -1870,6 +1890,7 @@ clean:
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rm -f examples/hello_world examples/timer \
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examples/eepro100_eeprom examples/sched \
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examples/mem_to_mem_idma2intr examples/82559_eeprom \
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examples/smc91111_eeprom \
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examples/test_burst
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rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr
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rm -f tools/mpc86x_clk tools/ncb
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@ -252,6 +252,8 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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if (hdr->ih_arch != IH_CPU_MICROBLAZE)
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#elif defined(__nios2__)
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if (hdr->ih_arch != IH_CPU_NIOS2)
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#elif defined(__blackfin__)
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if (hdr->ih_arch != IH_CPU_BLACKFIN)
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#else
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# error Unknown CPU type
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#endif
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@ -53,6 +53,10 @@ PLATFORM_CPPFLAGS+= -D__ARM__
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endif
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endif
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ifeq ($(ARCH),blackfin)
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PLATFORM_CPPFLAGS+= -D__BLACKFIN__ -mno-underscore
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endif
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ifdef ARCH
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sinclude $(TOPDIR)/$(ARCH)_config.mk # include architecture dependend rules
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endif
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@ -878,18 +878,27 @@ static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset
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debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd,
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cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
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*addr.cp = cword.c;
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#ifdef CONFIG_BLACKFIN
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asm("ssync;");
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#endif
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break;
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case FLASH_CFI_16BIT:
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debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp,
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cmd, cword.w,
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info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
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*addr.wp = cword.w;
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#ifdef CONFIG_BLACKFIN
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asm("ssync;");
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#endif
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break;
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case FLASH_CFI_32BIT:
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debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp,
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cmd, cword.l,
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info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
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*addr.lp = cword.l;
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#ifdef CONFIG_BLACKFIN
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asm("ssync;");
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#endif
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break;
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case FLASH_CFI_64BIT:
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#ifdef DEBUG
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@ -904,6 +913,9 @@ static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset
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}
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#endif
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*addr.llp = cword.ll;
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#ifdef CONFIG_BLACKFIN
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asm("ssync;");
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#endif
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break;
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}
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}
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@ -160,6 +160,9 @@ extern void eth_halt(void);
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extern int eth_rx(void);
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extern int eth_send(volatile void *packet, int length);
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#ifdef SHARED_RESOURCES
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extern void swap_to(int device_id);
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#endif
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/*
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. This is called by register_netdev(). It is responsible for
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@ -533,6 +536,9 @@ static void smc_shutdown()
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SMC_SELECT_BANK( 0 );
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SMC_outb( RCR_CLEAR, RCR_REG );
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SMC_outb( TCR_CLEAR, TCR_REG );
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#ifdef SHARED_RESOURCES
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swap_to(FLASH);
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#endif
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}
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@ -1511,6 +1517,9 @@ static void print_packet( byte * buf, int length )
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#endif
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int eth_init(bd_t *bd) {
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#ifdef SHARED_RESOURCES
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swap_to(ETHERNET);
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#endif
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return (smc_open(bd));
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}
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@ -185,6 +185,8 @@ typedef unsigned long int dword;
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#ifdef CONFIG_ADNPESC1
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#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))))
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#elif CONFIG_BLACKFIN
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#define SMC_inw(r) ({ word __v = (*((volatile word *)(SMC_BASE_ADDRESS+(r)))); asm("ssync;"); __v;})
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#else
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#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))))
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#endif
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@ -192,6 +194,8 @@ typedef unsigned long int dword;
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#ifdef CONFIG_ADNPESC1
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#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))) = d)
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#elif CONFIG_BLACKFIN
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#define SMC_outw(d,r) {(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d);asm("ssync;");}
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#else
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#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
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#endif
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@ -53,6 +53,10 @@ ifeq ($(ARCH),microblaze)
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LOAD_ADDR = 0x80F00000
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endif
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ifeq ($(ARCH),blackfin)
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LOAD_ADDR = 0x1000
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endif
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include $(TOPDIR)/config.mk
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SREC = hello_world.srec
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@ -73,6 +77,11 @@ SREC += sched.srec
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BIN += sched.bin sched
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endif
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ifeq ($(ARCH),blackfin)
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SREC += smc91111_eeprom.srec
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BIN += smc91111_eeprom.bin smc91111_eeprom
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endif
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# The following example is pretty 8xx specific...
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ifeq ($(CPU),mpc8xx)
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SREC += timer.srec
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@ -214,13 +214,11 @@ int smc91111_eeprom (int argc, char *argv[])
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switch (what) {
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case 1:
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printf ("Writing EEPROM register %02x with %04x\n",
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reg, value);
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printf ("Writing EEPROM register %02x with %04x\n", reg, value);
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write_eeprom_reg (value, reg);
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break;
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case 2:
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printf ("Writing MAC register bank %i,
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reg %02x with %04x\n", reg >> 4, reg & 0xE, value);
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printf ("Writing MAC register bank %i, reg %02x with %04x\n", reg >> 4, reg & 0xE, value);
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SMC_SELECT_BANK (reg >> 4);
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SMC_outw (value, reg & 0xE);
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break;
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@ -125,6 +125,19 @@ gd_t *global_data;
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" lwi r5, r5, %1\n" \
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" bra r5\n" \
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: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r5");
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#elif defined(CONFIG_BLACKFIN)
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/*
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* P5 holds the pointer to the global_data, P0 is a call-clobbered
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* register
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*/
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#define EXPORT_FUNC(x) \
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asm volatile ( \
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" .globl " #x "\n" \
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#x ":\n" \
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" P0 = [P5 + %0]\n" \
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" P0 = [P0 + %1]\n" \
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" JUMP (P0)\n" \
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: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "P0");
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#else
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#error stubs definition missing for this architecture
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#endif
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@ -242,6 +242,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
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#define STM_ID_29W320DT 0x22CA22CA /* M29W320DT ID (32 M, top boot sector) */
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#define STM_ID_29W320DB 0x22CB22CB /* M29W320DB ID (32 M, bottom boot sect) */
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#define STM_ID_29W040B 0x00E300E3 /* M29W040B ID (4M = 512K x 8) */
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#define FLASH_PSD4256GV 0x00E9 /* PSD4256 Flash and CPLD combination */
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#define INTEL_ID_28F016S 0x66a066a0 /* 28F016S[VS] ID (16M = 512k x 16) */
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#define INTEL_ID_28F800B3T 0x88928892 /* 8M = 512K x 16 top boot sector */
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@ -75,6 +75,7 @@
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#define IH_CPU_NIOS 13 /* Nios-32 */
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#define IH_CPU_MICROBLAZE 14 /* MicroBlaze */
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#define IH_CPU_NIOS2 15 /* Nios-II */
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#define IH_CPU_BLACKFIN 16 /* Blackfin */
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/*
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* Image Types
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@ -67,7 +67,7 @@ struct stat {
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#endif /* __PPC__ */
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#if defined (__ARM__) || defined (__I386__) || defined (__M68K__)
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#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__blackfin__)
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struct stat {
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unsigned short st_dev;
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@ -28,8 +28,8 @@ include $(TOPDIR)/config.mk
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LIB = librtc.a
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OBJS = date.o \
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ds12887.o ds1302.o ds1306.o ds1307.o ds1337.o \
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ds1556.o ds164x.o ds174x.o \
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bf533_rtc.o ds12887.o ds1302.o ds1306.o ds1307.o \
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ds1337.o ds1556.o ds164x.o ds174x.o \
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m41t11.o max6900.o m48t35ax.o mc146818.o mk48t59.o \
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mpc5xxx.o mpc8xx.o pcf8563.o s3c24x0_rtc.o rs5c372.o
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@ -93,6 +93,7 @@ table_entry_t arch_name[] = {
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{ IH_CPU_SH, "sh", "SuperH", },
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{ IH_CPU_SPARC, "sparc", "SPARC", },
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{ IH_CPU_SPARC64, "sparc64", "SPARC 64 Bit", },
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{ IH_CPU_BLACKFIN, "blackfin", "Blackfin", },
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{ -1, "", "", },
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};
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