mirror of
https://github.com/AsahiLinux/u-boot
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* Added VIA configuration table
* Added support for PCI2 on CDS Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
Matthew McClintock
parent
52c7a68b8d
commit
cbfc7ce756
15 changed files with 223 additions and 112 deletions
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@ -35,6 +35,9 @@ ft_board_setup(void *blob, bd_t *bd)
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u32 *p;
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int len;
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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ft_cpu_setup(blob, bd);
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p = ft_get_prop(blob, "/memory/reg", &len);
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99
board/cds/common/via.c
Normal file
99
board/cds/common/via.c
Normal file
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@ -0,0 +1,99 @@
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/*
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* Copyright 2006 Freescale Semiconductor.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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/* Config the VIA chip */
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void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab)
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{
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pci_dev_t bridge;
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/* Enable USB and IDE functions */
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pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
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pciauto_config_device(hose, dev);
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/*
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* Force the backplane P2P bridge to have a window
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* open from 0x00000000-0x00001fff in PCI I/O space.
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* This allows legacy I/O (i8259, etc) on the VIA
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* southbridge to be accessed.
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*/
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bridge = PCI_BDF(0,17,0);
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pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
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pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
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pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
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pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0);
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}
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/* Function 1, IDE */
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void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab)
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{
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pciauto_config_device(hose, dev);
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/*
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* Since the P2P window was forced to cover the fixed
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* legacy I/O addresses, it is necessary to manually
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* place the base addresses for the IDE and USB functions
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* within this window.
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*/
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0);
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}
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/* Function 2, USB ports 0-1 */
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void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab)
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{
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pciauto_config_device(hose, dev);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0);
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}
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/* Function 3, USB ports 2-3 */
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void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab)
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{
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pciauto_config_device(hose, dev);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80);
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}
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/* Function 5, Power Management */
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void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab)
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{
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pciauto_config_device(hose, dev);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8);
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}
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/* Function 6, AC97 Interface */
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void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab)
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{
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pciauto_config_device(hose, dev);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00);
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}
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18
board/cds/common/via.h
Normal file
18
board/cds/common/via.h
Normal file
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@ -0,0 +1,18 @@
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#ifndef _MPC85xx_VIA_H
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void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
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/* Function 1, IDE */
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void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
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/* Function 2, USB ports 0-1 */
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void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
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/* Function 3, USB ports 2-3 */
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void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
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/* Function 5, Power Management */
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void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
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/* Function 6, AC97 Interface */
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void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
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#endif /* _MPC85xx_VIA_H */
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@ -29,7 +29,8 @@ LIB = lib$(BOARD).a
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OBJS := $(BOARD).o \
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../common/cadmus.o \
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../common/eeprom.o \
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../common/ft_board.o
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../common/ft_board.o \
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../common/via.o
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SOBJS := init.o
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@ -210,8 +210,8 @@ tlb1_entry:
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
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* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
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* 0xe000_0000 0xe000_ffff CCSR 1M
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* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
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* 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
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* 0xe200_0000 0xe20f_ffff PCI1 IO 1M
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* 0xe210_0000 0xe21f_ffff PCI2 IO 1M
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* 0xf000_0000 0xf7ff_ffff SDRAM 128M
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* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
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* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
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@ -234,11 +234,11 @@ tlb1_entry:
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#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
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#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
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#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
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#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
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#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
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#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
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#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
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#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
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#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
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#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
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/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
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#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
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@ -31,6 +31,7 @@
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#include "../common/cadmus.h"
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#include "../common/eeprom.h"
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#include "../common/via.h"
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void ddr_enable_ecc(unsigned int dram_size);
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@ -468,26 +469,25 @@ testdram(void)
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#endif
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#if defined(CONFIG_PCI)
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/*
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* Initialize PCI Devices, report devices found.
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/* For some reason the Tundra PCI bridge shows up on itself as a
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* different device. Work around that by refusing to configure it.
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*/
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void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
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#ifndef CONFIG_PCI_PNP
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static struct pci_config_table pci_mpc85xxcds_config_table[] = {
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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PCI_IDSEL_NUMBER, PCI_ANY_ID,
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pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
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} },
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{ }
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{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
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{0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
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{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
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{0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
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{0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
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{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
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{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
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};
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#endif
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static struct pci_controller hose = {
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#ifndef CONFIG_PCI_PNP
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config_table: pci_mpc85xxcds_config_table,
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static struct pci_controller hose[] = {
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{ config_table: pci_mpc85xxcds_config_table,},
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#ifdef CONFIG_MPC85XX_PCI2
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{},
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#endif
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};
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@ -497,7 +497,7 @@ void
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pci_init_board(void)
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{
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#ifdef CONFIG_PCI
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extern void pci_mpc85xx_init(struct pci_controller *hose);
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extern void pci_mpc85xx_init(struct pci_controller **hose);
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pci_mpc85xx_init(&hose);
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#endif
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@ -29,7 +29,8 @@ LIB = lib$(BOARD).a
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OBJS := $(BOARD).o \
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../common/cadmus.o \
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../common/eeprom.o \
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../common/ft_board.o
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../common/ft_board.o \
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../common/via.o
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SOBJS := init.o
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@ -210,8 +210,8 @@ tlb1_entry:
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
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* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
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* 0xe000_0000 0xe000_ffff CCSR 1M
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* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
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* 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
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* 0xe200_0000 0xe20f_ffff PCI1 IO 1M
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* 0xe210_0000 0xe21f_ffff PCI2 IO 1M
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* 0xf000_0000 0xf7ff_ffff SDRAM 128M
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* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
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* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
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@ -234,11 +234,11 @@ tlb1_entry:
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#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
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#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
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#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
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#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
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#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
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#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
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#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
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#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
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#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
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#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
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/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
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#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
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@ -30,6 +30,7 @@
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#include "../common/cadmus.h"
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#include "../common/eeprom.h"
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#include "../common/via.h"
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void ddr_enable_ecc(unsigned int dram_size);
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@ -293,26 +294,25 @@ testdram(void)
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#endif
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#if defined(CONFIG_PCI)
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/*
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* Initialize PCI Devices, report devices found.
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/* For some reason the Tundra PCI bridge shows up on itself as a
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* different device. Work around that by refusing to configure it.
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*/
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void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
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#ifndef CONFIG_PCI_PNP
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static struct pci_config_table pci_mpc85xxcds_config_table[] = {
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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PCI_IDSEL_NUMBER, PCI_ANY_ID,
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pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
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} },
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{ }
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{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
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{0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
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{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
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{0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
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{0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
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{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
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{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
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};
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#endif
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static struct pci_controller hose = {
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#ifndef CONFIG_PCI_PNP
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config_table: pci_mpc85xxcds_config_table,
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static struct pci_controller hose[] = {
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{ config_table: pci_mpc85xxcds_config_table,},
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#ifdef CONFIG_MPC85XX_PCI2
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{},
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#endif
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};
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@ -322,7 +322,7 @@ void
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pci_init_board(void)
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{
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#ifdef CONFIG_PCI
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extern void pci_mpc85xx_init(struct pci_controller *hose);
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extern void pci_mpc85xx_init(struct pci_controller **hose);
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pci_mpc85xx_init(&hose);
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#endif
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@ -29,7 +29,8 @@ LIB = lib$(BOARD).a
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OBJS := $(BOARD).o \
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../common/cadmus.o \
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../common/eeprom.o \
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../common/ft_board.o
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../common/ft_board.o \
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../common/via.o
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SOBJS := init.o
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@ -210,8 +210,8 @@ tlb1_entry:
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
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* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
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* 0xe000_0000 0xe000_ffff CCSR 1M
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* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
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* 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
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* 0xe200_0000 0xe20f_ffff PCI1 IO 1M
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* 0xe210_0000 0xe21f_ffff PCI2 IO 1M
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* 0xf000_0000 0xf7ff_ffff SDRAM 128M
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* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
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* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
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@ -234,11 +234,11 @@ tlb1_entry:
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#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
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#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
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#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
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#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
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#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
|
||||
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
|
||||
|
||||
#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
|
||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
|
||||
#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
|
||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
|
||||
|
||||
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
|
||||
#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
|
||||
#include "../common/cadmus.h"
|
||||
#include "../common/eeprom.h"
|
||||
#include "../common/via.h"
|
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
||||
extern void ddr_enable_ecc(unsigned int dram_size);
|
||||
|
|
@ -464,38 +465,40 @@ testdram(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
|
||||
/*
|
||||
* Initialize PCI Devices, report devices found.
|
||||
#ifdef CONFIG_PCI
|
||||
/* For some reason the Tundra PCI bridge shows up on itself as a
|
||||
* different device. Work around that by refusing to configure it
|
||||
*/
|
||||
void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
|
||||
|
||||
#ifndef CONFIG_PCI_PNP
|
||||
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
|
||||
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
||||
PCI_IDSEL_NUMBER, PCI_ANY_ID,
|
||||
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
|
||||
PCI_ENET0_MEMADDR,
|
||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
|
||||
} },
|
||||
{ }
|
||||
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
|
||||
{0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
|
||||
{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
|
||||
{0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
|
||||
{0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
|
||||
{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
|
||||
{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct pci_controller hose = {
|
||||
#ifndef CONFIG_PCI_PNP
|
||||
|
||||
static struct pci_controller hose[] = {
|
||||
{
|
||||
config_table: pci_mpc85xxcds_config_table,
|
||||
},
|
||||
#ifdef CONFIG_MPC85XX_PCI2
|
||||
{ }
|
||||
#endif
|
||||
};
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
#endif
|
||||
|
||||
void
|
||||
pci_init_board(void)
|
||||
{
|
||||
#ifdef CONFIG_PCI
|
||||
extern void pci_mpc85xx_init(struct pci_controller *hose);
|
||||
extern void pci_mpc85xx_init(struct pci_controller **hose);
|
||||
|
||||
pci_mpc85xx_init(&hose);
|
||||
pci_mpc85xx_init(*pci_hose);
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -318,7 +318,7 @@ extern unsigned long get_clock_freq(void);
|
|||
#define OF_CPU "PowerPC,8541@0"
|
||||
#define OF_SOC "soc8541@e0000000"
|
||||
#define OF_TBCLK (bd->bi_busfreq / 8)
|
||||
#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4500"
|
||||
#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600"
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
|
|
@ -335,32 +335,27 @@ extern unsigned long get_clock_freq(void);
|
|||
#define CFG_PCI1_MEM_BASE 0x80000000
|
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
|
||||
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CFG_PCI1_IO_BASE 0xe2000000
|
||||
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
|
||||
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
|
||||
#define CFG_PCI1_IO_BASE 0x00000000
|
||||
#define CFG_PCI1_IO_PHYS 0xe2000000
|
||||
#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */
|
||||
|
||||
#define CFG_PCI2_MEM_BASE 0xa0000000
|
||||
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
|
||||
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CFG_PCI2_IO_BASE 0xe3000000
|
||||
#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
|
||||
#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
|
||||
#define CFG_PCI2_IO_BASE 0x00000000
|
||||
#define CFG_PCI2_IO_PHYS 0xe2100000
|
||||
#define CFG_PCI2_IO_SIZE 0x100000 /* 1M */
|
||||
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
|
||||
#define CONFIG_MPC85XX_PCI2
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
|
||||
#undef CONFIG_EEPRO100
|
||||
#undef CONFIG_TULIP
|
||||
|
||||
#if !defined(CONFIG_PCI_PNP)
|
||||
#define PCI_ENET0_IOADDR 0xe0000000
|
||||
#define PCI_ENET0_MEMADDR 0xe0000000
|
||||
#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
|
||||
#endif
|
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
|
||||
|
||||
|
|
|
|||
|
|
@ -324,7 +324,7 @@ extern unsigned long get_clock_freq(void);
|
|||
#define OF_CPU "PowerPC,8548@0"
|
||||
#define OF_SOC "soc8548@e0000000"
|
||||
#define OF_TBCLK (bd->bi_busfreq / 8)
|
||||
#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4500"
|
||||
#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600"
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
|
|
@ -341,32 +341,27 @@ extern unsigned long get_clock_freq(void);
|
|||
#define CFG_PCI1_MEM_BASE 0x80000000
|
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
|
||||
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CFG_PCI1_IO_BASE 0xe2000000
|
||||
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
|
||||
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
|
||||
#define CFG_PCI1_IO_BASE 0x00000000
|
||||
#define CFG_PCI1_IO_PHYS 0xe2000000
|
||||
#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
|
||||
|
||||
#define CFG_PCI2_MEM_BASE 0xa0000000
|
||||
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
|
||||
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CFG_PCI2_IO_BASE 0xe3000000
|
||||
#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
|
||||
#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
|
||||
#define CFG_PCI2_IO_BASE 0x00000000
|
||||
#define CFG_PCI2_IO_PHYS 0xe2100000
|
||||
#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
|
||||
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_85XX_PCI2
|
||||
|
||||
#undef CONFIG_EEPRO100
|
||||
#undef CONFIG_TULIP
|
||||
|
||||
#if !defined(CONFIG_PCI_PNP)
|
||||
#define PCI_ENET0_IOADDR 0xe0000000
|
||||
#define PCI_ENET0_MEMADDR 0xe0000000
|
||||
#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
|
||||
#endif
|
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
|
||||
|
||||
|
|
@ -386,7 +381,7 @@ extern unsigned long get_clock_freq(void);
|
|||
#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1"
|
||||
#define CONFIG_MPC85XX_TSEC3 1
|
||||
#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2"
|
||||
#define CONFIG_MPC85XX_TSEC4 1
|
||||
#undef CONFIG_MPC85XX_TSEC4
|
||||
#define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3"
|
||||
#undef CONFIG_MPC85XX_FEC
|
||||
|
||||
|
|
|
|||
|
|
@ -318,7 +318,7 @@ extern unsigned long get_clock_freq(void);
|
|||
#define OF_CPU "PowerPC,8555@0"
|
||||
#define OF_SOC "soc8555@e0000000"
|
||||
#define OF_TBCLK (bd->bi_busfreq / 8)
|
||||
#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4500"
|
||||
#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600"
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
|
|
@ -335,33 +335,28 @@ extern unsigned long get_clock_freq(void);
|
|||
#define CFG_PCI1_MEM_BASE 0x80000000
|
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
|
||||
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CFG_PCI1_IO_BASE 0xe2000000
|
||||
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
|
||||
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
|
||||
#define CFG_PCI1_IO_BASE 0x00000000
|
||||
#define CFG_PCI1_IO_PHYS 0xe2000000
|
||||
#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
|
||||
|
||||
#define CFG_PCI2_MEM_BASE 0xa0000000
|
||||
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
|
||||
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CFG_PCI2_IO_BASE 0xe3000000
|
||||
#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
|
||||
#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
|
||||
#define CFG_PCI2_IO_BASE 0x00000000
|
||||
#define CFG_PCI2_IO_PHYS 0xe2100000
|
||||
#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
|
||||
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_MPC85XX_PCI2
|
||||
|
||||
#undef CONFIG_EEPRO100
|
||||
#undef CONFIG_TULIP
|
||||
|
||||
#if !defined(CONFIG_PCI_PNP)
|
||||
#define PCI_ENET0_IOADDR 0xe0000000
|
||||
#define PCI_ENET0_MEMADDR 0xe0000000
|
||||
#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
|
||||
#endif
|
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
|
|
|||
Loading…
Reference in a new issue