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https://github.com/AsahiLinux/u-boot
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Support for DDR with 32-data path. Addotional notes on injecting
multiple-bit errors.
This commit is contained in:
Rafal Jaworowski
parent
d326f4a242
commit
dc9e499c62
5 changed files with 126 additions and 53 deletions
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@ -63,11 +63,12 @@ long int initdram (int board_type)
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
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return -1;
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puts("Initializing\n");
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/* DDR SDRAM - Main SODIMM */
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im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
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#if defined(CONFIG_SPD_EEPROM)
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msize = spd_sdram(0);
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msize = spd_sdram();
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#else
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msize = fixed_sdram();
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#endif
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@ -106,45 +107,40 @@ int fixed_sdram(void)
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return -1;
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}
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}
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im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
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im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
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#if (CFG_DDR_SIZE != 256)
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#warning Currenly any ddr size other than 256 is not supported
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#endif
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im->ddr.csbnds[0].csbnds = 0x00100017;
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im->ddr.csbnds[1].csbnds = 0x0018001f;
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im->ddr.csbnds[2].csbnds = 0x00000007;
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im->ddr.csbnds[3].csbnds = 0x0008000f;
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im->ddr.cs_config[0] = CFG_DDR_CONFIG;
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im->ddr.cs_config[1] = CFG_DDR_CONFIG;
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im->ddr.csbnds[2].csbnds = 0x0000000f;
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im->ddr.cs_config[2] = CFG_DDR_CONFIG;
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im->ddr.cs_config[3] = CFG_DDR_CONFIG;
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im->ddr.timing_cfg_1 =
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3 << TIMING_CFG1_PRETOACT_SHIFT |
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7 << TIMING_CFG1_ACTTOPRE_SHIFT |
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3 << TIMING_CFG1_ACTTORW_SHIFT |
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4 << TIMING_CFG1_CASLAT_SHIFT |
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3 << TIMING_CFG1_REFREC_SHIFT |
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3 << TIMING_CFG1_WRREC_SHIFT |
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2 << TIMING_CFG1_ACTTOACT_SHIFT |
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1 << TIMING_CFG1_WRTORD_SHIFT;
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im->ddr.timing_cfg_2 = 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT;
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/* currently we use only one CS, so disable the other banks */
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im->ddr.cs_config[0] = 0;
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im->ddr.cs_config[1] = 0;
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im->ddr.cs_config[3] = 0;
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im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
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im->ddr.sdram_cfg =
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SDRAM_CFG_SREN
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#if defined(CONFIG_DDR_2T_TIMING)
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| SDRAM_CFG_2T_EN
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#endif
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| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
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im->ddr.sdram_mode =
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0x2000 << SDRAM_MODE_ESD_SHIFT |
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0x0162 << SDRAM_MODE_SD_SHIFT;
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#if defined (CONFIG_DDR_32BIT)
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/* for 32-bit mode burst length is 8 */
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im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
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#endif
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im->ddr.sdram_mode = CFG_DDR_MODE;
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im->ddr.sdram_interval = 0x045B << SDRAM_INTERVAL_REFINT_SHIFT |
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0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT;
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im->ddr.sdram_interval = CFG_DDR_INTERVAL;
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udelay(200);
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/* enable DDR controller */
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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return msize;
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}
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#endif/*!CFG_SPD_EEPROM*/
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@ -1,4 +1,7 @@
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/*
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* (C) Copyright 2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright 2004 Freescale Semiconductor.
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* (C) Copyright 2003 Motorola Inc.
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* Xianghua Xiao (X.Xiao@motorola.com)
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@ -73,7 +76,32 @@ int read_spd(uint addr)
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return ((int) addr);
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}
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long int spd_sdram(int(read_spd)(uint addr))
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#undef SPD_DEBUG
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#ifdef SPD_DEBUG
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static void spd_debug(spd_eeprom_t *spd)
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{
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printf ("\nDIMM type: %-18.18s\n", spd->mpart);
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printf ("SPD size: %d\n", spd->info_size);
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printf ("EEPROM size: %d\n", 1 << spd->chip_size);
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printf ("Memory type: %d\n", spd->mem_type);
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printf ("Row addr: %d\n", spd->nrow_addr);
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printf ("Column addr: %d\n", spd->ncol_addr);
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printf ("# of rows: %d\n", spd->nrows);
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printf ("Row density: %d\n", spd->row_dens);
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printf ("# of banks: %d\n", spd->nbanks);
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printf ("Data width: %d\n",
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256 * spd->dataw_msb + spd->dataw_lsb);
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printf ("Chip width: %d\n", spd->primw);
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printf ("Refresh rate: %02X\n", spd->refresh);
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printf ("CAS latencies: %02X\n", spd->cas_lat);
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printf ("Write latencies: %02X\n", spd->write_lat);
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printf ("tRP: %d\n", spd->trp);
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printf ("tRCD: %d\n", spd->trcd);
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printf ("\n");
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}
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#endif /* SPD_DEBUG */
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long int spd_sdram()
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
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volatile ddr8349_t *ddr = &immap->ddr;
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@ -85,10 +113,10 @@ long int spd_sdram(int(read_spd)(uint addr))
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unsigned char caslat;
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unsigned int trfc, trfc_clk, trfc_low;
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#warning Current spd_sdram does not fit its usage... adjust implementation or API...
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CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
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#ifdef SPD_DEBUG
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spd_debug(&spd);
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#endif
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if (spd.nrows > 2) {
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puts("DDR:Only two chip selects are supported on ADS.\n");
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return 0;
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@ -223,25 +251,31 @@ long int spd_sdram(int(read_spd)(uint addr))
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* Only DDR I is supported
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* DDR I and II have different mode-register-set definition
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*/
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/* burst length is always 4 */
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switch(caslat) {
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case 2:
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ddr->sdram_mode = 0x52; /* 1.5 */
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tmp = 0x50; /* 1.5 */
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break;
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case 3:
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ddr->sdram_mode = 0x22; /* 2.0 */
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tmp = 0x20; /* 2.0 */
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break;
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case 4:
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ddr->sdram_mode = 0x62; /* 2.5 */
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tmp = 0x60; /* 2.5 */
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break;
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case 5:
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ddr->sdram_mode = 0x32; /* 3.0 */
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tmp = 0x30; /* 3.0 */
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break;
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default:
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puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n");
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return 0;
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}
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#if defined (CONFIG_DDR_32BIT)
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/* set burst length to 8 for 32-bit data path */
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tmp |= 0x03;
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#else
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/* set burst length to 4 - default for 64-bit data path */
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tmp |= 0x02;
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#endif
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ddr->sdram_mode = tmp;
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debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
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switch(spd.refresh) {
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@ -321,6 +355,10 @@ long int spd_sdram(int(read_spd)(uint addr))
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*/
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tmp = 0xc2000000;
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#if defined (CONFIG_DDR_32BIT)
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/* in 32-Bit mode burst len is 8 beats */
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tmp |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
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#endif
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/*
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* sdram_cfg[3] = RD_EN - registered DIMM enable
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* A value of 0x26 indicates micron registered DIMMS (micron.com)
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@ -350,8 +388,7 @@ long int spd_sdram(int(read_spd)(uint addr))
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udelay(500);
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debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
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return memsize;/*in MBytes*/
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return memsize; /*in MBytes*/
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}
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#endif /* CONFIG_SPD_EEPROM */
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@ -1,3 +1,24 @@
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Overview
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========
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The overall usage pattern for ECC diagnostic commands is the following:
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* (injecting errors is initially disabled)
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* define inject mask (which tells the DDR controller what type of errors
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we'll be injecting: single/multiple bit etc.)
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* enable injecting errors - from now on the controller injects errors as
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indicated in the inject mask
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IMPORTANT NOTICE: enabling injecting multiple-bit errors is potentially
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dangerous as such errors are NOT corrected by the controller. Therefore caution
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should be taken when enabling the injection of multiple-bit errors: it is only
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safe when used on a carefully selected memory area and used under control of
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the 'ecc test' command (see example 'Injecting Multiple-Bit Errors' below). In
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particular, when you simply set the multiple-bit errors in inject mask and
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enable injection, U-Boot is very likely to hang quickly as the errors will be
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injected when it accesses its code, data etc.
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Use cases for DDR 'ecc' command:
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@ -73,27 +73,46 @@
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#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
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#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
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/*
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* 32-bit data path mode.
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*
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* Please note that using this mode for devices with the real density of 64-bit
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* effectively reduces the amount of available memory due to the effect of
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* wrapping around while translating address to row/columns, for example in the
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* 256MB module the upper 128MB get aliased with contents of the lower
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* 128MB); normally this define should be used for devices with real 32-bit
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* data path.
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*/
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#undef CONFIG_DDR_32BIT
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#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
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#define CFG_SDRAM_BASE CFG_DDR_BASE
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#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
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#undef CONFIG_DDR_2T_TIMING
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#if defined(CONFIG_SPD_EEPROM)
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/*
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* Determine DDR configuration from I2C interface.
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*/
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#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
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/*
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* Determine DDR configuration from I2C interface.
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*/
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#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
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#else
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/*
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* Manually set up DDR parameters
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*/
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#define CFG_DDR_SIZE 128 /* Mb */
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#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
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#define CFG_DDR_TIMING_1 0x37344321
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#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
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#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
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#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
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#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
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/*
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* Manually set up DDR parameters
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*/
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#define CFG_DDR_SIZE 256 /* MB */
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#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
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#define CFG_DDR_TIMING_1 0x36332321
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#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
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#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
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#define CFG_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
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#if defined(CONFIG_DDR_32BIT)
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/* set burst length to 8 for 32-bit data path */
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#define CFG_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */
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#else
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/* the default burst length is 4 - for 64-bit data path */
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#define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */
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#endif
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#endif
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/*
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@ -1,6 +1,6 @@
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#ifndef _SPD_SDRAM_H_
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#define _SPD_SDRAM_H_
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long int spd_sdram(int(read_spd)(uint addr));
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long int spd_sdram(void);
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#endif
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