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https://github.com/AsahiLinux/u-boot
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Change delta board memory map to start at 0x80000000.
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2 changed files with 8 additions and 8 deletions
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@ -2,7 +2,7 @@
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#TEXT_BASE = 0xa1700000
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#TEXT_BASE = 0xa3080000
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#TEXT_BASE = 0x9ffe0000
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TEXT_BASE = 0xa3008000
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TEXT_BASE = 0x83008000
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# Compile the new NAND code (needed iff #ifdef CONFIG_NEW_NAND_CODE)
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BOARDLIBS = drivers/nand/libnand.a
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@ -125,8 +125,8 @@
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_DEVICE_NULLDEV 1
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#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
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#define CFG_MEMTEST_START 0x80400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x80800000 /* 4 ... 8 MB in DRAM */
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#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
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@ -159,16 +159,16 @@
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x1000000 /* 64 MB */
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#define PHYS_SDRAM_2 0xa1000000 /* SDRAM Bank #2 */
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#define PHYS_SDRAM_2 0x81000000 /* SDRAM Bank #2 */
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#define PHYS_SDRAM_2_SIZE 0x1000000 /* 64 MB */
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#define PHYS_SDRAM_3 0xa2000000 /* SDRAM Bank #3 */
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#define PHYS_SDRAM_3 0x82000000 /* SDRAM Bank #3 */
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#define PHYS_SDRAM_3_SIZE 0x1000000 /* 64 MB */
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#define PHYS_SDRAM_4 0xa3000000 /* SDRAM Bank #4 */
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#define PHYS_SDRAM_4 0x83000000 /* SDRAM Bank #4 */
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#define PHYS_SDRAM_4_SIZE 0x1000000 /* 64 MB */
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#define CFG_DRAM_BASE 0xa0000000 /* at CS0 */
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#define CFG_DRAM_BASE 0x80000000 /* at CS0 */
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#define CFG_DRAM_SIZE 0x04000000 /* 64 MB Ram */
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#undef CFG_SKIP_DRAM_SCRUB
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