mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-29 16:10:58 +00:00
Merge branch 'master' of http://www.denx.de/git/u-boot
This commit is contained in:
Markus Klotzbcher
commit
7d4d1ce48c
14 changed files with 3129 additions and 3352 deletions
26
CHANGELOG
26
CHANGELOG
|
|
@ -2,6 +2,32 @@
|
|||
Changes since U-Boot 1.1.4:
|
||||
======================================================================
|
||||
|
||||
* Add basic support for the SMMACO4 Board from PanDaCom.
|
||||
Patch by Heiko Schocher, 20 Feb 2006
|
||||
|
||||
* Add GIT version information (commid ID) to untagged U-Boot versions
|
||||
|
||||
As done in the linux kernel, the U-Boot version (U_BOOT_VERSION)
|
||||
of all unreleased (untagged) U-Boot images will be automatically
|
||||
extended upon compiletime with a part of the GIT commit ID and
|
||||
possibly with "dirty" if uncommited changes are detected.
|
||||
|
||||
Here an example for the resulting version:
|
||||
"U-Boot 1.1.4-g3457ac18-dirty"
|
||||
|
||||
The version is now maintained in the toplevel Makefile and the
|
||||
version headers are autogenerated.
|
||||
|
||||
Patch by Stefan Roese, 9 Feb 2006
|
||||
|
||||
* Update default environment for INKA4x00 board.
|
||||
|
||||
* Convert CPCI750 to use common CFI flash driver
|
||||
Patch by Reinhard Arlt, 8 Feb 2006
|
||||
|
||||
* Various changes to esd HH405 board specific files
|
||||
Patch by Matthias Fuchs, 07 Feb 2006
|
||||
|
||||
* Cleanup U-Boot boot messages on ARM.
|
||||
|
||||
To match the U-Boot user interface on ARM platforms to the U-Boot
|
||||
|
|
|
|||
36
Makefile
36
Makefile
|
|
@ -1,5 +1,5 @@
|
|||
#
|
||||
# (C) Copyright 2000-2005
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
|
|
@ -21,6 +21,13 @@
|
|||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
VERSION = 1
|
||||
PATCHLEVEL = 1
|
||||
SUBLEVEL = 4
|
||||
EXTRAVERSION =
|
||||
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
|
||||
VERSION_FILE = include/version_autogenerated.h
|
||||
|
||||
HOSTARCH := $(shell uname -m | \
|
||||
sed -e s/i.86/i386/ \
|
||||
-e s/sun4u/sparc64/ \
|
||||
|
|
@ -154,14 +161,14 @@ u-boot.bin: u-boot
|
|||
u-boot.img: u-boot.bin
|
||||
./tools/mkimage -A $(ARCH) -T firmware -C none \
|
||||
-a $(TEXT_BASE) -e 0 \
|
||||
-n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' include/version.h | \
|
||||
-n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
|
||||
sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
|
||||
-d $< $@
|
||||
|
||||
u-boot.dis: u-boot
|
||||
$(OBJDUMP) -d $< > $@
|
||||
|
||||
u-boot: depend $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
|
||||
u-boot: depend version $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
|
||||
UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
|
||||
$(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \
|
||||
--start-group $(LIBS) --end-group $(PLATFORM_LIBS) \
|
||||
|
|
@ -173,6 +180,13 @@ $(LIBS):
|
|||
$(SUBDIRS):
|
||||
$(MAKE) -C $@ all
|
||||
|
||||
version:
|
||||
@echo -n "#define U_BOOT_VERSION \"U-Boot " > $(VERSION_FILE); \
|
||||
echo -n "$(U_BOOT_VERSION)" >> $(VERSION_FILE); \
|
||||
echo -n $(shell $(CONFIG_SHELL) $(TOPDIR)/tools/setlocalversion \
|
||||
$(TOPDIR)) >> $(VERSION_FILE); \
|
||||
echo "\"" >> $(VERSION_FILE)
|
||||
|
||||
gdbtools:
|
||||
$(MAKE) -C tools/gdb || exit 1
|
||||
|
||||
|
|
@ -301,6 +315,14 @@ PM520_ROMBOOT_DDR_config: unconfig
|
|||
}
|
||||
@./mkconfig -a PM520 ppc mpc5xxx pm520
|
||||
|
||||
smmaco4_config: unconfig
|
||||
@./mkconfig -a smmaco4 ppc mpc5xxx tqm5200
|
||||
|
||||
spieval_config: unconfig
|
||||
echo "#define CONFIG_CS_AUTOCONF">>include/config.h
|
||||
echo "... with automatic CS configuration"
|
||||
@./mkconfig -a spieval ppc mpc5xxx tqm5200
|
||||
|
||||
MINI5200_config \
|
||||
EVAL5200_config \
|
||||
TOP5200_config: unconfig
|
||||
|
|
@ -366,11 +388,6 @@ MiniFAP_config: unconfig
|
|||
}
|
||||
@./mkconfig -a TQM5200 ppc mpc5xxx tqm5200
|
||||
|
||||
spieval_config: unconfig
|
||||
echo "#define CONFIG_CS_AUTOCONF">>include/config.h
|
||||
echo "... with automatic CS configuration"
|
||||
@./mkconfig -a spieval ppc mpc5xxx tqm5200
|
||||
|
||||
#########################################################################
|
||||
## MPC8xx Systems
|
||||
#########################################################################
|
||||
|
|
@ -1845,7 +1862,8 @@ clobber: clean
|
|||
-o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \
|
||||
-print0 \
|
||||
| xargs -0 rm -f
|
||||
rm -f $(OBJS) *.bak tags
|
||||
rm -f $(OBJS) *.bak tags TAGS include/version_autogenerated.h
|
||||
|
||||
rm -fr *.*~
|
||||
rm -f u-boot u-boot.map u-boot.hex $(ALL)
|
||||
rm -f tools/crc32.c tools/environment.c tools/env/crc32.c
|
||||
|
|
|
|||
|
|
@ -229,6 +229,9 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
|
|||
/*
|
||||
* Detect epson
|
||||
*/
|
||||
lcd_reg[0] = 0x00;
|
||||
lcd_reg[1] = 0x00;
|
||||
|
||||
if (lcd_reg[0] == 0x1c) {
|
||||
/*
|
||||
* Big epson detected
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ SOBJS = misc.o
|
|||
|
||||
OBJS = $(BOARD).o serial.o ../../Marvell/common/memory.o pci.o \
|
||||
mv_eth.o mpsc.o i2c.o \
|
||||
sdram_init.o strataflash.o ide.o
|
||||
sdram_init.o ide.o
|
||||
|
||||
$(LIB): .depend $(OBJS) $(SOBJS)
|
||||
$(AR) crv $@ $(OBJS) $(SOBJS)
|
||||
|
|
|
|||
|
|
@ -56,6 +56,7 @@
|
|||
|
||||
extern void flush_data_cache (void);
|
||||
extern void invalidate_l1_instruction_cache (void);
|
||||
extern flash_info_t flash_info[];
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
|
|
@ -363,6 +364,22 @@ int misc_init_r ()
|
|||
/* disable the dcache and MMU */
|
||||
dcache_lock ();
|
||||
#endif
|
||||
if (flash_info[3].size < CFG_FLASH_INCREMENT) {
|
||||
unsigned int flash_offset;
|
||||
unsigned int l;
|
||||
|
||||
flash_offset = CFG_FLASH_INCREMENT - flash_info[3].size;
|
||||
for (l = 0; l < CFG_MAX_FLASH_SECT; l++) {
|
||||
if (flash_info[3].start[l] != 0) {
|
||||
flash_info[3].start[l] += flash_offset;
|
||||
}
|
||||
}
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
CFG_MONITOR_BASE,
|
||||
CFG_MONITOR_BASE + monitor_flash_len - 1,
|
||||
&flash_info[3]);
|
||||
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,763 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/cache.h>
|
||||
|
||||
#undef DEBUG_FLASH
|
||||
/*
|
||||
* This file implements a Common Flash Interface (CFI) driver for U-Boot.
|
||||
* The width of the port and the width of the chips are determined at initialization.
|
||||
* These widths are used to calculate the address for access CFI data structures.
|
||||
* It has been tested on an Intel Strataflash implementation.
|
||||
*
|
||||
* References
|
||||
* JEDEC Standard JESD68 - Common Flash Interface (CFI)
|
||||
* JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
|
||||
* Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
|
||||
* Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
|
||||
*
|
||||
* TODO
|
||||
* Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
|
||||
* Add support for other command sets Use the PRI and ALT to determine command set
|
||||
* Verify erase and program timeouts.
|
||||
*/
|
||||
|
||||
#define FLASH_CMD_CFI 0x98
|
||||
#define FLASH_CMD_READ_ID 0x90
|
||||
#define FLASH_CMD_RESET 0xff
|
||||
#define FLASH_CMD_BLOCK_ERASE 0x20
|
||||
#define FLASH_CMD_ERASE_CONFIRM 0xD0
|
||||
#define FLASH_CMD_WRITE 0x40
|
||||
#define FLASH_CMD_PROTECT 0x60
|
||||
#define FLASH_CMD_PROTECT_SET 0x01
|
||||
#define FLASH_CMD_PROTECT_CLEAR 0xD0
|
||||
#define FLASH_CMD_CLEAR_STATUS 0x50
|
||||
#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
|
||||
#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
|
||||
|
||||
#define FLASH_STATUS_DONE 0x80
|
||||
#define FLASH_STATUS_ESS 0x40
|
||||
#define FLASH_STATUS_ECLBS 0x20
|
||||
#define FLASH_STATUS_PSLBS 0x10
|
||||
#define FLASH_STATUS_VPENS 0x08
|
||||
#define FLASH_STATUS_PSS 0x04
|
||||
#define FLASH_STATUS_DPS 0x02
|
||||
#define FLASH_STATUS_R 0x01
|
||||
#define FLASH_STATUS_PROTECT 0x01
|
||||
|
||||
#define FLASH_OFFSET_CFI 0x55
|
||||
#define FLASH_OFFSET_CFI_RESP 0x10
|
||||
#define FLASH_OFFSET_WTOUT 0x1F
|
||||
#define FLASH_OFFSET_WBTOUT 0x20
|
||||
#define FLASH_OFFSET_ETOUT 0x21
|
||||
#define FLASH_OFFSET_CETOUT 0x22
|
||||
#define FLASH_OFFSET_WMAX_TOUT 0x23
|
||||
#define FLASH_OFFSET_WBMAX_TOUT 0x24
|
||||
#define FLASH_OFFSET_EMAX_TOUT 0x25
|
||||
#define FLASH_OFFSET_CEMAX_TOUT 0x26
|
||||
#define FLASH_OFFSET_SIZE 0x27
|
||||
#define FLASH_OFFSET_INTERFACE 0x28
|
||||
#define FLASH_OFFSET_BUFFER_SIZE 0x2A
|
||||
#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
|
||||
#define FLASH_OFFSET_ERASE_REGIONS 0x2D
|
||||
#define FLASH_OFFSET_PROTECT 0x02
|
||||
#define FLASH_OFFSET_USER_PROTECTION 0x85
|
||||
#define FLASH_OFFSET_INTEL_PROTECTION 0x81
|
||||
|
||||
|
||||
#define FLASH_MAN_CFI 0x01000000
|
||||
|
||||
|
||||
typedef union {
|
||||
unsigned char c;
|
||||
unsigned short w;
|
||||
unsigned long l;
|
||||
} cfiword_t;
|
||||
|
||||
typedef union {
|
||||
unsigned char * cp;
|
||||
unsigned short *wp;
|
||||
unsigned long *lp;
|
||||
} cfiptr_t;
|
||||
|
||||
#define NUM_ERASE_REGIONS 4
|
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
|
||||
|
||||
static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
|
||||
static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
|
||||
static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
|
||||
static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
|
||||
static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
|
||||
static int flash_detect_cfi(flash_info_t * info);
|
||||
static ulong flash_get_size (ulong base, int banknum);
|
||||
static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
|
||||
static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
|
||||
#ifdef CFG_FLASH_USE_BUFFER_WRITE
|
||||
static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
|
||||
#endif
|
||||
/*-----------------------------------------------------------------------
|
||||
* create an address based on the offset and the port width
|
||||
*/
|
||||
inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
|
||||
{
|
||||
return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
|
||||
}
|
||||
/*-----------------------------------------------------------------------
|
||||
* read a character at a port width address
|
||||
*/
|
||||
inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
|
||||
{
|
||||
uchar *cp;
|
||||
cp = flash_make_addr(info, 0, offset);
|
||||
return (cp[info->portwidth - 1]);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* read a short word by swapping for ppc format.
|
||||
*/
|
||||
ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
|
||||
{
|
||||
uchar * addr;
|
||||
|
||||
addr = flash_make_addr(info, sect, offset);
|
||||
return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
|
||||
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* read a long word by picking the least significant byte of each maiximum
|
||||
* port size word. Swap for ppc format.
|
||||
*/
|
||||
ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
|
||||
{
|
||||
uchar * addr;
|
||||
|
||||
addr = flash_make_addr(info, sect, offset);
|
||||
return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
|
||||
(addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
|
||||
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size;
|
||||
int i;
|
||||
unsigned long address;
|
||||
|
||||
|
||||
/* The flash is positioned back to back, with the demultiplexing of the chip
|
||||
* based on the A24 address line.
|
||||
*
|
||||
*/
|
||||
|
||||
address = CFG_FLASH_BASE;
|
||||
size = 0;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
size += flash_info[i].size = flash_get_size(address, i);
|
||||
address += CFG_FLASH_INCREMENT;
|
||||
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
|
||||
printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
|
||||
flash_info[0].size, flash_info[i].size<<20);
|
||||
}
|
||||
}
|
||||
|
||||
#if 0 /* test-only */
|
||||
/* Monitor protection ON by default */
|
||||
#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
|
||||
for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++)
|
||||
(void)flash_real_protect(&flash_info[0], i, 1);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
return (size);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last)
|
||||
{
|
||||
int rcode = 0;
|
||||
int prot;
|
||||
int sect;
|
||||
|
||||
if( info->flash_id != FLASH_MAN_CFI) {
|
||||
printf ("Can't erase unknown flash type - aborted\n");
|
||||
return 1;
|
||||
}
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
printf ("- no sectors to erase\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect=s_first; sect<=s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
|
||||
for (sect = s_first; sect<=s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
|
||||
flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
|
||||
flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
|
||||
|
||||
if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
|
||||
rcode = 1;
|
||||
} else
|
||||
printf(".");
|
||||
}
|
||||
}
|
||||
printf (" done\n");
|
||||
return rcode;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
void flash_print_info (flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (info->flash_id != FLASH_MAN_CFI) {
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
printf("CFI conformant FLASH (%d x %d)",
|
||||
(info->portwidth << 3 ), (info->chipwidth << 3 ));
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
|
||||
info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i=0; i<info->sector_count; ++i) {
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n");
|
||||
printf (" %08lX%5s",
|
||||
info->start[i],
|
||||
info->protect[i] ? " (RO)" : " "
|
||||
);
|
||||
}
|
||||
printf ("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong wp;
|
||||
ulong cp;
|
||||
int aln;
|
||||
cfiword_t cword;
|
||||
int i, rc;
|
||||
|
||||
/* get lower aligned address */
|
||||
wp = (addr & ~(info->portwidth - 1));
|
||||
|
||||
/* handle unaligned start */
|
||||
if((aln = addr - wp) != 0) {
|
||||
cword.l = 0;
|
||||
cp = wp;
|
||||
for(i=0;i<aln; ++i, ++cp)
|
||||
flash_add_byte(info, &cword, (*(uchar *)cp));
|
||||
|
||||
for(; (i< info->portwidth) && (cnt > 0) ; i++) {
|
||||
flash_add_byte(info, &cword, *src++);
|
||||
cnt--;
|
||||
cp++;
|
||||
}
|
||||
for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
|
||||
flash_add_byte(info, &cword, (*(uchar *)cp));
|
||||
if((rc = flash_write_cfiword(info, wp, cword)) != 0)
|
||||
return rc;
|
||||
wp = cp;
|
||||
}
|
||||
|
||||
#ifdef CFG_FLASH_USE_BUFFER_WRITE
|
||||
while(cnt >= info->portwidth) {
|
||||
i = info->buffer_size > cnt? cnt: info->buffer_size;
|
||||
if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
|
||||
return rc;
|
||||
wp += i;
|
||||
src += i;
|
||||
cnt -=i;
|
||||
}
|
||||
#else
|
||||
/* handle the aligned part */
|
||||
while(cnt >= info->portwidth) {
|
||||
cword.l = 0;
|
||||
for(i = 0; i < info->portwidth; i++) {
|
||||
flash_add_byte(info, &cword, *src++);
|
||||
}
|
||||
if((rc = flash_write_cfiword(info, wp, cword)) != 0)
|
||||
return rc;
|
||||
wp += info->portwidth;
|
||||
cnt -= info->portwidth;
|
||||
}
|
||||
#endif /* CFG_FLASH_USE_BUFFER_WRITE */
|
||||
if (cnt == 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
cword.l = 0;
|
||||
for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
|
||||
flash_add_byte(info, &cword, *src++);
|
||||
--cnt;
|
||||
}
|
||||
for (; i<info->portwidth; ++i, ++cp) {
|
||||
flash_add_byte(info, & cword, (*(uchar *)cp));
|
||||
}
|
||||
|
||||
return flash_write_cfiword(info, wp, cword);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
int flash_real_protect(flash_info_t *info, long sector, int prot)
|
||||
{
|
||||
int retcode = 0;
|
||||
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
|
||||
if(prot)
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
|
||||
else
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
|
||||
|
||||
if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
|
||||
prot?"protect":"unprotect")) == 0) {
|
||||
|
||||
info->protect[sector] = prot;
|
||||
/* Intel's unprotect unprotects all locking */
|
||||
if(prot == 0) {
|
||||
int i;
|
||||
for(i = 0 ; i<info->sector_count; i++) {
|
||||
if(info->protect[i])
|
||||
flash_real_protect(info, i, 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return retcode;
|
||||
}
|
||||
/*-----------------------------------------------------------------------
|
||||
* wait for XSR.7 to be set. Time out with an error if it does not.
|
||||
* This routine does not set the flash to read-array mode.
|
||||
*/
|
||||
static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
|
||||
{
|
||||
ulong start;
|
||||
|
||||
/* Wait for command completion */
|
||||
start = get_timer (0);
|
||||
while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
|
||||
if (get_timer(start) > info->erase_blk_tout) {
|
||||
printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
|
||||
return ERR_TIMOUT;
|
||||
}
|
||||
}
|
||||
return ERR_OK;
|
||||
}
|
||||
/*-----------------------------------------------------------------------
|
||||
* Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
|
||||
* This routine sets the flash to read-array mode.
|
||||
*/
|
||||
static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
|
||||
{
|
||||
int retcode;
|
||||
retcode = flash_status_check(info, sector, tout, prompt);
|
||||
if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
|
||||
retcode = ERR_INVAL;
|
||||
printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
|
||||
if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
|
||||
printf("Command Sequence Error.\n");
|
||||
} else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
|
||||
printf("Block Erase Error.\n");
|
||||
retcode = ERR_NOT_ERASED;
|
||||
} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
|
||||
printf("Locking Error\n");
|
||||
}
|
||||
if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
|
||||
printf("Block locked.\n");
|
||||
retcode = ERR_PROTECTED;
|
||||
}
|
||||
if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
|
||||
printf("Vpp Low Error.\n");
|
||||
}
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
|
||||
return retcode;
|
||||
}
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
|
||||
{
|
||||
switch(info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
cword->c = c;
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
cword->w = (cword->w << 8) | c;
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
cword->l = (cword->l << 8) | c;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* make a proper sized command based on the port and chip widths
|
||||
*/
|
||||
static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
|
||||
{
|
||||
int i;
|
||||
uchar *cp = (uchar *)cmdbuf;
|
||||
for(i=0; i< info->portwidth; i++)
|
||||
*cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
|
||||
}
|
||||
|
||||
/*
|
||||
* Write a proper sized command to the correct address
|
||||
*/
|
||||
static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
|
||||
{
|
||||
|
||||
volatile cfiptr_t addr;
|
||||
cfiword_t cword;
|
||||
addr.cp = flash_make_addr(info, sect, offset);
|
||||
flash_make_cmd(info, cmd, &cword);
|
||||
switch(info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
*addr.cp = cword.c;
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
*addr.wp = cword.w;
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
*addr.lp = cword.l;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
|
||||
{
|
||||
cfiptr_t cptr;
|
||||
cfiword_t cword;
|
||||
int retval;
|
||||
cptr.cp = flash_make_addr(info, sect, offset);
|
||||
flash_make_cmd(info, cmd, &cword);
|
||||
switch(info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
retval = (cptr.cp[0] == cword.c);
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
retval = (cptr.wp[0] == cword.w);
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
retval = (cptr.lp[0] == cword.l);
|
||||
break;
|
||||
default:
|
||||
retval = 0;
|
||||
break;
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
|
||||
{
|
||||
cfiptr_t cptr;
|
||||
cfiword_t cword;
|
||||
int retval;
|
||||
cptr.cp = flash_make_addr(info, sect, offset);
|
||||
flash_make_cmd(info, cmd, &cword);
|
||||
switch(info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
retval = ((cptr.cp[0] & cword.c) == cword.c);
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
retval = ((cptr.wp[0] & cword.w) == cword.w);
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
retval = ((cptr.lp[0] & cword.l) == cword.l);
|
||||
break;
|
||||
default:
|
||||
retval = 0;
|
||||
break;
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* detect if flash is compatible with the Common Flash Interface (CFI)
|
||||
* http://www.jedec.org/download/search/jesd68.pdf
|
||||
*
|
||||
*/
|
||||
static int flash_detect_cfi(flash_info_t * info)
|
||||
{
|
||||
|
||||
for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
|
||||
info->portwidth <<= 1) {
|
||||
for(info->chipwidth =FLASH_CFI_BY8;
|
||||
info->chipwidth <= info->portwidth;
|
||||
info->chipwidth <<= 1) {
|
||||
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
|
||||
flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
|
||||
if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
|
||||
flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
|
||||
flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
/*
|
||||
* The following code cannot be run from FLASH!
|
||||
*
|
||||
*/
|
||||
static ulong flash_get_size (ulong base, int banknum)
|
||||
{
|
||||
flash_info_t * info = &flash_info[banknum];
|
||||
int i, j;
|
||||
int sect_cnt;
|
||||
unsigned long sector;
|
||||
unsigned long tmp;
|
||||
int size_ratio = 0;
|
||||
uchar num_erase_regions;
|
||||
int erase_region_size;
|
||||
int erase_region_count;
|
||||
|
||||
info->start[0] = base;
|
||||
|
||||
invalidate_dcache_range(base, base+0x400);
|
||||
|
||||
if(flash_detect_cfi(info)){
|
||||
|
||||
size_ratio = info->portwidth / info->chipwidth;
|
||||
num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
|
||||
|
||||
sect_cnt = 0;
|
||||
sector = base;
|
||||
for(i = 0 ; i < num_erase_regions; i++) {
|
||||
if(i > NUM_ERASE_REGIONS) {
|
||||
printf("%d erase regions found, only %d used\n",
|
||||
num_erase_regions, NUM_ERASE_REGIONS);
|
||||
break;
|
||||
}
|
||||
tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
|
||||
erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
|
||||
tmp >>= 16;
|
||||
erase_region_count = (tmp & 0xffff) +1;
|
||||
for(j = 0; j< erase_region_count; j++) {
|
||||
info->start[sect_cnt] = sector;
|
||||
sector += (erase_region_size * size_ratio);
|
||||
info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
|
||||
sect_cnt++;
|
||||
}
|
||||
}
|
||||
|
||||
info->sector_count = sect_cnt;
|
||||
/* multiply the size by the number of chips */
|
||||
info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
|
||||
info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
|
||||
tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
|
||||
info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
|
||||
tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
|
||||
info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
|
||||
tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
|
||||
info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
|
||||
info->flash_id = FLASH_MAN_CFI;
|
||||
}
|
||||
|
||||
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
|
||||
#ifdef DEBUG_FLASH
|
||||
printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
|
||||
#endif
|
||||
#ifdef DEBUG_FLASH
|
||||
printf("found %d erase regions\n", num_erase_regions);
|
||||
#endif
|
||||
#ifdef DEBUG_FLASH
|
||||
printf("size=%08x sectors=%08x \n", info->size, info->sector_count);
|
||||
#endif
|
||||
return(info->size);
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
|
||||
{
|
||||
|
||||
cfiptr_t ctladdr;
|
||||
cfiptr_t cptr;
|
||||
int flag;
|
||||
|
||||
ctladdr.cp = flash_make_addr(info, 0, 0);
|
||||
cptr.cp = (uchar *)dest;
|
||||
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
switch(info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
flag = ((cptr.cp[0] & cword.c) == cword.c);
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
flag = ((cptr.wp[0] & cword.w) == cword.w);
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
flag = ((cptr.lp[0] & cword.l) == cword.l);
|
||||
break;
|
||||
default:
|
||||
return 2;
|
||||
}
|
||||
if(!flag)
|
||||
return 2;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
|
||||
flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
|
||||
|
||||
switch(info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
cptr.cp[0] = cword.c;
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
cptr.wp[0] = cword.w;
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
cptr.lp[0] = cword.l;
|
||||
break;
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if(flag)
|
||||
enable_interrupts();
|
||||
|
||||
return flash_full_status_check(info, 0, info->write_tout, "write");
|
||||
}
|
||||
|
||||
#ifdef CFG_FLASH_USE_BUFFER_WRITE
|
||||
|
||||
/* loop through the sectors from the highest address
|
||||
* when the passed address is greater or equal to the sector address
|
||||
* we have a match
|
||||
*/
|
||||
static int find_sector(flash_info_t *info, ulong addr)
|
||||
{
|
||||
int sector;
|
||||
for(sector = info->sector_count - 1; sector >= 0; sector--) {
|
||||
if(addr >= info->start[sector])
|
||||
break;
|
||||
}
|
||||
return sector;
|
||||
}
|
||||
|
||||
static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
|
||||
{
|
||||
|
||||
int sector;
|
||||
int cnt;
|
||||
int retcode;
|
||||
volatile cfiptr_t src;
|
||||
volatile cfiptr_t dst;
|
||||
|
||||
src.cp = cp;
|
||||
dst.cp = (uchar *)dest;
|
||||
sector = find_sector(info, dest);
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
|
||||
if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
|
||||
"write to buffer")) == ERR_OK) {
|
||||
switch(info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
cnt = len;
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
cnt = len >> 1;
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
cnt = len >> 2;
|
||||
break;
|
||||
default:
|
||||
return ERR_INVAL;
|
||||
break;
|
||||
}
|
||||
flash_write_cmd(info, sector, 0, (uchar)cnt-1);
|
||||
while(cnt-- > 0) {
|
||||
switch(info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
*dst.cp++ = *src.cp++;
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
*dst.wp++ = *src.wp++;
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
*dst.lp++ = *src.lp++;
|
||||
break;
|
||||
default:
|
||||
return ERR_INVAL;
|
||||
break;
|
||||
}
|
||||
}
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
|
||||
retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
|
||||
"buffer write");
|
||||
}
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
|
||||
return retcode;
|
||||
}
|
||||
#endif /* CFG_USE_FLASH_BUFFER_WRITE */
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -5,6 +5,9 @@
|
|||
* (C) Copyright 2005
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* (C) Copyright 2006
|
||||
* Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
|
|
@ -31,7 +34,6 @@
|
|||
#include <pci.h>
|
||||
#include <sm501.h>
|
||||
|
||||
|
||||
#ifdef CONFIG_VIDEO_SM501
|
||||
|
||||
#define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
|
||||
|
|
@ -66,10 +68,12 @@ static const SMI_REGS init_regs_800x600 [] =
|
|||
{0x00040, SWAP32(0x00021807)},
|
||||
{0x00044, SWAP32(0x221a0a01)},
|
||||
{0x00054, SWAP32(0x00000000)},
|
||||
/* GPIO */
|
||||
{0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
|
||||
/* panel control regs... */
|
||||
{0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
|
||||
{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
|
||||
{0x8000C, SWAP32(0x00000000)}, /* panel fb address */
|
||||
{0x8000C, SWAP32(0x00010000)}, /* panel fb address */
|
||||
{0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */
|
||||
{0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
|
||||
{0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
|
||||
|
|
@ -100,10 +104,12 @@ static const SMI_REGS init_regs_1024x768 [] =
|
|||
{0x00040, SWAP32(0x00021807)},
|
||||
{0x00044, SWAP32(0x011a0a01)},
|
||||
{0x00054, SWAP32(0x00000000)},
|
||||
/* GPIO */
|
||||
{0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
|
||||
/* panel control regs... */
|
||||
{0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
|
||||
{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
|
||||
{0x8000C, SWAP32(0x00000000)}, /* panel fb address */
|
||||
{0x8000C, SWAP32(0x00010000)}, /* panel fb address */
|
||||
{0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */
|
||||
{0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
|
||||
{0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
|
||||
|
|
@ -144,10 +150,12 @@ static const SMI_REGS init_regs_800x600 [] =
|
|||
{0x00040, SWAP32(0x00021807)},
|
||||
{0x00044, SWAP32(0x221a0a01)},
|
||||
{0x00054, SWAP32(0x00000000)},
|
||||
/* GPIO */
|
||||
{0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
|
||||
/* panel control regs... */
|
||||
{0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
|
||||
{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
|
||||
{0x8000C, SWAP32(0x00000000)}, /* panel fb address */
|
||||
{0x8000C, SWAP32(0x00010000)}, /* panel fb address */
|
||||
{0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */
|
||||
{0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
|
||||
{0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
|
||||
|
|
@ -178,10 +186,12 @@ static const SMI_REGS init_regs_1024x768 [] =
|
|||
{0x00040, SWAP32(0x00021807)},
|
||||
{0x00044, SWAP32(0x011a0a01)},
|
||||
{0x00054, SWAP32(0x00000000)},
|
||||
/* GPIO */
|
||||
{0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
|
||||
/* panel control regs... */
|
||||
{0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
|
||||
{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
|
||||
{0x8000C, SWAP32(0x00000000)}, /* panel fb address */
|
||||
{0x8000C, SWAP32(0x00010000)}, /* panel fb address */
|
||||
{0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */
|
||||
{0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
|
||||
{0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
|
||||
|
|
@ -272,6 +282,9 @@ au_image_t au_image[] = {
|
|||
int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
|
||||
|
||||
|
||||
/*
|
||||
* Get version of HH405 board from GPIO's
|
||||
*/
|
||||
int board_revision(void)
|
||||
{
|
||||
unsigned long osrh_reg;
|
||||
|
|
@ -279,10 +292,6 @@ int board_revision(void)
|
|||
unsigned long tcr_reg;
|
||||
unsigned long value;
|
||||
|
||||
/*
|
||||
* Get version of HH405 board from GPIO's
|
||||
*/
|
||||
|
||||
/*
|
||||
* Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO)
|
||||
*/
|
||||
|
|
@ -305,15 +314,13 @@ int board_revision(void)
|
|||
|
||||
if (value & 0x80000000) {
|
||||
/* Revision 1.0 or 1.1 detected */
|
||||
return 0x0101;
|
||||
return 1;
|
||||
} else {
|
||||
if (value & 0x00400000) {
|
||||
/* unused */
|
||||
return 0x0103;
|
||||
return 3;
|
||||
} else {
|
||||
/* Revision >= 2.0 detected */
|
||||
/* rev. 2.x uses four SM501 GPIOs for revision coding */
|
||||
return 0x0200;
|
||||
return 2;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -349,6 +356,38 @@ int board_early_init_f (void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int cf_enable(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int i;
|
||||
|
||||
volatile unsigned short *fpga_ctrl =
|
||||
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
|
||||
volatile unsigned short *fpga_status =
|
||||
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2);
|
||||
|
||||
if (gd->board_type >= 2) {
|
||||
if (*fpga_status & CFG_FPGA_STATUS_CF_DETECT) {
|
||||
if (!(*fpga_ctrl & CFG_FPGA_CTRL_CF_BUS_EN)) {
|
||||
*fpga_ctrl &= ~CFG_FPGA_CTRL_CF_PWRN;
|
||||
|
||||
for (i=0; i<300; i++)
|
||||
udelay(1000);
|
||||
|
||||
*fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN;
|
||||
|
||||
for (i=0; i<20; i++)
|
||||
udelay(1000);
|
||||
}
|
||||
} else {
|
||||
*fpga_ctrl &= ~CFG_FPGA_CTRL_CF_BUS_EN;
|
||||
*fpga_ctrl |= CFG_FPGA_CTRL_CF_PWRN;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
|
|
@ -433,9 +472,6 @@ int misc_init_r (void)
|
|||
* Write Board revision into FPGA
|
||||
*/
|
||||
*fpga_ctrl |= gd->board_type & 0x0003;
|
||||
if (gd->board_type >= 0x0200) {
|
||||
*fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN;
|
||||
}
|
||||
|
||||
/*
|
||||
* Setup and enable EEPROM write protection
|
||||
|
|
@ -471,7 +507,7 @@ int misc_init_r (void)
|
|||
contrast0 = simple_strtol(str, NULL, 16);
|
||||
if (contrast0 > 255) {
|
||||
printf("ERROR: contrast0 value too high (0x%lx)!\n", contrast0);
|
||||
contrast0 = 0;
|
||||
contrast0 = 0xffffffff;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -544,9 +580,9 @@ int misc_init_r (void)
|
|||
*/
|
||||
*fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE;
|
||||
/*
|
||||
* Set lcd clock (small epson)
|
||||
* Set lcd clock (small epson), enable 1-wire interface
|
||||
*/
|
||||
*fpga_ctrl |= LCD_CLK_08330;
|
||||
*fpga_ctrl |= LCD_CLK_08330 | CFG_FPGA_CTRL_OW_ENABLE;
|
||||
|
||||
lcd_setup(0, 1);
|
||||
lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
|
||||
|
|
@ -565,8 +601,10 @@ int misc_init_r (void)
|
|||
puts("VGA: SM501 with 8 MB ");
|
||||
if (strcmp(str, "ppc221") == 0) {
|
||||
printf("(800*600, %dbpp)\n", BPP);
|
||||
*lcd_backlight = 0x002d; /* max. allowed brightness */
|
||||
} else if (strcmp(str, "ppc231") == 0) {
|
||||
printf("(1024*768, %dbpp)\n", BPP);
|
||||
*lcd_backlight = 0x0000;
|
||||
} else {
|
||||
printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
|
||||
return 0;
|
||||
|
|
@ -578,6 +616,8 @@ int misc_init_r (void)
|
|||
#endif /* CONFIG_VIDEO_SM501 */
|
||||
}
|
||||
|
||||
cf_enable();
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
|
@ -608,14 +648,7 @@ int checkboard (void)
|
|||
}
|
||||
|
||||
gd->board_type = board_revision();
|
||||
printf(", Rev %ld.%ld)\n",
|
||||
(gd->board_type >> 8) & 0xff,
|
||||
gd->board_type & 0xff);
|
||||
|
||||
/*
|
||||
* Disable sleep mode in LXT971
|
||||
*/
|
||||
lxt971_no_sleep();
|
||||
printf(", Rev %ld.x)\n", gd->board_type);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -637,28 +670,27 @@ long int initdram (int board_type)
|
|||
}
|
||||
|
||||
|
||||
int testdram (void)
|
||||
{
|
||||
/* TODO: XXX XXX XXX */
|
||||
printf ("test: 16 MB - ok\n");
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
#ifdef CONFIG_IDE_RESET
|
||||
void ide_set_reset(int on)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
volatile unsigned short *fpga_mode =
|
||||
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
|
||||
volatile unsigned short *fpga_status =
|
||||
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2);
|
||||
|
||||
/*
|
||||
* Assert or deassert CompactFlash Reset Pin
|
||||
*/
|
||||
if (on) { /* assert RESET */
|
||||
*fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
|
||||
} else { /* release RESET */
|
||||
*fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
|
||||
if (((gd->board_type >= 2) && (*fpga_status & CFG_FPGA_STATUS_CF_DETECT)) ||
|
||||
(gd->board_type < 2)) {
|
||||
/*
|
||||
* Assert or deassert CompactFlash Reset Pin
|
||||
*/
|
||||
if (on) { /* assert RESET */
|
||||
cf_enable();
|
||||
*fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
|
||||
} else { /* release RESET */
|
||||
*fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_IDE_RESET */
|
||||
|
|
@ -778,8 +810,7 @@ void video_get_info_str (int line_number, char *info)
|
|||
strcat(str, " (Missing bd_type!");
|
||||
}
|
||||
|
||||
sprintf(str2, ", Rev %ld.%ld)",
|
||||
(gd->board_type >> 8) & 0xff, gd->board_type & 0xff);
|
||||
sprintf(str2, ", Rev %ld.x)", gd->board_type);
|
||||
strcat(str, str2);
|
||||
strcpy(info, str);
|
||||
} else {
|
||||
|
|
@ -822,7 +853,11 @@ unsigned int board_video_get_fb (void)
|
|||
devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
|
||||
if (devbusfn != -1) {
|
||||
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr);
|
||||
return (addr & 0xfffffffe);
|
||||
addr &= 0xfffffffe;
|
||||
#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET
|
||||
addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET;
|
||||
#endif
|
||||
return addr;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -875,3 +910,15 @@ int board_get_height (void)
|
|||
}
|
||||
|
||||
#endif /* CONFIG_VIDEO_SM501 */
|
||||
|
||||
|
||||
void reset_phy(void)
|
||||
{
|
||||
#ifdef CONFIG_LXT971_NO_SLEEP
|
||||
|
||||
/*
|
||||
* Disable sleep mode in LXT971
|
||||
*/
|
||||
lxt971_no_sleep();
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -285,13 +285,19 @@
|
|||
* FLASH related
|
||||
*----------------------------------------------------------------------*/
|
||||
|
||||
#define CFG_FLASH_CFI_DRIVER
|
||||
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
|
||||
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
|
||||
#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */
|
||||
#define CFG_FLASH_INCREMENT 0x01000000 /* there is only one bank */
|
||||
#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
|
||||
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
|
||||
#define CFG_FLASH_BASE 0xfc000000 /* start of flash banks */
|
||||
#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */
|
||||
#define CFG_FLASH_INCREMENT 0x01000000 /* size of flash bank */
|
||||
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
|
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \
|
||||
CFG_FLASH_BASE + 1*CFG_FLASH_INCREMENT, \
|
||||
CFG_FLASH_BASE + 2*CFG_FLASH_INCREMENT, \
|
||||
CFG_FLASH_BASE + 3*CFG_FLASH_INCREMENT }
|
||||
#define CFG_FLASH_EMPTY_INFO 1 /* show if bank is empty */
|
||||
|
||||
/* areas to map different things with the GT in physical space */
|
||||
#define CFG_DRAM_BANKS 4
|
||||
|
|
|
|||
|
|
@ -5,6 +5,9 @@
|
|||
* (C) Copyright 2005
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* (C) Copyright 2006
|
||||
* Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
|
|
@ -61,9 +64,13 @@
|
|||
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#undef CONFIG_HAS_ETH1
|
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_PHY_ADDR 0 /* PHY address */
|
||||
#define CONFIG_PHY_ADDR 0 /* PHY address */
|
||||
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
|
||||
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
|
||||
|
||||
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
|
||||
|
||||
|
|
@ -79,6 +86,7 @@
|
|||
#else
|
||||
#define CONFIG_VIDEO_SM501_16BPP
|
||||
#endif
|
||||
#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
|
||||
#define CONFIG_CFB_CONSOLE
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_VGA_AS_SINGLE_DEVICE
|
||||
|
|
@ -434,9 +442,12 @@
|
|||
#define CFG_FPGA_CTRL_VGA0_BL_MODE 0x0008
|
||||
#define CFG_FPGA_CTRL_CF_RESET 0x0040
|
||||
#define CFG_FPGA_CTRL_PS2_PWR 0x0080
|
||||
#define CFG_FPGA_CTRL_CF_PWR 0x0100 /* low active */
|
||||
#define CFG_FPGA_CTRL_CF_PWRN 0x0100 /* low active */
|
||||
#define CFG_FPGA_CTRL_CF_BUS_EN 0x0200
|
||||
#define CFG_FPGA_CTRL_LCD_CLK 0x7000 /* Mask for lcd clock */
|
||||
#define CFG_FPGA_CTRL_OW_ENABLE 0x8000
|
||||
|
||||
#define CFG_FPGA_STATUS_CF_DETECT 0x8000
|
||||
|
||||
#define LCD_CLK_OFF 0x0000 /* Off */
|
||||
#define LCD_CLK_02083 0x1000 /* 2.083 MHz */
|
||||
|
|
|
|||
|
|
@ -101,7 +101,7 @@
|
|||
/*
|
||||
* Autobooting
|
||||
*/
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
|
|
@ -109,6 +109,16 @@
|
|||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_ETHADDR 00:a0:a4:03:00:00
|
||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE
|
||||
|
||||
#define CONFIG_IPADDR 192.168.100.2
|
||||
#define CONFIG_SERVERIP 192.168.100.1
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define HOSTNAME inka4x0
|
||||
#define CONFIG_BOOTFILE /tftpboot/inka4x0/uImage
|
||||
#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
|
|
@ -117,13 +127,22 @@
|
|||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;" \
|
||||
"addcons=setenv bootargs ${bootargs} " \
|
||||
"console=ttyS0,${baudrate}\0" \
|
||||
"flash_nfs=run nfsargs addip addcons;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_82xx\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};" \
|
||||
"run nfsargs addip addcons;bootm\0" \
|
||||
"enable_disp=mw.l 100000 04000000 1;" \
|
||||
"cp.l 100000 f0000b20 1;" \
|
||||
"cp.l 100000 f0000b28 1\0" \
|
||||
"ideargs=setenv bootargs root=/dev/hda1 rw\0" \
|
||||
"ide_boot=ext2load ide 0:1 200000 uImage;" \
|
||||
"run ideargs addip addcons enable_disp;bootm" \
|
||||
"brightness=255\0" \
|
||||
""
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "run net_nfs"
|
||||
#define CONFIG_BOOTCOMMAND "run ide_boot"
|
||||
|
||||
/*
|
||||
* IPB Bus clocking configuration.
|
||||
|
|
@ -193,6 +212,7 @@
|
|||
*/
|
||||
/* #define CONFIG_FEC_10MBIT 1 */
|
||||
#define CONFIG_PHY_ADDR 0x00
|
||||
#define CONFIG_MII
|
||||
|
||||
/*
|
||||
* GPIO configuration
|
||||
|
|
|
|||
373
include/configs/smmaco4.h
Normal file
373
include/configs/smmaco4.h
Normal file
|
|
@ -0,0 +1,373 @@
|
|||
/*
|
||||
* (C) Copyright 2003-2006
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* (C) Copyright 2004-2005
|
||||
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
|
||||
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
|
||||
#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
|
||||
#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
|
||||
|
||||
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
|
||||
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Serial console configuration
|
||||
*/
|
||||
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
|
||||
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
|
||||
|
||||
/* Partitions */
|
||||
#define CONFIG_MAC_PARTITION
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_ISO_PARTITION
|
||||
|
||||
/* POST support */
|
||||
#define CONFIG_POST (CFG_POST_MEMORY | \
|
||||
CFG_POST_CPU | \
|
||||
CFG_POST_I2C)
|
||||
|
||||
#ifdef CONFIG_POST
|
||||
#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
|
||||
/* preserve space for the post_word at end of on-chip SRAM */
|
||||
#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
|
||||
#else
|
||||
#define CFG_CMD_POST_DIAG 0
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Supported commands
|
||||
*/
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_ECHO | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_JFFS2 | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_POST_DIAG | \
|
||||
CFG_CMD_REGINFO | \
|
||||
CFG_CMD_SNTP )
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#define CONFIG_TIMESTAMP /* display image timestamps */
|
||||
|
||||
#if (TEXT_BASE == 0xFC000000) /* Boot low */
|
||||
# define CFG_LOWBOOT 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Autobooting
|
||||
*/
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"rootpath=/opt/eldk/ppc_6xx\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"flash_self=run ramargs addip;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"flash_nfs=run nfsargs addip;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
|
||||
"bootfile=/tftpboot/smmaco4/uImage\0" \
|
||||
"load=tftp 200000 ${u-boot}\0" \
|
||||
"u-boot=/tftpboot/smmaco4/u-boot.bin\0" \
|
||||
"update=protect off FC000000 FC05FFFF;" \
|
||||
"erase FC000000 FC05FFFF;" \
|
||||
"cp.b 200000 FC000000 ${filesize};" \
|
||||
"protect on FC000000 FC05FFFF\0" \
|
||||
""
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "run net_nfs"
|
||||
|
||||
/*
|
||||
* IPB Bus clocking configuration.
|
||||
*/
|
||||
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
|
||||
|
||||
#if defined(CFG_IPBSPEED_133)
|
||||
/*
|
||||
* PCI Bus clocking configuration
|
||||
*
|
||||
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
|
||||
* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
|
||||
* been tested with a IPB Bus Clock of 66 MHz.
|
||||
*/
|
||||
#define CFG_PCISPEED_66 /* define for 66MHz speed */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* I2C configuration
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#ifdef CONFIG_TQM5200_REV100
|
||||
#define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
|
||||
#else
|
||||
#define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* I2C clock frequency
|
||||
*
|
||||
* Please notice, that the resulting clock frequency could differ from the
|
||||
* configured value. This is because the I2C clock is derived from system
|
||||
* clock over a frequency divider with only a few divider values. U-boot
|
||||
* calculates the best approximation for CFG_I2C_SPEED. However the calculated
|
||||
* approximation allways lies below the configured value, never above.
|
||||
*/
|
||||
#define CFG_I2C_SPEED 100000 /* 100 kHz */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
|
||||
/*
|
||||
* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
|
||||
* also). For other EEPROMs configuration should be verified. On Mini-FAP the
|
||||
* EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
|
||||
* same configuration could be used.
|
||||
*/
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
|
||||
|
||||
/*
|
||||
* Flash configuration
|
||||
*/
|
||||
#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
|
||||
|
||||
/* use CFI flash driver if no module variant is spezified */
|
||||
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
|
||||
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
|
||||
#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
|
||||
#define CFG_FLASH_EMPTY_INFO
|
||||
#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
|
||||
#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
|
||||
#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
|
||||
|
||||
#if !defined(CFG_LOWBOOT)
|
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
|
||||
#else /* CFG_LOWBOOT */
|
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
|
||||
#endif /* CFG_LOWBOOT */
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
|
||||
(= chip selects) */
|
||||
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
|
||||
|
||||
/* Dynamic MTD partition support */
|
||||
#define CONFIG_JFFS2_CMDLINE
|
||||
#define MTDIDS_DEFAULT "nor0=TQM5200-0"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
|
||||
"1408k(kernel)," \
|
||||
"2m(initrd)," \
|
||||
"4m(small-fs)," \
|
||||
"16m(big-fs)," \
|
||||
"8m(misc)"
|
||||
|
||||
/*
|
||||
* Environment settings
|
||||
*/
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_SIZE 0x10000
|
||||
#define CFG_ENV_SECT_SIZE 0x20000
|
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
|
||||
/*
|
||||
* Memory map
|
||||
*/
|
||||
#define CFG_MBAR 0xF0000000
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_DEFAULT_MBAR 0x80000000
|
||||
|
||||
/* Use ON-Chip SRAM until RAM will be available */
|
||||
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
|
||||
#ifdef CONFIG_POST
|
||||
/* preserve space for the post_word at end of on-chip SRAM */
|
||||
#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
|
||||
#else
|
||||
#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
|
||||
#endif
|
||||
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
|
||||
# define CFG_RAMBOOT 1
|
||||
#endif
|
||||
|
||||
#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
|
||||
#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*
|
||||
* Ethernet configuration
|
||||
*/
|
||||
#define CONFIG_MPC5xxx_FEC 1
|
||||
/*
|
||||
* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
|
||||
*/
|
||||
/* #define CONFIG_FEC_10MBIT 1 */
|
||||
#define CONFIG_PHY_ADDR 0x00
|
||||
|
||||
/*
|
||||
* GPIO configuration
|
||||
*
|
||||
* use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
|
||||
* Bit 0 (mask: 0x80000000): 1
|
||||
* use ALT CAN position: Bits 2-3 (mask: 0x30000000):
|
||||
* 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
|
||||
* 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
|
||||
* Use for REV200 STK52XX boards. Do not use with REV100 modules
|
||||
* (because, there I2C1 is used as I2C bus)
|
||||
* use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
|
||||
* use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
|
||||
* 000 -> All PSC2 pins are GIOPs
|
||||
* 001 -> CAN1/2 on PSC2 pins
|
||||
* Use for REV100 STK52xx boards
|
||||
* use PSC6:
|
||||
* on STK52xx:
|
||||
* use as UART. Pins PSC6_0 to PSC6_3 are used.
|
||||
* Bits 9:11 (mask: 0x00700000):
|
||||
* 101 -> PSC6 : Extended POST test is not available
|
||||
* on MINI-FAP and TQM5200_IB:
|
||||
* use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
|
||||
* 000 -> PSC6 could not be used as UART, CODEC or IrDA
|
||||
* GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
|
||||
* tests.
|
||||
*/
|
||||
#if defined (CONFIG_MINIFAP)
|
||||
# define CFG_GPS_PORT_CONFIG 0x91000004
|
||||
#elif defined (CONFIG_STK52XX)
|
||||
# if defined (CONFIG_STK52XX_REV100)
|
||||
# define CFG_GPS_PORT_CONFIG 0x81500014
|
||||
# else /* STK52xx REV200 and above */
|
||||
# if defined (CONFIG_TQM5200_REV100)
|
||||
# error TQM5200 REV100 not supported on STK52XX REV200 or above
|
||||
# else/* TQM5200 REV200 and above */
|
||||
# define CFG_GPS_PORT_CONFIG 0x91500004
|
||||
# endif
|
||||
# endif
|
||||
#else /* TMQ5200 Inbetriebnahme-Board */
|
||||
# define CFG_GPS_PORT_CONFIG 0x81000004
|
||||
#endif
|
||||
|
||||
/*
|
||||
* RTC configuration
|
||||
*/
|
||||
#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
/* Enable an alternate, more extensive memory test */
|
||||
#define CFG_ALT_MEMTEST
|
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
/*
|
||||
* Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
|
||||
* which is normally part of the default commands (CFV_CMD_DFL)
|
||||
*/
|
||||
#define CONFIG_LOOPW
|
||||
|
||||
/*
|
||||
* Various low-level settings
|
||||
*/
|
||||
#if defined(CONFIG_MPC5200)
|
||||
#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
|
||||
#define CFG_HID0_FINAL HID0_ICE
|
||||
#else
|
||||
#define CFG_HID0_INIT 0
|
||||
#define CFG_HID0_FINAL 0
|
||||
#endif
|
||||
|
||||
#define CFG_BOOTCS_START CFG_FLASH_BASE
|
||||
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
|
||||
#ifdef CFG_PCISPEED_66
|
||||
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
|
||||
#else
|
||||
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
|
||||
#endif
|
||||
#define CFG_CS0_START CFG_FLASH_BASE
|
||||
#define CFG_CS0_SIZE CFG_FLASH_SIZE
|
||||
|
||||
#define CFG_CS_BURST 0x00000000
|
||||
#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
|
||||
|
||||
#define CFG_RESET_ADDRESS 0xff000000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2003
|
||||
* (C) Copyright 2000-2006
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
|
|
@ -24,6 +24,6 @@
|
|||
#ifndef __VERSION_H__
|
||||
#define __VERSION_H__
|
||||
|
||||
#define U_BOOT_VERSION "U-Boot 1.1.4"
|
||||
#include "version_autogenerated.h"
|
||||
|
||||
#endif /* __VERSION_H__ */
|
||||
|
|
|
|||
22
tools/setlocalversion
Executable file
22
tools/setlocalversion
Executable file
|
|
@ -0,0 +1,22 @@
|
|||
#!/bin/sh
|
||||
# Print additional version information for non-release trees.
|
||||
|
||||
usage() {
|
||||
echo "Usage: $0 [srctree]" >&2
|
||||
exit 1
|
||||
}
|
||||
|
||||
cd "${1:-.}" || usage
|
||||
|
||||
# Check for git and a git repo.
|
||||
if head=`git rev-parse --verify HEAD 2>/dev/null`; then
|
||||
# Do we have an untagged version?
|
||||
if [ "`git name-rev --tags HEAD`" = "HEAD undefined" ]; then
|
||||
printf '%s%s' -g `echo "$head" | cut -c1-8`
|
||||
fi
|
||||
|
||||
# Are there uncommitted changes?
|
||||
if git diff-files | read dummy; then
|
||||
printf '%s' -dirty
|
||||
fi
|
||||
fi
|
||||
Loading…
Reference in a new issue