Account for the changes done between merge proposal and the final merge.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The patch enables spread spectrum clocking (SSC) for MPU and LCD PLLs.
As reported by the TI spruh73x/spruhl7x RM, SSC is only supported for
the DISP/LCD and MPU PLLs on am33xx/am43xx. SSC is not supported for
DDR, PER, and CORE PLLs.
Calculating the required values and setting the registers accordingly
was taken from the set_mpu_spreadspectrum routine contained in the
arch/arm/mach-omap2/am33xx/clock_am33xx.c file of the u-boot project.
In locked condition, DPLL output clock = CLKINP *[M/N]. In case of
SSC enabled, the reference manual explains that there is a restriction
of range of M values. Since the clk_ti_am3_dpll_round_rate() attempts
to select the minimum possible N, the value of M obtained is not
guaranteed to be within the range required. With the new "ti,min-div"
parameter it is possible to increase N and consequently M to satisfy the
constraint imposed by SSC.
Link: https://lore.kernel.org/r/20210606202253.31649-6-dariobin@libero.it
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Registers for adjusting the spread spectrum clocking (SSC) have been
added. As reported by the TI spruhl7x RM, SSC is supported only for LCD
and MPU PLLs, but the PRCM_CM_SSC_DELTAMSTEP_DPLL_XXX and
PRCM_CM_SSC_MODFREQDIV_DPLL_XXX registers, as well as the enable field
in the PRCM_CM_CLKMODE_DPLL_XXX registers are mapped for all PLLs (CORE,
MPU, DDR, PER, DISP, EXTDEV).
Link: https://lore.kernel.org/r/20210606202253.31649-5-dariobin@libero.it
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Registers for adjusting the spread spectrum clocking (SSC) have been
added. As reported by the TI spruh73x RM, SSC is supported only for LCD
and MPU PLLs, but the CM_SSC_DELTAMSTEP_DPLL_XXX and
CM_SSC_MODFREQDIV_DPLL_XXX registers, as well as the enable field in the
CM_CLKMODE_DPLL_XXX registers are mapped for all PLLs (CORE, MPU, DDR,
PER, DISP).
Link: https://lore.kernel.org/r/20210606202253.31649-4-dariobin@libero.it
Signed-off-by: Dario Binacchi <dariobin@libero.it>
This adds support for the NanoPi R1S H5 board.
Allwinner H5 SoC
512MB DDR3 RAM
10/100/1000M Ethernet x 2
RTL8189ETV WiFi 802.11b/g/n
USB 2.0 host port (A)
MicroSD Slot
Reset button
Serial Debug Port
WAN - LAN - SYS LED
The dts file is taken from Linux 5.14 tag.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Since the beginning, all banks have had space for 32 pins, even when
not all pins were implemented. Let's use a single constant for the GPIO
bank size here, like the GPIO driver is already doing.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This clarifies which callers must be updated to complete the DM_GPIO
conversion.
The only remaining caller of name_to_gpio in generic code is inside the
!DM_GPIO block in cmd/gpio.c. DM_GPIO is always selected on sunxi, so
that code cannot be reached. And after this commit, there are only two
remaining implementations of name_to_gpio.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
As part of migrating to DM_GPIO and DM_PINCTRL, eventually we will
remove the asm/arch/gpio.h header. In preparation, clean up the various
files that include it.
Some files did not contain any GPIO code at all, so this header was
completely unused.
A few files contained only legacy platform-specific GPIO code for
setting up pin muxes. They were left unchanged, as that code will be
completely removed by the DM_PINCTRL migration.
The remaining files contain some combination of DM_GPIO and legacy GPIO
code. For those, switch to including asm/gpio.h (if it wasn't included
already). Right now, this header provides both sets of functions,
because ARCH_SUNXI selects GPIO_EXTRA_HEADER. This will still be the
right header to include once the DM_GPIO migration is complete and
GPIO_EXTRA_HEADER is no longer needed.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The only caller of this function was the MMC pinmux code, which used it
to parse a string given from a Kconfig symbol. As the Kconfig symbol has
been converted to a Boolean, this function is no longer needed.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Only one board, Yones Toptech BD1078, actually uses a non-default MMC
pinmux. All other uses of these symbols select the default value or an
invalid value. To simplify things, remove support for the unused pinmux
options, and convert the remaining option to a Boolean.
This allows the pinmux to be chosen by the preprocessor, instead of
having the code parse a string at runtime (for a build-time option!).
Not only does this reduce code size, but it also allows this Kconfig
option to be used in a table-driven DM pinctrl driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The CCU header is only used by the DM drivers, not any platform code.
Its current location adds an artificial dependency on CONFIG_ARM and
ARCH_SUNXI, which will be problematic when adding the CCU driver for
a RISC-V sunxi platform.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Add a host Kconfig for OF_LIBFDT. With this we can use
CONFIG_IS_ENABLED(OF_LIBFDT) directly in the tools build, so drop the
unnecessary indirection.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Make use of the host Kconfig for FIT. With this we can use
CONFIG_IS_ENABLED(FIT) directly in the host build, so drop the unnecessary
indirection.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Current CP1 pinctrl that is set on the Puzzle M801 is incorrect.
CP1 pins are only used for the SMI bus and the MSS I2C, all other
pins are just GPIO-s.
Due to this being set completely wrong, the pinctrl was actually
ended up being hardcoded in the board_early_init_f() step so that
SMI would work.
That is obviously not the right thing to do, so convert the register
hex values that were being written to individual pin modes and set it
in the DTS.
Add the SMI pins to the CP1 MDIO node as otherwise CP1 pinctrl does
not get probed without an consumer.
Fixes: 2ae2b8a2 ("arm: mvebu: Initial iEi Puzzle-M801 support")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
Select SPL_SKIP_LOWLEVEL_INIT on 32bit Armada platforms via Kconfig,
as this was removed from mach/config.h in a2ac2b96 ("Convert
CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig").
Signed-off-by: Stefan Roese <sr@denx.de>
Fixes: a2ac2b96 ("Convert CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig")
Cc: Tom Rini <trini@konsulko.com>
Cc: Marek Behún <kabel@kernel.org>
Cc: Pali Rohár <pali@kernel.org>
Tested-by: Pali Rohár <pali@kernel.org>
These are part of SOC_CONTROL_REG1 register, not PEX_CAPABILITIES_REG.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Remove unused PCIe functions from SerDes code. They are unused and are
duplicated either from generic PCIe code or from pci_mvebu.c.
Remove also unused PCIe macros from SerDes code. They are just obfuscated
variants of standards macros in include/pci.h or in pci_mvebu.c.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
This code is trying to parse PCIe config space of PCIe card connected on
the other end of link and then is trying to force 5.0 GT/s speed via Target
Link Speed bits in PCIe Root Port Link Control 2 Register on the local part
of link if it sees that card supports 5.0 GT/s via Max Link Speed bits in
Link Capabilities Register.
The code is incorrect for more reasons:
- Accessing config space of an endpoint card cannot be done immediately.
If the PCIe link is not up, reading vendor/device ID registers will
return all ones.
- Parsing is incomplete, so it can cause issues even for working cards.
Moreover there is no need to force speed to 5.0 GT/s via Target Link Speed
bits on PCIe Root Port Link Control 2 Register. Hardware changes speed from
2.5 GT/s to 5.0 GT/s autonomously when it is supported.
Most importantly, this code does not change link speed at all, since
because after updating Target Link Speed bits on PCIe Root Port Link
Control 2 Register, it is required to retrain the link, and the code for
that is completely missing.
The code was probably needed for making buggy endpoint cards work. Such a
workaround, though, should be implemented via PCIe subsystem (via quirks,
for example), as buggy cards could also affect other PCIe controllers.
Note that this code is fully unrelated to a38x SerDes code and really
should not have been included in SerDes initialization. Usage of magic
constants without names and comments made this SerDes code hard to read and
understand.
Remove this PCIe application code from low level SerDes code. As this code
is configuring only 5.0 GT/s part, in the worst case, it could leave buggy
cards at the initial speed of 2.5 GT/s (if somehow before this change they
could have been "upgraded" to 5.0 GT/s speed even with missing link
retraining). Compliant cards which just need longer initialization should
work better after this change.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
PCI device ID is part of the PCIe controller SoC / revision. For Root
Complex mode (which is the default and the only mode supported currently
by U-Boot and Linux kernel), it is PCI device ID of PCIe Root Port device.
If there is some issue with this device ID, it should be set / updated by
PCIe controller driver (pci_mvebu.c), as this register resides in address
space of the controller. It shouldn't be done in SerDes initialization
code.
In the worst case (a specific board for example) it could be done via
U-Boot's weak function board_pex_config().
But it should not be overwritten globally for all A38x devices.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Enabling Common Clock Configuration bit in PCIe Root Port Link Control
Register should not be done unconditionally. It is enabled by operating
system as part of ASPM. Also after enabling Common Clock Configuration it
is required to do more work, like retraining link. Some cards may be broken
due to this incomplete Common Clock Configuration and some cards are broken
and do not support ASPM at all.
Remove this incomplete code for Common Clock Configuration. It really
should not be done in SerDes code as it is not related to SerDes, but to
PCIe subsystem.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Device/Port Type bits of PCIe Root Port PCI Express Capabilities Register
are read-only SAR registers and are initialized according to current mode
configured by PCIe controller. Changing PCIe controller mode (from Root
Complex mode to Endpoint mode or the other way) is possible via PCI
Express Control Register (offset 0x41A00), bit 1 (ConfRoot Complex). This
has to be done in PCIe controller driver (in our case pci_mvebu.c). Note
that default mode is Root Complex.
Maximum Link Speed bits of PCIe Root Port Link Capabilities Register are
platform specific and overwriting them does not make sense. They are set by
PCIe controller according to current SerDes configuration. For A38x it is
5.0 GT/s if SerDes supports appropriate speed.
Maximum Link Width bits of PCIe Root Port Link Capabilities Register are
read-only SAR registers, but unfortunately if this is not set correctly
here, then access PCI config space of the endpoint card behind this Root
Port does not work.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Add comments to understand what this magic code is doing.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
SoC Control 1 Register (offset 0x18204) is already defined by macro
SOC_CONTROL_REG1.
Use macro SOC_CONTROL_REG1 instead of macro SOC_CTRL_REG in ctrl_pex.c
code and remove the other definition.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Replace magic register offsets by macros to make code more readable.
Add comments about what this code is doing.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Commit 079b35a261 ("arm: a37xx: pci: Increase PCIe MEM size from 16 MiB
to 127 MiB") increased size of PCIe MEM to 127 MiB, which is the maximal
possible size for allocated 128 MiB PCIe window. PCIe IO size in that
commit was unchanged.
Armada 3720 PCIe controller supports 32-bit IO space mapping so it is
possible to assign more than 64 KiB if address space for IO.
Currently controller has assigned 127 MiB + 64 KiB memory and therefore
there is 960 KiB of unused memory. So assign it to IO space by increasing
IO window from 64 KiB to 1 MiB.
Signed-off-by: Pali Rohár <pali@kernel.org>
Fixes: 079b35a261 ("arm: a37xx: pci: Increase PCIe MEM size from 16 MiB to 127 MiB")
Reviewed-by: Stefan Roese <sr@denx.de>
Remove the following STV0991 specific configs:
- CONFIG_STV0991 (never used, only defined in CONFIG_SYS_EXTRA_OPTIONS)
- CONFIG_STV0991_HZ (replaced by generic CONFIG_SYS_HZ)
- CONFIG_STV0991_HZ_CLOCK (replaced by generic CONFIG_SYS_HZ_CLOCK)
This patch allows to reduce the file config_whitelist.txt.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Use the common imx8mm-venice-u-boot.dtsi (dtb for the
'DEFAULT_DEVICE_TREE) so that it inherits things like binman.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Use the common imx8mm-venice-u-boot.dtsi (dtb for the
'DEFAULT_DEVICE_TREE) so that it inherits things like binman.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Use the common imx8mm-venice-u-boot.dtsi (dtb for the
'DEFAULT_DEVICE_TREE) so that it inherits things like binman.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
After switch to use binman, no need to use the bash script
to check file exsiting or not. And there is bug that
the script will be executed everytime Makefile is used which is
confusing people.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
The Kontron SoM-Line i.MX8MM (N801x) by Kontron Electronics GmbH is a SoM
module with an i.MX8M-Mini SoC, 1/2/4 GB LPDDR4 RAM, SPI NOR, eMMC and PMIC.
The matching evaluation boards (Board-Line) have 2 Ethernets, USB 2.0, HDMI/LVDS,
SD card, CAN, RS485 and much more.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Tested-by: Heiko Thiery <heiko.thiery@gmail.com>
Remove board_ehci_hcd_init function that is not used with DM_USB
and replace its functionality with device-tree configuraton that treats
USB HUB RST# as a gpio enable for the usbh1 vbus regulator.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
This adds support for i.MX6UL/ULL-based evaluation kits with SoMs by
Kontron Electronics GmbH.
Currently there are the following SoM flavors (SoM-Line):
* N6310: SOM with i.MX6UL-2, 256MB RAM, 256MB SPI NAND
* N6311: SOM with i.MX6UL-2, 512MB RAM, 512MB SPI NAND
* N6411: SOM with i.MX6ULL, 512MB RAM, 512MB SPI NAND
And the according evaluation boards (Board-Line):
* N6310-S: Baseboard with SOM N6310, eMMC, display (optional), ...
* N6311-S: Baseboard with SOM N6311, eMMC, display (optional), ...
* N6411-S: Baseboard with SOM N6411, eMMC, display (optional), ...
Currently U-Boot describes i.MX6UL and i.MX6ULL through separate config
options at compile-time. Though the differences are so minor, that for
the scope of these SoMs we just use a single defconfig that is compatible
with both SoCs.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Synchronize the u-boot and kernel imx device trees, using tuned
script from commit c0157bdcafa1 ("ARM: dts: imx: use generic name bus")
Per devicetree specification, generic names are recommended to be
used, such as bus.
i.MX AIPS is an AHB - IP bridge bus, so we could use bus as node
name.
Script:
sed -i "s/\<aips@/bus@/" arch/arm/dts/imx*.dtsi
sed -i "s/\<aips@/bus@/" arch/arm/dts/vf*.dtsi
sed -i "s/\<aips-bus@/bus@/" arch/arm/dts/imx*.dtsi
sed -i "s/\<aips-bus@/bus@/" arch/arm/dts/vf*.dtsi
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Update the mx7ulp wdog disable sequence to avoid potential reset
issue in unlock or refresh sequence. Both sequence need two words
write to wdog CNT register in 16 bus clocks window, if miss the
window, the write will cause violation in wdog and reset the chip.
Current u-boot code is using writel() function which has a DMB
barrier to order the memory access. The DMB between two words write
may introduce some delay in certain circumstance, causing the wdog
reset due to 16 bus clock window requirement.
Also, WDOG1 might have been enabled already depending on FUSE hence
we need to be as close as possible to its reconfiguration timing
requirement of 128 bus clock limit.
This patch replaces writel() function by __raw_writel() to avoid such
issue, and improve to check if watchdog is already disabled or
unlocked.
Signed-off-by: Ye Li <ye.li@nxp.com>
Co-developed-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Co-developed-by: Ricardo Salveti <ricardo@foundries.io>
Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Add u-boot.dtsi specific to imx6-apalis with a watchdog enabled.
If OP-TEE is loaded by SPL, it may use a watchdog to handle fails of
u-boot running. Enable the watchdog in SPL to use it by OP-TEE.
Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Since c6df0e2ffd ("net: phy: micrel: add support for DLL setup on ksz9131")
the Micrel PHY driver correctly configures the delay register. The Verdin PHY
is RGMII-ID, so reflect that in DT, otherwise the ethernet no longer works.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Max Krummenacher <max.krummenacher@toradex.com>
Cc: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
binman conversion made flashing flash.bin
and u-boot.itb necessary. Update binman config
to create a single flash.bin image again.
This updates imx8mp_evk and phyCORE-i.MX8MP as they share the
same binman config.
Updated also imx8mp_evk documentation.
Tested on phyCORE-i.MX8MP.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Since derivatives are moving to binman from usage of the FIT generator
script, and considering the warning introduced in f4a43d2925
("Makefile: Warn against using CONFIG_SPL_FIT_GENERATOR"), usage of FIT
generator is discouraged.
Current FIT generator also generates broken output, since commit
3f04db891a ("image: Check for unit addresses in FITs") prohibits using
'@' for unit addresses but the generator script still emits the old
sematics.
Remove the generator script and corresponding call in Makefile, all
derivatives should be migrated to binman in order to provide binary
images.
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Currently imx8mm-cl-iot-gate_defconfig fails to produce a working boot
binary due to the lack of fip.bin:
" BINMAN all
Image 'main-section' is missing external blobs and is non-functional: blob-ext
Some images are invalid"
To make the build process more consistent with the other i.MX8M targets,
split the defconfig in two:
- imx8mm-cl-iot-gate_defconfig: standard defconfig that only
requires ATF / DDR firmware.
- imx8mm-cl-iot-gate-optee_defconfig: "more advanced" defconfig that
requires ATF / Optee / mbedtls / DDR firmware.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Tested-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
When TEE is loaded, we need to restrict the memory usage based
on rom_pointer[0]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Frieder Schrempf <frieder.schrempf@kontron.de>
Cc: uboot-imx <uboot-imx@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
After the enforcement of DM_MMC the microSD card is not detected. Fix by
correctly configuring the card detect in the devicetree.
Signed-off-by: Andrej Rosano <andrej.rosano@f-secure.com>
According to 8MM/MN/MP reference manual, their pad registers only have
4 valid DSE values. And DSE2 and DSE4 are different with current
definitions in iomux-v3.h. Fix the issue to align with manual.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
cherry-picked from NXP code:
719d665a87c6: ("MLK-20467 imx8m: Fix issue for booting signed image through uuu")
which fixes secure boot on imx8m based boards. Problem was
that FIT header and so IVT header too, was loaded to
memallocated address. So the ivt header address coded
in IVT itself does not fit with the real position.
Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Tim Harvey <tharvey@gateworks.com>
read the address where the IVT header must sit
from IVT image header, loaded from SPL into
an malloced buffer and copy the IVT header
to this address
May make this dependend on SoC ?
Signed-off-by: Heiko Schocher <hs@denx.de>
Import the initial dts queued for Linux 5.16.y
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Alpha sort the Amlogic dtb list (same as the kernel).
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add support for new home automation devices.
JetHome Jethub D1 (http://jethome.ru/jethub-d1) is a home automation controller with the following features:
- DIN Rail Mounting case
- Amlogic A113X (ARM Cortex-A53) quad-core up to 1.5GHz
- no video out
- 512Mb/1GB DDR3
- 8/16GB eMMC flash
- 1 x USB 2.0
- 1 x 10/100Mbps ethernet
- WiFi / Bluetooth AMPAK AP6255 (Broadcom BCM43455) IEEE 802.11a/b/g/n/ac, Bluetooth 4.2.
- TI CC2538 + CC2592 Zigbee Wireless Module with up to 20dBm output power and Zigbee 3.0 support.
- 2 x gpio LEDS
- GPIO user Button
- 1 x 1-Wire
- 2 x RS-485
- 4 x dry contact digital GPIO inputs
- 3 x relay GPIO outputs
- DC source with a voltage of 9 to 56 V / Passive POE
JetHome Jethub H1 (http://jethome.ru/jethub-h1) is a home automation controller with the following features:
- Square plastic case
- Amlogic S905W (ARM Cortex-A53) quad-core up to 1.5GHz
- no video out
- 1GB DDR3
- 8/16GB eMMC flash
- 2 x USB 2.0
- 1 x 10/100Mbps ethernet
- WiFi / Bluetooth RTL8822CS IEEE 802.11a/b/g/n/ac, Bluetooth 5.0.
- TI CC2538 + CC2592 Zigbee Wireless Module with up to 20dBm output power and Zigbee 3.0 support.
- MicroSD 2.x/3.x/4.x DS/HS cards.
- 1 x gpio LED
- ADC user Button
- DC source 5V microUSB with serial console
Patches from:
- JetHub H1
https://lore.kernel.org/r/20210915085715.1134940-4-adeep@lexina.inhttps://git.kernel.org/amlogic/c/abfaae24ecf3e7f00508b60fa05e2b6789b8f607
- JetHub D1
https://lore.kernel.org/r/20210915085715.1134940-5-adeep@lexina.inhttps://git.kernel.org/amlogic/c/8e279fb2903990cc6296ec56b3b80b2f854b6c79
Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: removed unused variable value]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The Beelink GS-King X is a variant of the GS King boards but with an internal
USB to SATA bridge and advanced audio features.
[narmstrong: add missing CONFIG_SYS_LOAD_ADDR from defconfig]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The Odroid-HC4 is a variant of the Odroid-C4 board but with a PCIe-SATA bridge
instead of the USB3 ports.
[narmstrong: add missing CONFIG_SYS_LOAD_ADDR from defconfig]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Since Linux commmit [1], the order is fixed with aliases, in order to keep the
MMC device order, set it back to HW order in U-Boot dtsi files.
[1] ab547c4fb39f ("arm64: dts: amlogic: Assign a fixed index to mmc devices")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Import Amlogic DT changes from Linux commit 7d2a07b76933 ("Linux 5.14"),
dt-bindings clock changes and new meson-g12b-gsking-x.dts,
meson-sm1-bananapi-m5 & odroid-hc4 boards.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add the SOC ID for the S905Y2 to board info, see below for before/after
tested with a Radxa Zero board:
SoC: Amlogic Meson G12A (Unknown) Revision 28:b (30:2)
SoC: Amlogic Meson G12A (S905Y2) Revision 28:b (30:2)
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
We only include <linux/mtd/rawnand.h> in <nand.h> for the forward
declaration of struct nand_chip, so do that directly. Then, include
<linux/mtd/rawnand.h> where required directly.
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_SYS_NAND_BAD_BLOCK_POS
In order to do this, introduce a choice for HAS_LARGE/SMALL_BADBLOCK_POS
as those are the only valid values. Use LARGE as the default as no
in-tree boards use SMALL, but it is possible.
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_SPL_NAND_LOAD
CONFIG_SYS_NAND_BLOCK_SIZE
CONFIG_SYS_NAND_PAGE_SIZE
CONFIG_SYS_NAND_OOBSIZE
Signed-off-by: Tom Rini <trini@konsulko.com>
This config is only used by three boards with this SOC. Most other
platforms derive this information from devicetree, and are unlikely
to ever need this config.
Moreover, it is confusing when Kconfig asks for this value under
"Support OPTEE images", but does not do anything with the value.
Move it to imx7 for those boards who still make use of it.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Add stub for tee_find_device function when CONFIG_TEE is not activated
to simplify the caller code.
This patch allows to remove the CONFIG_IS_ENABLED(OPTEE) tests
for stm32 platform.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@inaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
The configuration CONFIG_OPTEE is defined 2 times:
1- in lib/optee/Kconfig for support of OPTEE images loaded by bootm command
2- in drivers/tee/optee/Kconfig for support of OP-TEE driver.
It is abnormal to have the same CONFIG define for 2 purpose;
and it is difficult to managed correctly their dependencies.
Moreover CONFIG_SPL_OPTEE is defined in common/spl/Kconfig
to manage OPTEE image load in SPL.
This definition causes an issue with the macro CONFIG_IS_ENABLED(OPTEE)
to test the availability of the OP-TEE driver.
This patch cleans the configuration dependency with:
- CONFIG_OPTEE_IMAGE (renamed) => support of OP-TEE image in U-Boot
- CONFIG_SPL_OPTEE_IMAGE (renamed) => support of OP-TEE image in SPL
- CONFIG_OPTEE (same) => support of OP-TEE driver in U-Boot
- CONFIG_OPTEE_LIB (new) => support of OP-TEE library
After this patch, the macro have the correct behavior:
- CONFIG_IS_ENABLED(OPTEE_IMAGE) => Load of OP-TEE image is supported
- CONFIG_IS_ENABLED(OPTEE) => OP-TEE driver is supported
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
This allows to use the watchdog in custom scripts but does not enforce
that the OS has to support it as well.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
This adds support for the IOT2050 Basic and Advanced devices. The Basic
used the dual-core AM6528 GP processor, the Advanced one the AM6548 HS
quad-core version.
Both variants are booted via a Siemens-provided FSBL that runs on the R5
cores. Consequently, U-Boot support is targeting the A53 cores. U-Boot
SPL, ATF and TEE have to reside in SPI flash.
Full integration into a bootable image can be found on
https://github.com/siemens/meta-iot2050
Based on original board support by Le Jin, Gao Nian and Chao Zeng.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Prepares for the addition of the IOT2050 board which is based on the TI
AM65x. The board comes in four variants, Basic and Advanced, each as
product generation 1 (SR1.0) and 2 (SR2.x), so there are separate dts
files needed. Furthermore, the SPL has its own device tree.
Based on original board support by Le Jin, Gao Nian and Chao Zeng.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
The WDT devices described in the general .dtsi file
should be marked as "disabled" by default.
A WDT should be then enabled in the board specific
.dts file on demands.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
This resyncs the dts files for all of the currently in-tree K3
platforms, along with relevant bindings, with the v5.14 Linux Kernel
release. Of note are that the main-navss/mcu-navss nodes were renamed
to main_navss / mcu_navss and so the u-boot.dtsi files needed to be
updated to match.
Tested on j721e_evm and am65x_evm.
Signed-off-by: Tom Rini <trini@konsulko.com>
This board has not been converted to CONFIG_DM by the deadline.
Remove it.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
This board has not been converted to CONFIG_DM by the deadline.
Remove it. As this is the last ARCH_MX25 platform, remove those
references as well.
Cc: Matthias Weisser <weisserm@arcor.de>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
This board has not been converted to CONFIG_DM by the deadline.
Remove it. As this is the last armada100 platform, remove that support
as well.
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This board has not been converted to CONFIG_DM by the deadline.
Remove it. As this is the last mx35 platform, remove that support as
well.
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefano Babic <sbabic@denx.de>
zynq:
- Enable capsule update for qspi and mmc
- Update zed DT qspi compatible string
zynqmp:
- Add missing modeboot for EMMC
- Add missing nand DT properties
- List all eeproms for SC on vck190
- Add vck190 SC psu_init
clk:
- Handle only GATE type clock for Versal
watchdog:
- Update versal driver to handle system reset
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Merge tag 'xilinx-for-v2022.01-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2022.01-rc1
zynq:
- Enable capsule update for qspi and mmc
- Update zed DT qspi compatible string
zynqmp:
- Add missing modeboot for EMMC
- Add missing nand DT properties
- List all eeproms for SC on vck190
- Add vck190 SC psu_init
clk:
- Handle only GATE type clock for Versal
watchdog:
- Update versal driver to handle system reset
XHCI firmware upload must be performed only once after initializing the
PCI bridge. This fixes USB stack initialization after calling "usb stop;
usb start" on Raspberry Pi 4B.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenz@kernel.org>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
During the migration to a single DTSI for the CP110-s specific pinctrl
compatibles were moved to the SoC DTSI as CP0 and CP1 have some specifics.
Namely, CP0 eMMC/SDIO support depends on the mvebu-pinctrl driver setting
the BIT(0) in eMMC PHY IO Control 0 Register to 0 in order for the connect
the eMMC/SDIO PHY to the controller and not use it as a MPP pin multiplexor.
So, the mvebu-pinctrl driver check specifically for the
"marvell,armada-8k-cpm-pinctrl" compatible to clear the that bit.
Issue is that compatibles in the 8040 DTSI were set to "marvell,8k-cpm-pinctrl"
for CP0 and "marvell,8k-cps-pinctrl" for the CP1.
This is obviously incorrect as the pinctrl driver does not know about these.
So fix the regression by applying correct compatibles to the DTSI.
Regression found and tested on the Puzzle M801 board.
Fixes: a0ba97e5 ("arm: armada: dts: Use a single dtsi for cp110 die description")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
Commit 0d52bab46 (mx7dsabre: Enable DM_ETH) changed these flags from 0
(aka GPIO_ACTIVE_HIGH) to GPIO_ACTIVE_LOW. It claimed to "Also sync
device tree with v5.5-rc1", but in the linux tree, these gpios have
always been GPIO_ACTIVE_HIGH ever since this node was introduced
around v4.13 (linux commit 184f39b5).
I'm guessing that the reason for the GPIO_ACTIVE_LOW was to work
around the behaviour of the soft-spi driver back then, which
effectively defaulted to spi-mode 3 and not 0. That was arguably a bug
in the soft-spi driver, which then got fixed in 0e146993bb (spi: add
support for all spi modes with soft spi), but that commit then broke
ethernet on this board.
Fix it by setting the gpios as active high, which as a bonus actually
brings us in sync with the .dts in the linux source tree.
Without this, one gets
Net: Could not get PHY for FEC0: addr 0
No ethernet found.
With this, ethernet (at least ping and tftp) works as expected from
the U-Boot shell.
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Joris Offouga <offougajoris@gmail.com>
Cc: "Christian Bräuner Sørensen" <yocto@bsorensen.net>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
After the discussion here:
https://lore.kernel.org/netdev/20210603143453.if7hgifupx5k433b@pali/
which resulted in this patch:
https://patchwork.kernel.org/project/netdevbpf/patch/20210704134325.24842-1-pali@kernel.org/
and many other discussions before it, notably:
https://patchwork.kernel.org/project/linux-arm-kernel/patch/1512016235-15909-1-git-send-email-Bhaskar.Upadhaya@nxp.com/
it became apparent that nobody really knows what "SGMII 2500" is.
Certainly, Freescale/NXP hardware engineers name this protocol
"SGMII 2500" in the reference manuals, but the PCS devices do not
support any "SGMII" specific features when operating at the speed of
2500 Mbps, no in-band autoneg and no speed change via symbol replication
. So that leaves a fixed speed of 2500 Mbps using a coding of 8b/10b
with a SERDES lane frequency of 3.125 GHz. In fact, "SGMII 2500 without
in-band autoneg and at a fixed speed" is indistinguishable from
"2500base-x without in-band autoneg", which is precisely what these NXP
devices support.
So it just appears that "SGMII 2500" is an unclear name with no clear
definition that stuck.
As such, in the Linux kernel, the drivers which use this SERDES protocol
use the 2500base-x phy-mode.
This patch converts U-Boot to use 2500base-x too, or at least, as much
as it can.
Note that I would have really liked to delete PHY_INTERFACE_MODE_SGMII_2500
completely, but the mvpp2 driver seems to even distinguish between SGMII
2500 and 2500base-X. Namely, it enables in-band autoneg for one but not
the other, and forces flow control for one but not the other. This goes
back to the idea that maybe 2500base-X is a fiber protocol and SGMII-2500
is an MII protocol (connects a MAC to a PHY such as Aquantia), but the
two are practically indistinguishable through everything except use case.
NXP devices can support both use cases through an identical configuration,
for example RX flow control can be unconditionally enabled in order to
support rate adaptation performed by an Aquantia PHY. At least I can
find no indication in online documents published by Cisco which would
point towards "SGMII-2500" being an actual standard with an actual
definition, so I cannot say "yes, NXP devices support it".
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
NXP Legal insists that the following are not fine:
- Saying "NXP Semiconductors" instead of "NXP", since the company's
registered name is "NXP"
- Putting a "(c)" sign in the copyright string
- Putting a comma in the copyright string
The only accepted copyright string format is "Copyright <year-range> NXP".
This patch changes the copyright headers in the networking files that
were sent by me, or derived from code sent by me.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
The USB peripheral controller is the DWC2 controller 1, not 0.
Update the phandle to fix UDC support on this board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
The WDT on this system should be enabled, make it so.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
We have individual SOC symbols for each keystone 2 platform. Use the
existing CONFIG_ARCH_KEYSTONE rather than CONFIG_SOC_KEYSTONE to
encompass all of the keystone families.
Signed-off-by: Tom Rini <trini@konsulko.com>
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Merge tag 'dm-pull-next-27sep21' of https://source.denx.de/u-boot/custodians/u-boot-dm into next
Various of-platdata improvements, including CONFIG_OF_REAL
Now that we have a 'positive' Kconfig option, use this instead of the
negative one, which is harder to understand.
Signed-off-by: Simon Glass <sjg@chromium.org>
The current API is outdated as it requires a devicetree pointer.
Move these functions to use the ofnode API and update this globally. Add
some tests while we are here.
Correct the call in exynos_dsim_config_parse_dt() which is obviously
wrong.
Signed-off-by: Simon Glass <sjg@chromium.org>
vexpress_ca9x4 is seemingly the only board except for qemu_arm which
is able to run U-Boot correctly, using the `-M vexpress-a9` option to
QEMU. Building for qemu_arm and running qemu-system-arm with the `-M
virt` argument has a number of downsides, most importantly that it
only supports virtio storage drivers. This significantly reduces its
usefulness in testing memory card and Flash solutions, especially when
the tested images are from a third party source.
So therefore we reintroduce the vexpress_ca9x4 board in this commit,
with the explicit goal of using it with QEMU.
A number of differences to note from the original:
* Since the board was apparently unmaintained, I have now set myself
as the maintainer.
* The board has been converted to use the driver model, which was the
reason it was removed in the first place.
* The vexpress_ca15_tc2 and vexpress_ca5x2 boards, which were removed
in the same commit, are not necessary for the QEMU use case, and
have been omitted.
* An `mmc0` alias was introduced in the dts file. The mmc is not
detected correctly without this, now that it's based on the device
tree instead of the board's init function.
* A couple of other nodes were removed because they were problematic
when trying to run the UEFI bootmgr. Once again, the primary use
case here is QEMU, and these nodes are not needed for that to work.
* Unnecessary board init code has been removed, thanks to driver model
and device tree.
* `CONFIG_OF_EMBED` has been enabled. I know this goes against
recommended practice, but there doesn't seem to be any other way to
pass the dtb to U-Boot in the QEMU scenario. Using the -dtb argument
does not work, I suppose because U-Boot doesn't use the same
mechanics as the kernel when it's booting.
* Load addresses have been changed to fit QEMU use case.
People wanting to get a more detailed, yet somewhat isolated, diff
between this and the original, can run this command:
git diff c6c26a05b89f25a06e7562f8c2071b60fd0c9eac~1 -- \
$( git diff-tree --diff-filter=A -r --name-only HEAD~1 HEAD)
(Make sure to either check out this commit first, or replace HEAD with
the commit ID of this commit)
Signed-off-by: Kristian Amlie <kristian.amlie@northern.tech>
Simplify the bootm and the spl code by using the new config
CONFIG_SUPPORT_PASSING_ATAGS.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This patch enables the use of the optimized memset(), memmove() &
memcpy() versions recently added on ARM64.
Please note that these optimized functions are now only enabled for
recent GCC versions (>= 9.4), as earlier GCC versions throw these
errors:
aarch64-linux-ar: warning: arch/arm/lib/memset-arm64.o: unsupported GNU_PROPERTY_TYPE (5) type: 0xc0000000
...
Signed-off-by: Stefan Roese <sr@denx.de>
[trini: Make this default to off as it causes problems on some platforms still]
Signed-off-by: Tom Rini <trini@konsulko.com>
The optimized memset uses the dc opcode, which causes problems when the
cache is disabled. This patch adds a check if the cache is disabled and
uses a very simple memset implementation in this case. Otherwise the
optimized version is used.
Signed-off-by: Stefan Roese <sr@denx.de>
Ported from https://github.com/ARM-software/optimized-routines
These files are included from this repository, including the latest
git commit ID:
string/aarch64/memcpy.S: afd6244a1f8d
string/aarch64/memset.S: e823e3abf5f8
string/asmdefs.h: e823e3abf5f8
Note that memmove is also handled by the memcpy function.
Please note that when adding these optimized functions as default memset
memcpy functions in U-Boot, U-Boot fails to boot on the LX2160ARDB.
After the initial ATF output, no U-Boot output is shown on the serial
console. Some exception is triggered here in the very early boot process
as some of the assembler opcodes need the caches to be enabled.
Because of this, a follow-up patch will add a check to use a simple
non-optimized memset for the "cache disabled" case.
Note:
I also integrated and tested with the Linux versions of these optimized
functions. They are similar to the ones now integrated but these ARM
versions are still a small bit faster.
Signed-off-by: Stefan Roese <sr@denx.de>
On MediaTek boards we cannot override the SYS_BOARD / SYS_CONFIG_NAME
variables from defconfig.
This is because in board/mediatek/mtXXXX/Kconfig this value was override
by default due to the if CONFIG_TARGET_MTXXXX condition.
Merge all the Kconfigs to the mach-medatek/Kconfig.
This way:
- we only define SYS_{SOC,VENDOR} once
- all board definitions are in a single place, simplifying the build logic.
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
This function is clearly architecture specific code, not board specific
code. The only difference from the previous arm arch_lmb_reserve() is the
extra reservation of 16k of memory below the stack bottom, rather than
the 4k. The common code now also uses 16k alignment. Remove this custom
implementation, as it now behaves exactly as the common code.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
Cc: Angelo Dureghello <angelo@sysam.it>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Cc: Hai Pham <hai.pham.ud@renesas.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Ye Li <ye.li@nxp.com>
According to input NXP, the 4k alignment is not always sufficient.
Currently iMX works around this problem by implementing board specific
LMB reservation, however it is likely this could also occur on other
systems. Increase the LMB reservation alignment to 16k by default.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
Cc: Angelo Dureghello <angelo@sysam.it>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Cc: Hai Pham <hai.pham.ud@renesas.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Switch arc/arm/m68k/microblaze/mips/ppc arch_lmb_reserve() to
arch_lmb_reserve_generic().
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
Cc: Angelo Dureghello <angelo@sysam.it>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Cc: Hai Pham <hai.pham.ud@renesas.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Wolfgang Denk <wd@denx.de>
The arch_lmb_reserve() is called by lib/lmb.c lmb_reserve_common() even
if CMD_BOOT{I,M,Z} is not enabled. However, the arm32/arm64 variant of
arch_lmb_reserve() is only compiled in if CMD_BOOT{I,M,Z} is enabled.
This currently does not trigger build error, because there is an empty
weak implementation of arch_lmb_reserve(), however that is not the
function that should be used on arm32/arm64.
Fix this by moving the arch_lmb_reserve() implementation into common
code and always compile it in.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
ARMv8.0 has optional crc32 instruction for crc32 calculation. The
instruction is mandatory since ARMv8.1. The crc32 calculation is
faster using the dedicated instruction, e.g. 1.4 GHz iMX8MN gives:
=> time crc32 0x50000000 0x2000000
time: 0.126 seconds # crc32 instruction
time: 0.213 seconds # software crc32
Add implementation using the compiler builtin wrapper for the crc32
instruction and enable it by default, since we don't support any
platforms which do not implement this instruction.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
[trini: Make crc32_table guarded by CONFIG_ARM64_CRC32]
Signed-off-by: Tom Rini <trini@konsulko.com>
Replace the current 2-instruction 2-step tripling code by a
corresponding single instruction leveraging ARMv8-A's "flexible second
operand as a register with optional shift". This has the added benefit
(albeit arguably negligible) of reducing the final code size.
Fix the comment as the tripled cache level is placed in x12, not x0.
Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
Improve the file's readability and conciseness by using the appropriate
Aarch64 instruction: ubfx (unsigned bitfield extract). This makes the
code easier to follow as it directly manipulates the offsets and widths
of the fields read from system registers, as they are expressed in the
Standard (ARM ARM). This has the added benefit (albeit arguably
negligible) of reducing the final code size.
Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
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Merge tag 'u-boot-at91-2022.01-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next
First set of u-boot-at91 features for the 2022.01 cycle:
This feature set includes : the support for CPU driver for arm926
(sam9x60 device); changes required for OP-TEE boot for sama5d2_xplained
and sama5d27_som1_ek boards; QSPI boot configuration for sama5d2_icp;
starting to remove old Kconfig unused symbols from config_whitelist.txt
(work will take more time); also small fixes and updates in mach, DT,
configs, etc.
The USB peripheral controller is the DWC2 controller 1, not 0.
Update the phandle to fix UDC support on this board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
The WDT on this system should be enabled, make it so.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Continue to use the "ssbl" name for GPT partition of secondary boot
stage = U-Boot for basic boot with SPL to avoid to disturb existing user.
The "fip" partition name is only used for TFA_BOOT with FIP, it is a TF-A
BL2 requirement; it the default configuration for STMicroelectronics
boards.
Fixes: b73e8bf453 ("arm: stm32mp: add defconfig for trusted boot with FIP")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Replace the number in the flexcom-mode property with the define from the
include file.
This corresponds to the approach in Linux kernel.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
The AT91 RM9200DK board was removed long time ago.
Remove existing references that were not cleaned up.
Fixes: 1c85752258 ("ARM: remove broken "at91rm9200dk" board")
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Fixed the following DTC build warning (reproducible with W=1)
arch/arm/dts/at91-sama5d2_icp.dtb: Warning (unit_address_format): /ahb/ohci@00400000: unit name should not have leading 0s
arch/arm/dts/at91-sama5d2_icp.dtb: Warning (unit_address_format): /ahb/ehci@00500000: unit name should not have leading 0s
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Alexander Dahl <ada@thorsis.com>
Reorder the nodes following the kernel rules: nodes in a range are sorted
by ascending bus address, and when referenced by phandle, are ordered
alphabetically.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Add support for sst26vf064b 64Mbit qspi-flash that is
present on sama5d2_icp board.
Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
[eugen.hristev@microchip.com: move u-boot properties to sama5d2_icp-u-boot.dtsi]
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
sama5d2_xplained DRAM detection code will be modified to use device tree
instead of hardcoded addresses. In order to prepare that, add the memory
node to at91-sama5d2_xplained.dts.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
When SYSRESET is enabled, cpu_reset function is also defined in
sysreset-uclass.c which lead to multiple definitions of this function
since reset.c is build unconditionally. Add a check in Makefile to build
this file only if SYSRESET isn't enabled.
SYSRESET can be enabled when building SYSRESET_PSCI for instance on this
platform.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Add bindings for CPU. This will allow displaying correctly the crystal,
CPU and master clock.
Reported-by: Eugen Hristev <eugen.hristev@microchip.com>
Fixes: a64862284f ("clk: at91: sam9x60: add support compatible with
CCF")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
With Device Manager firmware in an elf file form, we cannot load the FIT
image to the exact same address as any of the executable sections of the
elf file itself is located.
However, the device tree descriptions for the ARMV8 bootloader/OS
includes DDR regions only the final sections in DDR where the Device
Manager firmware is actually executing out of.
As the R5 uC is usually operating at a slower rate than an ARMv8 MPU,
by starting the Armv8 ahead of parsing the elf and copying the correct
sections to the required memories creates a race condition where the
ARMv8 could overwrite the elf image loaded from the FIT image prior to
the R5 completing parsing and putting the correct sections of elf in
the required memory locations. OR create rather obscure debug conditions
where data in the section is being modified by ARMV8 OS while the elf
copy is in progress.
To prevent all these conditions, lets make sure that the elf parse and
copy operations are completed ahead of ARMv8 being released to execute.
We will pay a penalty of elf copy time, but that is a valid tradeoff in
comparison to debug of alternate scenarios.
Signed-off-by: Nishanth Menon <nm@ti.com>
NB0 is bridge to SRAM and NB1 is bridge to DDR.
To ensure that SRAM transfers are not stalled due to delays during DDR
refreshes, SRAM traffic should be higher priority (threadmap=2) than
DDR traffic (threadmap=0).
This fixup is critical to provide deterministic access latency to
MSMC from ICSSG, it applies to all AM65 silicon revisions and is due
to incorrect reset values (has no erratum id) and statically setting
things up should be done independent of usecases and board.
This specific style of Northbridge configuration is specific only to
AM65x devices, follow-on K3 devices have different data prioritization
schemes (ASEL and the like) and hence the fixup applies purely to
AM65x.
Without this fix, ICSSG TX lock-ups due to delays in MSMC transfers in
case of SR1 devices, on SR2 devices, lockups were not observed so far
but high retry rates of ICSSG Ethernet (icssg-eth) and, thus, lower
throughput.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Andrew F. Davis <afd@ti.com>
Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Benoit Parrot <bparrot@ti.com>
[Jan: rebased, dropped used define, extended commit log]
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
[Nishanth: Provide relevant context in the commit message]
Signed-off-by: Nishanth Menon<nm@ti.com>
The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in
turn serve as inputs to other HSDIV output clocks. These clocks use
the actual value to compute the divider clock rate, and need to be
registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk
driver and data lacks the infrastructure to pass in divider flags.
Update the driver and data to account for these divider flags.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Add a note to the automatically generated clk-data and dev-data files
for j721e and j7200 to indicate that they are in fact auto-generated and
should not be hand edited.
Also adjust TI URL to use https instead of http and also add an empty
line before first header inclusion.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
divisors to generate the final FOUTPOSTDIV clock. These are in sequence
with POSTDIV2 following the POSTDIV1 clock. The current J7200 clock data
has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
opposite of the actual implementation. Fix the data by simply adjusting
the register bit-shifts.
The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0
register values, fix these as well.
Fixes: 277729eaf3 ("arm: mach-k3: Add platform data for j721e and j7200")
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
divisors to generate the final FOUTPOSTDIV clock. These are in sequence
with POSTDIV2 following the POSTDIV1 clock. The current J721E clock data
has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
opposite of the actual implementation. Fix the data by simply adjusting
the register bit-shifts.
The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0
register values, fix these as well.
Fixes: 277729eaf3 ("arm: mach-k3: Add platform data for j721e and j7200")
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Add a weak release_resources_for_core_shutdown() stub implementation
that can be overridden by actual implementation if a SoC supports that
function.
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Header file version.h does not use anything from timestamp.h. Including of
timestamp.h has side effect which cause recompiling object file at every
make run because timestamp.h changes at every run.
So remove timestamp.h from version.h and include timestamp.h in files
which needs it.
This change reduce recompilation time of final U-Boot binary when U-Boot
source files were not changed as less source files needs to be recompiled.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Add in lib/acpi/acpi_table.c and test/dm/acpi.c, rework a few others]
Signed-off-by: Tom Rini <trini@konsulko.com>
Move the XHCI PCI device base up in the virtual address space. This fixes
initialization failure observed with newer Raspberry Pi firmware, later
than 63b1922311 ("firmware: arm_loader: Update armstubs with those from
PR 117). It looks that chosing 0xff800000 as the XHCI PCI device base
conflicts with the updated ARM/VideoCore firmware.
This also requires to reduce the size of the mapped PCI device region
from 8MiB to 4MiB to fit into 32bit address space. This is still enough
for the XHCI PCI device.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenz@kernel.org>
Tested-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
At present SMBIOS tables are empty, which breaks some use-cases that
rely on that. Add some minimal information to fulfill this.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
In the cdns3 usb driver, the clock name looked for is ref. Therefore, fix
the clock-names property in usb0 instance for proper initialization of
cdns3 usb gadget driver.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
As per Device Tree Specification [1], the status parameter of nodes can
be "okay", "disabled", etc. "ok" is not a valid parameter.
U-boot Driver Model does not recognize status="ok" either and treats
the node as disabled.
[1] https://github.com/devicetree-org/devicetree-specification/releases/tag/v0.3
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Add u-boot,dm-spl tag in the pinmux device tree node, required for MMCSD1
subsystem.
Fixes: b6059ddc45 ("arm: dts: k3-am642: Add r5 specific dt support")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
USB nodes were mistakenly disabled in
commit 942853dd96 ("arm: dts: Resync BeagleBone device trees")
This commit is to fix the following issue:
starting USB...
No working controllers found
USB is stopped. Please issue 'usb start' first.
starting USB...
No working controllers found
Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0782e8572ce43f521ed6ff15e4a7ab9aa5acdc85
Fixes: 942853dd96 ("arm: dts: Resync BeagleBone device trees")
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Paul Barker <paul.barker@sancloud.com>
Since mvpp2 is using the new mdio driver and the cp110 has been
synced with the linux upstream, the mdio has to enabled in the
device tree file.
This is missing for some device tree files and therefore the
network cards do not come online.
Signed-off-by: Sven Auhagen <sven.auhagen@voleatech.de>
Reviewed-by: Stefan Roese <sr@denx.de>
SHA512_ALGO was used as a "either SHA512 or SHA384", although the
implementations of these two algorithms share a majority of code.
From a Kconfig interface perspective, it makes sense to present two
distinct options. This requires #ifdefing out the SHA512
implementation from sha512.c. The latter doesn't make any sense.
It's reasonable to say in Kconfig that SHA384 depends on SHA512, and
seems to be the more polite way to handle the selection.
Thus, automatically select SHA512 when SHA384 is enabled.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
With the exceptions of ds109, ds414, icnova-a20-swac, nokia_rx51 and
stemmy, disable ATAG support. A large number of platforms had enabled
support but never supported a kernel so old as to require it. Further,
some platforms are old enough to support both, but are well supported by
devicetree booting, and have been for a number of years. This is
because some of the ATAGs related functions have been re-used to provide
the same kind of information, but for devicetree or just generally to
inform the user. When needed still, rename these functions to
get_board_revision() instead, to avoid conflicts. In other cases, these
functions were simply unused, so drop them.
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Stefan Bosch <stefan_b@posteo.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
No iMX platforms have supported ATAG-based booting. They have however
re-used the CONFIG_SERIAL_TAG option as a way to enable support of
reading the OTP fuses and setting the serial# environment variable in
some cases. Change the warp7 support to use this symbol, use this for
updating the rest of the imx7 code, and update the imx8 conditionals.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
When booting in EFI, lib/efi_loader/efi_memory.c calls
board_get_usable_ram_top(0) which returns by default
gd->ram_base + gd->ram_size which is the top of DDR.
In case of OPTEE boot, the top of DDR is currently reserved by OPTEE,
board_get_usable_ram_top(0) must return an address outside OPTEE
reserved memory.
gd->ram_top matches this constraint as it has already been initialized
by substracting all DT reserved-memory (included OPTEE memory area).
Fixes: 92b611e8b0 ("stm32mp: correctly handle board_get_usable_ram_top(0)")
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Rename these options so that CONFIG_IS_ENABLED can be used with them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
[trini: Fixup some incorrect renames]
Signed-off-by: Tom Rini <trini@konsulko.com>
Per a request from Andre Przywara and agreed with by Peter Hoyes, the
vexpress aemv8r support wasn't quite ready to be merged, but the
discussion had moved off list. We should keep the first patch in the
series for now, but revert the rest. This reverts the following
commits:
e0bd6f31ce doc: Add documentation for the Arm vexpress board configs
30e5a449e8 arm: Use armv8_switch_to_el1 env to switch to EL1
b53bbca63b vexpress64: Add BASER_FVP vexpress board variant
2f5b7b7490 armv8: Add ARMv8 MPU configuration logic
37a757e227 armv8: Ensure EL1&0 VMSA is enabled
Signed-off-by: Tom Rini <trini@konsulko.com>
The prototype of psci_features() duplicated. Remove extra declaration.
Fixed: e21e3ffdd1 ("psci: Fix warnings when compiling with W=1")
Reported-by: Michael Scott <mike@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
For ARMv8-A, NEON is standard, so the compiler can use it even when no
special target flags are provided. For example, it can use stores from
NEON registers to zero-initialize large structures. GCC 11 decides to
do this inside the DRAM init code for the Allwinner H6.
However, GCC 11 has a bug where it generates misaligned NEON register
stores even with -mstrict-align. Since the MMU is not enabled this early
in SPL, the misaligned store causes an exception and breaks booting.
Work around this issue by restricting the compiler to using GPRs only,
not vector registers. This prevents any future surprises relating to
NEON use as well.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Use the environment variable armv8_switch_to_el1 to determine whether
to switch to EL1 at runtime. This is an alternative to the
CONFIG_ARMV8_SWITCH_TO_EL1 compile-time option.
The environment variable will be ineffective if the ARMV8_MULTIENTRY
config is used.
This is required by the Armv8r64 architecture, which must be able to
boot at S-EL1 for Linux but may need to boot at other ELs for other
systems.
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
The BASER_FVP board variant is implemented on top of the BASE_FVP board
config (which, in turn, is based on the Juno Versatile Express board
config). They all share a similar memory map - for BASER_FVP the map is
inverted from the BASE_FVP
(https://developer.arm.com/documentation/100964/1114/Base-Platform/Base---memory/BaseR-Platform-memory-map)
* Create new TARGET_VEXPRESS64_BASER_FVP target, which uses the same
board config as BASE_FVP and JUNO
* Adapt vexpress_aemv8a.h header file to support BASER_FVP (and rename
to vexpress_aemv8.h)
* Enable config to switch to EL1 for the BASER_FVP
* Create vexpress_aemv8r defconfig
* Provide an MPU memory map for the BASER_FVP
For now, only single core boot is supported.
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
[trini: Add MAINTAINERS, move BOOTCOMMAND to defconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
Armv8r64 is the first Armv8 platform that only has a PMSA at the
current exception level. The architecture supplement for Armv8r64
describes new fields in ID_AA64MMFR0_EL1 which can be used to detect
whether a VMSA or PMSA is present. These fields are RES0 on Armv8a.
Add logic to read these fields and, for the protection of the memory
used by U-Boot, initialize the MPU instead of the MMU during init, then
clear the MPU regions before transition to the next stage.
Provide a default (blank) MPU memory map, which can be overridden by
board configurations.
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
On Armv8-R, the EL1&0 memory system architecture is configurable as a
VMSA or PMSA, and resets to an "architecturally unknown" value.
Add code to armv8_switch_to_el1_m which detects whether the MSA at
EL1&0 is configurable using the id_aa64mmfr0_el1 register MSA fields.
If it is we must ensure the VMSA is enabled so that a rich OS can boot.
The MSA and MSA_FRAC fields are described in the Armv8-R architecture
profile supplement (section G1.3.7):
https://developer.arm.com/documentation/ddi0600/latest/
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
The use of ARMv8.3 pointer authentication (PAuth) is governed by fields
in HCR_EL2, which trigger a 'trap to EL2' if not enabled. The reset
value of these fields is 'architecturally unknown' so we must ensure
that the fields are enabled (to disable the traps) if we are entering
the kernel at EL1.
The APK field disables PAuth instruction traps and the API field
disables PAuth register traps
Add code to disable the traps in armv8_switch_to_el1_m. Prior to doing
so, it checks fields in the ID_AA64ISAR1_EL1 register to ensure pointer
authentication is supported by the hardware.
The runtime checks require a second temporary register, so add this to
the EL1 transition macro signature and update 2 call sites.
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
The logic in msm_generate_mac_addr() was originally taken from the LK
bootloader where the serial number is a string and must be parsed first.
However, in U-Boot msm_board_serial() returns an u32 and
msm_generate_mac_addr() has quite complicated code that will first
print it as a hex string and then immediately parse it again.
What this function actually does at the end is to put the serial number
encoded as big endian (the order used for the hex string) into the u8 *mac.
Use put_unaligned_be32() to do that with bit shifts instead of going
through the string format.
This should be slightly more efficient and cleaner but does not result
in any functional difference.
Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
At the moment U-Boot produces an empty MAC address (02:00:00:00:00:00)
if the eMMC is not used by anything in U-Boot (e.g. with
CONFIG_ENV_IS_NOWHERE=y instead of having the environment on eMMC).
This happens because then there is nothing that actually initializes
the eMMC and reads the "cid" that is later accessed.
To fix this, call mmc_init() to ensure the eMMC is initialized.
There is no functional difference if the eMMC is already initialized
since then mmc_init() will just return without doing anything.
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
A U-Boot image could be loaded and executed at a different
location than it was linked at.
For example, Aspeed takes a stable release version of U-Boot image
as the golden one for recovery purposes. When the primary storage
such as flash is corrupted, the golden image would be loaded to any
SRAM/DRAM address on demands through ethernet/UART/etc and run for
rescue.
To deal with this condition, the PIE is needed as there is only one
signed, golden image, which could be however executed at different
places.
This patch adds the PIE support for ARMv7 platform.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Enabling CONFIG_SYS_THUMB_BUILD produces a significantly smaller
U-Boot binary (250 KiB vs 320 KiB) that still seems to be fully
functional. Make use of that by default but keep it as "imply" so it
can be disabled for testing in case this causes trouble for someone.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Over the time, the "stemmy" U-Boot board was tested on several other
Samsung smartphones based on ST-Ericsson NovaThor Ux500. Convert the
documentation to reStructuredText at doc/board/ste/stemmy.rst and
make the device list complete. Also note that the board now boots
into USB Fastboot instead of just ending up at the U-Boot prompt.
The device table is mostly taken from the postmarketOS wiki article
(https://wiki.postmarketos.org/wiki/ST-Ericsson_NovaThor_U8500).
All the newly added devices were tested by Linus Walleij.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Make use of the new drivers for ARM U8500 introduced in the U-Boot
2021.10 merge window by adding basic support for USB Fastboot with
the "stemmy" board. As a first step this will always boot directly
into USB Fastboot for now with the console displayed on the screen
to make that obvious.
Samsung uses quite strange GPT partition labels on these boards,
so also add a bunch of fastboot_partition_alias_* to make this more
easy to use.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
So far there is no need for a clock driver in U-Boot because the
previous boot stage leaves all the necessary clocks on. However,
some drivers in U-Boot (e.g. arm_pl180_mmci) depend on having a clock
driver to obtain the clock frequency.
Setting up the clock drivers properly is a bit tricky on U8500,
so for now add a simple fixed-clock for the eMMC that allows obtaining
the clock frequency. This should be replaced eventually if some board
actually requires enabling some of the clocks.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Update ste-dbx5x0.dtsi, ste-ab8500.dtsi and ste-ab8505.dtsi with
the changes made in upstream Linux. They are taken from
https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git/
branch "ux500-dts-for-v5.15" (pending merge for Linux 5.15).
The only relevant change for U-Boot here is
"ARM: dts: ux500: ab8500: Link USB PHY to USB controller node" [1]
which links the USB PHY to the USB controller. This is necessary on
U-Boot because the PHY driver is implemented as part of the generic
PHY subsystem that makes use of these bindings.
[1]: https://lore.kernel.org/linux-arm-kernel/20210709182234.47232-1-stephan@gerhold.net/
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Imply the options for new drivers added for ARM U8500 during the
U-Boot 2021.10 merge window. Adding these as "imply" in the Kconfig
avoids having to add them to all the board defconfigs but still allows
disabling them if wanted.
Also select DM_USB_GADGET if DM_USB is selected because otherwise
the Ux500 MUSB glue driver does not show up in the configuration.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Move the function get_boot_device() from spl.c to cpu.c.
Make it visible, so that it may be used from other files.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
File mach/soc.h is included also in 64-bit mvebu processors, so define
Armada XP related macros only when compiling for Armada XP.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
default n/no doesn't need to be specified. It is default option anyway.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
[trini: Rework FSP_USE_UPD portion]
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_SKIP_LOWLEVEL_INIT
CONFIG_SKIP_LOWLEVEL_INIT_ONLY
In order to do this, we need to introduce SPL and TPL variants of these
options so that we can clearly disable these options only in SPL in some
cases, and both instances in other cases.
Signed-off-by: Tom Rini <trini@konsulko.com>
We move the SYS_CACHE_SHIFT_N options from arch/arm/Kconfig to
arch/Kconfig, and introduce SYS_CACHE_SHIFT_4 to provide a size of 16.
Introduce select statements for other architectures based on current
usage. For MIPS, we take the existing arch-specific symbol and migrate
to the generic symbol. This lets us remove a little bit of otherwise
unused code.
Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
Cc: Anup Patel <anup.patel@wdc.com>
Cc: Atish Patra <atish.patra@wdc.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Leo <ycliang@andestech.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
- Provide a default Kconfig value of the default script
- Largely continue to define this via the board Kconfig file
- For the boards that select a script based on defconfig rather than
TARGET, keep this within the defconfig.
Signed-off-by: Tom Rini <trini@konsulko.com>
Currently, there is no over-arching symbol for access to
arch/arm/mach-imx nor the CONFIG symbols that are common over all of
these related platforms. This new CONFIG symbol will allow us to start
down this path.
Signed-off-by: Tom Rini <trini@konsulko.com>
As this symbol can either be a fixed value or the function
get_board_ddr_clk, migration is tricky. Introduce a choice of DYNAMIC
or STATIC_DDR_CLK_FREQ. If DYNAMIC, we continue to use the board
defined get_board_ddr_clk function. If STATIC, set CONFIG_DDR_CLK_FREQ
to that value and now include/clock_legacy.h contains the function
prototype or defines get_board_ddr_clk() to that static value. Update
callers to test for DYNAMIC or STATIC.
Signed-off-by: Tom Rini <trini@konsulko.com>
Move the symbol that controls building some JEDEC SPD support functions
to Kconfig. This is required on the TI keystone 2 platforms and very
frequently (but not always) used on large number of Freescale/NXP
platforms, so use imply there.
Signed-off-by: Tom Rini <trini@konsulko.com>
Move CONFIG_DDR_32BIT/64BIT to Kconfig as a choice for Armada XP
platforms. Make 64bit the default as this mirrors the current code.
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
While the Kconfig language seems to accept either form of whitespace, we
use a space throughout the project, except in these spots.
Signed-off-by: Tom Rini <trini@konsulko.com>
Migrate CONFIG_GICV2 and CONFIG_GICV3 to Kconfig. We still have the GIC
related registers that need to be handled more cleanly but start by
moving this symbol to Kconfig.
Signed-off-by: Tom Rini <trini@konsulko.com>
- Migrate SYS_I2C_SH and related defines to Kconfig
- Remove currently unused SYS_I2C_SH related defines
- Cleanup related README section.
Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_SYS_I2C_MXC
CONFIG_SYS_I2C_MXC_I2C1
CONFIG_SYS_I2C_MXC_I2C2
CONFIG_SYS_I2C_MXC_I2C3
CONFIG_SYS_I2C_MXC_I2C4
Signed-off-by: Tom Rini <trini@konsulko.com>
The omap24xx I2C driver uses its own CONFIG namespace for common I2C
variables. Rather than convert more of them to Kconfig, rename these to
the common I2C ones and remove the entirely unused functionality. As
part of this, we make the am335x_shc platforms consistent with their
intended speed values.
Signed-off-by: Tom Rini <trini@konsulko.com>
Convert SYS_I2C_EARLY_INIT to Kconfig, and make it depend on
SPL_SYS_I2C_LEGACY. Remove the weak implementation as it's either
something that needs to exist for real, or shouldn't be called.
Signed-off-by: Tom Rini <trini@konsulko.com>
First, we convert CONFIG_SYS_I2C_LEGACY to Kconfig. Next, as you cannot
have SYS_I2C_LEGACY and DM_I2C at the same time, introduce
CONFIG_SPL_SYS_I2C_LEGACY so that we can enable the legacy option only
in SPL. Finally, for some PowerPC cases we also need
CONFIG_TPL_SYS_I2C_LEGACY support. Convert all of the existing users to
one or more symbols.
Signed-off-by: Tom Rini <trini@konsulko.com>
Looking over the current boards, there are no users of
CONFIG_MAC_ADDR_IN_EEPROM. Further, omapl138_lcdk uses
CONFIG_NET_RANDOM_ETHADDR. Drop various unused code paths.
Cc: Adam Ford <aford173@gmail.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
xilinx:
- Disable CONFIG_ARCH_FIXUP_FDT_MEMORY
- Print information about cpu via soc drivers and enable DISPLAY_CPUINFO
- Wire infrastructure for DTB_RESELECT and MULTI_DTB_FIT
zynq:
- Wire single QSPI
- Use power-source instead of io-standard properties
- Enable nor on zc770-xm012
zynqmp:
- Change handling around multi_boot()
- Setup offset for u-boot.itb in spi
- Generate run time dfu_alt_info for capsule update
- Use explicit values for enums (zynqmp_firmware.h)
- Enable RTC/SHA1/BUTTON/BUTTON_GPIO command
- Disable WDT driver by default
- Bind usb/scsi via preboot because of EFI
- DT updates/fixes
- Add soc driver
- Fix SPL SPI boot mode
versal:
- Add soc driver
sdhci:
- Update tap delay programming for zynq_sdhci driver
cmd:
- Fix RTC uclass handling in date command
- Update pwm help message
- Update reset help message
watchdog:
- Fix wwdt compilation
rtc:
- Deal with seq alias in rtc uclass
- Add zynqmp RTC driver
fdt:
- Add kernel-doc for fdt_fixup_memory_banks()
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Merge tag 'xilinx-for-v2021.10-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2021.10-rc3
xilinx:
- Disable CONFIG_ARCH_FIXUP_FDT_MEMORY
- Print information about cpu via soc drivers and enable DISPLAY_CPUINFO
- Wire infrastructure for DTB_RESELECT and MULTI_DTB_FIT
zynq:
- Wire single QSPI
- Use power-source instead of io-standard properties
- Enable nor on zc770-xm012
zynqmp:
- Change handling around multi_boot()
- Setup offset for u-boot.itb in spi
- Generate run time dfu_alt_info for capsule update
- Use explicit values for enums (zynqmp_firmware.h)
- Enable RTC/SHA1/BUTTON/BUTTON_GPIO command
- Disable WDT driver by default
- Bind usb/scsi via preboot because of EFI
- DT updates/fixes
- Add soc driver
- Fix SPL SPI boot mode
versal:
- Add soc driver
sdhci:
- Update tap delay programming for zynq_sdhci driver
cmd:
- Fix RTC uclass handling in date command
- Update pwm help message
- Update reset help message
watchdog:
- Fix wwdt compilation
rtc:
- Deal with seq alias in rtc uclass
- Add zynqmp RTC driver
fdt:
- Add kernel-doc for fdt_fixup_memory_banks()
Use TF-A instead of ATF in description. And update generic description with
removing ATF because also configurations without it are supported.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
U-Boot support board detection at run time and based on it change DT.
This feature is implemented for SOM Kria platforms which contain two
eeproms which contain information about SOM module and CC (Carrier card).
Full U-Boot starts with minimal DT file defined by
CONFIG_DEFAULT_DEVICE_TREE which is available in multi DTB fit image.
It is using default setup of board_name variable initializaed to
DEVICE_TREE which corresponds to CONFIG_DEFAULT_DEVICE_TREE option.
When DTB_RESELECT is enabled board_detection() is called. Keep it your mind
that this code is called before relocation. board_detection() is calling
xilinx_read_eeprom() which fills board_info (xilinx_board_description)
structure which are parsed in board_name_decode().
Based on DT configuration and amount of nvmemX aliases name of the board is
composed by concatenating CONFIG_SYS_BOARD "-" <board_name> "-rev"
<board_revision> "-" <cc_name> "-rev" <cc_revision>.
If CC is not present or more are available it keeps going.
When board name is composed and returned from board_name_decode() it is
assigned to board_name variable which is used by
board_fit_config_name_match() which is called via fdtdec_setup() when it
goes over config options in multi dtb FIT image.
From practical point of view multi DTB image is key point here which has to
contain configs for detected combinations. Unfortunately as of now they
have to be full DTBs and DTBOs are not supported.
That's why configuration like:
config_X {
description = "zynqmp-board-cc";
fdt = "board", "cc";
};
needs to be squashed together with:
fdtoverlay -o zynqmp-board-cc -i arch/arm/dts/zynqmp-board.dtb \
arch/arm/dts/zynqmp-cc.dtbo
and only one dtb is in fit:
config_X {
description = "zynqmp-board-cc";
fdt = "board-cc";
};
For creating multi DTBs fit image use mkimage -E, e.g.:
mkimage -E -f all.its all.dtb
When DTB_RESELECT is enabled xilinx_read_eeprom() is called before
relocation and it uses calloc for getting a buffer. Because this is dynamic
memory it is not relocated that's why xilinx_read_eeprom() is called again
as the part of board_init(). This second read with calloc buffer placed in
proper position board_late_init_xilinx() can setup u-boot variables as
before.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
When MULTI_DTB_FIT is enabled fit-dtb.blob fit image is created which
contain all DTBs listed by CONFIG_OF_LIST. And with DTB_RELESELECT there is
a need to handle it as one file with DTBs in it not as separate DTBs in
u-boot.its/itb.
That's why extend mkimage_fit_atf.sh to generate u-boot.itb correctly.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
