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f43312c974
For ARMv8-A, NEON is standard, so the compiler can use it even when no special target flags are provided. For example, it can use stores from NEON registers to zero-initialize large structures. GCC 11 decides to do this inside the DRAM init code for the Allwinner H6. However, GCC 11 has a bug where it generates misaligned NEON register stores even with -mstrict-align. Since the MMU is not enabled this early in SPL, the misaligned store causes an exception and breaks booting. Work around this issue by restricting the compiler to using GPRs only, not vector registers. This prevents any future surprises relating to NEON use as well. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Andre Przywara <andre.przywara@arm.com> |
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| .. | ||
| cpu | ||
| dts | ||
| include | ||
| lib | ||
| mach-aspeed | ||
| mach-at91 | ||
| mach-bcm283x | ||
| mach-bcmstb | ||
| mach-cortina | ||
| mach-davinci | ||
| mach-exynos | ||
| mach-highbank | ||
| mach-imx | ||
| mach-integrator | ||
| mach-ipq40xx | ||
| mach-k3 | ||
| mach-keystone | ||
| mach-kirkwood | ||
| mach-lpc32xx | ||
| mach-mediatek | ||
| mach-meson | ||
| mach-mvebu | ||
| mach-nexell | ||
| mach-octeontx | ||
| mach-octeontx2 | ||
| mach-omap2 | ||
| mach-orion5x | ||
| mach-owl | ||
| mach-qemu | ||
| mach-rmobile | ||
| mach-rockchip | ||
| mach-s5pc1xx | ||
| mach-snapdragon | ||
| mach-socfpga | ||
| mach-sti | ||
| mach-stm32 | ||
| mach-stm32mp | ||
| mach-sunxi | ||
| mach-tegra | ||
| mach-u8500 | ||
| mach-uniphier | ||
| mach-versal | ||
| mach-versatile | ||
| mach-zynq | ||
| mach-zynqmp | ||
| mach-zynqmp-r5 | ||
| thumb1/include/asm/proc-armv | ||
| config.mk | ||
| Kconfig | ||
| Kconfig.debug | ||
| Makefile | ||