Commit graph

13107 commits

Author SHA1 Message Date
Eugeniy Paltsev
fc86faf9d6 ARC: add asm/gpio.h to fix compilation error with CONFIG_CMD_GPIO
With CONFIG_CMD_GPIO compilation reports error:
-------------------------->8---------------------
common/cmd_gpio.c:13:22: fatal error: asm/gpio.h: No such file or directory
 #include <asm/gpio.h>
                      ^
-------------------------->8---------------------

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2017-12-10 21:13:05 +03:00
Marek Vasut
7387d4c234 ARM: rmobile: Add R8A77995 D3 Draak board
Add bits to support yet another board, the R8A77995 D3 Draak.
The DT file is from Linux 4.15-rc1 , commit
b35334447513c14a4dd55a67c269a743d4a4824b .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-12-09 13:36:27 +01:00
Marek Vasut
d21f08ba81 ARM: rmobile: Add R8A77970 V3M Eagle board
Add bits to support yet another board, the R8A77970 V3M Eagle.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-12-09 13:36:27 +01:00
Marek Vasut
1154541a52 ARM: rmobile: Add R8A77995 SoC
Add bits to support yet another SoC, the R8A77995 D3 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-12-09 13:36:25 +01:00
Marek Vasut
5cb19e7ad5 ARM: rmobile: Add R8A77970 SoC
Add bits to support yet another SoC, the R8A77970 V3M .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-12-09 13:36:25 +01:00
Maxime Ripard
03eb76b9a6 sunxi: Add the TBS A711 tablet
The TBS Tablet sports an LVDS display, an eMMC, an external SD, USB devices
and USB OTG.

Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-12-08 10:51:43 +01:00
Tom Rini
6c7010b779 Merge git://git.denx.de/u-boot-fsl-qoriq 2017-12-07 17:56:51 -05:00
York Sun
e421b646fc armv8: fix gd after relocation
Commit 21f4486faa ("armv8: update gd after relocate") sets x18
without checking the return value of spl_relocate_stack_gd().

Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Kever Yang <kever.yang@rock-chips.com>
CC: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-12-07 17:00:06 -05:00
Simon Glass
0b189b6ce1 Revert "sandbox: remove os_putc() and os_puts()"
While sandbox works OK without the special-case code, it does result in
console output being stored in the pre-console buffer while sandbox starts
up. If there is a crash or a problem then there is no indication of what
is going on.

For ease of debugging it seems better to revert this change.

This reverts commit 47b98ad0f6.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-12-07 15:17:00 -05:00
Udit Agarwal
30c41d2191 armv8: LS1088A_QSPI: SECURE_BOOT: Images validation
Validates PPA, MC, DPC, Bootscript, DPL and Kernel images in ESBC
phase using esbc_validate command.

Enable validation of boot.scr script prior to its execution dependent
on "secureboot" flag in environment

Add header address for PPA to be validated during ESBC phase for
LS1088A platform based on LAyerscape Chasis 3.

Moves sec_init prior to ppa_init as for validation of PPA sec must
be initialised before the PPA is initialised.

Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-12-06 14:55:17 -08:00
Ran Wang
819163c44e armv8: Workaround for USB erratua on LS1012A
This is suplement for patch which handle below errata:
A-009007, A-009008, A-008997, A-009798

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-12-06 14:55:17 -08:00
Prabhakar Kushwaha
2db53cfe96 armv8: fsl-layerscape: Add support of disabling core prefetch
Instruction prefetch feature is by default enabled during core
release. This patch add support of disabling instruction prefetch
by setting core mask in PPA. Here each core mask bit represents a
core and prefetch is disabled at the time of core release.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-12-06 14:55:17 -08:00
Jaehoon Chung
d8b385b708 arm: dts: exynos4: fix the device-tree compile warning
After updating dtc-1.4.5 version, there are too many warning.
This patch is to fix about exynos4 series.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2017-12-05 10:18:39 +09:00
Tom Rini
0c4d24823e Merge git://git.denx.de/u-boot-uniphier 2017-12-04 10:24:35 -05:00
Tom Rini
6b867dabe8 arm: Make gcc 6.0 or later a hard requirement now.
Move the warning to an error as we have been promising would happen in
this release.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-12-04 10:23:53 -05:00
Peng Fan
90351547ce armv8: mmu: fix page table mapping
To page mapping the lowest 2 bits needs to be 0x3.
If not fix this, the final lowest 3 bits for page mapping is 0x1
which is marked as reserved.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-12-04 10:23:52 -05:00
Peng Fan
082693f4f0 arm64 :show_regs: show the address before relocation
After relocation, when error happends, it is hard to track
ELR and LR with asm file objdumped from elf file.

So subtract the gd->reloc_off the reflect the compliation address.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-12-04 10:23:52 -05:00
Neil Armstrong
c7be3e5a79 ARM: arch-meson: build memory banks using reported memory from registers
As discussed at [1], the Amlogic Meson GX SoCs can embed a BL31 firmware
and a secondary BL32 firmware.
Since mid-2017, the reserved memory address of the BL31 firmware was moved
and grown for security reasons.

But mainline U-Boot and Linux has the old address and size fixed.

These SoCs have a register interface to get the two firmware reserved
memory start and sizes.

This patch adds a dynamic reservation of the memory zones in the device tree bootmem
reserved memory zone used by the kernel in early boot.
To be complete, the memory zones are also added to the EFI reserved zones.

Depends on patchset "Add support for Amlogic GXL Based SBCs" at [2].

[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-October/004860.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005410.html

Changes since v1:
- switched the #if to if(IS_ENABLED()) to compile all code paths
- renamed function to meson_board_add_reserved_memory()
- added a mem.h header with comment
- updated all boards ft_board_setup()

Changes since RFC v2:
- reduced preprocessor load
- kept Odroid-C2 static memory mapping as exception

Changes since RFC v1:
- switch to fdt rsv mem table and efi reserve memory
- replaced in_le32 by readl()

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[trini: Fix warning on khadas-vim over missing <asm/arch/mem.h>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-12-04 10:17:29 -05:00
Neil Armstrong
5ff2ee44ee arm: Add Khadas VIM support based on Meson GXL family
This adds platform code for the Khadas VIM board based on a
Meson GXL (S905X) SoC with the Meson GXL configuration.

This initial submission supports UART, MMC/SDCard and Ethernet with the
Internal RMII PHY.

The meson-gxl-s905x-khadas-vim.dts is synchronised from the linux 4.13
stable tree as of 4.13.8.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-12-04 09:59:03 -05:00
Neil Armstrong
96e7b5a174 arm: Add LibreTech CC support based on Meson GXL family
This adds platform code for the Libre Computer CC "Le Potato" board based on a
Meson GXL (S905X) SoC with the Meson GXL configuration.

This initial submission supports UART, MMC/SDCard and Ethernet with the
Internal RMII PHY.

The meson-gxl-s905x-libretech-cc.dts is synchronised from the linux 4.13
stable tree as of 4.13.8.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-12-04 09:59:03 -05:00
Neil Armstrong
6915b10331 ARM: arch-meson: add ethernet common init function
Introduce a generic common Ethernet Hardware init function
common to all Amlogic GX SoCs with support for the
Internal PHY enable for GXL SoCs.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-12-04 09:59:02 -05:00
Andre Przywara
78ad457b2d armv8: shrink exception table code
In the moment our exception entry code needs 34 instructions, so we
can't use put it directly into the table entry, which offers "only"
32 instructions there. Right now we just put an unconditional branch
there, then use a macro to place the 34 instructions *per entry* after
that. That effectivly doubles the size of our exception table, which
is quite a waste, given that we use it mostly for debugging purposes.

Since the register saving part is actually identical, let's just convert
that macro into a function, and "bl" into it directly from the exception
slot, of course after having saved at least the original LR.
This saves us about 950 bytes of code, which is quite a relief for some
tight SPLs, in particular the 64-bit Allwinner ones.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2017-12-04 09:59:02 -05:00
Dmitry Korunov
8993056fb3 add support for Raspberry Pi Zero W
Signed-off-by: Dmitry Korunov <dessel.k@gmail.com>
2017-12-04 09:59:02 -05:00
Masahiro Yamada
6ae3900a86 mtd: nand: Rename nand.h into rawnand.h
This header was renamed to rawnand.h in Linux.

The following is the corresponding commit in Linux.

  commit d4092d76a4a4e57b65910899948a83cc8646c5a5
  Author: Boris Brezillon <boris.brezillon@free-electrons.com>
  Date:   Fri Aug 4 17:29:10 2017 +0200

      mtd: nand: Rename nand.h into rawnand.h

      We are planning to share more code between different NAND based
      devices (SPI NAND, OneNAND and raw NANDs), but before doing that
      we need to move the existing include/linux/mtd/nand.h file into
      include/linux/mtd/rawnand.h so we can later create a nand.h header
      containing all common structure and function prototypes.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-04 22:00:00 +09:00
Masahiro Yamada
ac389b0749 ARM: uniphier: clean up board_init
Remove unnecessary DECLARE_GLOBAL_DATA_PTR and header includes.

<common.h> has been replaced with <linux/errno.h> and <linux/printk.h>.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-04 21:59:52 +09:00
Peter Robinson
b59670f2bd omap2: set the ethaddr as well as the usbethaddr env var to ensure static MAC
The kernel gets the ethernet MAC from the ethaddr variable, the omap boards for
devices with USB based eth adapters just set the usbethaddr which doesn't appear
to get passed to the kernel. The same Raspberry Pi code sets both ethaddr and
usbethaddr so lets do that so linux (tested 4.13 and 4.14) get a static rather
than a random MAC address, while not regressing users of usbethaddr.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
2017-12-02 18:32:58 -05:00
Icenowy Zheng
3cfecee49c sunxi: set the default CPUx frequency of H5 to 816MHz
Some H5 boards are designed to start at 1.1V CPUx voltage (e.g. Nano Pi
NEO2), which may not work properly at 1008MHz if the chip's quality is
not so good.

Lower the default CPUx frequency of H5 to 816MHz.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-12-02 21:55:25 +05:30
Philipp Tomsich
4fc495e9e2 rockchip: clk: rk3128: fix DCLK_VOP_DIV_CON_MASK
The DCLK_VOP_DIV_CON_MASK should cover only bits 8 through 15.
Fix this to remove an "integer-overflow on shifted constant" warning.

Fixes: 9246d9e ("rockchip: rk3128: add clock driver")
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-12-02 00:27:42 +01:00
Philipp Tomsich
cd401abcd5 rockchip: clk: rk3128: fix NANDC_PLL_SEL_MASK
The PLL selector field for NANDC is only 2 bits wide.
This fixes an 'int-overflow on shift' warning.

Fixes: 9246d9e ("rockchip: rk3128: add clock driver")
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-12-02 00:27:31 +01:00
Philipp Tomsich
5f104178bf rockchip: dts: rk3399-puma: add /config/sysreset-gpio property
On the RK3399-Q7, we want to trigger a full platform reset (so the
various software stacks supported don't have to deal with the same
complexities over and over again) in case that anything other than a
power-on reset occurred.

To do so, this defines the /config/sysreset-gpio property and has it
point to a GPIO that will perform a power-on reset of the entire
platform.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-11-30 22:59:54 +01:00
Philipp Tomsich
884ad05d34 rockchip: dts: rk3399-puma: add a 'tsd, usb-port-power' stringlist for USB1
USB1 is connected to the on-module USB 3.0 hub and power to the hub
(actually it's a reset signal, modeled as a fixed regulator, that will
be released) should be enabled only during the first probing of the
device to avoid the hub from entering its low-power mode (where it
tries to attach on a fixed interval, but we always miss the timeslot
when U-Boot has the controller listening).

This adds a 'tsd,usb-port-power' stringlist to enable the
infrastructure in the board-specific usb_hub_reset_devices to find and
control the fixed regulator associated with control of the USB hub.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
2017-11-30 22:55:27 +01:00
Kever Yang
fd1f80aab6 rockchip: rk3036: sdram: correct setting for pll integer mode
According to rk3036 TRM, should be set to '1' for the pll
integer mode, while the '0' means the frac mode.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30 22:55:27 +01:00
Kever Yang
731cafecc5 rockchip: rk3036: update clock driver for ddr
After the MASK MACRO update, we need to update the driver at the same time.
This is a fix to:
37943aa rockchip: rk3036: clean mask definition for cru reg

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30 22:55:27 +01:00
Kever Yang
faa75ad9e6 rockchip: rk3036: fix pll config for correct frequency
There is a fixed div-2 between PLL and clk_ddr/clk_ddrphy,
so we need to double to pll output and then ddr can work
in correct frequency.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30 22:55:27 +01:00
Kever Yang
6074cfaa8e rockchip: rk3128: add evb-rk3128 support
evb-rk3128 is an evb from Rockchip based on rk3128 SoC:
- 2 USB2.0 Host port;
- 1 HDMI port;
- 2 10/100M eth port;
- 2GB ddr;
- 16GB eMMC;
- UART to USB debug port;

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30 22:55:27 +01:00
Kever Yang
e129c480e4 rockchip: rk3128: add pinctrl driver
Add rk3128 pinctrl driver and grf/iomux structure definition.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30 22:55:26 +01:00
Kever Yang
9246d9e541 rockchip: rk3128: add clock driver
Add rk3128 clock driver and cru structure definition.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30 22:55:26 +01:00
Kever Yang
daeed1dbb5 rockchip: rk3128: add soc basic support
RK3128 is a SoC from Rockchip with quad-core Cortex-A7 CPU
and mali400 GPU. Support Nand flash, eMMC, SD card, USB 2.0 host
and device, HDMI/LVDS/MIPI display.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30 22:55:26 +01:00
Kever Yang
bbd6e6d729 rockchip: rk3128: add device tree file
Add dts binding header for rk3128, files origin from kernel.

Series-Changes: 2
- fix i2c address
- add saradc and usb phy node
- emmc using fifo mode for there is no dma support in rk3128 emmc
- add some clock id in cru.h

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30 22:55:26 +01:00
Tom Rini
9804d88630 Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-sh 2017-11-30 10:39:04 -05:00
Tom Rini
55e76b3c86 Merge git://git.denx.de/u-boot-marvell 2017-11-30 10:38:40 -05:00
Tom Rini
6ea51d2860 Merge git://git.denx.de/u-boot-x86 2017-11-30 10:37:43 -05:00
Marek Vasut
ab61e17571 ARM: rmobile: Rework the ULCB CPLD driver
Rework the ULCB CPLD driver and make it into a sysreset driver,
since that is what the ULCB CPLD driver is mostly for.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 08:54:18 +01:00
Sean Nyekjaer
926c8b2e32 arm: mvebu: enable boot from NAND
Check if we are booting from NAND and let the bootrom
continue to load the rest of the bootloader

Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-11-30 08:30:27 +01:00
Sean Nyekjaer
e83e2b3900 arm: mvebu: fix boot from UART when in fallback mode
It's the first 8 bits of the bootrom error register that
contain the boot error/fallback error code. Let's check that
and continue to boot from UART.

Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-11-30 08:29:59 +01:00
Sean Nyekjaer
348b488f5e arm: mvebu: add nand pins
Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-11-30 08:25:06 +01:00
Stefan Roese
aa7839b39c x86: lib: Implement standalone __udivdi3 etc instead of libgcc ones
This patch removes the inclusion of the libgcc math functions and
replaces them by functions coded in C, taken from the coreboot
project. This makes U-Boot building more independent from the toolchain
installed / available on the build system.

The code taken from coreboot is authored from Vadim Bendebury
<vbendeb@chromium.org> on 2014-11-28 and committed with commit
ID e63990ef [libpayload: provide basic 64bit division implementation]
(coreboot git repository located here [1]).

I modified the code so that its checkpatch clean without any
functional changes.

[1] git://github.com/coreboot/coreboot.git

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-30 13:50:17 +08:00
Anatolij Gustschin
254752494a Revert "x86: bootm: Fix FIT image booting on x86"
This reverts commit 13c531e52a.

The error message with FIT style image mentioned in the above commit
only happens when booting using FIT image containing bzImage kernel
and without setup node (setup.bin). The current documentation for
x86 FIT support in doc/uImage.FIT/x86-fit-boot.txt mentions that
kernel's setup.bin file is required for building x86 FIT images.
The above commit breaks FIT images generated as described in the
documentation. Revert it to allow booting with images built in the
documented way.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-30 13:50:17 +08:00
Heinrich Schuchardt
39670c341f x86: don't compare pointers to 0
x86_vendor_name is defined as

static const char *const x86_vendor_name[]

So its elements should not be compared to 0.

Remove superfluous paranthesis.

Problem identified with Coccinelle.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-30 13:50:17 +08:00
Anton Gerasimov
80f3425c57 x86: qemu: Move Cache-As-RAM memory from area mapped to ROM
ROM has been made read-only in qemu recently (namely commit 208fa0e4:
"pc: make 'pc.rom' readonly when machine has PCI enabled"). So this
patch restores compatibility between U-Boot and qemu.

Signed-off-by: Anton Gerasimov <anton@advancedtelematic.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: mention qemu commit title in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-30 13:50:17 +08:00
Ben Whitten
b2e01ff543 board: laird: add WB50N CPU module
This board is based on the Atmel sama5d3 eval boards.
Supporting the following features:
 - Boot from NAND Flash
 - Ethernet
 - FIT
 - SPL

Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com>
Signed-off-by: Dan Kephart <dan.kephart@lairdtech.com>
2017-11-29 22:36:59 -05:00
Ben Whitten
5aaef60077 board: laird: add WB45N CPU module
This board is based on the Atmel 9x5 eval board.
Supporting the following features:
 - Boot from NAND Flash
 - Ethernet
 - FIT
 - SPL

Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com>
Signed-off-by: Dan Kephart <dan.kephart@lairdtech.com>
2017-11-29 22:36:59 -05:00
Adam Ford
20188f519a ARM: dts: Rename logicpd-toredp-37xx-devkit in U-Boot
In U-Boot, this device tree is compatible with both the Torpedo and
SOM-LV kits.  Let's rename it in the device tree since the U-Boot code and
show a more generic OMAP3 name.  The code auto detects between the two and
loads the proper DTB file for Linux.  This would eliminate the SOM-LV showing
the name Torpedo during boot and hopefully eliminate some confusion.

Signed-off-by: Adam Ford <aford173@gmail.com>
2017-11-29 22:30:50 -05:00
Ludovic Desroches
aaa4ba930c board: atmel: add sama5d2_ptc_ek board
Add the SAMA5D2 PTC EK board and remove the SAMA5D2 PTC ENGI board
which was a prototype.

Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-11-29 22:30:50 -05:00
Ludovic Desroches
48e4851f49 ARM: at91: add sama5d2 smc header
Add a header for SAMA5D2 SMC since it's not compatible with
SAMA5D3 one.

Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
[wenyou: fix the wrong base address of the SMC register]
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-11-29 22:30:50 -05:00
Patrice Chotard
c729fb258a mach-stm32: Factorize MPU's region config for STM32 SoCs
MPU's region setup can be factorized between STM32F4/F7/H7 SoCs family
and used a common MPU's region config.

Only one exception for STM32H7 which doesn't have device area
located at 0xA000 0000.

For STM32F4, configure_clocks() need to be moved from arch_cpu_init()
to board_early_init_f().

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29 22:30:50 -05:00
Patrice Chotard
014a953c4a stm32: migrate clock structs in include/stm32_rcc.h
In order to factorize code between STM32F4 and STM32F7
migrate all structs related to RCC clocks in include/stm32_rcc.h

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29 22:30:50 -05:00
Patrice Chotard
4e97e25723 clk: clk_stm32fx: add clock configuration for mmc usage
MMC block needs 48Mhz source clock, for that we choose
to select the SAI PLL.
Update also stm32_clock_get_rate() to retrieve the MMC
clock source needed in MMC driver.

STM32F4 uses a different RCC variant than STM32F7. For STM32F4
sdmmc clocks bit are located into dckcfgr register whereas there
are located into dckcfgr2 registers on STM32F7.
In both registers, bits CK48MSEL and SDMMC1SEL are located at
the same position.

Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29 22:30:50 -05:00
Patrice Chotard
c88c6a9e03 clk: stm32fx: migrate define from rcc.h to driver
STM32F4 doesn't get rcc.h file, to avoid compilation
issue, migrate RCC related defines from rcc.h to driver
file and remove rcc.h file.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29 22:30:50 -05:00
Patrice Chotard
1555903c8d ARM: DTS: stm32: update rcc compatible for STM32F746
Align the RCC compatible string with the one used by kernel.
It will allow to use the same clock driver for STM32F4
and STM32F7 and to manage the differences between the 2 SoCs

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29 22:30:50 -05:00
Patrice Chotard
d0a768b1c8 clk: stm32f7: retrieve PWR base address from DT
PWR IP is used to enable over-drive feature in
order to reach a higher frequency.
Get its base address from DT instead of hard-coded value

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29 22:30:50 -05:00
Patrice Chotard
d3651aac46 ARM: DTS: stm32: add pwrcfg node for stm32f746
This node is needed to enable performance mode
when system frequency is set up to 200Mhz.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29 22:30:50 -05:00
Rick Chen
febcd97699 nds32: dts: Support ftsdc010 DM.
Add dts to support ftsdc010 dm flow on AG101P/AE3XX platform.

Signed-off-by: Rick Chen <rick@andestech.com>
2017-11-30 10:04:21 +08:00
Marek Vasut
02e80f0c11 ARM: rmobile: Migrate boards to RCar IIC drivers
Stop using the old ad-hoc SH I2C driver and use the new RCar IIC
driver instead. The SH I2C driver should be deprecated and removed
eventually.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 02:34:21 +01:00
Marek Vasut
d7f0b85269 ARM: rmobile: Use PRR driver on all Gen3 boards
Mark the PRR as u-boot,dm-pre-reloc in all Gen3 board DTs as it is
needed very early and turn on the CONFIG_SYSCON to allow the PRR
driver to bind as a syscon uclass.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 02:34:21 +01:00
Marek Vasut
aff151e5b2 ARM: rmobile: Convert PRR to DM and OF control
Implement DM driver for the Renesas PRR into RCar cpu info and convert
all users with DM and OF enabled to this new driver. This means all of
the boards with DM and OF enabled can fetch PRR address from DT, which
is useful on ie. V3M which has different PRR address than the rest of
Gen3 SoCs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 02:34:21 +01:00
Marek Vasut
ef5f1979ff ARM: rmobile: Zap checkboard on Gen3
The checkboard() function showing hard-coded board model for which the
U-Boot was built is superseded on Gen3 by show_board_info() displaying
the Model from device tree. Add small ifdef to stop compiling the
function into U-Boot.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 02:34:20 +01:00
Marek Vasut
f2b2bd6660 ARM: rmobile: Unify R8A7795 and R8A7796 in rmobile Makefile
Since both R8A7795 and R8A7796 now use the same files, unify the
Makefile entry to CONFIG_RCAR_GEN3.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 02:34:20 +01:00
Marek Vasut
a523af69e8 ARM: rmobile: Unify memory map for RCar Gen3
Unify the R7A7795 and R8A7796 memory maps in memmap-gen3 and, for now,
select which one is used based on which SoC is selected. Since this is
done in C code instead of statically assigned now, the decision can be
taken by PRR SoC match as well, which will be done in a subsequent patch.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 02:34:20 +01:00
Marek Vasut
262e91566f ARM: rmobile: Add PRR CPU ID macros
Replace the ad-hoc values in the PRR CPU ID table with macros,
so that users can use rmobile_get_cpu_type() can compare the
returned value with these macros to figure out on which CPU they
are running.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 02:34:20 +01:00
Marek Vasut
654f37da64 ARM: rmobile: Dispose of r8a779x.h for Gen3
These files no longer contain anything useful, so remove them.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 02:34:20 +01:00
Marek Vasut
5271dda050 ARM: rmobile: Zap Gen3 PFC tables
These old PFC tables are no longer needed as there is now a proper
PFC pinmux driver in drivers/pinctrl/renesas . Remove them .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 02:34:20 +01:00
Marek Vasut
d4bde6fa18 ARM: rmobile: Drop SDHI address macros from Gen3
Since the RCar Gen3 no longer uses the SH SDHI driver, but rather
uses the Matsushita SD driver, which loads all the properties from
device tree, these macros are no longer used, remove them.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 02:34:20 +01:00
Marek Vasut
5d1b875dfa ARM: rmobile: Fix eMMC signal voltage on ULCB
The eMMC is 1V8 device only and the signaling is always 1V8,
fix the DT for ULCB to describe the hardware correctly.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 02:34:20 +01:00
Tom Rini
b06c46de63 Xilinx changes for v2018.1
Zynq:
 - Add support for Syzygy and cc108 boards
 - Add support for mini u-boot configurations (cse)
 - dts updates
 - config/defconfig updates in connection to Kconfig changes
 - Fix psu_init handling
 
 ZynqMP:
 - SPL fixes
 - Remove slcr.c
 - Fixing r5 startup sequence
 - Add support for external pmufw
 - Add support for new ZynqMP chips
 - dts updates
 - Add support for zcu102 rev1.0 board
 
 Drivers:
 - nand: Support external timing setting and board init
 - ahci: Fix wording
 - axi_emac: Wait for bit, non processor mode, readl/write conversion
 - zynq_gem: Fix SGMII/PCS support
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Merge tag 'xilinx-for-v2018.01' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2018.1

Zynq:
- Add support for Syzygy and cc108 boards
- Add support for mini u-boot configurations (cse)
- dts updates
- config/defconfig updates in connection to Kconfig changes
- Fix psu_init handling

ZynqMP:
- SPL fixes
- Remove slcr.c
- Fixing r5 startup sequence
- Add support for external pmufw
- Add support for new ZynqMP chips
- dts updates
- Add support for zcu102 rev1.0 board

Drivers:
- nand: Support external timing setting and board init
- ahci: Fix wording
- axi_emac: Wait for bit, non processor mode, readl/write conversion
- zynq_gem: Fix SGMII/PCS support
2017-11-29 08:26:07 -05:00
Michal Simek
b8d4497f99 arm: zynq: Change Zynq/ZynqMP Kconfig description
Use more accurate description for Xilinx Zynq and ZynqMP based platforms.
With using driver model there shouldn't be a need to create separate
Kconfig config options.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:40 +01:00
Wilson Lee
310995d9f9 mtd: zynq: nand: Move board_nand_init() function to board.c
Putting board_nand_init() function inside NAND driver was not appropriate
due to it doesn't allow board vendor to customise their NAND
initialization code such as adding NAND lock/unlock code.

This commit was to move the board_nand_init() function from NAND driver
to board.c file. This allow customization of board_nand_init() function.

Signed-off-by: Wilson Lee <wilson.lee@ni.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Cc: Scott Wood <oss@buserror.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:40 +01:00
Michal Simek
30829447a4 arm: zynq: Use unsigned type with comparison with ARRAY_SIZE
Sparse is return warning about this:
arch/arm/mach-zynq/slcr.c: In function 'zynq_slcr_get_mio_pin_status':
arch/arm/mach-zynq/slcr.c:185:16: warning: comparison between signed and
unsigned integer expressions [-Wsign-compare]
  for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) {
                ^

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:39 +01:00
Michal Simek
11ea6f556c arm: zynq: Add support for EMIT_WRITE operation
Add proper support for EMIT_WRITE operation which is write only.
Do not use EMIT_MASKWRITE which is read-modify-write.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:39 +01:00
Michal Simek
f29074803c arm: zynq: Add ps7GetSiliconVersion() to ps7_spl_init
Unfortunately camelcase is coming from ps7_init* format.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:39 +01:00
Michal Simek
c0823a76df arm: zynq: Move common ps7_init* initialization to arch code
This patch is based on work done in topic board where the first address
word also storing operation which should be done. This is reducing size
of configuration data.
This patch is not breaking an option to copy default ps7_init_gpl* files
from hdf file but it is doing preparation for ps7_init* consolidation.

The patch is also marking ps7_config as weak function.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:39 +01:00
Michal Simek
f0b619ec29 arm: zynq: Move ps7_* to separate file
Extract ps7_* from spl code to prepare for extension.
And also return value.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:39 +01:00
Michal Simek
96b96adf0b arm: zynq: Add missing ps7_post_config declaration
Add missing declaration to header.

Warning log:
arch/arm/mach-zynq/spl.c:94:12: warning: symbol 'ps7_post_config' was
not declared. Should it be static?

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:38 +01:00
Tom Rini
fcc8250c2f Merge git://git.denx.de/u-boot-mips 2017-11-28 16:54:30 -05:00
Paul Burton
cc4f36435f MIPS: Break out of cache loops for unimplemented caches
If we run on a CPU which doesn't implement a particular cache then we
would previously get stuck in an infinite loop, executing a cache op on
the first "line" of the missing cache & then incrementing the address by
0. This was being avoided for the L2 caches, but not for the L1s. Fix
this by generalising the check for a zero line size & avoiding the cache
op loop when this is the case.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
2017-11-28 21:59:30 +01:00
Paul Burton
d8b326976a MIPS: Clear instruction hazards in flush_cache()
When writing code, for example during relocation, we ensure that the
icache has a coherent view of the new instructions with a call to
flush_cache(). This handles the bulk of the work to ensure the new
instructions will execute as expected, however it does not ensure that
the CPU pipeline doesn't already contain instructions taken from a stale
view of the affected memory. This could theoretically be a problem for
relocation, but in practice typically isn't because we sync caches for
enough code after the entry point of the newly written code that by the
time the CPU pipeline might possibly fetch any of it we'll have long ago
written it back & invalidated any stale icache entries. This is however
a problem for shorter regions of code.

In preparation for later patches which write shorter segments of code,
ensure any instruction hazards are cleared by flush_cache() by
introducing & using a new instruction_hazard_barrier() function which
makes use of the jr.hb instruction to clear the hazard.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
2017-11-28 21:59:30 +01:00
Paul Burton
219c2db384 MIPS: Ensure cache ops complete in cache maintenance functions
A typical use of cache maintenance functions is to force writeback of
data which a device is about to read using DMA - for example a
descriptor or command structure. Such users of cache maintenance
functions require that operations on the cache have completed before
they proceed to instruct a device to read memory. This requires that we
place a completion barrier (ie. sync instruction) between the cache ops
and whatever write informs the device to perform DMA.

Whilst strictly speaking this isn't all users of the cache maintenance
functions & we could instead place the barriers in the drivers that
require them, it would be much more invasive to do so than to just have
the barrier be the default by placing it in the cache functions
themselves. The cost is low enough that it shouldn't matter to us in any
rare cases that we use the cache functions when not performing DMA.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
2017-11-28 21:59:30 +01:00
Paul Burton
73780b012e MIPS: Drop unused PTR_COUNT_SHIFT from u-boot.lds
The u-boot.lds linker script for MIPS defines a PTR_COUNT_SHIFT macro to
2 or 3 for 32 bit or 64 bit builds respectively. This macro is never
actually used though, so remove the dead code.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2017-11-28 21:59:30 +01:00
Masahiro Yamada
b443fb4210 ARM: dts: uniphier: Sync with Linux 4.15-rc1
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:29:00 +09:00
Masahiro Yamada
10c62f41e3 ARM: uniphier: remove XIRQ pin settings
The XIRQ pins are now set up on the Linux side by the GPIO hogging.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:59 +09:00
Masahiro Yamada
eadd95a97e ARM: uniphier: remove IRQ settings
This work-around has been here in U-Boot because the AIDET and GPIO
drivers were missing in the upstream Linux.  Both are now available
in Linus' tree:
  - drivers/irqchip/irq-uniphier-aidet.c
  - drivers/gpio/gpio-uniphier.c

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:59 +09:00
Masahiro Yamada
ed3986ca30 bitops: collect BIT macros to include/linux/bitops.h
Same macros are defined in various places.  Collect them into
include/linux/bitops.h like Linux.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:57 +09:00
Shubhrajyoti Datta
fe16aa4b02 arm64: zynqmp: Enable watchdog by default
Enable watchdog in dts for zcu102.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:17 +01:00
Michal Simek
b10255f8e0 arm64: zynqmp: Add note about si5328 interrupt
Add comment about irq present on the board connected to PL.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:16 +01:00
Anurag Kumar Vulisha
8861dcf2b9 arm64: zynqmp: usb: Correct IOMMU node for making SMMU work with USB
This patch makes SMMU work by moving the iommus node under the dwc3 child
entry from parent node.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:16 +01:00
Michal Simek
a41bd46c2a arm64: zynqmp: Remove clock setting from dtsi
clock setting is handled via clk dtsi file.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:16 +01:00
Anurag Kumar Vulisha
397a08ab92 arm64: zynqmp: Uncomment snps,quirk-frame-length-adjustment flag in dwc3
This patch uncomments snps,quirk-frame-length-adjustment which has
the value to adjust the SOF/ITP generated from the controller.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:16 +01:00
Manish Narani
2ef98667b7 arm64: zynqmp: Add USB OTG interrupts support in dt
This patch adds OTG interrupt support in device tree. It will add
an extra interrupt line number dedicated to OTG events. This will
enable OTG interrupts to serve in DWC3 OTG driver.

Signed-off-by: Manish Narani <mnarani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:16 +01:00
Manish Narani
f7346ef14c arm64: zynqmp: Enabled CCI support for USB
This patch adds CCI support for USB when CCI is enabled in design.
This patch also adds 'reg' property for Xilinx USB 3.0 IP. The 'reg'
property is added in order to modify a register in that to enable
coherency in Hardware.

Also add address to unit name to avoid dtc warning

Signed-off-by: Manish Narani <mnarani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:15 +01:00
Anurag Kumar Vulisha
8e5a4e6f0e arm64: zynqmp: Add support reading SoC revision using nvmem driver in dwc3
This patch adds support for reading silicon revision using zynqmp nvmem
driver.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:15 +01:00
Michal Simek
b0c55207bf arm64: zynqmp: Move nodes which have no reg property out of bus
Nodes without reg properties shouldn't be placed in amba node.
Move them out.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:15 +01:00
Michal Simek
795ebc0e64 arm64: zynqmp: dt: Add AMS node
The AMS includes an ADC as well as on-chip sensors that can be used to
sample external voltages and monitor on-die operating conditions, such as
temperature and supply voltage levels.

Signed-off-by: Rajnikant Bhojani <rajnikant.bhojani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:15 +01:00
Manish Narani
5e3c90d238 arm64: zynqmp: sdhci: set host quirk2 for no 1.8V support for 1.0 silicon
This patch sets host quirk2 bit field for No 1.8V supported in case of
1.0 silicon. The 1.0 silicon doesn't have support for UHS-I modes. This
property will ensure the SD runs on High Speed mode.

Signed-off-by: Manish Narani <mnarani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:15 +01:00
Anurag Kumar Vulisha
0aada397b5 arm64: zynqmp: Use reset controller framework for asserting/de-asserting reset
This patch modifies the phy_zynqmp.c driver to use reset-controller
framework for asserting/de-asserting reset for High Speed modules.

Also fix documentation and dtsi.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:15 +01:00
Anurag Kumar Vulisha
98ad47bfab arm64: zynqmp: Add reset-controller support in serdes driver
This patch add the reset nodes in zynqmp.dtsi which are used by
reset-controller framework

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:15 +01:00
Michal Simek
3940bca4a8 arm64: zynqmp: Remove tx_termination_fix detection on silicon v1
Only silicon v1 requires this termination fix. With new nvmem soc
revision nvmem detection driver this can be autodetected at run time and
this flag is not needed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:15 +01:00
Nava kishore Manne
0d87c4fd9b arm64: zynqmp: Add support for zynqmp nvmem firmware driver
Add support for zynqmp nvmem firmware driver.

Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:15 +01:00
Michal Simek
ae9775f822 arm64: zynqmp: Add support for zcu102 1.0 rev
1.0 rev is the latest rev. Describe information in eeprom.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:11 +01:00
Michal Simek
9c77cb73c7 arm64: zynqmp: Update device tree for pinmux
Added pin control support in device tree for zynqmp.

Signed-off-by: Chirag Parekh <chirag.parekh@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:10 +01:00
Michal Simek
6507be7800 arm64: zynqmp: Remove local-mac-address from dtsi file
Generic dtsi file can't use the same mac address for all.
U-Boot read mac from eeprom in zcu102 case and for others random mac
address is generated.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:09 +01:00
Michal Simek
5fe03269f2 arm64: zynqmp: Use SPDX license with dc4
Just header change.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:09 +01:00
Michal Simek
b9f7edee07 arm64: zynqmp: Remove leading 0s from mtd table for spi flashes
dtc reports issues with it.
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dtb: Warning
(unit_address_format): Node
/amba/spi@ff040000/spi0_flash0@0/spi0_flash0@00000000 unit name should
not have leading 0s
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dtb: Warning
(unit_address_format): Node
/amba/spi@ff050000/spi1_flash0@0/spi1_flash0@00000000 unit name should
not have leading 0s
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning
(unit_address_format): Node
/amba/spi@ff040000/spi0_flash0@0/spi0_flash0@00000000 unit name should
not have leading 0s
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning
(unit_address_format): Node
/amba/spi@ff050000/spi1_flash0@0/spi1_flash0@00000000 unit name should
not have leading 0s

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:09 +01:00
Michal Simek
816019a8d4 arm64: zynqmp: Add missing alias for gem0 for ep108
Add missing alias for gem0 for ep108 to have proper sequence number.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:09 +01:00
Bharat Kumar Gogada
f811eca9db arm64: zynqmp: zcu102: Modifying GTR lane-0 to PCIe
- Enabling GTR lane-0 to PCIe
- Enabling PCIe node in device tree

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:09 +01:00
Chirag Parekh
d801ce553e arm64: zynqmp: Update device tree for gpio
Used defines rather than raw values for gpio configurations.

Signed-off-by: Chirag Parekh <chirag.parekh@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:09 +01:00
Michal Simek
582ee92417 arm64: zynqmp: Add revB string to compatible string
Some user space libraries reading platform compatible string and based
on that changing behavior. Mark revB board with revB string.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:09 +01:00
Michal Simek
23b34d1456 arm64: zynqmp: Use revision in dts file description
Trivial change.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:09 +01:00
Jyotheeswar Reddy Mutthareddyvari
5f9b083cdb arm64: zynqmp: PM: Specify power domains for DP related nodes
Currently DP power domain (pd_dp) is not attached to any of the DP nodes which is
causing genpd to trigger a power down request for DP domain, making all DP related
peripherals unusable. So assign power domains for all DP related nodes to enable
proper accounting of DP power domain usage.

Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:09 +01:00
Naga Sureshkumar Relli
10f2a292b1 arm64: zynqmp: disable smmu
This patch disables the smmu and also removes the mmu-masters

Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:09 +01:00
Nava kishore Manne
4d9d69856f arm64: zynqmp: rtc: Add calibration
This patch adds the calibration property with required value,
calculated based on rtc input crystal oscillator frequency (32.768Khz).

Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:08 +01:00
Anurag Kumar Vulisha
110d06b2e3 arm64: zynqmp: Add SMMU support for SATA IP
AXI master interface in CEVA AHCI controller requires two unique
Write/Read ID tags per port. This is because, ahci controller uses
different AXI ID[3:0] bits for identifying non-data transfers(like
reading descriptors, updating PRD tables, etc) and data transfers
(like sending/receiving FIS).To make SMMU work with SATA we need to
add correct SMMU stream id for SATA. SMMU stream id for SATA is
determined based on the AXI ID[1:0] as shown below

	SATA SMMU ID =  <TBU number>, 0011, 00, 00, AXI ID[1:0]
	Note: SATA in  ZynqMp uses TBU1 so TBU number = 0x1, so
	      SMMU ID = 001, 0011, 00, 00, AXI ID[1:0]

Since we have four different AXI ID[3:0] (2 for port0 & 2 for port1
as said above) we get four different SMMU stream id's combinations
for SATA. These AXI ID can be configured using PAXIC register.
In this patch we assumed the below AXI ID values

 Read ID/ Write ID for Non-Data Port0 transfers = 0
 Read ID/ Write ID for Data Port0 transfers = 1
 Read ID/ Write ID for Non-Data Port1 transfers = 2
 Read ID/ Write ID for Data Port1 transfers = 3

Based on the above values,SMMU stream ID's for SATA will be 0x4c0 &
0x4c1 for PORT0, 0x4c2 & 0x4c3 for PORT1. These values needed to be
added to iommus dts property. This patch does the same.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:08 +01:00
Rob Herring
ec2b2d4c53 arm64: dts: xilinx: fix PCI bus dtc warnings
dtc recently added PCI bus checks. Fix these warnings.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:08 +01:00
Michal Simek
0b33e0b156 arm64: zynqmp: Add missing gpio property to dtsi
All gpio controllers should contain this property.
This property is not checked by the code that's why this issue wasn't
found earlier.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:08 +01:00
Hyun Kwon
834ec8e9dd arm64: zynqmp: Update the GPU address size
The correct register size is 0x10000, otherwise
it overlaps with other register space.

Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:08 +01:00
Madhurkiran Harikrishnan
59206dd1e3 arm64: zynqmp: Add clock name for GPU
This patch will add names to the clocks used by GPU.

Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:08 +01:00
Nava kishore Manne
7689dce753 arm64: zynqmp: Label whole PL part as fpga_full region
This will simplify dt overlay structure for the whole PL.

Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:08 +01:00
Michal Simek
6db82e0956 arm64: zynqmp: Fix broken architected timer interrupt trigger
Extract from Linux mainline patch:
The ARM architected timer specification mandates that the interrupt
associated with each timer is level triggered (which corresponds to
the "counter >= comparator" condition).

A number of DTs are being remarkably creative, declaring the interrupt
to be edge triggered. A quick look at the TRM for the corresponding ARM
CPUs clearly shows that this is wrong, and I've corrected those.
For non-ARM designs (and in the absence of a publicly available TRM),
I've made them active low as well, which can't be completely wrong
as the GIC cannot disinguish between level low and level high.

The respective maintainers are of course welcome to prove me wrong.

While I was at it, I took the liberty to fix a couple of related issue,
such as some spurious affinity bits on ThunderX, and their complete
absence on ls1043a (both of which seem to be related to copy-pasting
from other DTs).

Acked-by: Duc Dang <dhdang@apm.com>
Acked-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:08 +01:00
Soren Brinkmann
19ee402d08 arm64: zynqmp: PM: Add IRQ
PM callbacks are delivered to the NS OS. Let the PM driver handle the
IRQ and retrieve callback data from the secure HW.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:08 +01:00
Jolly Shah
6a097b0d05 arm64: zynqmp: Reduced min-residency time for idle state node
Changed min-residence to 10ms(was 100 ms) for cpu-sleep-0.
Tried lower values 5ms and 8ms and it worked fine with Debug Off.
But to accommodate PM Debug On case, 10 ms is required. With this
change, low power idle state is into effect more frequently.
Measured boot time with PM debugs On and Off. No change observed
compared to 100ms value.

Signed-off-by: Jolly Shah <jollys@xilinx.com>
Acked-by: Will Wong <willw@xilinx.com>
Tested-by: Koteswararao Nayudu <kotin@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:07 +01:00
Jyotheeswar Reddy
fec547397f arm64: zynqmp: DT: Fix typo in idle-states node definition
Fixed a typo in specifying "entry-method"

Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:07 +01:00
Shubhrajyoti Datta
941f61fe80 arm64: zynqmp: Update the OPPs for cpu freq
Add operating-points-v2.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:07 +01:00
Michal Simek
585ca873ef arm64: zynqmp: Add references to cpu nodes
Add missing references to all cpu nodes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:07 +01:00
Michal Simek
40d1f8af17 arm64: zynqmp: Wire QSPI boot mode for SPL
ZynqMP qspi driver is on the way to mainline

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:02 +01:00
Michal Simek
494fffe70d arm64: zynqmp: Add support for CG/EG/EV device detection
Version string has unused fields 31:20 which can be used for exporting 9
bits from efuse IPDISABLE regs to recognize eg/cg/ev devices.

These efuse bits are setup for certain devices.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:01 +01:00
Michal Simek
011f0c4f7c arm64: zynqmp: Add SD1 level shifter mode to alternative selection
Extend Kconfig to cover SD1 level shifter mode.

Reported-by: Jason Wu <jason.hy.wu@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:01 +01:00
Siva Durga Prasad Paladugu
89401481bd arm64: zynqmp: Enable config DEFINE_TCM_OCM_MMAP if CONFIG_MP defined
This modifies default value of config DEFINE_TCM_OCM_MMAP
to yes if CONFIG_MP is defined MP supports needs OCM and TCM
part of memory map.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:01 +01:00
Michal Simek
c85a6b79d1 tools: mkimage: Extend mkimage to also include pmufw
The patch is adding external pmufw "Platform Management Unit firmware"
to boot.bin image. Boot.bin is a Xilinx format which bootrom is capable
to read and boot the system. pmufw is copied to the header data section
follows by u-boot-spl.bin. pmufw is consumed by PMU unit (Microblaze)
and SPL runs on a53-0.

This is generated command line when PMUFW_INIT_FILE is setup.

./tools/mkimage -T zynqmpimage -R ./"" -n
./"board/xilinx/zynqmp/pmufw.bin" -d spl/u-boot-spl.bin spl/boot.bin

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-28 16:08:57 +01:00
Siva Durga Prasad Paladugu
e042d36e17 arm64: zynqmp: Provide a Kconfig option to use specified memory for MMU table
This patch provides a Kconfig option to use specified
memory for MMU table using reserve_mmu platform specific
routine. Here we used TCM space for MMU table.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:08:56 +01:00
Siva Durga Prasad Paladugu
f322ad604e arm64: zynqmp: mp: Correct the R5 release sequence
This patch corrects the R5 release sequence by adding the
below steps.
1. Flush dcache to ensure that image loaded into memory.
2. Keep R5 reset just to ensure R5 in reset.
3. Disable caches before accessing TCM as with out this
   A53 can do speculative and may result in ECC failures
   if TCM's are not initialized. So, it is always better
   to disable dcaches before accessing TCM and enable back.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reported-by: John Linn <linnj@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:08:56 +01:00
Michal Simek
62e950fad3 arm64: zynqmp: Remove slcr with mio status pin detection
This code is not used on this platform and it is not called.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:08:55 +01:00
Michal Simek
dea4d2f01d arm: zynq: Add mini u-boot configuration for zynq
Add configuration files/dtses for mini u-boot configurations which runs
out of OCM.

ram top is calculated from 0 that's why +#define CONFIG_SYS_SDRAM_BASE
0xfffc0000
+#define CONFIG_SYS_SDRAM_SIZE  0x40000
was hardcoded.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-28 16:08:47 +01:00
Michal Simek
70ca290422 arm: zynq: Sort dts names
Sort names.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-28 16:08:45 +01:00
Michal Simek
bc133e80ae arm: zynq: Add board support for cc108
cc108 board is wiring uart via PL which is good platform for SPL fpga
support.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-28 16:08:40 +01:00
Michal Simek
534f7e0235 arm: zynq: Sync location of DT properties with Linux
This is trival change which only ensures the same location with Linux
kernel.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 15:53:08 +01:00
Sai Pavan Boddu
5fad1ab3d0 arm: zynq: Add device-type property for zynq ethernet phy nodes
Mention device-type = "ethernet-phy", as qemu will need this in absence
of compatible.

Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 15:53:07 +01:00
Chirag Parekh
57bcc7fd37 arm: zynq: Add SCL & SDA GPIO entries for recovery
Wire i2c pinmuxing gpio recovery for zc702.

Signed-off-by: Chirag Parekh <chiragp@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 15:53:07 +01:00
Tom McLeod
413ab5b0e1 arm: zynq: Add support for SYZYGY Hub board
Add the Zynq-based SYZYGY Hub board from Opal Kelly. The board
contains a Xilinx Zynq xc7z012s SoC, 1GB DDR3 RAM, and supports
booting from SD.

Signed-off-by: Tom McLeod <tom.mcleod@opalkelly.com>
Cc: Michal Simek <monstr@monstr.eu>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 15:53:07 +01:00
Heinrich Schuchardt
549d684d4e arm64: zynqmp: remove unnecessary logical constraint
In

if (a || b)
else if (!a)

the constraint (!a) is always true if else is reached and
can be removed.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 15:53:07 +01:00
Tom Rini
6e6cf015e7 Merge git://www.denx.de/git/u-boot-imx
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-11-27 07:22:11 -05:00
Jagan Teki
52aaddd6f4 i.MX6: engicam: Add imx6q/imx6ul boards for existing boards
Add new board names for existing board support
imx6q - icore and icore_rqs boards
imx6ul - geam6ul and isiot boards

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-11-27 10:36:40 +01:00
Jagan Teki
539b1e228f board: icore-rqs: Fix mmc get env device
As per USDHC boot eFUSE descriptions:
USDHC3 => devno 2
USDHC4 => devno 3

Linux will detect mmc0, mmc1, mmc2 based on the status
"okay" on usdhc so imx6qdl-icore-rqs.dtsi has enabled
usdhc1, usdhc3 and usdhc4.But U-Boot can detect based
on the aliases so add mmc1, mmc2 for usdhc3 and usdhc4
respectively and return the board_mmc_get_env_dev
by subtracting -1

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-11-27 10:36:40 +01:00
Jagan Teki
152038ea18 i.MX6UL: icore: Add SPL_OF_CONTROL support
Add OF_CONTROL support for SPL code.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-11-27 10:36:40 +01:00
Jagan Teki
1f6e9bd2a7 i.MX6Q: icore: Add SPL_OF_CONTROL support
Add OF_CONTROL support for SPL code.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-11-27 10:36:40 +01:00
Fabio Estevam
e2162d709f imx: Remove boolean parameter from wdog powerdown function
imx_set_wdog_powerdown() is always used to disable the power down
enable bit, so remove the boolean parameter of the function.

It is also a bit strange to write a boolean value into registers,
so this new version makes explicit that we are writing 0.

While at it, rename it to imx_wdog_disable_powerdown().

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-11-27 10:34:49 +01:00
Fabio Estevam
b42287f4c9 imx: Also clear powerdown enable bit for WDOG3 on i.MX6ULL
Clear powerdown enable bit for WDOG3 on i.MX6ULL to avoid unwanted
kernel reboots.

Suggested-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-11-27 10:34:40 +01:00
Fabio Estevam
23ecca2cd8 mx6ull: Fix WDOG3 base address
i.MX6ULL has the same WDOG3 base address as i.MX6UL, so take this
into account in the base address definition.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-11-27 10:34:31 +01:00
Philipp Tomsich
f07d76c00d rockchip: fix turning off boot-mode via Kconfig
The ROCKCHIP_BOOT_MODE_REG option defaults to a hex value, so 0 will
show as 0x0 if a default is provided and changed via Kconfig.
However, it still will show as 0, if no default is given.

Consequently, the "is set to something other than 0" test in a
Makefile is cumbersome.  Instead this check can easily be performed in
the C-code.

This removes the ifeq-check from mach-rockchip/Makefile, adds a
matching #if-check to boot_mode.c and fixes resulting link issues (if
boot_mode.o was not included due to the Makefile check) by defining a
stub function (in case the functionality is not built in) for
setup_boot_mode in boot_mode.c.

Fixes: e306779 (rockchip: make boot_mode related codes reused across all platforms)
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-26 14:57:11 +01:00
Philipp Tomsich
8c2bb589e2 rockchip: pinctrl: rk3399: add support for I2C8
The RK3399 has a total of 9 I2C controllers.  To support these, the
enum in periph.h is extended and the mapping from the IRQ numbers to
the peripheral-ids is extended to ensure that pinctrl requests are
passed through to the function configuring the I2C pins.

For I2C8, the pinctrl is implemented and tested (on a RK3399-Q7) using
communication with the FAN53555 connected on I2C8.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-11-26 00:39:08 +01:00
Alexey Brodkin
f2a226780f arc: cache: Add required NOPs after invalidation of instruction cache
As per ARC HS databook (see chapter 5.3.3.2) it is required to add
3 NOPs after each write to IC_IVIC which we do from now on.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Eugeniy Paltsev <paltsev@synopsys.com>
2017-11-24 19:38:23 +03:00
Alexey Brodkin
d764a20f2b arc: bootm: Move slave cores kick-starting under !fake
Currently slave cores will be kick-started even if we want
to dry run bootm which is not what we really want.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Eugeniy Paltsev <paltsev@synopsys.com>
2017-11-24 19:38:07 +03:00
Andy Yan
ecb103bf68 rockchip: check download key before bootup
Enter download mode if the download key pressed.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Converted printfs in boot_mode.c to debug/pr_err:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21 23:57:24 +01:00
Andy Yan
b4d23f7643 rockchip: add support for enter to bootrom download mode
Rockchip bootrom will enter download mode if it returns from
spl/tpl with a non-zero value and couldn't find a valid image
in the backup partition.
This patch provide a method to instruct the system to back to
bootrom download mode by checking the BROM_DOWNLOAD_FLAG register.
As the bootrom download function relys on some modules such as
interrupts, so we need to back to bootrom as early as possbile
before the tpl/spl code override the interrupt configurations.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21 23:57:23 +01:00
Andy Yan
e3067793c3 rockchip: make boot_mode related codes reused across all platforms
setup_boot_mode function use the same logic but different
mode register address across all the rockchip platforms,
so it's better to make this function reused across all the
platforms, and let the mode register address setting from
the config file.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21 23:57:23 +01:00
Kever Yang
6ba54058ed rockchip: sysreset: merge into one common driver
Use a common driver for all Rockchip SOC instead of one for each SoC.
Use driver_data for reg offset.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21 23:57:23 +01:00
Philipp Tomsich
4bbb05bcb5 rockchip: rk3188: move CONFIG_SPL_* entries from rk3188_common.h to Kconfig
There still are a few CONFIG_SPL_* options selected using defines from
rk3188_common.h instead of via Kconfig.  This migrates those over to
Kconfig.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21 23:57:23 +01:00
Philipp Tomsich
b82bd1f8d4 rockchip: back-to-bootrom: allow passing a cmd to the bootrom
The BROM supports forcing it to enter download-mode, if an appropriate
result/cmd-word is returned to it.  There already is a series to
support this in review, so this prepares the (newly C-version) of the
back-to-bootrom code to accept a cmd to passed on to the BROM.

All the existing call-sites are adjusted to match the changed function
signature.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
2017-11-21 23:57:22 +01:00
Philipp Tomsich
4d9253fb76 rockchip: rk3188: use boot0 hook to load up SPL in 2 steps
For the RK3188, the BROM will attempt to load up the first stage
image (SPL for the RK3188) in two steps: first 1KB to offset 0x800
in the SRAM and then the remainder to offset 0xc00 in the SRAM.
It always enters at 0x804, though.

With this changeset, the RK3188 boot removes the TPL (stub) stage and
builds a single SPL binary that utilizes the early back-to-bootrom via
the boot0-hook.

Consequently, the passing of the saved boot params via pmu->os_reg[2]
is also removed.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21 23:57:22 +01:00
Philipp Tomsich
ecfd71891a rockchip: back-to-bootrom: replace assembly-implementation with C-code
The back-to-bootrom implementation for Rockchip has always relied on
the stack-pointer being valid on entry, so there was little reason to
have this as an assembly implementation.

This provides a new C-only implementation of save_boot_params and
back_to_bootrom (relying on setjmp/longjmp) and removes the older
assembly-only implementation.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
2017-11-21 23:57:22 +01:00
Philipp Tomsich
b4806d6f1f arm: provide a PCS-compliant setjmp implementation
The previous setjmp-implementation (as a static inline function that
contained an 'asm volatile' sequence) was extremely fragile: (some
versions of) GCC optimised the set of registers.  One critical example
was the removal of 'r9' from the clobber list, if -ffixed-reg9 was
supplied.

To increase robustness and ensure PCS-compliant behaviour, the setjmp
and longjmp implementation are now in assembly and closely match what
one would expect to find in a libc implementation.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
2017-11-21 23:57:22 +01:00
Philipp Tomsich
ff143d5556 arm: mark save_boot_params_ret as a function
As no '.type' was set for save_boot_params_ret in start.S, binutils
did not track whether it was emitted as A32 or T32.  By properly
marking save_boot_params_ret as a potential function entry, we can
make sure that the compiler will insert the appropriate instructions
for branching to save_boot_params_ret both for call-sites emitted as
A32 and T32.

Reported-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
2017-11-21 23:57:22 +01:00
Philipp Tomsich
7776cc011d arm: make save_boot_params_ret prototype visible for AArch64
The save_boot_params_ret() prototype (for those of us, that have a
valid SP on entry and can implement save_boot_params() in C), was
previously only defined for !defined(CONFIG_ARM64).

This moves the declaration to a common block to ensure the prototype
is available to everyone that might need it.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
2017-11-21 23:57:22 +01:00
Philipp Tomsich
b377d22264 rockchip: boot0 hook: support early return for RK3188/RK3066-style BROM
Some Rockchip BROM versions (e.g. the RK3188 and RK3066) first read 1KB data
from NAND into SRAM and executes it. Then, following a return to bootrom, the
BROM loads additional code to SRAM (not overwriting the first block read) and
reenters at the same address as the first time.

To support booting either a TPL (on the RK3066) or SPL (on the RK3188) using
this model of having to count entries, this commit adds code to the boot0
hook to track the number of entries and handle them accordingly.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
2017-11-21 23:57:22 +01:00
Philipp Tomsich
16d761e3dd bcm281xx: boot0 hook: adjust to unified boot0 semantics
This updates the BCM281xx boot0-hook to the updated boot0 semantics
by emitting _start and the vector table before the boot0 hook (as
was the case before).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21 23:57:22 +01:00
Philipp Tomsich
62269f02ab bcm235xx: boot0 hook: adjust to unified boot0 semantics
This updates the BCM235xx boot0-hook to the updated boot0 semantics
by emitting _start and the vector table before the boot0 hook (as
was the case before).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Version-changes: 5
- ran 'whitespace-cleanup'
2017-11-21 23:57:21 +01:00
Philipp Tomsich
a002077d7d socfpga: boot0 hook: adjust to unified boot0 semantics
With the updated boot0 semantics (i.e. giving the boot0-hook control
over when and where the vector table is emitted), the boot0-hook for
the socfpga needs to be adjusted.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21 23:57:21 +01:00
Philipp Tomsich
14ad6eb264 rockchip: enable boot0-hook for all Rockchip SoCs
Rockchip SoCs bootrom design is like this:
- First 2KB or 4KB internal memory is for bootrom stack and heap;
- Then the first 4-byte suppose to be a TAG like 'RK33';
- The the following memory address end with '0004' is the first
  instruction load and running by bootrom;

Let's use the boot0 hook to reserve the first 4-byte tag for all
the Rockchip SoCs.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Commit message taken from an older patch by:]
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-11-21 23:57:21 +01:00
Kever Yang
cee7470cd8 rockchip: boot0: align to 0x20 for armv7 '_start'
The '_start' is using as vector table base address, and will write
to VBAR register, so it needs to be aligned to 0x20 for armv7.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[Updated to current code base:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21 23:57:21 +01:00
Philipp Tomsich
ef70a42f0f arm: boot0 hook: move boot0 hook before '_start'
The boot0 hook on ARM does not insert its payload before the vector
table. This is both a mismatch with thec comment above it and
contradict usage of the boot0 hook on ARM64.

To fix this (and unify the semantics for ARM and ARM64), we change the
boot0-hook semantics on ARM to match those on ARM64:
  (1) if a boot0-hook is present it is inserted at the start of
      the image
  (2) if a boot0-hook is present, emitting the ARM vector table
      (and the _start) symbol are suppressed in vectors.S and
      the boot0-hook has full control over where and when it
      wants to emit these

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21 23:57:21 +01:00
Antony Antony
6130b1f6bc sun50i: h5: Add NanoPi Neo Plus2 DT initial support
Add initial DT for NanoPi NEO Plus2 by FriendlyARM
- Allwinner quad core H5 Cortex A53 with an ARM Mali-450MP GPU
- 1 GB DDR3 RAM
- 8GB eMMC flash (Samsung KLM8G1WEPD-B031)
- micro SD card slot
- Gigabit Ethernet (external RTL8211E-VB-CG chip)
- 802.11 b/g/n WiFi, Bluetooth 4.0 (Ampak AP6212A module)
- 2x USB 2.0 host ports

Signed-off-by: Antony Antony <antony@phenome.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-11-21 19:11:57 +05:30
Antony Antony
8faac0941c arm64: sun50i-h5.dtsi : update to kernel 4.14
last Kernel commit of sun50i-h5.dtsi d86e63e1f0b7

Signed-off-by: Antony Antony <antony@phenome.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-11-21 19:11:47 +05:30
Faiz Abbas
16fa2eb951 ARM: dra7: Kconfig: Add thermal configs for dra7xx and am57xx
Configure thermal configs to remain set by default for dra7xx and am57xx
devices.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-21 08:03:39 -05:00
Faiz Abbas
12dd1e5c6a ARM: dts: OMAP5+: Add support for bandgap sensor in SPL
Mark bandgap node as uboot,dm-spl so that it can be accessed in spl

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-11-21 08:03:38 -05:00
Tom Rini
56d5a10f3a Merge git://git.denx.de/u-boot-i2c 2017-11-20 10:51:11 -05:00
Beniamino Galvani
456efb5127 odroid-c2: enable I2C
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
2017-11-20 10:11:44 +01:00
Beniamino Galvani
f8d9ca1833 i2c: add Amlogic Meson driver
Add a driver for the I2C controller available on Amlogic Meson SoCs.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
2017-11-20 10:11:34 +01:00
Fabio Estevam
74da017a49 mx6: Select MX6QDL option via Kconfig
Currently the MX6QDL option is selected via CONFIG_SYS_EXTRA_OPTIONS,
but it is better to select it directly via Kconfig.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-11-20 10:01:35 +01:00
Peter Senna Tschudin
6b0071c110 mx53: Add Board support for GE PPD
Create board support for GE PPD, based on mx53loco.

Use mx53ppd_defconfig make target to configure for this board.

Signed-off-by: Peter Senna Tschudin <peter.senna@collabora.com>
Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Nandor Han <nandor.han@ge.com>
Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2017-11-20 09:59:02 +01:00
Martyn Welch
54d8d4942f arm: mx5: Add more register definitions
Add register definitions require for video configuration.

Signed-off-by: Nandor Han <nandor.han@ge.com>
Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-11-20 09:58:31 +01:00
Martyn Welch
065a1ece7a pwm: imx: Enable PWM support on i.MX53
Add missing parts for i.MX53 PWM support

Acked-by: Nandor Han <nandor.han@ge.com>
Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2017-11-20 09:58:31 +01:00
Tom Rini
29c4992256 Merge git://git.denx.de/u-boot-dm 2017-11-19 20:35:45 -05:00
Landheer-Cieslak, Ronald
48c7f77128 Add UART base addresses for additional UARTs
UARTs 1 through 5 were missing in the code - added.
Also pick the default according to the configuration setting for the
console index.

Signed-off-by: Ronald Landheer-Cieslak <ronaldlandheercieslak@eaton.com>
2017-11-17 10:53:45 -05:00
Gan, Yau Wai
9587dee937 nios2: 10m50: Add CPU pre-relocation in device tree
Tag CPU with dm-pre-reloc to enable driver before
relocation.

Signed-off-by: Gan, Yau Wai <yau.wai.gan@intel.com>
Cc: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Marek Vasut <marex@denx.de>
2017-11-17 10:51:24 -05:00
Jorge Ramirez-Ortiz
9a16153834 configs: dragonboard410c: Save environment data on eMMC
Save the environment data at the end of the boot partition on emmc

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
2017-11-17 07:44:13 -05:00
Kever Yang
21f4486faa armv8: update gd after relocate
We need to update gd in assamble code after relocate,
this is a fix to:
adc421e arm: move gd handling outside of C code

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-17 07:44:13 -05:00
Stephen Warren
49e93875a6 arm64: support running at addr other than linked to
This is required in the case where U-Boot is typically loaded and run at
a particular address, but for some reason the RAM at that location is not
available, e.g. due to memory fragmentation loading other boot binaries or
firmware, splitting an SMP complex between various different OSs without
using e.g. the EL2 second-stage page tables to hide the memory asignments,
or due to known ECC failures.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2017-11-17 07:44:13 -05:00
Neil Armstrong
ea990816fe arm: meson: Add supplementary ethernet registers definitions
On Amlogic Meson GXL/GXM, supplementary ethernet configuration registers
were added to configure the internal RMII PHY interface.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-11-17 07:44:13 -05:00
Masahiro Yamada
d6a0c78a4e pylibfdt: compile pylibfdt only when dtoc/binman is necessary
Currently, pylibfdt is always compiled if swig is installed on your
machine.  It is really annoying because most of targets (excepts
x86, sunxi, rockchip) do not use dtoc or binman.

"checkbinman" and "checkdtoc" are wrong.  It is odd that the final
build stage checks if we have built necessary tools.  If your platform
depends on dtoc/binman, you must be able to build pylibfdt.  If swig
is not installed, it should fail immediately.

I added PYLIBFDT, DTOC, BINMAN entries to Kconfig.  They should be
property select:ed by platforms that need them.  Kbuild will descend
into scripts/dtc/pylibfdt/ only when CONFIG_PYLIBFDT is enabled.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-17 07:43:32 -05:00
Neil Armstrong
cade865a43 arm: add initial support for Amlogic P212 based on Meson GXL family
This adds platform code for the Amlogic P212 reference board based on a
Meson GXL (S905X) SoC with the Meson GXL configuration.

This initial submission only supports UART and MMC/SDCard, support for the
internal Ethernet PHY in Work In Progress.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Beniamino Galvani <b.galvani@gmail.com>
2017-11-17 07:43:32 -05:00
Neil Armstrong
4862215649 ARM: dts: Synchronize Amlogic from Linux Mainline 4.13.5
Synchronize the Amlogic ARM64 dts from mainline Linux 4.13.5

In the preparation of the support of the Amlogic P212 board,
import the corresponding meson-gxl-s905x-p212.dts file.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Beniamino Galvani <b.galvani@gmail.com>
2017-11-17 07:43:32 -05:00
Felix Brack
c07bf9bea7 am33xx: Add a function to query MPU voltage in uV
For the DM TPS65910 driver I'm working on, querying the MPU voltage
should return a value in uV. This value can then be used by the
regulator's standard function set_value to set the MPU voltage.

Signed-off-by: Felix Brack <fb@ltec.ch>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-11-17 07:43:32 -05:00
Tom Rini
35172cfee8 sandbox: Add clrbits/setbits macros
We borrow the macros for these functions from ARM and remove references
to '__raw_'.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-11-16 18:45:05 -07:00
Tom Rini
ebca2083d3 Merge git://www.denx.de/git/u-boot-marvell 2017-11-16 09:32:04 -05:00
Baruch Siach
8c1ce928f4 arm: mvebu: clearfog: update SPI flash DT description
All current ClearFog SOMs have the SPI flash populated. Enable SPI flash in
the device tree.

Add an alias to the SPI bus so that the 'sf' command can probe the flash on
bus 1.

Add the "spi-flash" compatible string to make the standard SPI flash driver
probe the device.

Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-11-16 11:45:20 +01:00
Jon Nettleton
78aa018f07 arm: mvebu: Add board_setup for xhci hardware
This fixes the USB 3.0 support for the a38x SOC.

Signed-off-by: Jon Nettleton <jon@solid-run.com>
[baruch: use fdt_addr_t]
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-11-16 11:45:20 +01:00
Prabhakar Kushwaha
f53e12d80a driver: net: fsl-mc: Use base 16 in simple_strtoul
Value provided in MC_MEM_SIZE_ENV_VAR is in hex. Use 16 as base
in simple_strtoul.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-11-15 10:53:15 -08:00
Ashish Kumar
91fded6200 armv8: ls1088aqds: Add SD boot support for ls1088qds
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-11-15 10:52:19 -08:00
Ashish Kumar
099f4093a5 armv8: ls1088ardb: Add SD boot support for ls1088
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-11-15 10:51:46 -08:00
Ashish Kumar
f65425fb46 armv8: ls1088: Enable SATA for ls1088
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-11-15 10:50:54 -08:00
Marek Vasut
2bfd43e550 ARM: rmobile: Fix eMMC signal voltage on Salvator-X/XS
The eMMC is 1V8 device only and the signaling is always 1V8,
fix the DT for Salvator-X/XS to describe the hardware correctly.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-12 16:17:31 -05:00
Tom Rini
3c674b7e87 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2017-11-09 08:11:30 -05:00
Lukasz Majewski
9c8979cdb7 imx7: Add include guards for include/asm/arch-mx7/sys_proto.h file
Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-11-09 11:32:49 +01:00
Lukasz Majewski
e895e996ab imx5: Add include guards for include/asm/arch-mx5/sys_proto.h file
Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-11-09 11:32:49 +01:00
Lukasz Majewski
90d0e38c1e imx6: Add include guards for include/asm/arch-mx6/sys_proto.h file
Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-11-09 11:32:49 +01:00
Lukasz Majewski
a3eec24ad3 imx:display5: Add support for LWN's DISPLAY5 board
This commit provides support for LWN's IMX6Q based DISPLAY5 board.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-11-09 11:32:49 +01:00
Lukasz Majewski
ec1b26973c imx6: iomux: Add generic function to set RGMII IO voltage on IMX6 SoCs
This commit provides generic function to set the RGMII/HSIC IO voltage
level on iMX6 devices.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-11-09 11:32:49 +01:00
Fabio Estevam
b2e6ad451b mx51: Select the ESDHC_A001 erratum
When a high speed card is connected to mx51evk the following error is seen:

U-Boot 2017.11-rc2 (Oct 18 2017 - 13:49:26 -0200)

CPU:   Freescale i.MX51 rev3.0 at 800 MHz
Reset cause: POR
Board: MX51EVK
DRAM:  512 MiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
*** Warning - read failed, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   FEC
Hit any key to stop autoboot:  0
=> saveenv
Saving Environment to MMC...
Writing to MMC(0)... failed

The root cause for the failure is the eSDHC-A001 erratum:

"eSDHC-A001 : Data timeout counter (SYSCTL[DTOCV]) is not reliable for
values of 0x4,0x8, and 0xC" that is listed
on some PowerArchitecture chips:
https://www.nxp.com/files-static/32bit/doc/errata/MPC8379ECE.pdf

Even though eSDHC-A001 is not documented on the i.MX51 errata document,
I have confirmed with the NXP design team that this erratum does affect
i.MX51, so fix the problem by selecting SYS_FSL_ERRATUM_ESDHC_A001
at SoC level.

The i.MX51 ts4800 board already selects this option, but it is better
to move this selection to the i.MX51 SoC level instead.

Successfully tested with a high speed SD card on a mx51evk board.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
2017-11-07 10:13:11 +01:00
Fabio Estevam
5d09c27138 mx25: Select the ESDHC_A001 erratum
When a high speed card is connected to mx25 the following error is seen:

U-Boot 2017.11-rc2-00104-gb79372a (Oct 31 2017 - 11:02:22 -0200)

CPU:   Freescale i.MX25 rev1.2 at 399 MHz
Reset cause: POR
Board: MX25PDK
I2C:   ready
DRAM:  64 MiB
No arch specific invalidate_icache_all available!
MMC:   FSL_SDHC: 0
*** Warning - read failed, using default environment
In:    serial
Out:   serial
Err:   serial
Net:   FEC
Hit any key to stop autoboot:  0
=> saveenv
Saving Environment to MMC...
Writing to MMC(0)... failed

, which prevents any usage of the SD card.

The root cause for the failure is the eSDHC-A001 erratum:

"eSDHC-A001 : Data timeout counter (SYSCTL[DTOCV]) is not reliable for
values of 0x4,0x8, and 0xC" that is listed
on some PowerArchitecture chips:
https://www.nxp.com/files-static/32bit/doc/errata/MPC8379ECE.pdf

Even though eSDHC-A001 is not documented on the i.MX25 errata document,
I have confirmed with the NXP design team that this erratum does affect
i.MX25, so fix the problem by selecting SYS_FSL_ERRATUM_ESDHC_A001
at SoC level.

Successfully tested with a high speed SD card on a mx25pdk board.

Suggested-by: Benoît Thébaudeau <benoit@wsystem.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Tested-by: Otavio Salvador <otavio@ossystems.com.br> # mx25pdk
2017-11-07 10:13:00 +01:00
Fabio Estevam
07df697e14 mx25: Move MX25 selection to Kconfig
The motivation for moving MX25 selection to Kconfig is to be
able to better handle MX25 specific errata, so that an errata option
can be selected at SoC level instead of board level.

This selection method also aligns with the way other i.MX SoCs are
selected in U-Boot.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
2017-11-07 10:12:50 +01:00
Klaus Goger
4f70039b36 rockchip: dts: rk3399: change sd-card io voltage to 3.0V
The VCC_SD and VCC_SDIO rail should only be powered up to 3.0V on RK3399
platforms.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-07 09:16:57 +01:00
Klaus Goger
366812fa26 rockchip: dts: Use defines for pin names in rk3399-puma.dtsi and rk3368-lion.dts
pinctrl/rockchip.h provides defines that map pin numbers to pin names.
Use them to make the dts more human readable.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-07 09:16:57 +01:00
Philipp Tomsich
b1e1ce2cd4 rockchip: dts: rk3399-puma: update USB configuration
This change updates the USB configuration for the RK3399-Q7 in the DTS:
 * fixes the OTG board configuration by enabling it ('okay')
 * improves the speed of 'usb start' by disabling the unused EHCI/OHCI
   controllers

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-11-07 09:16:57 +01:00
Philipp Tomsich
f2a9513168 rockchip: dts: rk3399-puma: update usbhub_enable regulator
To correctly model the usbhub_enable regulator for U-Boot, we need
to change the settings to:
 * the GPIO polarity is GPIO_ACTIVE_LOW
 * should be set to inactive (enable-active-low) when boot-on settings
   are applied
 * it can be changed at runtime (i.e. remove the always-on)

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-11-07 09:16:57 +01:00
Philipp Tomsich
df1e6212f9 rockchip: dts: rk3399-puma: fix the modelling of BIOS_DISABLE
The fixed regulator for overriding BIOS_DISABLE had been modelling
backwards (i.e. the GPIO polarity and the enable-active-low/high
property had both been inverted), causing the 'regulator' command
to always print/expect 'disabled'/'enabled' backwards.

This fixes the mix-up and models it correctly:
 * the GPIO is low-active
 * the regulator should be enabled (enable-active-high) during
   boot-on initialisation

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-11-07 09:16:56 +01:00
Chris Brandt
fc85605018 cosmetic: rmobile: renesas spelled wrong
Renesas was spelled wrong.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
2017-11-06 09:59:03 -05:00
Patrice Chotard
e36591c350 spear: fix STMicroelectronics copyright
Uniformize STMicroelectronics copyrights headers for SPEAR
related code.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-06 09:51:01 -05:00
Patrice Chotard
1537d38619 stv0991: fix STMicroelectronics copyright
Uniformize STMicroelectronics copyrights headers for STV0991
related code.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-06 09:51:01 -05:00
Patrice Chotard
3bc599c956 stm32: fix STMicroelectronics copyright
Uniformize STMicroelectronics copyrights headers for STM32
related code.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-06 09:51:01 -05:00
Patrice Chotard
fb48bc448c sti: fix STMicroelectronics copyright
Uniformize all STMicroelectronics copyrights headers for STi
related code.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-06 09:51:01 -05:00
Dongjin Kim
568197fa03 ARM: dts: exynos: fix property values of LDO15/17 for ODROID-XU3/4
Looking at the schematic, LDO15 and LDO17 are tied as a power source of a
builtin network chipset. The voltage on LDO15 is corrected to 3.3V and the
name of LDO17 is corrected to "vdd_ldo17".

Signed-off-by: Dongjin Kim <tobetter@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2017-11-06 16:59:32 +09:00
Kever Yang
36de37f5ca rockchip: rk3328: fix rockchip_get_cru api
The API for get priv pointer is wrong, fix it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-01 11:21:32 +01:00
Fabio Estevam
e1f0715f64 wandboard: Add support for the MX6QP variant
Add support for the latest MX6QP wandboard variant.

Based on Richard Hu's work from Technexion's U-Boot tree.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-10-31 11:01:38 +01:00
Tom Rini
2d5e6b4aac Merge git://git.denx.de/u-boot-video 2017-10-29 10:11:08 -04:00
Tom Rini
bb3d9ed3a9 Merge git://git.denx.de/u-boot-fsl-qoriq 2017-10-27 21:59:10 -04:00
Sumit Garg
9b3f40ad09 armv8: sec_firmware: Add support for loadables in FIT
Enable support for loadables in SEC firmware FIT image. Currently
support is added for single loadable image.

Brief description of implementation:
  Add two more address pointers (loadable_h, loadable_l) as arguments to
  sec_firmware_init() api.
  Create new api: sec_firmware_checks_copy_loadable() to check if loadables
  node is present in SEC firmware FIT image. If present, verify loadable
  image and copies it to secure DDR memory.
  Populate address pointers with secure DDR memory addresses where loadable
  is copied.

Example use-case could be trusted OS (tee.bin) as loadables node in SEC
firmware FIT image.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:47:14 -07:00
Sumit Garg
9781d9ff5f armv8: layerscape: Allocate 66 MB DDR for secure memory
Change DDR allocated for secure memory from 2 MB to 66 MB. This
additional 64 MB secure memory is required for trusted OS running
in Trusted Execution Environment using ARMv8 TrustZone.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:47:14 -07:00
Ran Wang
d4c746c7b1 armv8: ls1088ardb: Enable USB command RDB qspi-boot
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:47:06 -07:00
Ran Wang
4417e83495 arm64: layerscape: Move CONFIG_HAS_FSL_XHCI_USB to Kconfig
Use Kconfig to select QE-HDLC and USB pin-mux.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:43:57 -07:00
Tom Rini
ae6ac0a06e Merge git://git.denx.de/u-boot-x86 2017-10-27 08:50:16 -04:00
Vasily Khoruzhick
1d7eef3f3f sunxi: video: add LCD support to DE2 driver
Extend DE2 driver with LCD support. Tested on Pinebook which is based
on A64 and has ANX6345 eDP bridge with eDP panel connected to it.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
[agust: rebased v5 on u-boot-video/master]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-10-27 09:44:48 +02:00
Vasily Khoruzhick
79f285ddeb sunxi: video: split out PLL configuration code
It will be reused in new DM LCD driver.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2017-10-27 09:39:19 +02:00
Bin Meng
411898dc87 x86: acpi: Put sleepstates.asl to the common place
The supported sleep states are generic on Intel processors. Move the
ASL definition to the common place.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
Bin Meng
dc80d3b230 x86: fsp: graphics: Add some notes about the graphics info hob
On some platforms (eg: Braswell), the FSP will not produce the
graphics info HOB unless you plug some cables to the display
interface (eg: HDMI) on the board. Add such notes in the FSP
video driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
Bin Meng
4c9f4c5ee4 x86: braswell: cherryhill: Update dts for SPI lock down
Intel Braswell FSP requires SPI controller settings to be locked down,
let's do this in the chrryhill.dts and remove previous Kconfig option.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
Bin Meng
fb2c53091f Revert "x86: fsp: Configure SPI opcode registers before SPI is locked down"
This reverts commit 1e6ebee667.

It's not appropriate to call the Intel SPI driver specific stuff in
the FSP codes. We may add a simple DTS property "intel,spi-lock-down"
and let the Intel SPI driver call these stuff instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-27 15:13:47 +08:00
Bin Meng
aa9c5956c9 x86: Fix ACPI resume dependency to MRC cache
In an S3 resume path, MRC cache is mandatory. Enforce the dependency
in the Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
Bin Meng
3a856473fd env: x86: braswell: Set ENV_IS_IN_SPI_FLASH as default
Imply does not work for a Kconfig choice. Update ENV_IS_IN_SPI_FLASH
to be the default one for Intel Braswell.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
Bin Meng
4a5a7fcac2 x86: braswell: Fix unexpected crash during Linux kernel boot
It was observed that when booting Linux kernel on Intel Cherry Hill
board, unexpected crash happens quite randomly. Sometimes kernel
just oops, while sometimes kernel throws MCE errors and hangs:

  mce: [Hardware Error]: Machine check events logged
  mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 4: c400000000010151
  mce: [Hardware Error]: TSC 0 ADDR 130f3f2c0
  mce: [Hardware Error]: PROCESSOR 0:406c3 TIME 1508160686 SOCKET 0 APIC 0 microcode 363

This looks like a hardware error per mcelog. After debugging, it
seems turning off turbo mode on the processor does not expose this
behavior, although U-Boot runs OK with turbo mode on. Suspect it is
related to an errata of Braswell processor.

To fix this, remove the Braswell cpu driver which does the turbo
mode configuration, and switch to use the generic cpu-x86 driver.
Also there is a configuration option in the FSP that turns on the
turbo mode and that has been turned off too.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
Icenowy Zheng
be5b96f0e4 sunxi: setup simplefb for Allwinner DE2
As the support of EFI boot on Allwinner H3 is broken, we still need to
use simplefb to pass the framebuffer to Linux.

Add code to setup simplefb for Allwinner DE2 driver.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-26 11:57:14 +02:00
Icenowy Zheng
f6bdddc92b video: add an option for video simplefb via DT
Add an option to indicate that the video driver should setup a SimpleFB
node that passes the video framebuffer initialized by U-Boot to the
operating system kernel.

Currently only the Allwinner DE driver uses this option, and the
definition of this option in the sunxi-common.h config header is
converted to an imply of this option from CONFIG_VIDEO_SUNXI.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-26 11:53:39 +02:00
Icenowy Zheng
401a3ca0fb sunxi: change the DE1 video option to CONFIG_VIDEO_SUNXI
The sunxi DE1 video option used to be CONFIG_VIDEO, which has the same
name as the "Enable legacy video support" option in
drivers/video/Kconfig.

Change the option name to CONFIG_VIDEO_SUNXI, which is really used by
Makefile under drivers/video/sunxi/, and defined in sunxi-common.h
when CONFIG_VIDEO is selected before this change. Now CONFIG_VIDEO_SUNXI
selects CONFIG_VIDEO and the usages of CONFIG_VIDEO in sunxi Kconfig and
config headers are all converted to use CONFIG_VIDEO_SUNXI.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2017-10-26 11:48:49 +02:00