rockchip: sysreset: merge into one common driver

Use a common driver for all Rockchip SOC instead of one for each SoC.
Use driver_data for reg offset.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
Kever Yang 2017-11-03 15:16:12 +08:00 committed by Philipp Tomsich
parent 95d363cc30
commit 6ba54058ed
10 changed files with 52 additions and 397 deletions

View file

@ -39,6 +39,11 @@ static inline int rk_pll_id(enum rk_clk_id clk_id)
return clk_id - 1;
}
struct sysreset_reg {
unsigned int glb_srst_fst_value;
unsigned int glb_srst_snd_value;
};
/**
* clk_get_divisor() - Calculate the required clock divisior
*

View file

@ -1,45 +0,0 @@
/*
* (C) Copyright 2015 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <sysreset.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3036.h>
#include <asm/arch/hardware.h>
#include <linux/err.h>
int rk3036_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
struct rk3036_cru *cru = rockchip_get_cru();
if (IS_ERR(cru))
return PTR_ERR(cru);
switch (type) {
case SYSRESET_WARM:
writel(0xeca8, &cru->cru_glb_srst_snd_value);
break;
case SYSRESET_COLD:
writel(0xfdb9, &cru->cru_glb_srst_fst_value);
break;
default:
return -EPROTONOSUPPORT;
}
return -EINPROGRESS;
}
static struct sysreset_ops rk3036_sysreset = {
.request = rk3036_sysreset_request,
};
U_BOOT_DRIVER(sysreset_rk3036) = {
.name = "rk3036_sysreset",
.id = UCLASS_SYSRESET,
.ops = &rk3036_sysreset,
};

View file

@ -1,62 +0,0 @@
/*
* (C) Copyright 2015 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <syscon.h>
#include <sysreset.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3188.h>
#include <asm/arch/grf_rk3188.h>
#include <asm/arch/hardware.h>
#include <linux/err.h>
int rk3188_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
struct rk3188_cru *cru = rockchip_get_cru();
struct rk3188_grf *grf;
if (IS_ERR(cru))
return PTR_ERR(cru);
switch (type) {
case SYSRESET_WARM:
grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
if (IS_ERR(grf))
return -EPROTONOSUPPORT;
/*
* warm-reset keeps the remap value,
* so make sure it's disabled.
*/
rk_clrsetreg(&grf->soc_con0,
NOC_REMAP_MASK << NOC_REMAP_SHIFT,
0 << NOC_REMAP_SHIFT);
rk_clrreg(&cru->cru_mode_con, 0xffff);
writel(0xeca8, &cru->cru_glb_srst_snd_value);
break;
case SYSRESET_COLD:
rk_clrreg(&cru->cru_mode_con, 0xffff);
writel(0xfdb9, &cru->cru_glb_srst_fst_value);
break;
default:
return -EPROTONOSUPPORT;
}
return -EINPROGRESS;
}
static struct sysreset_ops rk3188_sysreset = {
.request = rk3188_sysreset_request,
};
U_BOOT_DRIVER(sysreset_rk3188) = {
.name = "rk3188_sysreset",
.id = UCLASS_SYSRESET,
.ops = &rk3188_sysreset,
};

View file

@ -1,45 +0,0 @@
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <sysreset.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk322x.h>
#include <asm/arch/hardware.h>
#include <linux/err.h>
int rk322x_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
struct rk322x_cru *cru = rockchip_get_cru();
if (IS_ERR(cru))
return PTR_ERR(cru);
switch (type) {
case SYSRESET_WARM:
writel(0xeca8, &cru->cru_glb_srst_snd_value);
break;
case SYSRESET_COLD:
writel(0xfdb9, &cru->cru_glb_srst_fst_value);
break;
default:
return -EPROTONOSUPPORT;
}
return -EINPROGRESS;
}
static struct sysreset_ops rk322x_sysreset = {
.request = rk322x_sysreset_request,
};
U_BOOT_DRIVER(sysreset_rk322x) = {
.name = "rk322x_sysreset",
.id = UCLASS_SYSRESET,
.ops = &rk322x_sysreset,
};

View file

@ -1,47 +0,0 @@
/*
* (C) Copyright 2015 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <sysreset.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3288.h>
#include <asm/arch/hardware.h>
#include <linux/err.h>
int rk3288_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
struct rk3288_cru *cru = rockchip_get_cru();
if (IS_ERR(cru))
return PTR_ERR(cru);
switch (type) {
case SYSRESET_WARM:
rk_clrreg(&cru->cru_mode_con, 0xffff);
writel(0xeca8, &cru->cru_glb_srst_snd_value);
break;
case SYSRESET_COLD:
rk_clrreg(&cru->cru_mode_con, 0xffff);
writel(0xfdb9, &cru->cru_glb_srst_fst_value);
break;
default:
return -EPROTONOSUPPORT;
}
return -EINPROGRESS;
}
static struct sysreset_ops rk3288_sysreset = {
.request = rk3288_sysreset_request,
};
U_BOOT_DRIVER(sysreset_rk3288) = {
.name = "rk3288_sysreset",
.id = UCLASS_SYSRESET,
.ops = &rk3288_sysreset,
};

View file

@ -1,45 +0,0 @@
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <sysreset.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3328.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
#include <linux/err.h>
int rk3328_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
struct rk3328_cru *cru = rockchip_get_cru();
if (IS_ERR(cru))
return PTR_ERR(cru);
switch (type) {
case SYSRESET_WARM:
writel(0xeca8, &cru->glb_srst_snd_value);
break;
case SYSRESET_COLD:
writel(0xfdb9, &cru->glb_srst_fst_value);
break;
default:
return -EPROTONOSUPPORT;
}
return -EINPROGRESS;
}
static struct sysreset_ops rk3328_sysreset = {
.request = rk3328_sysreset_request,
};
U_BOOT_DRIVER(sysreset_rk3328) = {
.name = "rk3328_sysreset",
.id = UCLASS_SYSRESET,
.ops = &rk3328_sysreset,
};

View file

@ -1,62 +0,0 @@
/*
* (C) Copyright Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <sysreset.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3368.h>
#include <asm/arch/hardware.h>
#include <linux/err.h>
static void rk3368_pll_enter_slow_mode(struct rk3368_cru *cru)
{
struct rk3368_pll *pll;
int i;
for (i = 0; i < 6; i++) {
pll = &cru->pll[i];
rk_clrreg(&pll->con3, PLL_MODE_MASK);
}
}
static int rk3368_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
struct rk3368_cru *cru = rockchip_get_cru();
if (IS_ERR(cru))
return PTR_ERR(cru);
switch (type) {
case SYSRESET_WARM:
rk3368_pll_enter_slow_mode(cru);
rk_clrsetreg(&cru->glb_rst_con, PMU_GLB_SRST_CTRL_MASK,
PMU_RST_BY_SND_GLB_SRST << PMU_GLB_SRST_CTRL_SHIFT);
writel(0xeca8, &cru->glb_srst_snd_val);
break;
case SYSRESET_COLD:
rk3368_pll_enter_slow_mode(cru);
rk_clrsetreg(&cru->glb_rst_con, PMU_GLB_SRST_CTRL_MASK,
PMU_RST_BY_FST_GLB_SRST << PMU_GLB_SRST_CTRL_SHIFT);
writel(0xfdb9, &cru->glb_srst_fst_val);
break;
default:
return -EPROTONOSUPPORT;
}
return -EINPROGRESS;
}
static struct sysreset_ops rk3368_sysreset = {
.request = rk3368_sysreset_request,
};
U_BOOT_DRIVER(sysreset_rk3368) = {
.name = "rk3368_sysreset",
.id = UCLASS_SYSRESET,
.ops = &rk3368_sysreset,
};

View file

@ -1,45 +0,0 @@
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <sysreset.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3399.h>
#include <asm/arch/hardware.h>
#include <linux/err.h>
int rk3399_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
struct rk3399_cru *cru = rockchip_get_cru();
if (IS_ERR(cru))
return PTR_ERR(cru);
switch (type) {
case SYSRESET_WARM:
writel(0xeca8, &cru->glb_srst_snd_value);
break;
case SYSRESET_COLD:
writel(0xfdb9, &cru->glb_srst_fst_value);
break;
default:
return -EPROTONOSUPPORT;
}
return -EINPROGRESS;
}
static struct sysreset_ops rk3399_sysreset = {
.request = rk3399_sysreset_request,
};
U_BOOT_DRIVER(sysreset_rk3399) = {
.name = "rk3399_sysreset",
.id = UCLASS_SYSRESET,
.ops = &rk3399_sysreset,
};

View file

@ -0,0 +1,47 @@
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <sysreset.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3328.h>
#include <asm/arch/hardware.h>
#include <linux/err.h>
int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
struct sysreset_reg *offset = dev_get_priv(dev);
unsigned long cru_base = (unsigned long)rockchip_get_cru();
if (IS_ERR_VALUE(cru_base))
return (int)cru_base;
switch (type) {
case SYSRESET_WARM:
writel(0xeca8, cru_base + offset->glb_srst_snd_value);
break;
case SYSRESET_COLD:
writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
break;
default:
return -EPROTONOSUPPORT;
}
return -EINPROGRESS;
}
static struct sysreset_ops rockchip_sysreset = {
.request = rockchip_sysreset_request,
};
U_BOOT_DRIVER(sysreset_rockchip) = {
.name = "rockchip_sysreset",
.id = UCLASS_SYSRESET,
.ops = &rockchip_sysreset,
};

View file

@ -1,46 +0,0 @@
/*
* (C) Copyright 2015 Rockchip Electronics Co., Ltd
* Author: Andy Yan <andy.yan@rock-chips.com>
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <sysreset.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rv1108.h>
#include <asm/arch/hardware.h>
#include <linux/err.h>
int rv1108_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
struct rv1108_cru *cru = rockchip_get_cru();
if (IS_ERR(cru))
return PTR_ERR(cru);
switch (type) {
case SYSRESET_WARM:
writel(0xeca8, &cru->glb_srst_snd_val);
break;
case SYSRESET_COLD:
writel(0xfdb9, &cru->glb_srst_fst_val);
break;
default:
return -EPROTONOSUPPORT;
}
return -EINPROGRESS;
}
static struct sysreset_ops rv1108_sysreset = {
.request = rv1108_sysreset_request,
};
U_BOOT_DRIVER(sysreset_rv1108) = {
.name = "rv1108_sysreset",
.id = UCLASS_SYSRESET,
.ops = &rv1108_sysreset,
};