mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
rockchip: sysreset: merge into one common driver
Use a common driver for all Rockchip SOC instead of one for each SoC. Use driver_data for reg offset. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
parent
95d363cc30
commit
6ba54058ed
10 changed files with 52 additions and 397 deletions
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@ -39,6 +39,11 @@ static inline int rk_pll_id(enum rk_clk_id clk_id)
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return clk_id - 1;
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}
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struct sysreset_reg {
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unsigned int glb_srst_fst_value;
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unsigned int glb_srst_snd_value;
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};
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/**
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* clk_get_divisor() - Calculate the required clock divisior
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*
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@ -1,45 +0,0 @@
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/*
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* (C) Copyright 2015 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <sysreset.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rk3036.h>
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#include <asm/arch/hardware.h>
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#include <linux/err.h>
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int rk3036_sysreset_request(struct udevice *dev, enum sysreset_t type)
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{
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struct rk3036_cru *cru = rockchip_get_cru();
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if (IS_ERR(cru))
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return PTR_ERR(cru);
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switch (type) {
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case SYSRESET_WARM:
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writel(0xeca8, &cru->cru_glb_srst_snd_value);
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break;
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case SYSRESET_COLD:
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writel(0xfdb9, &cru->cru_glb_srst_fst_value);
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break;
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default:
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return -EPROTONOSUPPORT;
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}
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return -EINPROGRESS;
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}
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static struct sysreset_ops rk3036_sysreset = {
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.request = rk3036_sysreset_request,
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};
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U_BOOT_DRIVER(sysreset_rk3036) = {
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.name = "rk3036_sysreset",
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.id = UCLASS_SYSRESET,
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.ops = &rk3036_sysreset,
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};
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@ -1,62 +0,0 @@
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/*
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* (C) Copyright 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <syscon.h>
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#include <sysreset.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rk3188.h>
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#include <asm/arch/grf_rk3188.h>
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#include <asm/arch/hardware.h>
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#include <linux/err.h>
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int rk3188_sysreset_request(struct udevice *dev, enum sysreset_t type)
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{
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struct rk3188_cru *cru = rockchip_get_cru();
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struct rk3188_grf *grf;
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if (IS_ERR(cru))
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return PTR_ERR(cru);
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switch (type) {
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case SYSRESET_WARM:
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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if (IS_ERR(grf))
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return -EPROTONOSUPPORT;
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/*
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* warm-reset keeps the remap value,
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* so make sure it's disabled.
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*/
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rk_clrsetreg(&grf->soc_con0,
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NOC_REMAP_MASK << NOC_REMAP_SHIFT,
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0 << NOC_REMAP_SHIFT);
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rk_clrreg(&cru->cru_mode_con, 0xffff);
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writel(0xeca8, &cru->cru_glb_srst_snd_value);
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break;
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case SYSRESET_COLD:
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rk_clrreg(&cru->cru_mode_con, 0xffff);
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writel(0xfdb9, &cru->cru_glb_srst_fst_value);
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break;
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default:
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return -EPROTONOSUPPORT;
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}
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return -EINPROGRESS;
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}
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static struct sysreset_ops rk3188_sysreset = {
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.request = rk3188_sysreset_request,
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};
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U_BOOT_DRIVER(sysreset_rk3188) = {
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.name = "rk3188_sysreset",
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.id = UCLASS_SYSRESET,
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.ops = &rk3188_sysreset,
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};
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@ -1,45 +0,0 @@
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <sysreset.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rk322x.h>
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#include <asm/arch/hardware.h>
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#include <linux/err.h>
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int rk322x_sysreset_request(struct udevice *dev, enum sysreset_t type)
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{
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struct rk322x_cru *cru = rockchip_get_cru();
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if (IS_ERR(cru))
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return PTR_ERR(cru);
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switch (type) {
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case SYSRESET_WARM:
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writel(0xeca8, &cru->cru_glb_srst_snd_value);
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break;
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case SYSRESET_COLD:
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writel(0xfdb9, &cru->cru_glb_srst_fst_value);
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break;
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default:
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return -EPROTONOSUPPORT;
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}
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return -EINPROGRESS;
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}
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static struct sysreset_ops rk322x_sysreset = {
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.request = rk322x_sysreset_request,
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};
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U_BOOT_DRIVER(sysreset_rk322x) = {
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.name = "rk322x_sysreset",
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.id = UCLASS_SYSRESET,
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.ops = &rk322x_sysreset,
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};
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@ -1,47 +0,0 @@
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/*
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* (C) Copyright 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <sysreset.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rk3288.h>
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#include <asm/arch/hardware.h>
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#include <linux/err.h>
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int rk3288_sysreset_request(struct udevice *dev, enum sysreset_t type)
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{
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struct rk3288_cru *cru = rockchip_get_cru();
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if (IS_ERR(cru))
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return PTR_ERR(cru);
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switch (type) {
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case SYSRESET_WARM:
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rk_clrreg(&cru->cru_mode_con, 0xffff);
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writel(0xeca8, &cru->cru_glb_srst_snd_value);
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break;
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case SYSRESET_COLD:
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rk_clrreg(&cru->cru_mode_con, 0xffff);
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writel(0xfdb9, &cru->cru_glb_srst_fst_value);
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break;
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default:
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return -EPROTONOSUPPORT;
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}
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return -EINPROGRESS;
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}
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static struct sysreset_ops rk3288_sysreset = {
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.request = rk3288_sysreset_request,
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};
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U_BOOT_DRIVER(sysreset_rk3288) = {
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.name = "rk3288_sysreset",
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.id = UCLASS_SYSRESET,
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.ops = &rk3288_sysreset,
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};
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@ -1,45 +0,0 @@
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <sysreset.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rk3328.h>
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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#include <linux/err.h>
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int rk3328_sysreset_request(struct udevice *dev, enum sysreset_t type)
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{
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struct rk3328_cru *cru = rockchip_get_cru();
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if (IS_ERR(cru))
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return PTR_ERR(cru);
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switch (type) {
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case SYSRESET_WARM:
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writel(0xeca8, &cru->glb_srst_snd_value);
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break;
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case SYSRESET_COLD:
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writel(0xfdb9, &cru->glb_srst_fst_value);
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break;
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default:
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return -EPROTONOSUPPORT;
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}
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return -EINPROGRESS;
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}
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static struct sysreset_ops rk3328_sysreset = {
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.request = rk3328_sysreset_request,
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};
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U_BOOT_DRIVER(sysreset_rk3328) = {
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.name = "rk3328_sysreset",
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.id = UCLASS_SYSRESET,
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.ops = &rk3328_sysreset,
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};
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@ -1,62 +0,0 @@
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/*
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* (C) Copyright Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <sysreset.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rk3368.h>
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#include <asm/arch/hardware.h>
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#include <linux/err.h>
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static void rk3368_pll_enter_slow_mode(struct rk3368_cru *cru)
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{
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struct rk3368_pll *pll;
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int i;
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for (i = 0; i < 6; i++) {
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pll = &cru->pll[i];
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rk_clrreg(&pll->con3, PLL_MODE_MASK);
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}
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}
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static int rk3368_sysreset_request(struct udevice *dev, enum sysreset_t type)
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{
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struct rk3368_cru *cru = rockchip_get_cru();
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if (IS_ERR(cru))
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return PTR_ERR(cru);
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switch (type) {
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case SYSRESET_WARM:
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rk3368_pll_enter_slow_mode(cru);
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rk_clrsetreg(&cru->glb_rst_con, PMU_GLB_SRST_CTRL_MASK,
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PMU_RST_BY_SND_GLB_SRST << PMU_GLB_SRST_CTRL_SHIFT);
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writel(0xeca8, &cru->glb_srst_snd_val);
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break;
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case SYSRESET_COLD:
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rk3368_pll_enter_slow_mode(cru);
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rk_clrsetreg(&cru->glb_rst_con, PMU_GLB_SRST_CTRL_MASK,
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PMU_RST_BY_FST_GLB_SRST << PMU_GLB_SRST_CTRL_SHIFT);
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writel(0xfdb9, &cru->glb_srst_fst_val);
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break;
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default:
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return -EPROTONOSUPPORT;
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}
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return -EINPROGRESS;
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}
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static struct sysreset_ops rk3368_sysreset = {
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.request = rk3368_sysreset_request,
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};
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U_BOOT_DRIVER(sysreset_rk3368) = {
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.name = "rk3368_sysreset",
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.id = UCLASS_SYSRESET,
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.ops = &rk3368_sysreset,
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};
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@ -1,45 +0,0 @@
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <sysreset.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rk3399.h>
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#include <asm/arch/hardware.h>
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#include <linux/err.h>
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int rk3399_sysreset_request(struct udevice *dev, enum sysreset_t type)
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{
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struct rk3399_cru *cru = rockchip_get_cru();
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if (IS_ERR(cru))
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return PTR_ERR(cru);
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switch (type) {
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case SYSRESET_WARM:
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writel(0xeca8, &cru->glb_srst_snd_value);
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break;
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case SYSRESET_COLD:
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writel(0xfdb9, &cru->glb_srst_fst_value);
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break;
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default:
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return -EPROTONOSUPPORT;
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}
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return -EINPROGRESS;
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}
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static struct sysreset_ops rk3399_sysreset = {
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.request = rk3399_sysreset_request,
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};
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U_BOOT_DRIVER(sysreset_rk3399) = {
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.name = "rk3399_sysreset",
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.id = UCLASS_SYSRESET,
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.ops = &rk3399_sysreset,
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};
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47
drivers/sysreset/sysreset_rockchip.c
Normal file
47
drivers/sysreset/sysreset_rockchip.c
Normal file
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <sysreset.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rk3328.h>
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#include <asm/arch/hardware.h>
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#include <linux/err.h>
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int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type)
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{
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struct sysreset_reg *offset = dev_get_priv(dev);
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unsigned long cru_base = (unsigned long)rockchip_get_cru();
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if (IS_ERR_VALUE(cru_base))
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return (int)cru_base;
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switch (type) {
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case SYSRESET_WARM:
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writel(0xeca8, cru_base + offset->glb_srst_snd_value);
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break;
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case SYSRESET_COLD:
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writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
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break;
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default:
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return -EPROTONOSUPPORT;
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}
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return -EINPROGRESS;
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}
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static struct sysreset_ops rockchip_sysreset = {
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.request = rockchip_sysreset_request,
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};
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U_BOOT_DRIVER(sysreset_rockchip) = {
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.name = "rockchip_sysreset",
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.id = UCLASS_SYSRESET,
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.ops = &rockchip_sysreset,
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};
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@ -1,46 +0,0 @@
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/*
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* (C) Copyright 2015 Rockchip Electronics Co., Ltd
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* Author: Andy Yan <andy.yan@rock-chips.com>
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <sysreset.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rv1108.h>
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#include <asm/arch/hardware.h>
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#include <linux/err.h>
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int rv1108_sysreset_request(struct udevice *dev, enum sysreset_t type)
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{
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struct rv1108_cru *cru = rockchip_get_cru();
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if (IS_ERR(cru))
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return PTR_ERR(cru);
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switch (type) {
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case SYSRESET_WARM:
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writel(0xeca8, &cru->glb_srst_snd_val);
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break;
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case SYSRESET_COLD:
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writel(0xfdb9, &cru->glb_srst_fst_val);
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break;
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default:
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return -EPROTONOSUPPORT;
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}
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return -EINPROGRESS;
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}
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static struct sysreset_ops rv1108_sysreset = {
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.request = rv1108_sysreset_request,
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};
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U_BOOT_DRIVER(sysreset_rv1108) = {
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.name = "rv1108_sysreset",
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.id = UCLASS_SYSRESET,
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.ops = &rv1108_sysreset,
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};
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