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Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-sh

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This commit is contained in:
Tom Rini 2017-11-30 10:39:04 -05:00
commit 9804d88630
43 changed files with 785 additions and 12845 deletions
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1
MAINTAINERS
View file

@ -133,6 +133,7 @@ F: arch/arm/include/asm/arch-pxa/
ARM RENESAS RMOBILE/R-CAR
M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
M: Marek Vasut <marek.vasut+renesas@gmail.com>
S: Maintained
T: git git://git.denx.de/u-boot-sh.git
F: arch/arm/mach-rmobile/

1
arch/arm/dts/r8a7795.dtsi
View file

@ -394,6 +394,7 @@
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
u-boot,dm-pre-reloc;
};
sysc: system-controller@e6180000 {

1
arch/arm/dts/r8a7796.dtsi
View file

@ -377,6 +377,7 @@
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
u-boot,dm-pre-reloc;
};
sysc: system-controller@e6180000 {

15
arch/arm/dts/ulcb.dtsi
View file

@ -24,6 +24,15 @@
stdout-path = "serial0:115200n8";
};
cpld {
compatible = "renesas,ulcb-cpld";
status = "okay";
gpio-sck = <&gpio6 8 0>;
gpio-mosi = <&gpio6 7 0>;
gpio-miso = <&gpio6 10 0>;
gpio-sstbz = <&gpio2 3 0>;
};
audio_clkout: audio-clkout {
/*
* This is same as <&rcar_sound 0>
@ -190,6 +199,10 @@
};
};
&i2c_dvfs {
status = "okay";
};
&ohci1 {
status = "okay";
};
@ -247,7 +260,7 @@
sdhi2_pins: sd2 {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <3300>;
power-source = <1800>;
};
sdhi2_pins_uhs: sd2_uhs {

3
arch/arm/mach-rmobile/Makefile
View file

@ -16,7 +16,6 @@ obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o
obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7792.o
obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o
obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o
obj-$(CONFIG_R8A7795) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7795.o memmap-r8a7795.o
obj-$(CONFIG_R8A7796) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7796.o memmap-r8a7796.o
obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o

2
arch/arm/mach-rmobile/board.c
View file

@ -8,8 +8,10 @@
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#ifndef CONFIG_RCAR_GEN3
int checkboard(void)
{
printf("Board: %s\n", sysinfo.board_string);
return 0;
}
#endif

61
arch/arm/mach-rmobile/cpu_info-rcar.c
View file

@ -8,19 +8,20 @@
#include <common.h>
#include <asm/io.h>
#define PRR 0xFF000044
#define PRR_MASK 0x7fff
#define R8A7796_REV_1_0 0x5200
#define R8A7796_REV_1_1 0x5210
static u32 rmobile_get_prr(void);
u32 rmobile_get_cpu_type(void)
{
return (readl(PRR) & 0x00007F00) >> 8;
return (rmobile_get_prr() & 0x00007F00) >> 8;
}
u32 rmobile_get_cpu_rev_integer(void)
{
const u32 prr = readl(PRR);
const u32 prr = rmobile_get_prr();
if ((prr & PRR_MASK) == R8A7796_REV_1_1)
return 1;
@ -30,10 +31,62 @@ u32 rmobile_get_cpu_rev_integer(void)
u32 rmobile_get_cpu_rev_fraction(void)
{
const u32 prr = readl(PRR);
const u32 prr = rmobile_get_prr();
if ((prr & PRR_MASK) == R8A7796_REV_1_1)
return 1;
else
return prr & 0x0000000F;
}
#if !CONFIG_IS_ENABLED(DM) || !CONFIG_IS_ENABLED(SYSCON)
static u32 rmobile_get_prr(void)
{
/*
* On RCar/RMobile Gen2 and older systems, the PRR is always
* located at the address below. On newer systems, the PRR
* may be located at different address, but that information
* is obtained from DT. This code will be removed when all
* of the older systems get converted to DM and OF control.
*/
return readl(0xFF000044);
}
#else
#include <dm.h>
#include <syscon.h>
#include <regmap.h>
struct renesas_prr_priv {
fdt_addr_t regs;
};
enum {
PRR_RCAR,
};
static u32 rmobile_get_prr(void)
{
struct regmap *map;
map = syscon_get_regmap_by_driver_data(PRR_RCAR);
if (!map) {
printf("PRR regmap failed!\n");
hang();
}
return readl(map->base);
}
static const struct udevice_id renesas_prr_ids[] = {
{ .compatible = "renesas,prr", .data = PRR_RCAR },
{ }
};
U_BOOT_DRIVER(renesas_prr) = {
.name = "renesas_prr",
.id = UCLASS_SYSCON,
.of_match = renesas_prr_ids,
.flags = DM_FLAG_PRE_RELOC,
};
#endif

21
arch/arm/mach-rmobile/cpu_info.c
View file

@ -18,6 +18,9 @@ int arch_cpu_init(void)
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
#if defined(CONFIG_RCAR_GEN3)
rcar_gen3_memmap_fixup();
#endif
dcache_enable();
}
#endif
@ -49,15 +52,15 @@ static const struct {
u16 cpu_type;
u8 cpu_name[10];
} rmobile_cpuinfo[] = {
{ 0x37, "SH73A0" },
{ 0x40, "R8A7740" },
{ 0x45, "R8A7790" },
{ 0x47, "R8A7791" },
{ 0x4A, "R8A7792" },
{ 0x4B, "R8A7793" },
{ 0x4C, "R8A7794" },
{ 0x4F, "R8A7795" },
{ 0x52, "R8A7796" },
{ RMOBILE_CPU_TYPE_SH73A0, "SH73A0" },
{ RMOBILE_CPU_TYPE_R8A7740, "R8A7740" },
{ RMOBILE_CPU_TYPE_R8A7790, "R8A7790" },
{ RMOBILE_CPU_TYPE_R8A7791, "R8A7791" },
{ RMOBILE_CPU_TYPE_R8A7792, "R8A7792" },
{ RMOBILE_CPU_TYPE_R8A7793, "R8A7793" },
{ RMOBILE_CPU_TYPE_R8A7794, "R8A7794" },
{ RMOBILE_CPU_TYPE_R8A7795, "R8A7795" },
{ RMOBILE_CPU_TYPE_R8A7796, "R8A7796" },
{ 0x0, "CPU" },
};

6
arch/arm/mach-rmobile/include/mach/gpio.h
View file

@ -22,12 +22,6 @@ void r8a7793_pinmux_init(void);
#elif defined(CONFIG_R8A7794)
#include "r8a7794-gpio.h"
void r8a7794_pinmux_init(void);
#elif defined(CONFIG_R8A7795)
#include "r8a7795-gpio.h"
void r8a7795_pinmux_init(void);
#elif defined(CONFIG_R8A7796)
#include "r8a7796-gpio.h"
void r8a7796_pinmux_init(void);
#endif
#endif /* __ASM_ARCH_GPIO_H */

1016
arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h
View file

File diff suppressed because it is too large Load diff

36
arch/arm/mach-rmobile/include/mach/r8a7795.h
View file

@ -1,36 +0,0 @@
/*
* arch/arm/mach-rmobile/include/mach/r8a7795.h
* This file defines registers and value for r8a7795.
*
* Copyright (C) 2015 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_R8A7795_H
#define __ASM_ARCH_R8A7795_H
#include "rcar-gen3-base.h"
/* Module stop control/status register bits */
#define MSTP0_BITS 0x00640800
#define MSTP1_BITS 0xF3EE9390
#define MSTP2_BITS 0x340FAFDC
#define MSTP3_BITS 0xD80C7CDF
#define MSTP4_BITS 0x80000184
#define MSTP5_BITS 0x40BFFF46
#define MSTP6_BITS 0xE5FBEECF
#define MSTP7_BITS 0x39FFFF0E
#define MSTP8_BITS 0x01F19FF4
#define MSTP9_BITS 0xFFDFFFFF
#define MSTP10_BITS 0xFFFEFFE0
#define MSTP11_BITS 0x00000000
/* SDHI */
#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000
#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000
#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 /* either MMC0 */
#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 /* either MMC1 */
#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4
#endif /* __ASM_ARCH_R8A7795_H */

1084
arch/arm/mach-rmobile/include/mach/r8a7796-gpio.h
View file

File diff suppressed because it is too large Load diff

36
arch/arm/mach-rmobile/include/mach/r8a7796.h
View file

@ -1,36 +0,0 @@
/*
* arch/arm/include/asm/arch-rcar_gen3/r8a7796.h
* This file defines registers and value for r8a7796.
*
* Copyright (C) 2016 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_R8A7796_H
#define __ASM_ARCH_R8A7796_H
#include "rcar-gen3-base.h"
/* Module stop control/status register bits */
#define MSTP0_BITS 0x00200000
#define MSTP1_BITS 0xFFFFFFFF
#define MSTP2_BITS 0x340E2FDC
#define MSTP3_BITS 0xFFFFFFDF
#define MSTP4_BITS 0x80000184
#define MSTP5_BITS 0xC3FFFFFF
#define MSTP6_BITS 0xFFFFFFFF
#define MSTP7_BITS 0xFFFFFFFF
#define MSTP8_BITS 0x01F1FFF7
#define MSTP9_BITS 0xFFFFFFFE
#define MSTP10_BITS 0xFFFEFFE0
#define MSTP11_BITS 0x000000B7
/* SDHI */
#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000
#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000
#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 /* either MMC0 */
#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 /* either MMC1 */
#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4
#endif /* __ASM_ARCH_R8A7796_H */

6
arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h
View file

@ -68,12 +68,6 @@
#define SMSTPCR10 0xE6150998
#define SMSTPCR11 0xE615099C
/* SDHI */
#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000
#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000
#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000
#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000
/* PFC */
#define PFC_PUEN5 0xE6060414
#define PUEN_SSI_SDATA4 BIT(17)

18
arch/arm/mach-rmobile/include/mach/rmobile.h
View file

@ -16,19 +16,29 @@
#include <asm/arch/r8a7793.h>
#elif defined(CONFIG_R8A7794)
#include <asm/arch/r8a7794.h>
#elif defined(CONFIG_R8A7795)
#include <asm/arch/r8a7795.h>
#elif defined(CONFIG_R8A7796)
#include <asm/arch/r8a7796.h>
#elif defined(CONFIG_RCAR_GEN3)
#include <asm/arch/rcar-gen3-base.h>
#else
#error "SOC Name not defined"
#endif
#endif /* CONFIG_ARCH_RMOBILE */
/* PRR CPU IDs */
#define RMOBILE_CPU_TYPE_SH73A0 0x37
#define RMOBILE_CPU_TYPE_R8A7740 0x40
#define RMOBILE_CPU_TYPE_R8A7790 0x45
#define RMOBILE_CPU_TYPE_R8A7791 0x47
#define RMOBILE_CPU_TYPE_R8A7792 0x4A
#define RMOBILE_CPU_TYPE_R8A7793 0x4B
#define RMOBILE_CPU_TYPE_R8A7794 0x4C
#define RMOBILE_CPU_TYPE_R8A7795 0x4F
#define RMOBILE_CPU_TYPE_R8A7796 0x52
#ifndef __ASSEMBLY__
u32 rmobile_get_cpu_type(void);
u32 rmobile_get_cpu_rev_integer(void);
u32 rmobile_get_cpu_rev_fraction(void);
void rcar_gen3_memmap_fixup(void);
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_RMOBILE_H */

66
arch/arm/mach-rmobile/memmap-gen3.c Normal file
View file

@ -0,0 +1,66 @@
/*
* Renesas RCar Gen3 memory map tables
*
* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/armv8/mmu.h>
static struct mm_region r8a7795_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
static struct mm_region r8a7796_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0xe0000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xe0000000UL,
.phys = 0xe0000000UL,
.size = 0xe0000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = r8a7795_mem_map;
void rcar_gen3_memmap_fixup(void)
{
u32 cpu_type = rmobile_get_cpu_type();
switch (cpu_type) {
case RMOBILE_CPU_TYPE_R8A7795:
mem_map = r8a7795_mem_map;
break;
case RMOBILE_CPU_TYPE_R8A7796:
mem_map = r8a7796_mem_map;
break;
}
}

30
arch/arm/mach-rmobile/memmap-r8a7795.c
View file

@ -1,30 +0,0 @@
/*
* Copyright (C) 2016 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/armv8/mmu.h>
static struct mm_region r8a7795_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = r8a7795_mem_map;

30
arch/arm/mach-rmobile/memmap-r8a7796.c
View file

@ -1,30 +0,0 @@
/*
* Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/armv8/mmu.h>
static struct mm_region r8a7796_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0xe0000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xe0000000UL,
.phys = 0xe0000000UL,
.size = 0xe0000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = r8a7796_mem_map;

5005
arch/arm/mach-rmobile/pfc-r8a7795.c
View file

File diff suppressed because it is too large Load diff

5253
arch/arm/mach-rmobile/pfc-r8a7796.c
View file

File diff suppressed because it is too large Load diff

2
board/renesas/salvator-x/Makefile
View file

@ -6,4 +6,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := salvator-x.o ../rcar-common/common.o
obj-y := salvator-x.o

48
board/renesas/salvator-x/salvator-x.c
View file

@ -79,17 +79,19 @@ int board_early_init_f(void)
int board_init(void)
{
u32 cpu_type = rmobile_get_cpu_type();
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
#if defined(CONFIG_R8A7795)
/* GSX: force power and clock supply */
writel(0x0000001F, SYSC_PWRONCR2);
while (readl(SYSC_PWRSR2) != 0x000003E0)
mdelay(20);
if (cpu_type == RMOBILE_CPU_TYPE_R8A7795) {
/* GSX: force power and clock supply */
writel(0x0000001F, SYSC_PWRONCR2);
while (readl(SYSC_PWRSR2) != 0x000003E0)
mdelay(20);
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
#endif
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
}
/* USB1 pull-up */
setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
@ -107,43 +109,19 @@ int board_init(void)
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_1_SIZE;
#if (CONFIG_NR_DRAM_BANKS >= 2)
gd->ram_size += PHYS_SDRAM_2_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 3)
gd->ram_size += PHYS_SDRAM_3_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 4)
gd->ram_size += PHYS_SDRAM_4_SIZE;
#endif
if (fdtdec_setup_memory_size() != 0)
return -EINVAL;
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
#if (CONFIG_NR_DRAM_BANKS >= 2)
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 3)
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 4)
gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
#endif
fdtdec_setup_memory_banksize();
return 0;
}
const struct rmobile_sysinfo sysinfo = {
CONFIG_RCAR_BOARD_STRING
};
#define RST_BASE 0xE6160000
#define RST_CA57RESCNT (RST_BASE + 0x40)
#define RST_CA53RESCNT (RST_BASE + 0x44)

2
board/renesas/ulcb/Makefile
View file

@ -6,4 +6,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := ulcb.o cpld.o ../rcar-common/common.o
obj-y := ulcb.o cpld.o

208
board/renesas/ulcb/cpld.c
View file

@ -8,14 +8,12 @@
*/
#include <common.h>
#include <spi.h>
#include <asm/io.h>
#include <asm/gpio.h>
#define SCLK (192 + 8) /* GPIO6 8 */
#define SSTBZ (64 + 3) /* GPIO2 3 */
#define MOSI (192 + 7) /* GPIO6 8 */
#define MISO (192 + 10) /* GPIO6 10 */
#include <asm/io.h>
#include <dm.h>
#include <errno.h>
#include <linux/err.h>
#include <sysreset.h>
#define CPLD_ADDR_MODE 0x00 /* RW */
#define CPLD_ADDR_MUX 0x02 /* RW */
@ -23,111 +21,89 @@
#define CPLD_ADDR_RESET 0x80 /* RW */
#define CPLD_ADDR_VERSION 0xFF /* R */
static int cpld_initialized;
struct renesas_ulcb_sysreset_priv {
struct gpio_desc miso;
struct gpio_desc mosi;
struct gpio_desc sck;
struct gpio_desc sstbz;
};
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
/* Always valid */
return 1;
}
void spi_cs_activate(struct spi_slave *slave)
{
/* Always active */
}
void spi_cs_deactivate(struct spi_slave *slave)
{
/* Always active */
}
void ulcb_softspi_sda(int set)
{
gpio_set_value(MOSI, set);
}
void ulcb_softspi_scl(int set)
{
gpio_set_value(SCLK, set);
}
unsigned char ulcb_softspi_read(void)
{
return !!gpio_get_value(MISO);
}
static void cpld_rw(u8 write)
{
gpio_set_value(MOSI, write);
gpio_set_value(SSTBZ, 0);
gpio_set_value(SCLK, 1);
gpio_set_value(SCLK, 0);
gpio_set_value(SSTBZ, 1);
}
static u32 cpld_read(u8 addr)
static u32 cpld_read(struct udevice *dev, u8 addr)
{
struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
u32 data = 0;
int i;
spi_xfer(NULL, 8, &addr, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
for (i = 0; i < 8; i++) {
dm_gpio_set_value(&priv->mosi, !!(addr & 0x80)); /* MSB first */
dm_gpio_set_value(&priv->sck, 1);
addr <<= 1;
dm_gpio_set_value(&priv->sck, 0);
}
cpld_rw(0);
dm_gpio_set_value(&priv->mosi, 0); /* READ */
dm_gpio_set_value(&priv->sstbz, 0);
dm_gpio_set_value(&priv->sck, 1);
dm_gpio_set_value(&priv->sck, 0);
dm_gpio_set_value(&priv->sstbz, 1);
spi_xfer(NULL, 32, NULL, &data, SPI_XFER_BEGIN | SPI_XFER_END);
for (i = 0; i < 32; i++) {
dm_gpio_set_value(&priv->sck, 1);
data <<= 1;
data |= dm_gpio_get_value(&priv->miso); /* MSB first */
dm_gpio_set_value(&priv->sck, 0);
}
return swab32(data);
return data;
}
static void cpld_write(u8 addr, u32 data)
static void cpld_write(struct udevice *dev, u8 addr, u32 data)
{
data = swab32(data);
struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
int i;
spi_xfer(NULL, 32, &data, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
for (i = 0; i < 32; i++) {
dm_gpio_set_value(&priv->mosi, data & (1 << 31)); /* MSB first */
dm_gpio_set_value(&priv->sck, 1);
data <<= 1;
dm_gpio_set_value(&priv->sck, 0);
}
spi_xfer(NULL, 8, NULL, &addr, SPI_XFER_BEGIN | SPI_XFER_END);
for (i = 0; i < 8; i++) {
dm_gpio_set_value(&priv->mosi, addr & 0x80); /* MSB first */
dm_gpio_set_value(&priv->sck, 1);
addr <<= 1;
dm_gpio_set_value(&priv->sck, 0);
}
cpld_rw(1);
}
static void cpld_init(void)
{
if (cpld_initialized)
return;
/* PULL-UP on MISO line */
setbits_le32(PFC_PUEN5, PUEN_SSI_SDATA4);
gpio_request(SCLK, NULL);
gpio_request(SSTBZ, NULL);
gpio_request(MOSI, NULL);
gpio_request(MISO, NULL);
gpio_direction_output(SCLK, 0);
gpio_direction_output(SSTBZ, 1);
gpio_direction_output(MOSI, 0);
gpio_direction_input(MISO);
/* Dummy read */
cpld_read(CPLD_ADDR_VERSION);
cpld_initialized = 1;
dm_gpio_set_value(&priv->mosi, 1); /* WRITE */
dm_gpio_set_value(&priv->sstbz, 0);
dm_gpio_set_value(&priv->sck, 1);
dm_gpio_set_value(&priv->sck, 0);
dm_gpio_set_value(&priv->sstbz, 1);
}
static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct udevice *dev;
u32 addr, val;
int ret;
cpld_init();
ret = uclass_get_device_by_driver(UCLASS_SYSRESET,
DM_GET_DRIVER(sysreset_renesas_ulcb),
&dev);
if (ret)
return ret;
if (argc == 2 && strcmp(argv[1], "info") == 0) {
printf("CPLD version:\t\t\t0x%08x\n",
cpld_read(CPLD_ADDR_VERSION));
cpld_read(dev, CPLD_ADDR_VERSION));
printf("H3 Mode setting (MD0..28):\t0x%08x\n",
cpld_read(CPLD_ADDR_MODE));
cpld_read(dev, CPLD_ADDR_MODE));
printf("Multiplexer settings:\t\t0x%08x\n",
cpld_read(CPLD_ADDR_MUX));
cpld_read(dev, CPLD_ADDR_MUX));
printf("DIPSW (SW6):\t\t\t0x%08x\n",
cpld_read(CPLD_ADDR_DIPSW6));
cpld_read(dev, CPLD_ADDR_DIPSW6));
return 0;
}
@ -143,10 +119,10 @@ static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
}
if (argc == 3 && strcmp(argv[1], "read") == 0) {
printf("0x%x\n", cpld_read(addr));
printf("0x%x\n", cpld_read(dev, addr));
} else if (argc == 4 && strcmp(argv[1], "write") == 0) {
val = simple_strtoul(argv[3], NULL, 16);
cpld_write(addr, val);
cpld_write(dev, addr, val);
}
return 0;
@ -160,8 +136,56 @@ U_BOOT_CMD(
"cpld write addr val\n"
);
void reset_cpu(ulong addr)
static int renesas_ulcb_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
cpld_init();
cpld_write(CPLD_ADDR_RESET, 1);
cpld_write(dev, CPLD_ADDR_RESET, 1);
return -EINPROGRESS;
}
static int renesas_ulcb_sysreset_probe(struct udevice *dev)
{
struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
if (gpio_request_by_name(dev, "gpio-miso", 0, &priv->miso,
GPIOD_IS_IN))
return -EINVAL;
if (gpio_request_by_name(dev, "gpio-sck", 0, &priv->sck,
GPIOD_IS_OUT))
return -EINVAL;
if (gpio_request_by_name(dev, "gpio-sstbz", 0, &priv->sstbz,
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE))
return -EINVAL;
if (gpio_request_by_name(dev, "gpio-mosi", 0, &priv->mosi,
GPIOD_IS_OUT))
return -EINVAL;
/* PULL-UP on MISO line */
setbits_le32(PFC_PUEN5, PUEN_SSI_SDATA4);
/* Dummy read */
cpld_read(dev, CPLD_ADDR_VERSION);
return 0;
}
static struct sysreset_ops renesas_ulcb_sysreset = {
.request = renesas_ulcb_sysreset_request,
};
static const struct udevice_id renesas_ulcb_sysreset_ids[] = {
{ .compatible = "renesas,ulcb-cpld" },
{ }
};
U_BOOT_DRIVER(sysreset_renesas_ulcb) = {
.name = "renesas_ulcb_sysreset",
.id = UCLASS_SYSRESET,
.ops = &renesas_ulcb_sysreset,
.probe = renesas_ulcb_sysreset_probe,
.of_match = renesas_ulcb_sysreset_ids,
.priv_auto_alloc_size = sizeof(struct renesas_ulcb_sysreset_priv),
};

32
board/renesas/ulcb/ulcb.c
View file

@ -97,39 +97,15 @@ int board_init(void)
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_1_SIZE;
#if (CONFIG_NR_DRAM_BANKS >= 2)
gd->ram_size += PHYS_SDRAM_2_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 3)
gd->ram_size += PHYS_SDRAM_3_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 4)
gd->ram_size += PHYS_SDRAM_4_SIZE;
#endif
if (fdtdec_setup_memory_size() != 0)
return -EINVAL;
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
#if (CONFIG_NR_DRAM_BANKS >= 2)
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 3)
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 4)
gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
#endif
fdtdec_setup_memory_banksize();
return 0;
}
const struct rmobile_sysinfo sysinfo = {
CONFIG_RCAR_BOARD_STRING
};

7
configs/r8a7795_salvator-x_defconfig
View file

@ -13,8 +13,8 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
@ -26,10 +26,14 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
CONFIG_MMC_UNIPHIER=y
CONFIG_PHY_MICREL=y
@ -45,6 +49,7 @@ CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y

9
configs/r8a7795_ulcb_defconfig
View file

@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
@ -25,12 +26,18 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
CONFIG_MMC_UNIPHIER=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
CONFIG_PINCTRL=y
@ -40,8 +47,10 @@ CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y

7
configs/r8a7796_salvator-x_defconfig
View file

@ -14,8 +14,8 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
@ -27,10 +27,14 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
CONFIG_MMC_UNIPHIER=y
CONFIG_PHY_MICREL=y
@ -46,6 +50,7 @@ CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y

9
configs/r8a7796_ulcb_defconfig
View file

@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
@ -26,12 +27,18 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
CONFIG_MMC_UNIPHIER=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
CONFIG_PINCTRL=y
@ -41,8 +48,10 @@ CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y

60
drivers/clk/renesas/clk-rcar-gen3.c
View file

@ -490,6 +490,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = {
DEF_MOD("sdif0", 314, R8A7796_CLK_SD0),
DEF_MOD("pcie1", 318, R8A7796_CLK_S3D1),
DEF_MOD("pcie0", 319, R8A7796_CLK_S3D1),
DEF_MOD("usb3-if0", 328, R8A7796_CLK_S3D1),
DEF_MOD("usb-dmac0", 330, R8A7796_CLK_S3D1),
DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1),
DEF_MOD("rwdt", 402, R8A7796_CLK_R),
@ -1074,6 +1075,64 @@ static int gen3_clk_probe(struct udevice *dev)
return 0;
}
struct mstp_stop_table {
u32 dis;
u32 en;
};
static struct mstp_stop_table r8a7795_mstp_table[] = {
{ 0x00640800, 0x0 }, { 0xF3EE9390, 0x0 },
{ 0x340FAFDC, 0x2040 }, { 0xD80C7CDF, 0x400 },
{ 0x80000184, 0x180 }, { 0x40BFFF46, 0x0 },
{ 0xE5FBEECF, 0x0 }, { 0x39FFFF0E, 0x0 },
{ 0x01F19FF4, 0x0 }, { 0xFFDFFFFF, 0x0 },
{ 0xFFFEFFE0, 0x0 }, { 0x00000000, 0x0 },
};
static struct mstp_stop_table r8a7796_mstp_table[] = {
{ 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 },
{ 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 },
{ 0x80000184, 0x180 }, { 0xC3FFFFFF, 0x0 },
{ 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 },
{ 0x01F1FFF7, 0x0 }, { 0xFFFFFFFE, 0x0 },
{ 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
};
#define TSTR0 0x04
#define TSTR0_STR0 BIT(0)
static int gen3_clk_remove(struct udevice *dev)
{
struct gen3_clk_priv *priv = dev_get_priv(dev);
enum gen3_clk_model model = dev_get_driver_data(dev);
struct mstp_stop_table *tbl;
unsigned int i, tbl_size;
switch (model) {
case CLK_R8A7795:
tbl = r8a7795_mstp_table;
tbl_size = ARRAY_SIZE(r8a7795_mstp_table);
break;
case CLK_R8A7796:
tbl = r8a7796_mstp_table;
tbl_size = ARRAY_SIZE(r8a7796_mstp_table);
break;
default:
return -EINVAL;
}
/* Stop TMU0 */
clrbits_le32(TMU_BASE + TSTR0, TSTR0_STR0);
/* Stop module clock */
for (i = 0; i < tbl_size; i++) {
clrsetbits_le32(priv->base + SMSTPCR(i), tbl[i].dis, tbl[i].en);
clrsetbits_le32(priv->base + RMSTPCR(i), tbl[i].dis, 0x0);
}
return 0;
}
static const struct udevice_id gen3_clk_ids[] = {
{ .compatible = "renesas,r8a7795-cpg-mssr", .data = CLK_R8A7795 },
{ .compatible = "renesas,r8a7796-cpg-mssr", .data = CLK_R8A7796 },
@ -1087,4 +1146,5 @@ U_BOOT_DRIVER(clk_gen3) = {
.priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
.remove = gen3_clk_remove,
};

20
drivers/gpio/gpio-rcar.c
View file

@ -10,6 +10,7 @@
#include <errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include "../pinctrl/renesas/sh_pfc.h"
#define GPIO_IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
#define GPIO_INOUTSEL 0x04 /* General Input/Output Switching Register */
@ -29,7 +30,8 @@
DECLARE_GLOBAL_DATA_PTR;
struct rcar_gpio_priv {
void __iomem *regs;
void __iomem *regs;
int pfc_offset;
};
static int rcar_gpio_get_value(struct udevice *dev, unsigned offset)
@ -113,7 +115,22 @@ static int rcar_gpio_get_function(struct udevice *dev, unsigned offset)
return GPIOF_INPUT;
}
static int rcar_gpio_request(struct udevice *dev, unsigned offset,
const char *label)
{
struct rcar_gpio_priv *priv = dev_get_priv(dev);
struct udevice *pctldev;
int ret;
ret = uclass_get_device(UCLASS_PINCTRL, 0, &pctldev);
if (ret)
return ret;
return sh_pfc_config_mux_for_gpio(pctldev, priv->pfc_offset + offset);
}
static const struct dm_gpio_ops rcar_gpio_ops = {
.request = rcar_gpio_request,
.direction_input = rcar_gpio_direction_input,
.direction_output = rcar_gpio_direction_output,
.get_value = rcar_gpio_get_value,
@ -135,6 +152,7 @@ static int rcar_gpio_probe(struct udevice *dev)
ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges",
NULL, 3, 0, &args);
priv->pfc_offset = ret == 0 ? args.args[1] : -1;
uc_priv->gpio_count = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
ret = clk_get_by_index(dev, 0, &clk);

6
drivers/i2c/Kconfig
View file

@ -157,6 +157,12 @@ config SYS_I2C_OMAP24XX
help
Add support for the OMAP2+ I2C driver.
config SYS_I2C_RCAR_IIC
bool "Renesas RCar Gen3 IIC driver"
depends on RCAR_GEN3 && DM_I2C
help
Support for Renesas RCar Gen3 IIC controller.
config SYS_I2C_ROCKCHIP
bool "Rockchip I2C driver"
depends on DM_I2C

1
drivers/i2c/Makefile
View file

@ -31,6 +31,7 @@ obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o
obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o
obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o
obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o

271
drivers/i2c/rcar_iic.c Normal file
View file

@ -0,0 +1,271 @@
/*
* Renesas RCar IIC driver
*
* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
*
* Based on
* Copyright (C) 2011, 2013 Renesas Solutions Corp.
* Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <i2c.h>
#include <asm/io.h>
struct rcar_iic_priv {
void __iomem *base;
struct clk clk;
u8 iccl;
u8 icch;
};
#define RCAR_IIC_ICDR 0x00
#define RCAR_IIC_ICCR 0x04
#define RCAR_IIC_ICSR 0x08
#define RCAR_IIC_ICIC 0x0c
#define RCAR_IIC_ICCL 0x10
#define RCAR_IIC_ICCH 0x14
/* ICCR */
#define RCAR_IIC_ICCR_ICE BIT(7)
#define RCAR_IIC_ICCR_RACK BIT(6)
#define RCAR_IIC_ICCR_RTS BIT(4)
#define RCAR_IIC_ICCR_BUSY BIT(2)
#define RCAR_IIC_ICCR_SCP BIT(0)
/* ICSR / ICIC */
#define RCAR_IC_BUSY BIT(4)
#define RCAR_IC_TACK BIT(2)
#define RCAR_IC_DTE BIT(0)
#define IRQ_WAIT 1000
static void sh_irq_dte(struct udevice *dev)
{
struct rcar_iic_priv *priv = dev_get_priv(dev);
int i;
for (i = 0; i < IRQ_WAIT; i++) {
if (RCAR_IC_DTE & readb(priv->base + RCAR_IIC_ICSR))
break;
udelay(10);
}
}
static int sh_irq_dte_with_tack(struct udevice *dev)
{
struct rcar_iic_priv *priv = dev_get_priv(dev);
int i;
for (i = 0; i < IRQ_WAIT; i++) {
if (RCAR_IC_DTE & readb(priv->base + RCAR_IIC_ICSR))
break;
if (RCAR_IC_TACK & readb(priv->base + RCAR_IIC_ICSR))
return -ETIMEDOUT;
udelay(10);
}
return 0;
}
static void sh_irq_busy(struct udevice *dev)
{
struct rcar_iic_priv *priv = dev_get_priv(dev);
int i;
for (i = 0; i < IRQ_WAIT; i++) {
if (!(RCAR_IC_BUSY & readb(priv->base + RCAR_IIC_ICSR)))
break;
udelay(10);
}
}
static int rcar_iic_set_addr(struct udevice *dev, u8 chip, u8 read)
{
struct rcar_iic_priv *priv = dev_get_priv(dev);
clrbits_8(priv->base + RCAR_IIC_ICCR, RCAR_IIC_ICCR_ICE);
setbits_8(priv->base + RCAR_IIC_ICCR, RCAR_IIC_ICCR_ICE);
writeb(priv->iccl, priv->base + RCAR_IIC_ICCL);
writeb(priv->icch, priv->base + RCAR_IIC_ICCH);
writeb(RCAR_IC_TACK, priv->base + RCAR_IIC_ICIC);
writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_RTS | RCAR_IIC_ICCR_BUSY,
priv->base + RCAR_IIC_ICCR);
sh_irq_dte(dev);
clrbits_8(priv->base + RCAR_IIC_ICSR, RCAR_IC_TACK);
writeb(chip << 1 | read, priv->base + RCAR_IIC_ICDR);
return sh_irq_dte_with_tack(dev);
}
static void rcar_iic_finish(struct udevice *dev)
{
struct rcar_iic_priv *priv = dev_get_priv(dev);
writeb(0, priv->base + RCAR_IIC_ICSR);
clrbits_8(priv->base + RCAR_IIC_ICCR, RCAR_IIC_ICCR_ICE);
}
static int rcar_iic_read_common(struct udevice *dev, struct i2c_msg *msg)
{
struct rcar_iic_priv *priv = dev_get_priv(dev);
int i, ret = -EREMOTEIO;
if (rcar_iic_set_addr(dev, msg->addr, 1) != 0)
goto err;
udelay(10);
writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_SCP,
priv->base + RCAR_IIC_ICCR);
for (i = 0; i < msg->len; i++) {
if (sh_irq_dte_with_tack(dev) != 0)
goto err;
msg->buf[i] = readb(priv->base + RCAR_IIC_ICDR) & 0xff;
if (msg->len - 1 == i) {
writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_RACK,
priv->base + RCAR_IIC_ICCR);
}
}
sh_irq_busy(dev);
ret = 0;
err:
rcar_iic_finish(dev);
return ret;
}
static int rcar_iic_write_common(struct udevice *dev, struct i2c_msg *msg)
{
struct rcar_iic_priv *priv = dev_get_priv(dev);
int i, ret = -EREMOTEIO;
if (rcar_iic_set_addr(dev, msg->addr, 0) != 0)
goto err;
udelay(10);
for (i = 0; i < msg->len; i++) {
writeb(msg->buf[i], priv->base + RCAR_IIC_ICDR);
if (sh_irq_dte_with_tack(dev) != 0)
goto err;
}
if (msg->flags & I2C_M_STOP) {
writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_RTS,
priv->base + RCAR_IIC_ICCR);
if (sh_irq_dte_with_tack(dev) != 0)
goto err;
}
sh_irq_busy(dev);
ret = 0;
err:
rcar_iic_finish(dev);
return ret;
}
static int rcar_iic_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
{
int ret;
for (; nmsgs > 0; nmsgs--, msg++) {
if (msg->flags & I2C_M_RD)
ret = rcar_iic_read_common(dev, msg);
else
ret = rcar_iic_write_common(dev, msg);
if (ret)
return -EREMOTEIO;
}
return ret;
}
static int rcar_iic_set_speed(struct udevice *dev, uint speed)
{
struct rcar_iic_priv *priv = dev_get_priv(dev);
const unsigned int ratio_high = 4;
const unsigned int ratio_low = 5;
int clkrate, denom;
clkrate = clk_get_rate(&priv->clk);
if (clkrate < 0)
return clkrate;
/*
* Calculate the value for ICCL and ICCH. From the data sheet:
* iccl = (p-clock / transfer-rate) * (L / (L + H))
* icch = (p clock / transfer rate) * (H / (L + H))
* where L and H are the SCL low and high ratio.
*/
denom = speed * (ratio_high + ratio_low);
priv->iccl = DIV_ROUND_CLOSEST(clkrate * ratio_low, denom);
priv->icch = DIV_ROUND_CLOSEST(clkrate * ratio_high, denom);
return 0;
}
static int rcar_iic_probe_chip(struct udevice *dev, uint addr, uint flags)
{
struct rcar_iic_priv *priv = dev_get_priv(dev);
int ret;
rcar_iic_set_addr(dev, addr, 1);
writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_SCP,
priv->base + RCAR_IIC_ICCR);
ret = sh_irq_dte_with_tack(dev);
rcar_iic_finish(dev);
return ret;
}
static int rcar_iic_probe(struct udevice *dev)
{
struct rcar_iic_priv *priv = dev_get_priv(dev);
int ret;
priv->base = dev_read_addr_ptr(dev);
ret = clk_get_by_index(dev, 0, &priv->clk);
if (ret)
return ret;
ret = clk_enable(&priv->clk);
if (ret)
return ret;
rcar_iic_finish(dev);
return rcar_iic_set_speed(dev, 100000);
}
static const struct dm_i2c_ops rcar_iic_ops = {
.xfer = rcar_iic_xfer,
.probe_chip = rcar_iic_probe_chip,
.set_bus_speed = rcar_iic_set_speed,
};
static const struct udevice_id rcar_iic_ids[] = {
{ .compatible = "renesas,rmobile-iic" },
{ }
};
U_BOOT_DRIVER(iic_rcar) = {
.name = "iic_rcar",
.id = UCLASS_I2C,
.of_match = rcar_iic_ids,
.probe = rcar_iic_probe,
.priv_auto_alloc_size = sizeof(struct rcar_iic_priv),
.ops = &rcar_iic_ops,
};

7
drivers/net/ravb.c
View file

@ -492,8 +492,8 @@ static int ravb_probe(struct udevice *dev)
if (ret < 0)
goto err_mdio_alloc;
gpio_request_by_name_nodev(dev_ofnode(dev), "reset-gpios", 0,
&eth->reset_gpio, GPIOD_IS_OUT);
gpio_request_by_name(dev, "reset-gpios", 0, &eth->reset_gpio,
GPIOD_IS_OUT);
mdiodev = mdio_alloc();
if (!mdiodev) {
@ -528,7 +528,8 @@ static int ravb_remove(struct udevice *dev)
free(eth->phydev);
mdio_unregister(eth->bus);
mdio_free(eth->bus);
dm_gpio_free(dev, &eth->reset_gpio);
if (dm_gpio_is_valid(&eth->reset_gpio))
dm_gpio_free(dev, &eth->reset_gpio);
unmap_physmem(eth->iobase, MAP_NOCACHE);
return 0;

60
drivers/pinctrl/renesas/pfc.c
View file

@ -448,6 +448,51 @@ static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
return priv->pfc.info->functions[selector].name;
}
int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector)
{
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
struct sh_pfc_pinctrl *pmx = &priv->pmx;
struct sh_pfc *pfc = &priv->pfc;
struct sh_pfc_pin_config *cfg;
const struct sh_pfc_pin *pin = NULL;
int i, idx;
for (i = 1; i < pfc->info->nr_pins; i++) {
if (priv->pfc.info->pins[i].pin != pin_selector)
continue;
pin = &priv->pfc.info->pins[i];
break;
}
if (!pin)
return -EINVAL;
idx = sh_pfc_get_pin_index(pfc, pin->pin);
cfg = &pmx->configs[idx];
if (cfg->type != PINMUX_TYPE_NONE)
return -EBUSY;
return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
}
static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
unsigned func_selector)
{
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
struct sh_pfc_pinctrl *pmx = &priv->pmx;
struct sh_pfc *pfc = &priv->pfc;
const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
int idx = sh_pfc_get_pin_index(pfc, pin->pin);
struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
if (cfg->type != PINMUX_TYPE_NONE)
return -EBUSY;
return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
}
static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
unsigned func_selector)
{
@ -642,6 +687,19 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
return 0;
}
static int sh_pfc_pinconf_pin_set(struct udevice *dev,
unsigned int pin_selector,
unsigned int param, unsigned int arg)
{
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
struct sh_pfc_pinctrl *pmx = &priv->pmx;
struct sh_pfc *pfc = &priv->pfc;
const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
return 0;
}
static int sh_pfc_pinconf_group_set(struct udevice *dev,
unsigned int group_selector,
@ -671,8 +729,10 @@ static struct pinctrl_ops sh_pfc_pinctrl_ops = {
#if CONFIG_IS_ENABLED(PINCONF)
.pinconf_num_params = ARRAY_SIZE(sh_pfc_pinconf_params),
.pinconf_params = sh_pfc_pinconf_params,
.pinconf_set = sh_pfc_pinconf_pin_set,
.pinconf_group_set = sh_pfc_pinconf_group_set,
#endif
.pinmux_set = sh_pfc_pinctrl_pin_set,
.pinmux_group_set = sh_pfc_pinctrl_group_set,
.set_state = pinctrl_generic_set_state,
};

1
drivers/pinctrl/renesas/sh_pfc.h
View file

@ -243,6 +243,7 @@ void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data)
const struct sh_pfc_bias_info *
sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
unsigned int num, unsigned int pin);
int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector);
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
extern const struct sh_pfc_soc_info r8a7796_pinmux_info;

3
drivers/serial/serial_sh.h
View file

@ -226,8 +226,7 @@ struct uart_port {
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
defined(CONFIG_R8A7792) || defined(CONFIG_R8A7793) || \
defined(CONFIG_R8A7794) || defined(CONFIG_R8A7795) || \
defined(CONFIG_R8A7796)
defined(CONFIG_R8A7794) || defined(CONFIG_RCAR_GEN3)
# if defined(CONFIG_SCIF_A)
# define SCIF_ORER 0x0200
# else

29
include/configs/rcar-gen3-common.h
View file

@ -31,6 +31,11 @@
#define CONFIG_ARCH_CPU_INIT
/* Generic Interrupt Controller Definitions */
#define CONFIG_GICV2
#define GICD_BASE 0xF1010000
#define GICC_BASE 0xF1020000
/* console */
#define CONFIG_SYS_CBSIZE 2048
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
@ -43,30 +48,12 @@
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
#define DRAM_RSV_SIZE 0x08000000
#if defined(CONFIG_R8A7795)
#define CONFIG_NR_DRAM_BANKS 4
#define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE)
#define PHYS_SDRAM_1_SIZE (0x40000000u - DRAM_RSV_SIZE)
#define PHYS_SDRAM_2 0x500000000
#define PHYS_SDRAM_2_SIZE 0x40000000u
#define PHYS_SDRAM_3 0x600000000
#define PHYS_SDRAM_3_SIZE 0x40000000u
#define PHYS_SDRAM_4 0x700000000
#define PHYS_SDRAM_4_SIZE 0x40000000u
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE
#elif defined(CONFIG_R8A7796)
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE)
#define PHYS_SDRAM_1_SIZE (0x80000000u - DRAM_RSV_SIZE)
#define PHYS_SDRAM_2 0x0600000000
#define PHYS_SDRAM_2_SIZE 0x80000000u
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE
#endif
#define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE)
#define CONFIG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE)
#define CONFIG_SYS_LOAD_ADDR 0x48080000
#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_SDRAM_SIZE
#define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)
#define CONFIG_SYS_MONITOR_BASE 0x00000000
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)

54
include/configs/salvator-x.h
View file

@ -12,74 +12,22 @@
#undef DEBUG
#define CONFIG_RCAR_BOARD_STRING "Salvator-X"
#include "rcar-gen3-common.h"
/* SCIF */
#define CONFIG_CONS_SCIF2
#define CONFIG_CONS_INDEX 2
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ
/* [A] Hyper Flash */
/* use to RPC(SPI Multi I/O Bus Controller) */
/* Ethernet RAVB */
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
#define RCAR_XTAL_CLK 33333333u
#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK
/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */
/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */
#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2)
#define CONFIG_S3D2_CLK_FREQ (266666666u/2)
#define CONFIG_S3D4_CLK_FREQ (266666666u/4)
#define CONFIG_SYS_CLK_FREQ 33333333u
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
/* Generic Interrupt Controller Definitions */
#define CONFIG_GICV2
#define GICD_BASE 0xF1010000
#define GICC_BASE 0xF1020000
/* i2c */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SH
#define CONFIG_SYS_I2C_SLAVE 0x60
#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1
#define CONFIG_SYS_I2C_SH_SPEED0 400000
#define CONFIG_SH_I2C_DATA_HIGH 4
#define CONFIG_SH_I2C_DATA_LOW 5
#define CONFIG_SH_I2C_CLOCK 10000000
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30
/* USB */
#ifdef CONFIG_R8A7795
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
#else
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
/* SDHI */
#define CONFIG_SH_SDHI_FREQ 200000000
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
/* Module stop status bits */
/* MFIS, SCIF1 */
#define CONFIG_SMSTP2_ENA 0x00002040
/* SCIF2 */
#define CONFIG_SMSTP3_ENA 0x00000400
/* INTC-AP, IRQC */
#define CONFIG_SMSTP4_ENA 0x00000180
#endif /* __SALVATOR_X_H */

76
include/configs/ulcb.h
View file

@ -12,96 +12,22 @@
#undef DEBUG
#define CONFIG_RCAR_BOARD_STRING "ULCB"
#include "rcar-gen3-common.h"
/* M3 ULCB has 2 banks, each with 1 GiB of RAM */
#if defined(CONFIG_R8A7796)
#undef PHYS_SDRAM_1_SIZE
#undef PHYS_SDRAM_2_SIZE
#define PHYS_SDRAM_1_SIZE (0x40000000u - DRAM_RSV_SIZE)
#define PHYS_SDRAM_2_SIZE 0x40000000u
#endif
/* SCIF */
#define CONFIG_CONS_SCIF2
#define CONFIG_CONS_INDEX 2
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ
/* [A] Hyper Flash */
/* use to RPC(SPI Multi I/O Bus Controller) */
/* Ethernet RAVB */
#define CONFIG_PHY_MICREL
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
#define RCAR_XTAL_CLK 33333333u
#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK
/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */
/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */
#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2)
#define CONFIG_S3D2_CLK_FREQ (266666666u/2)
#define CONFIG_S3D4_CLK_FREQ (266666666u/4)
#define CONFIG_SYS_CLK_FREQ 33333333u
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
/* Generic Interrupt Controller Definitions */
#define CONFIG_GICV2
#define GICD_BASE 0xF1010000
#define GICC_BASE 0xF1020000
/* CPLD SPI */
#define CONFIG_CMD_SPI
#define CONFIG_SOFT_SPI
#define SPI_DELAY udelay(0)
#define SPI_SDA(val) ulcb_softspi_sda(val)
#define SPI_SCL(val) ulcb_softspi_scl(val)
#define SPI_READ ulcb_softspi_read()
#ifndef __ASSEMBLY__
void ulcb_softspi_sda(int);
void ulcb_softspi_scl(int);
unsigned char ulcb_softspi_read(void);
#endif
/* i2c */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SH
#define CONFIG_SYS_I2C_SLAVE 0x60
#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1
#define CONFIG_SYS_I2C_SH_SPEED0 400000
#define CONFIG_SH_I2C_DATA_HIGH 4
#define CONFIG_SH_I2C_DATA_LOW 5
#define CONFIG_SH_I2C_CLOCK 10000000
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30
/* USB */
#ifdef CONFIG_R8A7795
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
#else
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
/* SDHI */
#define CONFIG_SH_SDHI_FREQ 200000000
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
/* Module stop status bits */
/* MFIS, SCIF1 */
#define CONFIG_SMSTP2_ENA 0x00002040
/* SCIF2 */
#define CONFIG_SMSTP3_ENA 0x00000400
/* INTC-AP, IRQC */
#define CONFIG_SMSTP4_ENA 0x00000180
#endif /* __ULCB_H */

24
lib/fdtdec.c
View file

@ -1176,21 +1176,33 @@ int fdtdec_setup_memory_size(void)
#if defined(CONFIG_NR_DRAM_BANKS)
int fdtdec_setup_memory_banksize(void)
{
int bank, ret, mem;
int bank, ret, mem, reg = 0;
struct fdt_resource res;
mem = fdt_path_offset(gd->fdt_blob, "/memory");
mem = fdt_node_offset_by_prop_value(gd->fdt_blob, -1, "device_type",
"memory", 7);
if (mem < 0) {
debug("%s: Missing /memory node\n", __func__);
return -EINVAL;
}
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
ret = fdt_get_resource(gd->fdt_blob, mem, "reg", bank, &res);
if (ret == -FDT_ERR_NOTFOUND)
break;
if (ret != 0)
ret = fdt_get_resource(gd->fdt_blob, mem, "reg", reg++, &res);
if (ret == -FDT_ERR_NOTFOUND) {
reg = 0;
mem = fdt_node_offset_by_prop_value(gd->fdt_blob, mem,
"device_type",
"memory", 7);
if (mem == -FDT_ERR_NOTFOUND)
break;
ret = fdt_get_resource(gd->fdt_blob, mem, "reg", reg++, &res);
if (ret == -FDT_ERR_NOTFOUND)
break;
}
if (ret != 0) {
return -EINVAL;
}
gd->bd->bi_dram[bank].start = (phys_addr_t)res.start;
gd->bd->bi_dram[bank].size =

3
scripts/config_whitelist.txt
View file

@ -346,7 +346,6 @@ CONFIG_CPU_SH7785
CONFIG_CPU_SH_TYPE_R
CONFIG_CPU_TYPE_R
CONFIG_CPU_VR41XX
CONFIG_CP_CLK_FREQ
CONFIG_CQSPI_DECODER
CONFIG_CQSPI_REF_CLK
CONFIG_CRC32
@ -1886,8 +1885,6 @@ CONFIG_RUN_FROM_DDR1
CONFIG_RUN_FROM_IRAM_ONLY
CONFIG_RX_DESCR_NUM
CONFIG_S32V234
CONFIG_S3D2_CLK_FREQ
CONFIG_S3D4_CLK_FREQ
CONFIG_S5P
CONFIG_S5PC100
CONFIG_S5PC110