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cc4f36435f
If we run on a CPU which doesn't implement a particular cache then we would previously get stuck in an infinite loop, executing a cache op on the first "line" of the missing cache & then incrementing the address by 0. This was being avoided for the L2 caches, but not for the L1s. Fix this by generalising the check for a zero line size & avoiding the cache op loop when this is the case. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: u-boot@lists.denx.de |
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