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arm64: zynqmp: mp: Correct the R5 release sequence

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This patch corrects the R5 release sequence by adding the
below steps.
1. Flush dcache to ensure that image loaded into memory.
2. Keep R5 reset just to ensure R5 in reset.
3. Disable caches before accessing TCM as with out this
   A53 can do speculative and may result in ECC failures
   if TCM's are not initialized. So, it is always better
   to disable dcaches before accessing TCM and enable back.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reported-by: John Linn <linnj@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Siva Durga Prasad Paladugu 2017-08-01 16:24:52 +05:30 committed by Michal Simek
parent 62e950fad3
commit f322ad604e
1 changed files with 14 additions and 0 deletions
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14
arch/arm/cpu/armv8/zynqmp/mp.c
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@ -257,22 +257,36 @@ int cpu_release(int nr, int argc, char * const argv[])
boot_addr = ZYNQMP_R5_LOVEC_ADDR;
}
/*
* Since we don't know where the user may have loaded the image
* for an R5 we have to flush all the data cache to ensure
* the R5 sees it.
*/
flush_dcache_all();
if (!strncmp(argv[1], "lockstep", 8)) {
printf("R5 lockstep mode\n");
set_r5_reset(LOCK);
set_r5_tcm_mode(LOCK);
set_r5_halt_mode(HALT, LOCK);
set_r5_start(boot_addr);
enable_clock_r5();
release_r5_reset(LOCK);
dcache_disable();
write_tcm_boot_trampoline(boot_addr_uniq);
dcache_enable();
set_r5_halt_mode(RELEASE, LOCK);
} else if (!strncmp(argv[1], "split", 5)) {
printf("R5 split mode\n");
set_r5_reset(SPLIT);
set_r5_tcm_mode(SPLIT);
set_r5_halt_mode(HALT, SPLIT);
set_r5_start(boot_addr);
enable_clock_r5();
release_r5_reset(SPLIT);
dcache_disable();
write_tcm_boot_trampoline(boot_addr_uniq);
dcache_enable();
set_r5_halt_mode(RELEASE, SPLIT);
} else {
printf("Unsupported mode\n");